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Merge branch 'work/b_transport' into 'develop'

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Implement b_transport and add tests

See merge request ems/astdm/modeling.dram/dram.sys.5!3
This commit is contained in:
Lukas Steiner
2023-03-22 09:51:17 +00:00
parent 7621ac4a1d d18778a40a
commit e3b872446f
19 changed files with 624 additions and 70 deletions
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10
src/configuration/DRAMSys/config/McConfig.cpp
View File

@@ -60,7 +60,9 @@ void to_json(json_t &j, const McConfig &c)
{"ThinkDelayFw", c.thinkDelayFw},
{"ThinkDelayBw", c.thinkDelayBw},
{"PhyDelayFw", c.phyDelayFw},
{"PhyDelayBw", c.phyDelayBw}};
{"PhyDelayBw", c.phyDelayBw},
{"BlockingReadDelay", c.blockingReadDelay},
{"BlockingWriteDelay", c.blockingWriteDelay}};
remove_null_values(j);
}
@@ -132,6 +134,12 @@ void from_json(const json_t &j, McConfig &c)
if (j_mcconfig.contains("PhyDelayBw"))
j_mcconfig.at("PhyDelayBw").get_to(c.phyDelayBw);
if (j_mcconfig.contains("BlockingReadDelay"))
j_mcconfig.at("BlockingReadDelay").get_to(c.blockingReadDelay);
if (j_mcconfig.contains("BlockingWriteDelay"))
j_mcconfig.at("BlockingWriteDelay").get_to(c.blockingWriteDelay);
invalidateEnum(c.pagePolicy);
invalidateEnum(c.scheduler);
invalidateEnum(c.schedulerBuffer);

2
src/configuration/DRAMSys/config/McConfig.h
View File

@@ -171,6 +171,8 @@ struct McConfig
std::optional<unsigned int> thinkDelayBw;
std::optional<unsigned int> phyDelayFw;
std::optional<unsigned int> phyDelayBw;
std::optional<unsigned int> blockingReadDelay;
std::optional<unsigned int> blockingWriteDelay;
};
void to_json(json_t &j, const McConfig &c);

10
src/libdramsys/DRAMSys/configuration/Configuration.cpp
View File

@@ -274,6 +274,16 @@ void Configuration::loadMCConfig(const DRAMSys::Config::McConfig &mcConfig)
{
phyDelayBw = std::round(sc_time(*_phyDelayBw, SC_NS) / memSpec->tCK) * memSpec->tCK;
}
{
auto _blockingReadDelay = mcConfig.blockingReadDelay.value_or(60);
blockingReadDelay = std::round(sc_time(_blockingReadDelay, SC_NS) / memSpec->tCK) * memSpec->tCK;
}
{
auto _blockingWriteDelay = mcConfig.blockingWriteDelay.value_or(60);
blockingWriteDelay = std::round(sc_time(_blockingWriteDelay, SC_NS) / memSpec->tCK) * memSpec->tCK;
}
}
void Configuration::loadMemSpec(const DRAMSys::Config::MemSpec &memSpecConfig)

2
src/libdramsys/DRAMSys/configuration/Configuration.h
View File

@@ -79,6 +79,8 @@ public:
sc_core::sc_time thinkDelayBw = sc_core::SC_ZERO_TIME;
sc_core::sc_time phyDelayFw = sc_core::SC_ZERO_TIME;
sc_core::sc_time phyDelayBw = sc_core::SC_ZERO_TIME;
sc_core::sc_time blockingReadDelay = sc_core::SC_ZERO_TIME;
sc_core::sc_time blockingWriteDelay = sc_core::SC_ZERO_TIME;
// SimConfig
std::string simulationName = "default";

2
src/libdramsys/DRAMSys/controller/Command.h
View File

@@ -147,7 +147,7 @@ public:
struct CommandTuple
{
using Type = std::tuple<::Command, tlm::tlm_generic_payload *, sc_core::sc_time>;
using Type = std::tuple<::Command, tlm::tlm_generic_payload*, sc_core::sc_time>;
enum Accessor
{
Command = 0,

81
src/libdramsys/DRAMSys/controller/Controller.cpp
View File

@@ -80,6 +80,7 @@ Controller::Controller(const sc_module_name& name, const Configuration& config,
ControllerIF(name, config), addressDecoder(addressDecoder),
thinkDelayFw(config.thinkDelayFw), thinkDelayBw(config.thinkDelayBw),
phyDelayFw(config.phyDelayFw), phyDelayBw(config.phyDelayBw),
blockingReadDelay(config.blockingReadDelay), blockingWriteDelay(config.blockingWriteDelay),
minBytesPerBurst(config.memSpec->defaultBytesPerBurst),
maxBytesPerBurst(config.memSpec->maxBytesPerBurst)
{
@@ -302,11 +303,11 @@ void Controller::controllerMethod()
{
commandTuple = cmdMux->selectCommand(readyCommands);
Command command = std::get<CommandTuple::Command>(commandTuple);
tlm_generic_payload *payload = std::get<CommandTuple::Payload>(commandTuple);
tlm_generic_payload* trans = std::get<CommandTuple::Payload>(commandTuple);
if (command != Command::NOP) // can happen with FIFO strict
{
Rank rank = ControllerExtension::getRank(*payload);
Bank bank = ControllerExtension::getBank(*payload);
Rank rank = ControllerExtension::getRank(*trans);
Bank bank = ControllerExtension::getBank(*trans);
if (command.isRankCommand())
{
@@ -329,16 +330,16 @@ void Controller::controllerMethod()
refreshManagers[rank.ID()]->updateState(command);
powerDownManagers[rank.ID()]->updateState(command);
checker->insert(command, *payload);
checker->insert(command, *trans);
if (command.isCasCommand())
{
scheduler->removeRequest(*payload);
scheduler->removeRequest(*trans);
manageRequests(thinkDelayFw);
respQueue->insertPayload(payload, sc_time_stamp()
+ thinkDelayFw + phyDelayFw
+ memSpec.getIntervalOnDataStrobe(command, *payload).end
+ phyDelayBw + thinkDelayBw);
respQueue->insertPayload(trans, sc_time_stamp()
+ thinkDelayFw + phyDelayFw
+ memSpec.getIntervalOnDataStrobe(command, *trans).end
+ phyDelayBw + thinkDelayBw);
sc_time triggerTime = respQueue->getTriggerTime();
if (triggerTime != sc_max_time())
@@ -351,7 +352,7 @@ void Controller::controllerMethod()
sc_time fwDelay = thinkDelayFw + phyDelayFw;
tlm_phase phase = command.toPhase();
iSocket->nb_transport_fw(*payload, phase, fwDelay);
iSocket->nb_transport_fw(*trans, phase, fwDelay);
}
else
readyCmdBlocked = true;
@@ -383,18 +384,17 @@ void Controller::controllerMethod()
controllerEvent.notify(timeForNextTrigger - sc_time_stamp());
}
tlm_sync_enum Controller::nb_transport_fw(tlm_generic_payload &trans,
tlm_phase &phase, sc_time &delay)
tlm_sync_enum Controller::nb_transport_fw(tlm_generic_payload& trans, tlm_phase& phase, sc_time& delay)
{
if (phase == BEGIN_REQ)
{
transToAcquire.payload = &trans;
transToAcquire.time = sc_time_stamp() + delay;
transToAcquire.arrival = sc_time_stamp() + delay;
beginReqEvent.notify(delay);
}
else if (phase == END_RESP)
{
transToRelease.time = sc_time_stamp() + delay;
transToRelease.arrival = sc_time_stamp() + delay;
endRespEvent.notify(delay);
}
else
@@ -406,21 +406,26 @@ tlm_sync_enum Controller::nb_transport_fw(tlm_generic_payload &trans,
return TLM_ACCEPTED;
}
tlm_sync_enum Controller::nb_transport_bw(tlm_generic_payload &,
tlm_phase &, sc_time &)
tlm_sync_enum Controller::nb_transport_bw(tlm_generic_payload& ,tlm_phase& , sc_time&)
{
SC_REPORT_FATAL("Controller", "nb_transport_bw of controller must not be called!");
return TLM_ACCEPTED;
}
unsigned int Controller::transport_dbg(tlm_generic_payload &trans)
void Controller::b_transport(tlm_generic_payload& trans, sc_time& delay)
{
iSocket->b_transport(trans, delay);
delay += trans.is_write() ? blockingWriteDelay : blockingReadDelay;
}
unsigned int Controller::transport_dbg(tlm_generic_payload& trans)
{
return iSocket->transport_dbg(trans);
}
void Controller::manageRequests(const sc_time &delay)
void Controller::manageRequests(const sc_time& delay)
{
if (transToAcquire.payload != nullptr && transToAcquire.time <= sc_time_stamp())
if (transToAcquire.payload != nullptr && transToAcquire.arrival <= sc_time_stamp())
{
// TODO: here we assume that the scheduler always has space not only for a single burst transaction
// but for a maximum size transaction
@@ -492,8 +497,8 @@ void Controller::manageResponses()
{
if (transToRelease.payload != nullptr)
{
assert(transToRelease.time >= sc_time_stamp());
if (transToRelease.time == sc_time_stamp()) // END_RESP completed
assert(transToRelease.arrival >= sc_time_stamp());
if (transToRelease.arrival == sc_time_stamp()) // END_RESP completed
{
transToRelease.payload->release();
transToRelease.payload = nullptr;
@@ -508,25 +513,25 @@ void Controller::manageResponses()
return; // END_RESP not completed
}
tlm_generic_payload* nextPayloadInRespQueue = respQueue->nextPayload();
if (nextPayloadInRespQueue != nullptr)
tlm_generic_payload* nextTransInRespQueue = respQueue->nextPayload();
if (nextTransInRespQueue != nullptr)
{
numberOfBeatsServed += ControllerExtension::getBurstLength(*nextPayloadInRespQueue);
if (ChildExtension::isChildTrans(*nextPayloadInRespQueue))
numberOfBeatsServed += ControllerExtension::getBurstLength(*nextTransInRespQueue);
if (ChildExtension::isChildTrans(*nextTransInRespQueue))
{
tlm_generic_payload& parentTrans = ChildExtension::getParentTrans(*nextPayloadInRespQueue);
tlm_generic_payload& parentTrans = ChildExtension::getParentTrans(*nextTransInRespQueue);
if (ParentExtension::notifyChildTransCompletion(parentTrans))
{
transToRelease.payload = &parentTrans;
tlm_phase bwPhase = BEGIN_RESP;
sc_time bwDelay;
if (transToRelease.time == sc_time_stamp()) // last payload was released in this cycle
if (transToRelease.arrival == sc_time_stamp()) // last payload was released in this cycle
bwDelay = memSpec.tCK;
else
bwDelay = SC_ZERO_TIME;
sendToFrontend(*transToRelease.payload, bwPhase, bwDelay);
transToRelease.time = sc_max_time();
transToRelease.arrival = sc_max_time();
}
else
{
@@ -537,16 +542,16 @@ void Controller::manageResponses()
}
else
{
transToRelease.payload = nextPayloadInRespQueue;
transToRelease.payload = nextTransInRespQueue;
tlm_phase bwPhase = BEGIN_RESP;
sc_time bwDelay;
if (transToRelease.time == sc_time_stamp()) // last payload was released in this cycle
if (transToRelease.arrival == sc_time_stamp()) // last payload was released in this cycle
bwDelay = memSpec.tCK;
else
bwDelay = SC_ZERO_TIME;
sendToFrontend(*transToRelease.payload, bwPhase, bwDelay);
transToRelease.time = sc_max_time();
transToRelease.arrival = sc_max_time();
}
}
else
@@ -557,19 +562,19 @@ void Controller::manageResponses()
}
}
void Controller::sendToFrontend(tlm_generic_payload& payload, tlm_phase& phase, sc_time& delay)
void Controller::sendToFrontend(tlm_generic_payload& trans, tlm_phase& phase, sc_time& delay)
{
tSocket->nb_transport_bw(payload, phase, delay);
tSocket->nb_transport_bw(trans, phase, delay);
}
Controller::MemoryManager::~MemoryManager()
{
while (!freePayloads.empty())
{
tlm_generic_payload* payload = freePayloads.top();
tlm_generic_payload* trans = freePayloads.top();
freePayloads.pop();
payload->reset();
delete payload;
trans->reset();
delete trans;
}
}
@@ -588,9 +593,9 @@ tlm::tlm_generic_payload& Controller::MemoryManager::allocate()
}
}
void Controller::MemoryManager::free(tlm::tlm_generic_payload* payload)
void Controller::MemoryManager::free(tlm::tlm_generic_payload* trans)
{
freePayloads.push(payload);
freePayloads.push(trans);
}
void Controller::createChildTranses(tlm::tlm_generic_payload& parentTrans)

9
src/libdramsys/DRAMSys/controller/Controller.h
View File

@@ -61,6 +61,7 @@ protected:
sc_core::sc_time& delay) override;
tlm::tlm_sync_enum nb_transport_bw(tlm::tlm_generic_payload& trans, tlm::tlm_phase& phase,
sc_core::sc_time& delay) override;
void b_transport(tlm::tlm_generic_payload& trans, sc_core::sc_time& delay) override;
unsigned int transport_dbg(tlm::tlm_generic_payload& trans) override;
virtual void sendToFrontend(tlm::tlm_generic_payload& trans, tlm::tlm_phase& phase, sc_core::sc_time& delay);
@@ -73,6 +74,8 @@ protected:
const sc_core::sc_time thinkDelayBw;
const sc_core::sc_time phyDelayFw;
const sc_core::sc_time phyDelayBw;
const sc_core::sc_time blockingReadDelay;
const sc_core::sc_time blockingWriteDelay;
private:
unsigned totalNumberOfPayloads = 0;
@@ -90,10 +93,10 @@ private:
const AddressDecoder& addressDecoder;
uint64_t nextChannelPayloadIDToAppend = 1;
struct Transaction
struct PayloadAndArrival
{
tlm::tlm_generic_payload* payload = nullptr;
sc_core::sc_time time = sc_core::sc_max_time();
sc_core::sc_time arrival = sc_core::sc_max_time();
} transToAcquire, transToRelease;
void manageResponses();
@@ -113,7 +116,7 @@ private:
public:
~MemoryManager() override;
tlm::tlm_generic_payload& allocate();
void free(tlm::tlm_generic_payload* payload) override;
void free(tlm::tlm_generic_payload* trans) override;
private:
std::stack<tlm::tlm_generic_payload*> freePayloads;

4
src/libdramsys/DRAMSys/controller/ControllerIF.h
View File

@@ -111,6 +111,7 @@ protected:
{
tSocket.register_nb_transport_fw(this, &ControllerIF::nb_transport_fw);
tSocket.register_transport_dbg(this, &ControllerIF::transport_dbg);
tSocket.register_b_transport(this, &ControllerIF::b_transport);
iSocket.register_nb_transport_bw(this, &ControllerIF::nb_transport_bw);
idleTimeCollector.start();
@@ -120,9 +121,10 @@ protected:
// Virtual transport functions
virtual tlm::tlm_sync_enum nb_transport_fw(tlm::tlm_generic_payload& trans, tlm::tlm_phase& phase,
sc_core::sc_time& delay) = 0;
virtual unsigned int transport_dbg(tlm::tlm_generic_payload& trans) = 0;
virtual tlm::tlm_sync_enum nb_transport_bw(tlm::tlm_generic_payload& trans, tlm::tlm_phase& phase,
sc_core::sc_time& delay) = 0;
virtual void b_transport(tlm::tlm_generic_payload& trans, sc_core::sc_time& delay) = 0;
virtual unsigned int transport_dbg(tlm::tlm_generic_payload& trans) = 0;
// Bandwidth related
class IdleTimeCollector

9
src/libdramsys/DRAMSys/simulation/Arbiter.cpp
View File

@@ -59,6 +59,7 @@ Arbiter::Arbiter(const sc_module_name& name, const Configuration& config,
{
iSocket.register_nb_transport_bw(this, &Arbiter::nb_transport_bw);
tSocket.register_nb_transport_fw(this, &Arbiter::nb_transport_fw);
tSocket.register_b_transport(this, &Arbiter::b_transport);
tSocket.register_transport_dbg(this, &Arbiter::transport_dbg);
}
@@ -161,6 +162,14 @@ tlm_sync_enum Arbiter::nb_transport_bw(int, tlm_generic_payload& payload,
return TLM_ACCEPTED;
}
void Arbiter::b_transport(int, tlm::tlm_generic_payload& trans, sc_core::sc_time& delay)
{
trans.set_address(trans.get_address() - addressOffset);
DecodedAddress decodedAddress = addressDecoder.decodeAddress(trans.get_address());
iSocket[static_cast<int>(decodedAddress.channel)]->b_transport(trans, delay);
}
unsigned int Arbiter::transport_dbg(int /*id*/, tlm::tlm_generic_payload& trans)
{
trans.set_address(trans.get_address() - addressOffset);

1
src/libdramsys/DRAMSys/simulation/Arbiter.h
View File

@@ -86,6 +86,7 @@ protected:
tlm::tlm_phase& phase, sc_core::sc_time& fwDelay);
tlm::tlm_sync_enum nb_transport_bw(int, tlm::tlm_generic_payload& trans,
tlm::tlm_phase& phase, sc_core::sc_time& bwDelay);
void b_transport(int, tlm::tlm_generic_payload& trans, sc_core::sc_time& delay);
unsigned int transport_dbg(int /*id*/, tlm::tlm_generic_payload& trans);
const sc_core::sc_time tCK;

2
src/libdramsys/DRAMSys/simulation/DRAMSys.cpp
View File

@@ -103,7 +103,7 @@ DRAMSys::DRAMSys(const sc_core::sc_module_name& name,
}
}
const Configuration& DRAMSys::getConfig()
const Configuration& DRAMSys::getConfig() const
{
return config;
}

2
src/libdramsys/DRAMSys/simulation/DRAMSys.h
View File

@@ -69,7 +69,7 @@ public:
DRAMSys(const sc_core::sc_module_name& name,
const ::DRAMSys::Config::Configuration& configLib);
const Configuration& getConfig();
const Configuration& getConfig() const;
protected:
DRAMSys(const sc_core::sc_module_name& name,

68
src/libdramsys/DRAMSys/simulation/dram/Dram.cpp
View File

@@ -35,6 +35,7 @@
* Peter Ehses
* Eder F. Zulian
* Felipe S. Prado
* Derek Christ
*/
#include "Dram.h"
@@ -82,12 +83,14 @@ Dram::Dram(const sc_module_name& name, const Configuration& config)
SC_REPORT_FATAL("Dram", "On Windows Storage is not yet supported");
memory = 0; // FIXME
#else
memory = (unsigned char *)mmap(nullptr, channelSize, PROT_READ | PROT_WRITE, MAP_PRIVATE | MAP_ANON | MAP_NORESERVE, -1, 0);
memory = (unsigned char *)mmap(nullptr, channelSize,
PROT_READ | PROT_WRITE, MAP_PRIVATE | MAP_ANON | MAP_NORESERVE, -1, 0);
#endif
}
}
tSocket.register_nb_transport_fw(this, &Dram::nb_transport_fw);
tSocket.register_b_transport(this, &Dram::b_transport);
tSocket.register_transport_dbg(this, &Dram::transport_dbg);
}
@@ -119,15 +122,14 @@ void Dram::reportPower()
#endif
}
tlm_sync_enum Dram::nb_transport_fw(tlm_generic_payload &payload,
tlm_phase &phase, sc_time &delay)
tlm_sync_enum Dram::nb_transport_fw(tlm_generic_payload& trans, tlm_phase& phase, sc_time& delay)
{
assert(phase >= BEGIN_RD && phase <= END_SREF);
#ifdef DRAMPOWER
if (powerAnalysis)
{
int bank = static_cast<int>(ControllerExtension::getBank(payload).ID());
int bank = static_cast<int>(ControllerExtension::getBank(trans).ID());
int64_t cycle = std::lround((sc_time_stamp() + delay) / memSpec.tCK);
DRAMPower->doCommand(phaseToDRAMPowerCommand(phase), bank, cycle);
}
@@ -137,44 +139,39 @@ tlm_sync_enum Dram::nb_transport_fw(tlm_generic_payload &payload,
{
if (phase == BEGIN_RD || phase == BEGIN_RDA)
{
unsigned char *phyAddr = memory + payload.get_address();
memcpy(payload.get_data_ptr(), phyAddr, payload.get_data_length());
unsigned char* phyAddr = memory + trans.get_address();
memcpy(trans.get_data_ptr(), phyAddr, trans.get_data_length());
}
else if (phase == BEGIN_WR || phase == BEGIN_WRA)
{
unsigned char *phyAddr = memory + payload.get_address();
memcpy(phyAddr, payload.get_data_ptr(), payload.get_data_length());
unsigned char* phyAddr = memory + trans.get_address();
memcpy(phyAddr, trans.get_data_ptr(), trans.get_data_length());
}
}
return TLM_ACCEPTED;
}
unsigned int Dram::transport_dbg(tlm_generic_payload &trans)
unsigned int Dram::transport_dbg(tlm_generic_payload& trans)
{
PRINTDEBUGMESSAGE(name(), "transport_dgb");
// TODO: This part is not tested yet, neither with traceplayers nor with GEM5 coupling
if (storeMode == Configuration::StoreMode::NoStorage)
{
SC_REPORT_FATAL("DRAM",
"Debug Transport is used in combination with NoStorage");
SC_REPORT_FATAL("DRAM", "Debug Transport is used in combination with NoStorage");
}
else
{
tlm_command cmd = trans.get_command();
//uint64_t adr = trans.get_address(); // TODO: - offset;
unsigned char *ptr = trans.get_data_ptr();
unsigned int len = trans.get_data_length();
//unsigned int bank = DramExtension::getExtension(trans).getBank().ID();
//cout << "cmd " << (cmd ? "write" : "read") << " adr " << hex << adr << " len " << len << endl;
unsigned char* ptr = trans.get_data_ptr();
unsigned int len = trans.get_data_length();
if (cmd == TLM_READ_COMMAND)
{
if (storeMode == Configuration::StoreMode::Store)
{ // Use Storage
unsigned char *phyAddr = memory + trans.get_address();
{
unsigned char* phyAddr = memory + trans.get_address();
memcpy(ptr, phyAddr, trans.get_data_length());
}
else
@@ -186,8 +183,8 @@ unsigned int Dram::transport_dbg(tlm_generic_payload &trans)
else if (cmd == TLM_WRITE_COMMAND)
{
if (storeMode == Configuration::StoreMode::Store)
{ // Use Storage
unsigned char *phyAddr = memory + trans.get_address();
{
unsigned char* phyAddr = memory + trans.get_address();
memcpy(phyAddr, ptr, trans.get_data_length());
}
else
@@ -200,3 +197,32 @@ unsigned int Dram::transport_dbg(tlm_generic_payload &trans)
}
return 0;
}
void Dram::b_transport(tlm_generic_payload& trans, sc_time& delay)
{
static bool printedWarning = false;
if (!printedWarning)
{
SC_REPORT_WARNING("DRAM", BLOCKING_WARNING.data());
printedWarning = true;
}
if (storeMode == Configuration::StoreMode::Store)
{
if (trans.is_read())
{
unsigned char* phyAddr = memory + trans.get_address();
memcpy(trans.get_data_ptr(), phyAddr, trans.get_data_length());
}
else
{
unsigned char* phyAddr = memory + trans.get_address();
memcpy(phyAddr, trans.get_data_ptr(), trans.get_data_length());
}
}
else if (storeMode != Configuration::StoreMode::NoStorage)
{
SC_REPORT_FATAL("DRAM", "Blocking transport not supported with error model yet.");
}
}

9
src/libdramsys/DRAMSys/simulation/dram/Dram.h
View File

@@ -35,6 +35,7 @@
* Peter Ehses
* Eder F. Zulian
* Felipe S. Prado
* Derek Christ
*/
#ifndef DRAM_H
@@ -68,12 +69,16 @@ protected:
std::unique_ptr<libDRAMPower> DRAMPower;
#endif
virtual tlm::tlm_sync_enum nb_transport_fw(tlm::tlm_generic_payload& payload,
virtual tlm::tlm_sync_enum nb_transport_fw(tlm::tlm_generic_payload& trans,
tlm::tlm_phase& phase, sc_core::sc_time& delay);
virtual void b_transport(tlm::tlm_generic_payload& trans, sc_core::sc_time& delay);
virtual unsigned int transport_dbg(tlm::tlm_generic_payload& trans);
public:
static constexpr std::string_view BLOCKING_WARNING =
"Use the blocking mode of DRAMSys with caution! "
"The simulated timings do not reflect the real system!";
tlm_utils::simple_target_socket<Dram> tSocket;
virtual void reportPower();