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Readme updates.

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This commit is contained in:
Lukas Steiner
2020-05-27 13:59:00 +02:00
parent dcc23198b3
commit d9c12be99b
4 changed files with 79 additions and 216 deletions
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49
DRAMSys/library/resources/configs/amconfigs/congen_extended.json
View File

@@ -1,49 +0,0 @@
{
"CONGEN": {
"BANK_BIT": [
13,
14,
15
],
"BYTE_BIT": [
0,
1,
2
],
"COLUMN_BIT": [
3,
4,
5,
6,
7,
8,
9,
10,
11,
12
],
"ROW_BIT": [
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26,
27,
28,
29
],
"XOR": [
{
"FIRST": 13,
"SECOND": 16
}
]
}
}

98
DRAMSys/library/resources/configs/amconfigs/congen_extended_solution.json
View File

@@ -1,98 +0,0 @@
{
"CONGEN":
{"SOLUTION":[{
"XOR":[
{
"FIRST":13,
"SECOND":16
}
],
"BYTE_BIT": [
0,
1,
2
],
"COLUMN_BIT": [
3,
4,
5,
6,
7,
8,
9,
10,
11,
12
],
"BANK_BIT": [
13,
14,
15
],
"ROW_BIT": [
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26,
27,
28,
29
],
"ID": 0
},
{
"XOR":[
{
"FIRST":13,
"SECOND":16
}
],
"BYTE_BIT": [
0,
1,
2
],
"COLUMN_BIT": [
3,
4,
5,
6,
7,
8,
9,
10,
11,
12
],
"BANK_BIT": [
13,
14,
15
],
"ROW_BIT": [
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26,
27,
28,
29
],
"ID": 1
}]
}
}

4
DRAMSys/library/resources/simulations/ddr3-example.json
View File

@@ -1,10 +1,10 @@
{
"simulation": {
"addressmapping": "congen_extended_solution.json",
"addressmapping": "am_ddr3_8x1Gbx8_dimm_p1KB_rbc.json",
"mcconfig": "fifoStrict.json",
"memspec": "MICRON_1Gb_DDR3-1600_8bit_G.json",
"simconfig": "ddr3.json",
"simulationid": "ddr3-example-all-json",
"simulationid": "ddr3-example",
"thermalconfig": "config.json",
"tracesetup": [
{

144
README.md
View File

@@ -115,12 +115,13 @@ The compilation generates executable binary files **DRAMSys** and
From the build directory use the commands below to execute DRAMSys.
```bash
$ cd simulator
$ ./DRAMSys
```
To run DRAMSys with a specific config:
```bash
$ ./DRAMSys ../DRAMSys/library/resources/simulations/ddr3-example.json
$ ./DRAMSys ../../DRAMSys/library/resources/simulations/ddr3-example.json
```
To run DRAMSys with a specific config and a resource folder somewhere else to the standard:
@@ -128,12 +129,12 @@ To run DRAMSys with a specific config and a resource folder somewhere else to th
$ ./DRAMSys ../../DRAMSys/tests/example_ddr3/simulations/ddr3-example.json ../../DRAMSys/tests/example_ddr3/
```
From the build directory use the commands below to execute the traceAnalyzer.
From the build directory use the commands below to execute the Trace Analyzer.
```bash
$ cd traceAnalyzer
$ export QT_QPA_PLATFORMTHEME=qgnomeplatform
$ ./traceAnalyzer
$ ./TraceAnalyzer
```
### Building on MacOS (Formerly OSX)
@@ -184,11 +185,11 @@ The JSON code below shows a typic configuration:
```json
{
"simulation": {
"simulationid": "ddr3-example2-id",
"simulationid": "ddr3-example",
"simconfig": "ddr3.json",
"thermalconfig": "config.json",
"memspec": "MICRON_1Gb_DDR3-1600_8bit_G.json",
"addressmapping": "congen_extended_solution.json",
"addressmapping": "am_ddr3_8x1Gbx8_dimm_p1KB_brc.json",
"mcconfig":"fifoStrict.json",
"tracesetup": [{
"clkMhz": 300,
@@ -205,7 +206,7 @@ Fields Description
"simconfig": Configuration file for the DRAMSys Simulator
"thermalconfig": Temperature Simulator Configuration File
"memspec": Memory Device Specification File
"addressmapping":Addressmapping Configuration of the Memory Controller File.
"addressmapping": Addressmapping Configuration of the Memory Controller File.
"mcconfig": Memory Controller Configuration File.
"tracesetup": The trace setup is only used in standalone mode.
In library mode e.g. in Platform Architect the trace setup is ignored.
@@ -282,9 +283,7 @@ Below, the sub-configurations are listed and explained.
- **Simulator Configuration**
The content of
[ddr3.json](DRAMSys/library/resources/configs/simulator/ddr3.json) is
presented below as an example.
The content of [ddr3.json](DRAMSys/library/resources/configs/simulator/ddr3.json) is presented below as an example.
```json
{
@@ -311,6 +310,7 @@ Below, the sub-configurations are listed and explained.
```
- *SimulationName* (boolean)
- Give the name of the simulation for distingushing from other simulations.
- *Debug* (boolean)
- true: enables debug output on console
@@ -325,8 +325,10 @@ Below, the sub-configurations are listed and explained.
- true: enables temporal windowing
- false: disables temporal windowing
- *WindowSize* (unisgned int)
- Size of the window in clock cycles used to evaluate average bandwidth and average power consumption
- *NumberOfMemChannels* (unsigned int)
- Number of memory channels
- *ControllerCoreRefDisable* (boolean)
- true: disables refreshes
@@ -341,6 +343,7 @@ Below, the sub-configurations are listed and explained.
- true: enables the simulation progress bar
- false: disables the simulation progress bar
- *NumberOfDevicesOnDIMM* (unsigned int)
- Number of devices on dual inline memory module
- *CheckTLM2Protocol* (boolean)
- true: enables the TLM-2.0 Protocol Checking
@@ -354,9 +357,7 @@ Below, the sub-configurations are listed and explained.
- **Temperature Simulator Configuration**
The content of
[config.json](DRAMSys/library/resources/configs/thermalsim/config.json) is
presented below as an example.
The content of [config.json](DRAMSys/library/resources/configs/thermalsim/config.json) is presented below as an example.
```json
{
@@ -374,14 +375,16 @@ Below, the sub-configurations are listed and explained.
"GeneratePowerMap": true
}
}
```
```
- *TemperatureScale* (string)
- "Celsius"
- "Fahrenheit"
- "Kelvin"
- *StaticTemperatureDefaultValue* (int)
- Temperature value for simulations with static temperature
- *ThermalSimPeriod* (double)
- Period of the thermal simulation
- *ThermalSimUnit* (string)
- "s": seconds
@@ -391,14 +394,19 @@ Below, the sub-configurations are listed and explained.
- "ps": picoseconds
- "fs": femtoseconds
- *PowerInfoFile* (string)
- File containing power related information: devices identifiers, initial power values and power thresholds.
- *IceServerIp* (string)
- 3D-Ice server IP address
- *IceServerPort* (unsigned int)
- 3D-Ice server port
- *SimPeriodAdjustFactor* (unsigned int)
- When substantial changes in power occur (i.e., changes that exceed the thresholds), then the simulation period will be divided by this number causing the thermal simulation to be executed more often.
- *NPowStableCyclesToIncreasePeriod* (unsigned int)
- Wait this number of thermal simulation cycles with power stability (i.e., changes that do not exceed the thresholds) to start increasing the simulation period back to its configured value.
- *GenerateTemperatureMap* (boolean)
- true: generate temperature map files during thermal simulation
@@ -428,42 +436,44 @@ Below, the sub-configurations are listed and explained.
This file format is generated by ConGen.
The format delivers more information than needed for an address mapping.
Unused data:
Optional data (unused):
- "NAME": Name of the trace file which was used by ConGen
- "COSTS": Number of row misses which this configuration produces while playing the trace.
Used data:
- "COSTS": Number of row misses which this configuration produces while playing the trace.
- "CONFIG": Gives you information about the ConGen configuration
Used data:
- "SOLUTION": (OBS.:Different solutions should be added as json objects inside the "SOLUTION" array)
- "ID": Unique identifier for this solution. It is used to specify a certain solution.
- "XOR": Defines an xor connection of a bank and row bit
- "BANK_BIT": Number of an address bit which is connected to a bank bit
- "ROW_BIT": Number of an address bit which is connected to a row bit
- "BYTE_BIT": Address bits that are connected to the byte bits in ascending order
- "COLUMN_BIT": Address bits that are connected to the column bits in ascending order
- "ROW_BIT": Address bits that are connected to the row bits in ascending order
- "BANK_BIT": Address bits that are connected to the bank bits in ascending order
- "BANKGROUP_BIT": Address bits that are connected to the bankgroup bits in ascending order
- "RANK_BIT": Address bits that are connected to the rank bits in ascending order
- "CHANNEL_BIT": Address bits that are connected to the channel bits in ascending order
```json
{
"CONGEN":
{"SOLUTION":[{
"XOR":[
{
"FIRST":13,
"SECOND":16
}
],
"BYTE_BIT": [
0,1,2
],
"COLUMN_BIT": [
3,4,5,6,7,8,9,10,11,12
],
"BANK_BIT": [
13,14,15
],
"ROW_BIT": [
16,17,18,19,20,21,22,23,24,25,26,27,28,29
],
"ID": 0
}]
"CONGEN": {
"SOLUTION": [
{
"ID": 0,
"XOR": [
{
"FIRST": 13,
"SECOND": 16
}
],
"BYTE_BIT": [0,1,2],
"COLUMN_BIT": [3,4,5,6,7,8,9,10,11,12],
"BANK_BIT": [13,14,15],
"ROW_BIT": [16,17,18,19,20,21,22,23,24,25,26,27,28,29]
}
]
}
}
@@ -476,21 +486,21 @@ Below, the sub-configurations are listed and explained.
```json
{
"mcconfig": {
"PagePolicy": "Open",
"Scheduler": "Fifo",
"RequestBufferSize": 8,
"CmdMux": "Oldest",
"RespQueue": "Fifo",
"RefreshPolicy": "Rankwise",
"RefreshMode": 1,
"RefreshMaxPostponed": 8,
"RefreshMaxPulledin": 8,
"PowerDownPolicy": "NoPowerDown",
"PowerDownTimeout": 100
"mcconfig": {
"PagePolicy": "Open",
"Scheduler": "Fifo",
"RequestBufferSize": 8,
"CmdMux": "Oldest",
"RespQueue": "Fifo",
"RefreshPolicy": "Rankwise",
"RefreshMode": 1,
"RefreshMaxPostponed": 8,
"RefreshMaxPulledin": 8,
"PowerDownPolicy": "NoPowerDown",
"PowerDownTimeout": 100
}
}
```
```
- *BankwiseLogic* (boolean)
- true: perform bankwise-refresh [3] and bankwise-powerdown [4]
@@ -1474,24 +1484,24 @@ The simconfig should be changed in order to support storage and address offsets:
``` json
{
"simconfig": {
"CheckTLM2Protocol": "0",
"DatabaseRecording": "1",
"Debug": "0",
"CheckTLM2Protocol": false,
"DatabaseRecording": true,
"Debug": false,
"ECCControllerMode": "Disabled",
"EnableWindowing": "0",
"EnableWindowing": false,
"ErrorCSVFile": "",
"ErrorChipSeed": "42",
"NumberOfDevicesOnDIMM": "8",
"NumberOfMemChannels": "1",
"PowerAnalysis": "0",
"ErrorChipSeed": 42,
"NumberOfDevicesOnDIMM": 8,
"NumberOfMemChannels": 1,
"PowerAnalysis": false,
"SimulationName": "ddr3",
"SimulationProgressBar": "1",
"ThermalSimulation": "0",
"WindowSize": "1000"
"SimulationProgressBar": true,
"ThermalSimulation": false,
"WindowSize": 1000,
"StoreMode": "Store",
"AddressOffset": "2147483648",
"UseMalloc": "1",
"AddressOffset": 2147483648,
"UseMalloc": true
}
}
```