derek/DRAMSys
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

polished ddr3 example for the DRAMSys Workshop

Browse Source
This commit is contained in:
Matthias Jung
2016-10-18 22:53:11 +02:00
parent 2f0f26900b
commit d5496c5caa
1 changed files with 14 additions and 3 deletions
Download Patch File Download Diff File Expand all files Collapse all files

17
DRAMSys/simulator/resources/simulations/ddr3-example.xml
View File

@@ -5,7 +5,7 @@
<DatabaseRecording value="1" />
<PowerAnalysis value="1" />
<EnableWindowing value = "1" />
<WindowSize value="1000" />
<WindowSize value="100" />
<NumberOfTracePlayers value="1"/>
<NumberOfMemChannels value="1"/>
<ControllerCoreDisableRefresh value="0"/>
@@ -29,21 +29,32 @@
<GeneratePowerMap value="1" />
</thermalsimconfig>
<!-- Memory Device Specification: Which Device is on our simulated DDR3 DIMM -->
<memspecs>
<memspec src="../../DRAMSys/simulator/resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G.xml"></memspec>
</memspecs>
<!-- Addressmapping Configuration of the Memory Controller -->
<addressmappings>
<addressmapping src="../../DRAMSys/simulator/resources/configs/amconfigs/am_ddr3.xml"></addressmapping>
<addressmapping src="../../DRAMSys/simulator/resources/configs/amconfigs/am_ddr3_8x1Gbx8_dimm_p1KB.xml"></addressmapping>
</addressmappings>
<!-- Memory Controller Configuration -->
<memconfigs>
<!-- Without Scheduler FIFO -->
<memconfig src="../../DRAMSys/simulator/resources/configs/memconfigs/fifoStrict.xml"/>
<!-- With FR-FCFS Scheduler -->
<!--<memconfig src="../../DRAMSys/simulator/resources/configs/memconfigs/fr_fcfs.xml"/>-->
</memconfigs>
<tracesetups>
<tracesetup id="fifo">
<device clkMhz="200">chstone-adpcm_32.stl</device>
<!--
This device mimics an image processing application
running on an FPGA with 200 Mhz.
-->
<device clkMhz="200">ddr3_example.stl</device>
</tracesetup>
</tracesetups>