Added DDR3 generated dependencies.

2022-03-03 10:26:47 +01:00
parent b2581bbce3
commit d0ecbb7835
5 changed files with 416 additions and 1 deletions
--- a/DRAMSys/traceAnalyzer/CMakeLists.txt
+++ b/DRAMSys/traceAnalyzer/CMakeLists.txt
@@ -122,6 +122,7 @@ add_executable(TraceAnalyzer
    
    businessObjects/dramTimeDependencies/dbEntries/specialized/DDR3dbphaseentry.cpp
    businessObjects/dramTimeDependencies/deviceDependencies/specialized/DDR3TimeDependencies.cpp
+    businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoDDR3.cpp
    businessObjects/dramTimeDependencies/configurations/specialized/DDR3Configuration.cpp

    businessObjects/dramTimeDependencies/phasedependenciestracker.cpp
--- a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/DDR3Configuration.cpp
+++ b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/DDR3Configuration.cpp
@@ -2,7 +2,8 @@
 #include "DDR3Configuration.h"

 DDR3Configuration::DDR3Configuration(const TraceDB& tdb) {
-    mDeviceDeps = std::make_shared<DDR3TimeDependencies>(std::forward<const QJsonObject>(mGetMemspec(tdb)), mGetClk(tdb));
+    // mDeviceDeps = std::make_shared<DDR3TimeDependencies>(std::forward<const QJsonObject>(mGetMemspec(tdb)), mGetClk(tdb));
+    mDeviceDeps = std::make_shared<TimeDependenciesInfoDDR3>(std::forward<const QJsonObject>(mGetMemspec(tdb)), mGetClk(tdb));

 }

--- a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/DDR3Configuration.h
+++ b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/DDR3Configuration.h
@@ -3,6 +3,7 @@

 #include "businessObjects/dramTimeDependencies/configurations/configurationIF.h"
 #include "businessObjects/dramTimeDependencies/deviceDependencies/specialized/DDR3TimeDependencies.h"
+#include "businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoDDR3.h"
 #include "businessObjects/dramTimeDependencies/dbEntries/specialized/DDR3dbphaseentry.h"

 class DDR3Configuration : public ConfigurationIF {
--- a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoDDR3.cpp
+++ b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoDDR3.cpp
@@ -0,0 +1,354 @@
+/* Generated by JetBrains MPS */
+
+#include "TimeDependenciesInfoDDR3.h"
+
+using namespace std;
+
+TimeDependenciesInfoDDR3::TimeDependenciesInfoDDR3(const QJsonObject& memspec, const uint tCK) : DRAMTimeDependenciesIF(memspec, tCK) {
+  mInitializeValues();
+}
+
+void TimeDependenciesInfoDDR3::mInitializeValues() {
+  burstLength = mMemspecJson["memarchitecturespec"].toObject()["burstLength"].toInt();
+  dataRate = mMemspecJson["memarchitecturespec"].toObject()["dataRate"].toInt();
+
+  mPools.insert({
+    "CMD_BUS", {
+      1, {
+        "ACT",
+        "RD",
+        "WR",
+        "PREPB",
+        "RDA",
+        "WRA",
+        "REFAB",
+        "PREAB",
+        "PDEP",
+        "PDXP",
+        "SREFEN",
+        "SREFEX",
+        "PDEA",
+        "PDXA",
+      }
+    }
+  });
+
+  mPools.insert({
+    "NAW", {
+      4, {
+        "ACT",
+      }
+    }
+  });
+
+  tCCD = tCK * mMemspecJson["memtimingspec"].toObject()["CCD"].toInt();
+  tRCD = tCK * mMemspecJson["memtimingspec"].toObject()["RCD"].toInt();
+  tRP = tCK * mMemspecJson["memtimingspec"].toObject()["RP"].toInt();
+  tRAS = tCK * mMemspecJson["memtimingspec"].toObject()["RAS"].toInt();
+  tCL = tCK * mMemspecJson["memtimingspec"].toObject()["CL"].toInt();
+  tCWL = tCK * mMemspecJson["memtimingspec"].toObject()["CWL"].toInt();
+  tAL = tCK * mMemspecJson["memtimingspec"].toObject()["AL"].toInt();
+  tRL = tCK * mMemspecJson["memtimingspec"].toObject()["RL"].toInt();
+  tWL = tCK * mMemspecJson["memtimingspec"].toObject()["WL"].toInt();
+  tRTP = tCK * mMemspecJson["memtimingspec"].toObject()["RTP"].toInt();
+  tWTR = tCK * mMemspecJson["memtimingspec"].toObject()["WTR"].toInt();
+  tRRD = tCK * mMemspecJson["memtimingspec"].toObject()["RRD"].toInt();
+  tWR = tCK * mMemspecJson["memtimingspec"].toObject()["WR"].toInt();
+  tFAW = tCK * mMemspecJson["memtimingspec"].toObject()["FAW"].toInt();
+  tRFC = tCK * mMemspecJson["memtimingspec"].toObject()["RFC"].toInt();
+  tRC = tCK * mMemspecJson["memtimingspec"].toObject()["RC"].toInt();
+  tXP = tCK * mMemspecJson["memtimingspec"].toObject()["XP"].toInt();
+  tXS = tCK * mMemspecJson["memtimingspec"].toObject()["XS"].toInt();
+  tXSDLL = tCK * mMemspecJson["memtimingspec"].toObject()["XSDLL"].toInt();
+  tCKE = tCK * mMemspecJson["memtimingspec"].toObject()["CKE"].toInt();
+  tCKESR = tCK * mMemspecJson["memtimingspec"].toObject()["CKESR"].toInt();
+  tREFPDEN = tCK * mMemspecJson["memtimingspec"].toObject()["REFPDEN"].toInt();
+  tACTPDEN = tCK * mMemspecJson["memtimingspec"].toObject()["ACTPDEN"].toInt();
+  tPRPDEN = tCK * mMemspecJson["memtimingspec"].toObject()["PRPDEN"].toInt();
+  tRTRS = tCK * mMemspecJson["memtimingspec"].toObject()["RTRS"].toInt();
+
+  tPD = tCKE;
+
+  tBURST = (uint) (burstLength / (float) dataRate) * tCK;
+  tRDWR = tRL + tBURST + 2 * tCK - tWL;
+  tRDWR_R = tRL + tBURST + tRTRS - tWL;
+  tWRRD = tWL + tBURST + tWTR - tAL;
+  tWRPRE = tWL + tBURST + tWR;
+  tWRRD_R = tWL + tBURST + tRTRS - tRL;
+  tRDPDEN = tRL + tBURST + tCK;
+  tWRPDEN = tWL + tBURST + tWR;
+  tWRAPDEN = tWL + tBURST + tWR + tCK;
+
+}
+
+const std::vector<QString> TimeDependenciesInfoDDR3::getPossiblePhases() {
+  return {
+    "ACT",
+    "RD",
+    "WR",
+    "PREPB",
+    "RDA",
+    "WRA",
+    "REFAB",
+    "PREAB",
+    "PDEP",
+    "PDXP",
+    "SREFEN",
+    "SREFEX",
+    "PDEA",
+    "PDXA",
+  };
+}
+
+DependencyMap TimeDependenciesInfoDDR3::mSpecializedGetDependencies() const {
+  DependencyMap dmap;
+
+  dmap.emplace(
+    piecewise_construct,
+    forward_as_tuple("ACT"),
+    forward_as_tuple(
+      initializer_list<TimeDependency>{
+        {tRC, "ACT", DependencyType::IntraBank, "tRC"},
+        {tRRD, "ACT", DependencyType::IntraRank, "tRRD"},
+        {tAL + tRTP + tRP, "RDA", DependencyType::IntraBank, "tAL + tRTP + tRP"},
+        {tWRPRE + tRP, "WRA", DependencyType::IntraBank, "tWRPRE + tRP"},
+        {tRP, "PREPB", DependencyType::IntraBank, "tRP"},
+        {tRP, "PREAB", DependencyType::IntraRank, "tRP"},
+        {tXP, "PDXA", DependencyType::IntraRank, "tXP"},
+        {tXP, "PDXP", DependencyType::IntraRank, "tXP"},
+        {tRFC, "REFAB", DependencyType::IntraRank, "tRFC"},
+        {tXS, "SREFEX", DependencyType::IntraRank, "tXS"},
+        {tCK, "CMD_BUS", DependencyType::InterRank, "CommandBus"},
+        {tFAW, "NAW", DependencyType::IntraRank, "tFAW"},
+      }
+    )
+  );
+
+  dmap.emplace(
+    piecewise_construct,
+    forward_as_tuple("RD"),
+    forward_as_tuple(
+      initializer_list<TimeDependency>{
+        {tRCD - tAL, "ACT", DependencyType::IntraBank, "tRCD - tAL"},
+        {tCCD, "RD", DependencyType::IntraBank, "tCCD"},
+        {tCCD, "RD", DependencyType::IntraRank, "tCCD"},
+        {tBURST + tRTRS, "RD", DependencyType::InterRank, "tBURST + tRTRS"},
+        {tCCD, "RDA", DependencyType::IntraRank, "tCCD"},
+        {tBURST + tRTRS, "RDA", DependencyType::InterRank, "tBURST + tRTRS"},
+        {tWRRD, "WR", DependencyType::IntraBank, "tWRRD"},
+        {tWRRD, "WR", DependencyType::IntraRank, "tWRRD"},
+        {tWRRD_R, "WR", DependencyType::InterRank, "tWRRD_R"},
+        {tWRRD, "WRA", DependencyType::IntraRank, "tWRRD"},
+        {tWRRD_R, "WRA", DependencyType::InterRank, "tWRRD_R"},
+        {tXP, "PDXA", DependencyType::IntraRank, "tXP"},
+        {tXSDLL, "SREFEX", DependencyType::IntraRank, "tXSDLL"},
+        {tCK, "CMD_BUS", DependencyType::InterRank, "CommandBus"},
+      }
+    )
+  );
+
+  dmap.emplace(
+    piecewise_construct,
+    forward_as_tuple("WR"),
+    forward_as_tuple(
+      initializer_list<TimeDependency>{
+        {tRCD - tAL, "ACT", DependencyType::IntraBank, "tRCD - tAL"},
+        {tRDWR, "RD", DependencyType::IntraBank, "tRDWR"},
+        {tRDWR, "RD", DependencyType::IntraRank, "tRDWR"},
+        {tRDWR_R, "RD", DependencyType::InterRank, "tRDWR_R"},
+        {tRDWR, "RDA", DependencyType::IntraRank, "tRDWR"},
+        {tRDWR_R, "RDA", DependencyType::InterRank, "tRDWR_R"},
+        {tCCD, "WR", DependencyType::IntraBank, "tCCD"},
+        {tCCD, "WR", DependencyType::IntraRank, "tCCD"},
+        {tBURST + tRTRS, "WR", DependencyType::InterRank, "tBURST + tRTRS"},
+        {tCCD, "WRA", DependencyType::IntraRank, "tCCD"},
+        {tBURST + tRTRS, "WRA", DependencyType::InterRank, "tBURST + tRTRS"},
+        {tXP, "PDXA", DependencyType::IntraRank, "tXP"},
+        {tXSDLL, "SREFEX", DependencyType::IntraRank, "tXSDLL"},
+        {tCK, "CMD_BUS", DependencyType::InterRank, "CommandBus"},
+      }
+    )
+  );
+
+  dmap.emplace(
+    piecewise_construct,
+    forward_as_tuple("PREPB"),
+    forward_as_tuple(
+      initializer_list<TimeDependency>{
+        {tRAS, "ACT", DependencyType::IntraBank, "tRAS"},
+        {tAL + tRTP, "RD", DependencyType::IntraBank, "tAL + tRTP"},
+        {tWRPRE, "WR", DependencyType::IntraBank, "tWRPRE"},
+        {tXP, "PDXA", DependencyType::IntraRank, "tXP"},
+        {tCK, "CMD_BUS", DependencyType::InterRank, "CommandBus"},
+      }
+    )
+  );
+
+  dmap.emplace(
+    piecewise_construct,
+    forward_as_tuple("RDA"),
+    forward_as_tuple(
+      initializer_list<TimeDependency>{
+        {tRCD - tAL, "ACT", DependencyType::IntraBank, "tRCD - tAL"},
+        {tCCD, "RD", DependencyType::IntraBank, "tCCD"},
+        {tCCD, "RD", DependencyType::IntraRank, "tCCD"},
+        {tBURST + tRTRS, "RD", DependencyType::InterRank, "tBURST + tRTRS"},
+        {tCCD, "RDA", DependencyType::IntraRank, "tCCD"},
+        {tBURST + tRTRS, "RDA", DependencyType::InterRank, "tBURST + tRTRS"},
+        {max({tWRRD, tWRPRE - tRTP - tAL}), "WR", DependencyType::IntraBank, "max(tWRRD, tWRPRE - tRTP - tAL)"},
+        {tWRRD, "WR", DependencyType::IntraRank, "tWRRD"},
+        {tWRRD_R, "WR", DependencyType::InterRank, "tWRRD_R"},
+        {tWRRD, "WRA", DependencyType::IntraRank, "tWRRD"},
+        {tWRRD_R, "WRA", DependencyType::InterRank, "tWRRD_R"},
+        {tXP, "PDXA", DependencyType::IntraRank, "tXP"},
+        {tXSDLL, "SREFEX", DependencyType::IntraRank, "tXSDLL"},
+        {tCK, "CMD_BUS", DependencyType::InterRank, "CommandBus"},
+      }
+    )
+  );
+
+  dmap.emplace(
+    piecewise_construct,
+    forward_as_tuple("WRA"),
+    forward_as_tuple(
+      initializer_list<TimeDependency>{
+        {tRCD - tAL, "ACT", DependencyType::IntraBank, "tRCD - tAL"},
+        {tRDWR, "RD", DependencyType::IntraBank, "tRDWR"},
+        {tRDWR, "RD", DependencyType::IntraRank, "tRDWR"},
+        {tRDWR_R, "RD", DependencyType::InterRank, "tRDWR_R"},
+        {tRDWR, "RDA", DependencyType::IntraRank, "tRDWR"},
+        {tRDWR_R, "RDA", DependencyType::InterRank, "tRDWR_R"},
+        {tCCD, "WR", DependencyType::IntraBank, "tCCD"},
+        {tCCD, "WR", DependencyType::IntraRank, "tCCD"},
+        {tBURST + tRTRS, "WR", DependencyType::InterRank, "tBURST + tRTRS"},
+        {tCCD, "WRA", DependencyType::IntraRank, "tCCD"},
+        {tBURST + tRTRS, "WRA", DependencyType::InterRank, "tBURST + tRTRS"},
+        {tXP, "PDXA", DependencyType::IntraRank, "tXP"},
+        {tXSDLL, "SREFEX", DependencyType::IntraRank, "tXSDLL"},
+        {tCK, "CMD_BUS", DependencyType::InterRank, "CommandBus"},
+      }
+    )
+  );
+
+  dmap.emplace(
+    piecewise_construct,
+    forward_as_tuple("REFAB"),
+    forward_as_tuple(
+      initializer_list<TimeDependency>{
+        {tRC, "ACT", DependencyType::IntraRank, "tRC"},
+        {tAL + tRTP + tRP, "RDA", DependencyType::IntraRank, "tAL + tRTP + tRP"},
+        {tWRPRE + tRP, "WRA", DependencyType::IntraRank, "tWRPRE + tRP"},
+        {tRP, "PREPB", DependencyType::IntraRank, "tRP"},
+        {tRP, "PREAB", DependencyType::IntraRank, "tRP"},
+        {tXP, "PDXP", DependencyType::IntraRank, "tXP"},
+        {tRFC, "REFAB", DependencyType::IntraRank, "tRFC"},
+        {tXS, "SREFEX", DependencyType::IntraRank, "tXS"},
+        {tCK, "CMD_BUS", DependencyType::InterRank, "CommandBus"},
+      }
+    )
+  );
+
+  dmap.emplace(
+    piecewise_construct,
+    forward_as_tuple("PREAB"),
+    forward_as_tuple(
+      initializer_list<TimeDependency>{
+        {tRAS, "ACT", DependencyType::IntraRank, "tRAS"},
+        {tAL + tRTP, "RD", DependencyType::IntraRank, "tAL + tRTP"},
+        {tAL + tRTP, "RDA", DependencyType::IntraRank, "tAL + tRTP"},
+        {tWRPRE, "WR", DependencyType::IntraRank, "tWRPRE"},
+        {tWRPRE, "WRA", DependencyType::IntraRank, "tWRPRE"},
+        {tXP, "PDXA", DependencyType::IntraRank, "tXP"},
+        {tCK, "CMD_BUS", DependencyType::InterRank, "CommandBus"},
+      }
+    )
+  );
+
+  dmap.emplace(
+    piecewise_construct,
+    forward_as_tuple("PDEP"),
+    forward_as_tuple(
+      initializer_list<TimeDependency>{
+        {tRDPDEN, "RD", DependencyType::IntraRank, "tRDPDEN"},
+        {tRDPDEN, "RDA", DependencyType::IntraRank, "tRDPDEN"},
+        {tWRAPDEN, "WRA", DependencyType::IntraRank, "tWRAPDEN"},
+        {tPRPDEN, "PREPB", DependencyType::IntraRank, "tPRPDEN"},
+        {tPRPDEN, "PREAB", DependencyType::IntraRank, "tPRPDEN"},
+        {tCKE, "PDXP", DependencyType::IntraRank, "tCKE"},
+        {tREFPDEN, "REFAB", DependencyType::IntraRank, "tREFPDEN"},
+        {tXS, "SREFEX", DependencyType::IntraRank, "tXS"},
+        {tCK, "CMD_BUS", DependencyType::InterRank, "CommandBus"},
+      }
+    )
+  );
+
+  dmap.emplace(
+    piecewise_construct,
+    forward_as_tuple("PDXP"),
+    forward_as_tuple(
+      initializer_list<TimeDependency>{
+        {tPD, "PDEP", DependencyType::IntraRank, "tPD"},
+        {tCK, "CMD_BUS", DependencyType::InterRank, "CommandBus"},
+      }
+    )
+  );
+
+  dmap.emplace(
+    piecewise_construct,
+    forward_as_tuple("SREFEN"),
+    forward_as_tuple(
+      initializer_list<TimeDependency>{
+        {tRC, "ACT", DependencyType::IntraRank, "tRC"},
+        {max({tRDPDEN, tAL + tRTP + tRP}), "RDA", DependencyType::IntraRank, "max(tRDPDEN, tAL + tRTP + tRP)"},
+        {max({tWRAPDEN, tWRPRE + tRP}), "WRA", DependencyType::IntraRank, "max(tWRAPDEN, tWRPRE + tRP)"},
+        {tRP, "PREPB", DependencyType::IntraRank, "tRP"},
+        {tRP, "PREAB", DependencyType::IntraRank, "tRP"},
+        {tXP, "PDXP", DependencyType::IntraRank, "tXP"},
+        {tRFC, "REFAB", DependencyType::IntraRank, "tRFC"},
+        {tXS, "SREFEX", DependencyType::IntraRank, "tXS"},
+        {tCK, "CMD_BUS", DependencyType::InterRank, "CommandBus"},
+      }
+    )
+  );
+
+  dmap.emplace(
+    piecewise_construct,
+    forward_as_tuple("SREFEX"),
+    forward_as_tuple(
+      initializer_list<TimeDependency>{
+        {tCKESR, "SREFEN", DependencyType::IntraRank, "tCKESR"},
+        {tCK, "CMD_BUS", DependencyType::InterRank, "CommandBus"},
+      }
+    )
+  );
+
+  dmap.emplace(
+    piecewise_construct,
+    forward_as_tuple("PDEA"),
+    forward_as_tuple(
+      initializer_list<TimeDependency>{
+        {tACTPDEN, "ACT", DependencyType::IntraRank, "tACTPDEN"},
+        {tRDPDEN, "RD", DependencyType::IntraRank, "tRDPDEN"},
+        {tRDPDEN, "RDA", DependencyType::IntraRank, "tRDPDEN"},
+        {tWRPDEN, "WR", DependencyType::IntraRank, "tWRPDEN"},
+        {tWRAPDEN, "WRA", DependencyType::IntraRank, "tWRAPDEN"},
+        {tPRPDEN, "PREPB", DependencyType::IntraRank, "tPRPDEN"},
+        {tCKE, "PDXA", DependencyType::IntraRank, "tCKE"},
+        {tCK, "CMD_BUS", DependencyType::InterRank, "CommandBus"},
+      }
+    )
+  );
+
+  dmap.emplace(
+    piecewise_construct,
+    forward_as_tuple("PDXA"),
+    forward_as_tuple(
+      initializer_list<TimeDependency>{
+        {tPD, "PDEA", DependencyType::IntraRank, "tPD"},
+        {tCK, "CMD_BUS", DependencyType::InterRank, "CommandBus"},
+      }
+    )
+  );
+
+  return dmap;
+}
--- a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoDDR3.h
+++ b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoDDR3.h
@@ -0,0 +1,58 @@
+/* Generated by JetBrains MPS */
+
+#pragma once
+
+#include "../dramtimedependenciesIF.h"
+
+class TimeDependenciesInfoDDR3 final : public DRAMTimeDependenciesIF {
+  public:
+    TimeDependenciesInfoDDR3(const QJsonObject& memspec, const uint clk);
+
+    static const std::vector<QString> getPossiblePhases();
+
+  protected:
+    void mInitializeValues() override;
+    DependencyMap mSpecializedGetDependencies() const override;
+
+  protected:
+    uint burstLength;
+    uint dataRate;
+
+    uint tCCD;
+    uint tRCD;
+    uint tRP;
+    uint tRAS;
+    uint tCL;
+    uint tCWL;
+    uint tAL;
+    uint tRL;
+    uint tWL;
+    uint tRTP;
+    uint tWTR;
+    uint tRRD;
+    uint tWR;
+    uint tFAW;
+    uint tRFC;
+    uint tRC;
+    uint tXP;
+    uint tXS;
+    uint tXSDLL;
+    uint tCKE;
+    uint tCKESR;
+    uint tPD;
+    uint tREFPDEN;
+    uint tACTPDEN;
+    uint tPRPDEN;
+    uint tRTRS;
+
+    uint tBURST;
+    uint tRDWR;
+    uint tRDWR_R;
+    uint tWRRD;
+    uint tWRPRE;
+    uint tWRRD_R;
+    uint tRDPDEN;
+    uint tWRPDEN;
+    uint tWRAPDEN;
+
+};