Port to the new Json configuration library
The DRAMSysLibrary and the Simulator were now ported to support the new configuration library.
This commit is contained in:
@@ -322,5 +322,5 @@ endif()
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target_link_libraries(DRAMSysLibrary
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PUBLIC ${SYSTEMC_LIBRARY}
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PRIVATE DRAMPower
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PRIVATE DRAMSysConfiguration
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PUBLIC DRAMSysConfiguration
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)
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@@ -348,14 +348,8 @@ void TlmRecorder::insertGeneralInfo()
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sqlite3_bind_int64(insertGeneralInfoStatement, 6, static_cast<int64_t>(Configuration::getInstance().memSpec->tCK.value()));
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sqlite3_bind_text(insertGeneralInfoStatement, 7, "PS", 2, nullptr);
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std::fstream mcconfig_stream, memspec_stream;
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mcconfig_stream.open(mcconfig, std::ios::in);
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memspec_stream.open(memspec, std::ios::in);
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std::string mcconfig_dump((std::istreambuf_iterator<char>(mcconfig_stream)), (std::istreambuf_iterator<char>()));
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std::string memspec_dump((std::istreambuf_iterator<char>(memspec_stream)), (std::istreambuf_iterator<char>()));
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sqlite3_bind_text(insertGeneralInfoStatement, 8, mcconfig_dump.c_str(), static_cast<int>(mcconfig_dump.length()), nullptr);
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sqlite3_bind_text(insertGeneralInfoStatement, 9, memspec_dump.c_str(), static_cast<int>(memspec_dump.length()), nullptr);
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sqlite3_bind_text(insertGeneralInfoStatement, 8, mcconfig.c_str(), static_cast<int>(mcconfig.length()), nullptr);
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sqlite3_bind_text(insertGeneralInfoStatement, 9, memspec.c_str(), static_cast<int>(memspec.length()), nullptr);
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sqlite3_bind_text(insertGeneralInfoStatement, 10, traces.c_str(), static_cast<int>(traces.length()), nullptr);
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if (Configuration::getInstance().enableWindowing)
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sqlite3_bind_int64(insertGeneralInfoStatement, 11, static_cast<int64_t>((Configuration::getInstance().memSpec->tCK
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@@ -52,6 +52,7 @@ void to_json(json &j, const AddressMapping &m)
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{"CHANNEL_BIT", m.channelBits},
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{"BYTE_BIT", m.byteBits},
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{"BANKGROUP_BIT", m.bankGroupBits},
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{"RANK_BIT", m.rankBits},
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{"XOR", m.xorBits}};
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j["CONGEN"] = congen;
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@@ -71,6 +72,9 @@ void from_json(const json &j, AddressMapping &m)
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congen.at("BANK_BIT").get_to(m.bankBits);
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congen.at("ROW_BIT").get_to(m.rowBits);
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if (congen.contains("RANK_BIT"))
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congen.at("RANK_BIT").get_to(m.rankBits);
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if (congen.contains("CHANNEL_BIT"))
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congen.at("CHANNEL_BIT").get_to(m.channelBits);
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@@ -64,6 +64,7 @@ struct AddressMapping
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Optional<std::unordered_set<unsigned int>> bankGroupBits;
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std::unordered_set<unsigned int> rowBits;
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Optional<std::unordered_set<unsigned int>> channelBits;
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Optional<std::unordered_set<unsigned int>> rankBits;
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Optional<std::vector<XorPair>> xorBits;
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};
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@@ -55,7 +55,7 @@ add_library(DRAMSysConfiguration STATIC
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util.cpp
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)
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target_compile_definitions(DRAMSysConfiguration PRIVATE DRAMSysResourceDirectory="${CMAKE_SOURCE_DIR}/library/resources")
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target_compile_definitions(DRAMSysConfiguration PUBLIC DRAMSysResourceDirectory="${CMAKE_SOURCE_DIR}/library/resources")
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target_include_directories(DRAMSysConfiguration PUBLIC ${CMAKE_CURRENT_SOURCE_DIR})
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@@ -35,11 +35,14 @@
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#include "Configuration.h"
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#include <exception>
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#include <fstream>
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namespace DRAMSysConfiguration
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{
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std::string Configuration::resourceDirectory;
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void to_json(json &j, const Configuration &c)
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{
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j = json{{"addressmapping", c.addressMapping}, {"mcconfig", c.mcConfig}, {"memspec", c.memSpec},
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@@ -64,11 +67,21 @@ void from_json(const json &j, Configuration &c)
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j.at("tracesetup").get_to(c.traceSetup);
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}
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Configuration from_path(const std::string &path)
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Configuration from_path(const std::string &path, const std::string &resourceDirectory)
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{
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Configuration::resourceDirectory = resourceDirectory;
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std::ifstream file(path);
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json simulation = json::parse(file).at("simulation");
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return simulation.get<DRAMSysConfiguration::Configuration>();
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if (file.is_open())
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{
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json simulation = json::parse(file).at("simulation");
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return simulation.get<DRAMSysConfiguration::Configuration>();
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}
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else
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{
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throw std::runtime_error("Failed to open file " + path);
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}
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}
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} // namespace DRAMSysConfiguration
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@@ -71,12 +71,14 @@ struct Configuration
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std::string simulationId;
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Optional<ThermalConfig> thermalConfig;
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Optional<TraceSetup> traceSetup;
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static std::string resourceDirectory;
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};
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void to_json(json &j, const Configuration &p);
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void from_json(const json &j, Configuration &p);
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Configuration from_path(const std::string &path);
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Configuration from_path(const std::string &path, const std::string &resourceDirectory = DRAMSysResourceDirectory);
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} // namespace DRAMSysConfiguration
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@@ -111,4 +111,9 @@ void from_json(const json &j, McConfig &c)
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invalidateEnum(c.arbiter);
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}
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std::string dump(const McConfig &c)
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{
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return json{c}.dump();
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}
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} // namespace DRAMSysConfiguration
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@@ -117,6 +117,7 @@ enum class RefreshPolicy
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NoRefresh,
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AllBank,
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PerBank,
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Per2Bank,
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SameBank,
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Invalid = -1
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};
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@@ -124,6 +125,7 @@ enum class RefreshPolicy
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NLOHMANN_JSON_SERIALIZE_ENUM(RefreshPolicy, {{RefreshPolicy::Invalid, nullptr},
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{RefreshPolicy::AllBank, "AllBank"},
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{RefreshPolicy::PerBank, "PerBank"},
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{RefreshPolicy::Per2Bank, "Per2Bank"},
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{RefreshPolicy::SameBank, "SameBank"}})
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enum class PowerDownPolicy
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@@ -170,6 +172,8 @@ struct McConfig
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void to_json(json &j, const McConfig &c);
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void from_json(const json &j, McConfig &c);
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std::string dump(const McConfig &c);
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} // namespace Configuration
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#endif // MCCONFIG_H
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@@ -84,20 +84,25 @@ void from_json(const json &j, DramDieChannel &c)
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void to_json(json &j, const PowerInfo &c)
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{
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j = json{{"dram_die_channel0", c.channel0},
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{"dram_die_channel1", c.channel1},
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{"dram_die_channel2", c.channel2},
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{"dram_die_channel3", c.channel3}};
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j = json{};
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for (const auto &channel : c.channels)
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{
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j.emplace(channel.identifier, channel);
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}
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}
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void from_json(const json &j, PowerInfo &c)
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{
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json j_powerinfo = get_config_json(j, thermalConfigPath, "powerInfo");
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j_powerinfo.at("dram_die_channel0").get_to(c.channel0);
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j_powerinfo.at("dram_die_channel1").get_to(c.channel1);
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j_powerinfo.at("dram_die_channel2").get_to(c.channel2);
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j_powerinfo.at("dram_die_channel3").get_to(c.channel3);
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for (const auto &entry : j_powerinfo.items())
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{
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DramDieChannel channel;
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j_powerinfo.at(entry.key()).get_to(channel);
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c.channels.push_back(channel);
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}
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}
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} // namespace DRAMSysConfiguration
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@@ -78,6 +78,7 @@ NLOHMANN_JSON_SERIALIZE_ENUM(ThermalSimUnit, {{ThermalSimUnit::Invalid, nullptr}
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struct DramDieChannel
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{
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std::string identifier;
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double init_pow;
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double threshold;
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};
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@@ -87,10 +88,7 @@ void from_json(const json &j, DramDieChannel &c);
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struct PowerInfo
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{
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DramDieChannel channel0;
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DramDieChannel channel1;
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DramDieChannel channel2;
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DramDieChannel channel3;
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std::vector<DramDieChannel> channels;
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};
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void to_json(json &j, const PowerInfo &c);
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@@ -53,6 +53,8 @@ void to_json(json &j, const TraceSetup &c)
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inititator_j["name"] = initiator->name;
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inititator_j["clkMhz"] = initiator->clkMhz;
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inititator_j["maxPendingReadRequests"] = initiator->maxPendingReadRequests;
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inititator_j["maxPendingWriteRequests"] = initiator->maxPendingWriteRequests;
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if (const auto generator = dynamic_cast<TraceGenerator *>(initiator.get()))
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{
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@@ -61,8 +63,6 @@ void to_json(json &j, const TraceSetup &c)
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inititator_j["rwRatio"] = generator->rwRatio;
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inititator_j["addressDistribution"] = generator->addressDistribution;
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inititator_j["seed"] = generator->seed;
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inititator_j["maxPendingReadRequests"] = generator->maxPendingReadRequests;
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inititator_j["maxPendingWriteRequests"] = generator->maxPendingWriteRequests;
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inititator_j["minAddress"] = generator->minAddress;
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inititator_j["maxAddress"] = generator->maxAddress;
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}
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@@ -105,12 +105,6 @@ void from_json(const json &j, TraceSetup &c)
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if (initiator_j.contains("seed"))
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initiator_j.at("seed").get_to(generator->seed);
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if (initiator_j.contains("maxPendingReadRequests"))
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initiator_j.at("maxPendingReadRequests").get_to(generator->maxPendingReadRequests);
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if (initiator_j.contains("maxPendingWriteRequests"))
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initiator_j.at("maxPendingWriteRequests").get_to(generator->maxPendingWriteRequests);
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if (initiator_j.contains("minAddress"))
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initiator_j.at("minAddress").get_to(generator->minAddress);
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@@ -132,6 +126,12 @@ void from_json(const json &j, TraceSetup &c)
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initiator_j.at("name").get_to(initiator->name);
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initiator_j.at("clkMhz").get_to(initiator->clkMhz);
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if (initiator_j.contains("maxPendingReadRequests"))
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initiator_j.at("maxPendingReadRequests").get_to(initiator->maxPendingReadRequests);
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if (initiator_j.contains("maxPendingWriteRequests"))
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initiator_j.at("maxPendingWriteRequests").get_to(initiator->maxPendingWriteRequests);
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c.initiators.emplace(std::move(initiator));
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}
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}
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@@ -74,8 +74,10 @@ struct TrafficInitiator
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{
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virtual ~TrafficInitiator() = 0;
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unsigned int clkMhz;
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uint64_t clkMhz;
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std::string name;
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Optional<unsigned int> maxPendingReadRequests;
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Optional<unsigned int> maxPendingWriteRequests;
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};
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struct TracePlayer : public TrafficInitiator
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@@ -84,21 +86,19 @@ struct TracePlayer : public TrafficInitiator
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struct TraceGenerator : public TrafficInitiator
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{
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unsigned int numRequests;
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uint64_t numRequests;
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double rwRatio;
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AddressDistribution addressDistribution;
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Optional<unsigned int> addressIncrement;
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Optional<unsigned int> seed;
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Optional<unsigned int> maxPendingReadRequests;
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Optional<unsigned int> maxPendingWriteRequests;
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Optional<unsigned int> minAddress;
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Optional<unsigned int> maxAddress;
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Optional<uint64_t> addressIncrement;
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Optional<uint64_t> seed;
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Optional<uint64_t> minAddress;
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Optional<uint64_t> maxAddress;
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};
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struct TraceHammer : public TrafficInitiator
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{
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unsigned int numRequests;
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unsigned int rowIncrement;
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uint64_t numRequests;
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uint64_t rowIncrement;
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};
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struct TraceSetup
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@@ -45,7 +45,7 @@ using json = nlohmann::json;
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struct MemPowerSpec
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{
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std::unordered_map<std::string, unsigned int> entries;
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std::unordered_map<std::string, double> entries;
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};
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void to_json(json &j, const MemPowerSpec &c);
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@@ -62,4 +62,9 @@ void from_json(const json &j, MemSpec &c)
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j_memspecs.at("mempowerspec").get_to(c.memPowerSpec);
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}
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std::string dump(const MemSpec &c)
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{
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return json{c}.dump();
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}
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} // namespace Configuration
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@@ -61,6 +61,8 @@ struct MemSpec
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void to_json(json &j, const MemSpec &c);
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void from_json(const json &j, MemSpec &c);
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std::string dump(const MemSpec &c);
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} // namespace Configuration
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#endif // MEMSPEC_H
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@@ -12,6 +12,7 @@ DRAMSysConfiguration::AddressMapping getAddressMapping()
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{{13, 14, 15}},
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{17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32},
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{{33}},
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{{}},
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{{}}};
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}
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@@ -42,12 +43,14 @@ DRAMSysConfiguration::SimConfig getSimConfig()
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DRAMSysConfiguration::ThermalConfig getThermalConfig()
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{
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std::vector<DRAMSysConfiguration::DramDieChannel> channels {{"dram_die_channel0", 0.0, 1.0}, {"dram_die_channel1", 0.0, 1.0}, {"dram_die_channel2", 0.0, 1.0}, {"dram_die_channel3", 0.0, 1.0}};
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return DRAMSysConfiguration::ThermalConfig{
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DRAMSysConfiguration::TemperatureScale::Celsius,
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89,
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100,
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DRAMSysConfiguration::ThermalSimUnit::Microseconds,
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DRAMSysConfiguration::PowerInfo{{0.0, 1.0}, {0.0, 1.0}, {0.0, 1.0}, {0.0, 1.0}},
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DRAMSysConfiguration::PowerInfo{channels},
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"127.0.0.1",
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118800,
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10,
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@@ -34,9 +34,10 @@
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*/
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#include "util.h"
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#include "Configuration.h"
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#include <fstream>
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#include <iostream>
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namespace DRAMSysConfiguration
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{
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@@ -51,7 +52,7 @@ json get_config_json(const json &j, const std::string &configPath, const std::st
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std::string jsonFileName;
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j.get_to(jsonFileName);
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std::ifstream file(std::string(DRAMSysResourceDirectory) + "/" + configPath + "/" + jsonFileName);
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std::ifstream file(std::string(Configuration::resourceDirectory) + "/" + configPath + "/" + jsonFileName);
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json j_object = json::parse(file);
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return j_object.at(objectName);
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}
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@@ -43,7 +43,6 @@
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using namespace sc_core;
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using namespace tlm;
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using json = nlohmann::json;
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bool TimeInterval::timeIsInInterval(const sc_time &time) const
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{
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@@ -71,89 +70,6 @@ std::string getPhaseName(const tlm_phase &phase)
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return oss.str();
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}
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json parseJSON(const std::string &path)
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{
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std::ifstream file(path);
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if (file.is_open())
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{
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json j = json::parse(file, nullptr, false);
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if (!j.is_discarded())
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return j;
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else
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throw std::invalid_argument("JSON parse error in file '" + path + "'.");
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}
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else
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throw std::invalid_argument("Failed to open file '" + path + "'.");
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}
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bool parseBool(json &spec, const std::string &name)
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{
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json param = spec[name];
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if (!param.empty())
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{
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if (param.is_boolean())
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return param;
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else
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throw std::invalid_argument("Expected type for parameter '" + name + "': bool");
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}
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else
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{
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SC_REPORT_WARNING("utils", ("Parameter '" + name + "' does not exist, default is false.").c_str());
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return false;
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}
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}
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unsigned int parseUint(json &spec, const std::string &name)
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{
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json param = spec[name];
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if (!param.empty())
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{
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if (param.is_number_unsigned())
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return param;
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else
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throw std::invalid_argument("Expected type for parameter '" + name + "': unsigned int");
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}
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else
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{
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SC_REPORT_WARNING("utils", ("Parameter '" + name + "' does not exist, default is 1.").c_str());
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return 1;
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}
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}
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double parseUdouble(json &spec, const std::string &name)
|
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{
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json param = spec[name];
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if (!param.empty())
|
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{
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if (param.is_number() && (param > 0))
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return param;
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else
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throw std::invalid_argument("Expected type for parameter '" + name + "': positive double");
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}
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else
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{
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SC_REPORT_WARNING("utils", ("Parameter '" + name + "' does not exist, default is 1.").c_str());
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return 1;
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}
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}
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std::string parseString(json &spec, const std::string &name)
|
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{
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json param = spec[name];
|
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if (!param.empty())
|
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{
|
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if (param.is_string())
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return param;
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else
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throw std::invalid_argument("Expected type for parameter '" + name + "': string");
|
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}
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else
|
||||
{
|
||||
SC_REPORT_WARNING("utils", ("Parameter '" + name + "' does not exist.").c_str());
|
||||
return {};
|
||||
}
|
||||
}
|
||||
|
||||
void setUpDummy(tlm_generic_payload &payload, uint64_t channelPayloadID, Rank rank, BankGroup bankGroup, Bank bank)
|
||||
{
|
||||
payload.set_address(0);
|
||||
|
||||
@@ -44,7 +44,6 @@
|
||||
#include <systemc>
|
||||
#include <tlm>
|
||||
#include "dramExtensions.h"
|
||||
#include "../common/third_party/nlohmann/single_include/nlohmann/json.hpp"
|
||||
|
||||
class TimeInterval
|
||||
{
|
||||
@@ -63,12 +62,6 @@ constexpr const char headline[] =
|
||||
|
||||
std::string getPhaseName(const tlm::tlm_phase &phase);
|
||||
|
||||
nlohmann::json parseJSON(const std::string &path);
|
||||
bool parseBool(nlohmann::json &spec, const std::string &name);
|
||||
unsigned int parseUint(nlohmann::json &spec, const std::string &name);
|
||||
double parseUdouble(nlohmann::json &spec, const std::string &name);
|
||||
std::string parseString(nlohmann::json &spec, const std::string &name);
|
||||
|
||||
void setUpDummy(tlm::tlm_generic_payload &payload, uint64_t channelPayloadID,
|
||||
Rank rank = Rank(0), BankGroup bankGroup = BankGroup(0), Bank bank = Bank(0));
|
||||
|
||||
|
||||
@@ -55,10 +55,6 @@
|
||||
#include "memspec/MemSpecSTTMRAM.h"
|
||||
|
||||
using namespace sc_core;
|
||||
using json = nlohmann::json;
|
||||
|
||||
std::string Configuration::memspecUri;
|
||||
std::string Configuration::mcconfigUri;
|
||||
|
||||
enum sc_time_unit string2TimeUnit(const std::string &s)
|
||||
{
|
||||
@@ -81,218 +77,211 @@ enum sc_time_unit string2TimeUnit(const std::string &s)
|
||||
}
|
||||
}
|
||||
|
||||
void Configuration::setParameter(const std::string &name, const nlohmann::json &value)
|
||||
{
|
||||
// MCConfig
|
||||
if (name == "PagePolicy")
|
||||
{
|
||||
if (value == "Open")
|
||||
pagePolicy = PagePolicy::Open;
|
||||
else if (value == "Closed")
|
||||
pagePolicy = PagePolicy::Closed;
|
||||
else if (value == "OpenAdaptive")
|
||||
pagePolicy = PagePolicy::OpenAdaptive;
|
||||
else if (value == "ClosedAdaptive")
|
||||
pagePolicy = PagePolicy::ClosedAdaptive;
|
||||
else
|
||||
SC_REPORT_FATAL("Configuration", "Unsupported page policy!");
|
||||
}
|
||||
else if (name == "Scheduler")
|
||||
{
|
||||
if (value == "Fifo")
|
||||
scheduler = Scheduler::Fifo;
|
||||
else if (value == "FrFcfs")
|
||||
scheduler = Scheduler::FrFcfs;
|
||||
else if (value == "FrFcfsGrp")
|
||||
scheduler = Scheduler::FrFcfsGrp;
|
||||
else
|
||||
SC_REPORT_FATAL("Configuration", "Unsupported scheduler!");
|
||||
}
|
||||
else if (name == "SchedulerBuffer")
|
||||
{
|
||||
if (value == "Bankwise")
|
||||
schedulerBuffer = SchedulerBuffer::Bankwise;
|
||||
else if (value == "ReadWrite")
|
||||
schedulerBuffer = SchedulerBuffer::ReadWrite;
|
||||
else if (value == "Shared")
|
||||
schedulerBuffer = SchedulerBuffer::Shared;
|
||||
else
|
||||
SC_REPORT_FATAL("Configuration", "Unsupported scheduler buffer!");
|
||||
}
|
||||
else if (name == "RequestBufferSize")
|
||||
{
|
||||
requestBufferSize = value;
|
||||
if (requestBufferSize == 0)
|
||||
SC_REPORT_FATAL("Configuration", "Minimum request buffer size is 1!");
|
||||
}
|
||||
else if (name == "CmdMux")
|
||||
{
|
||||
if (value == "Oldest")
|
||||
cmdMux = CmdMux::Oldest;
|
||||
else if (value == "Strict")
|
||||
cmdMux = CmdMux::Strict;
|
||||
else
|
||||
SC_REPORT_FATAL("Configuration", "Unsupported cmd mux!");
|
||||
}
|
||||
else if (name == "RespQueue")
|
||||
{
|
||||
if (value == "Fifo")
|
||||
respQueue = RespQueue::Fifo;
|
||||
else if (value == "Reorder")
|
||||
respQueue = RespQueue::Reorder;
|
||||
else
|
||||
SC_REPORT_FATAL("Configuration", "Unsupported response queue!");
|
||||
}
|
||||
else if (name == "Arbiter")
|
||||
{
|
||||
if (value == "Simple")
|
||||
arbiter = Arbiter::Simple;
|
||||
else if (value == "Fifo")
|
||||
arbiter = Arbiter::Fifo;
|
||||
else if (value == "Reorder")
|
||||
arbiter = Arbiter::Reorder;
|
||||
else
|
||||
SC_REPORT_FATAL("Configuration", "Unsupported arbiter!");
|
||||
}
|
||||
else if (name == "RefreshPolicy")
|
||||
{
|
||||
if (value == "NoRefresh")
|
||||
refreshPolicy = RefreshPolicy::NoRefresh;
|
||||
else if (value == "AllBank" || value == "Rankwise")
|
||||
refreshPolicy = RefreshPolicy::AllBank;
|
||||
else if (value == "PerBank" || value == "Bankwise")
|
||||
refreshPolicy = RefreshPolicy::PerBank;
|
||||
else if (value == "Per2Bank")
|
||||
refreshPolicy = RefreshPolicy::Per2Bank;
|
||||
else if (value == "SameBank" || value == "Groupwise")
|
||||
refreshPolicy = RefreshPolicy::SameBank;
|
||||
else
|
||||
SC_REPORT_FATAL("Configuration", "Unsupported refresh policy!");
|
||||
}
|
||||
else if (name == "RefreshMaxPostponed")
|
||||
refreshMaxPostponed = value;
|
||||
else if (name == "RefreshMaxPulledin")
|
||||
refreshMaxPulledin = value;
|
||||
else if (name == "PowerDownPolicy")
|
||||
{
|
||||
if (value == "NoPowerDown")
|
||||
powerDownPolicy = PowerDownPolicy::NoPowerDown;
|
||||
else if (value == "Staggered")
|
||||
powerDownPolicy = PowerDownPolicy::Staggered;
|
||||
else
|
||||
SC_REPORT_FATAL("Configuration", "Unsupported power down policy!");
|
||||
}
|
||||
else if (name == "RefreshManagement")
|
||||
refreshManagement = value;
|
||||
else if (name == "PowerDownTimeout")
|
||||
powerDownTimeout = value;
|
||||
else if (name == "MaxActiveTransactions")
|
||||
maxActiveTransactions = value;
|
||||
else if (name == "ArbitrationDelayFw")
|
||||
arbitrationDelayFw = std::round(sc_time(value, SC_NS) / memSpec->tCK) * memSpec->tCK;
|
||||
else if (name == "ArbitrationDelayBw")
|
||||
arbitrationDelayBw = std::round(sc_time(value, SC_NS) / memSpec->tCK) * memSpec->tCK;
|
||||
else if (name == "ThinkDelayFw")
|
||||
thinkDelayFw = std::round(sc_time(value, SC_NS) / memSpec->tCK) * memSpec->tCK;
|
||||
else if (name == "ThinkDelayBw")
|
||||
thinkDelayBw = std::round(sc_time(value, SC_NS) / memSpec->tCK) * memSpec->tCK;
|
||||
else if (name == "PhyDelayFw")
|
||||
phyDelayFw = std::round(sc_time(value, SC_NS) / memSpec->tCK) * memSpec->tCK;
|
||||
else if (name == "PhyDelayBw")
|
||||
phyDelayBw = std::round(sc_time(value, SC_NS) / memSpec->tCK) * memSpec->tCK;
|
||||
//SimConfig------------------------------------------------
|
||||
else if (name == "SimulationName")
|
||||
simulationName = value;
|
||||
else if (name == "DatabaseRecording")
|
||||
databaseRecording = value;
|
||||
else if (name == "PowerAnalysis")
|
||||
powerAnalysis = value;
|
||||
else if (name == "EnableWindowing")
|
||||
enableWindowing = value;
|
||||
else if (name == "WindowSize")
|
||||
{
|
||||
windowSize = value;
|
||||
if (windowSize == 0)
|
||||
SC_REPORT_FATAL("Configuration", "Minimum window size is 1");
|
||||
}
|
||||
else if (name == "Debug")
|
||||
debug = value;
|
||||
else if (name == "ThermalSimulation")
|
||||
thermalSimulation = value;
|
||||
else if (name == "SimulationProgressBar")
|
||||
simulationProgressBar = value;
|
||||
else if (name == "AddressOffset")
|
||||
addressOffset = value;
|
||||
else if (name == "UseMalloc")
|
||||
useMalloc = value;
|
||||
else if (name == "CheckTLM2Protocol")
|
||||
checkTLM2Protocol = value;
|
||||
else if (name == "ECCControllerMode")
|
||||
{
|
||||
if (value == "Disabled")
|
||||
eccMode = ECCMode::Disabled;
|
||||
else if (value == "Hamming")
|
||||
eccMode = ECCMode::Hamming;
|
||||
else
|
||||
SC_REPORT_FATAL("Configuration", "Unsupported ECC mode!");
|
||||
}
|
||||
// Specification for ErrorChipSeed, ErrorCSVFile path and StoreMode
|
||||
else if (name == "ErrorChipSeed")
|
||||
errorChipSeed = value;
|
||||
else if (name == "ErrorCSVFile")
|
||||
errorCSVFile = value;
|
||||
else if (name == "StoreMode")
|
||||
{
|
||||
if (value == "NoStorage")
|
||||
storeMode = StoreMode::NoStorage;
|
||||
else if (value == "Store")
|
||||
storeMode = StoreMode::Store;
|
||||
else if (value == "ErrorModel")
|
||||
storeMode = StoreMode::ErrorModel;
|
||||
else
|
||||
SC_REPORT_FATAL("Configuration", "Unsupported store mode!");
|
||||
}
|
||||
|
||||
// Temperature Simulation related
|
||||
else if (name == "TemperatureScale")
|
||||
{
|
||||
if (value != "Celsius" && value != "Fahrenheit" && value != "Kelvin")
|
||||
SC_REPORT_FATAL("Configuration",
|
||||
("Invalid value for parameter " + name + ".").c_str());
|
||||
temperatureSim.temperatureScale = value;
|
||||
}
|
||||
else if (name == "StaticTemperatureDefaultValue")
|
||||
temperatureSim.staticTemperatureDefaultValue = value;
|
||||
else if (name == "ThermalSimPeriod")
|
||||
temperatureSim.thermalSimPeriod = value;
|
||||
else if (name == "ThermalSimUnit")
|
||||
temperatureSim.thermalSimUnit = string2TimeUnit(value);
|
||||
else if (name == "PowerInfoFile")
|
||||
{
|
||||
temperatureSim.powerInfoFile = value;
|
||||
temperatureSim.parsePowerInfoFile();
|
||||
}
|
||||
else if (name == "IceServerIp")
|
||||
temperatureSim.iceServerIp = value;
|
||||
else if (name == "IceServerPort")
|
||||
temperatureSim.iceServerPort = value;
|
||||
else if (name == "SimPeriodAdjustFactor")
|
||||
temperatureSim.simPeriodAdjustFactor = value;
|
||||
else if (name == "NPowStableCyclesToIncreasePeriod")
|
||||
temperatureSim.nPowStableCyclesToIncreasePeriod = value;
|
||||
else if (name == "GenerateTemperatureMap")
|
||||
temperatureSim.generateTemperatureMap = value;
|
||||
else if (name == "GeneratePowerMap")
|
||||
temperatureSim.generatePowerMap = value;
|
||||
else
|
||||
SC_REPORT_FATAL("Configuration",
|
||||
("Parameter " + name + " not defined in Configuration").c_str());
|
||||
}
|
||||
|
||||
void Configuration::setPathToResources(const std::string &path)
|
||||
{
|
||||
temperatureSim.setPathToResources(path);
|
||||
}
|
||||
// void Configuration::setParameter(const std::string &name, const nlohmann::json &value)
|
||||
// {
|
||||
// MCConfig
|
||||
// if (name == "PagePolicy")
|
||||
// {
|
||||
// if (value == "Open")
|
||||
// pagePolicy = PagePolicy::Open;
|
||||
// else if (value == "Closed")
|
||||
// pagePolicy = PagePolicy::Closed;
|
||||
// else if (value == "OpenAdaptive")
|
||||
// pagePolicy = PagePolicy::OpenAdaptive;
|
||||
// else if (value == "ClosedAdaptive")
|
||||
// pagePolicy = PagePolicy::ClosedAdaptive;
|
||||
// else
|
||||
// SC_REPORT_FATAL("Configuration", "Unsupported page policy!");
|
||||
// }
|
||||
// else if (name == "Scheduler")
|
||||
// {
|
||||
// if (value == "Fifo")
|
||||
// scheduler = Scheduler::Fifo;
|
||||
// else if (value == "FrFcfs")
|
||||
// scheduler = Scheduler::FrFcfs;
|
||||
// else if (value == "FrFcfsGrp")
|
||||
// scheduler = Scheduler::FrFcfsGrp;
|
||||
// else
|
||||
// SC_REPORT_FATAL("Configuration", "Unsupported scheduler!");
|
||||
// }
|
||||
// else if (name == "SchedulerBuffer")
|
||||
// {
|
||||
// if (value == "Bankwise")
|
||||
// schedulerBuffer = SchedulerBuffer::Bankwise;
|
||||
// else if (value == "ReadWrite")
|
||||
// schedulerBuffer = SchedulerBuffer::ReadWrite;
|
||||
// else if (value == "Shared")
|
||||
// schedulerBuffer = SchedulerBuffer::Shared;
|
||||
// else
|
||||
// SC_REPORT_FATAL("Configuration", "Unsupported scheduler buffer!");
|
||||
// }
|
||||
// else if (name == "RequestBufferSize")
|
||||
// {
|
||||
// requestBufferSize = value;
|
||||
// if (requestBufferSize == 0)
|
||||
// SC_REPORT_FATAL("Configuration", "Minimum request buffer size is 1!");
|
||||
// }
|
||||
// else if (name == "CmdMux")
|
||||
// {
|
||||
// if (value == "Oldest")
|
||||
// cmdMux = CmdMux::Oldest;
|
||||
// else if (value == "Strict")
|
||||
// cmdMux = CmdMux::Strict;
|
||||
// else
|
||||
// SC_REPORT_FATAL("Configuration", "Unsupported cmd mux!");
|
||||
// }
|
||||
// else if (name == "RespQueue")
|
||||
// {
|
||||
// if (value == "Fifo")
|
||||
// respQueue = RespQueue::Fifo;
|
||||
// else if (value == "Reorder")
|
||||
// respQueue = RespQueue::Reorder;
|
||||
// else
|
||||
// SC_REPORT_FATAL("Configuration", "Unsupported response queue!");
|
||||
// }
|
||||
// else if (name == "Arbiter")
|
||||
// {
|
||||
// if (value == "Simple")
|
||||
// arbiter = Arbiter::Simple;
|
||||
// else if (value == "Fifo")
|
||||
// arbiter = Arbiter::Fifo;
|
||||
// else if (value == "Reorder")
|
||||
// arbiter = Arbiter::Reorder;
|
||||
// else
|
||||
// SC_REPORT_FATAL("Configuration", "Unsupported arbiter!");
|
||||
// }
|
||||
// else if (name == "RefreshPolicy")
|
||||
// {
|
||||
// if (value == "NoRefresh")
|
||||
// refreshPolicy = RefreshPolicy::NoRefresh;
|
||||
// else if (value == "AllBank" || value == "Rankwise")
|
||||
// refreshPolicy = RefreshPolicy::AllBank;
|
||||
// else if (value == "PerBank" || value == "Bankwise")
|
||||
// refreshPolicy = RefreshPolicy::PerBank;
|
||||
// else if (value == "SameBank" || value == "Groupwise")
|
||||
// refreshPolicy = RefreshPolicy::SameBank;
|
||||
// else
|
||||
// SC_REPORT_FATAL("Configuration", "Unsupported refresh policy!");
|
||||
// }
|
||||
// else if (name == "RefreshMaxPostponed")
|
||||
// refreshMaxPostponed = value;
|
||||
// else if (name == "RefreshMaxPulledin")
|
||||
// refreshMaxPulledin = value;
|
||||
// else if (name == "PowerDownPolicy")
|
||||
// {
|
||||
// if (value == "NoPowerDown")
|
||||
// powerDownPolicy = PowerDownPolicy::NoPowerDown;
|
||||
// else if (value == "Staggered")
|
||||
// powerDownPolicy = PowerDownPolicy::Staggered;
|
||||
// else
|
||||
// SC_REPORT_FATAL("Configuration", "Unsupported power down policy!");
|
||||
// }
|
||||
// else if (name == "RefreshManagement")
|
||||
// refreshManagement = value;
|
||||
// else if (name == "PowerDownTimeout")
|
||||
// powerDownTimeout = value;
|
||||
// else if (name == "MaxActiveTransactions")
|
||||
// maxActiveTransactions = value;
|
||||
// else if (name == "ArbitrationDelayFw")
|
||||
// arbitrationDelayFw = std::round(sc_time(value, SC_NS) / memSpec->tCK) * memSpec->tCK;
|
||||
// else if (name == "ArbitrationDelayBw")
|
||||
// arbitrationDelayBw = std::round(sc_time(value, SC_NS) / memSpec->tCK) * memSpec->tCK;
|
||||
// else if (name == "ThinkDelayFw")
|
||||
// thinkDelayFw = std::round(sc_time(value, SC_NS) / memSpec->tCK) * memSpec->tCK;
|
||||
// else if (name == "ThinkDelayBw")
|
||||
// thinkDelayBw = std::round(sc_time(value, SC_NS) / memSpec->tCK) * memSpec->tCK;
|
||||
// else if (name == "PhyDelayFw")
|
||||
// phyDelayFw = std::round(sc_time(value, SC_NS) / memSpec->tCK) * memSpec->tCK;
|
||||
// else if (name == "PhyDelayBw")
|
||||
// phyDelayBw = std::round(sc_time(value, SC_NS) / memSpec->tCK) * memSpec->tCK;
|
||||
// SimConfig------------------------------------------------
|
||||
// else if (name == "SimulationName")
|
||||
// simulationName = value;
|
||||
// else if (name == "DatabaseRecording")
|
||||
// databaseRecording = value;
|
||||
// else if (name == "PowerAnalysis")
|
||||
// powerAnalysis = value;
|
||||
// else if (name == "EnableWindowing")
|
||||
// enableWindowing = value;
|
||||
// else if (name == "WindowSize")
|
||||
// {
|
||||
// windowSize = value;
|
||||
// if (windowSize == 0)
|
||||
// SC_REPORT_FATAL("Configuration", "Minimum window size is 1");
|
||||
// }
|
||||
// else if (name == "Debug")
|
||||
// debug = value;
|
||||
// else if (name == "ThermalSimulation")
|
||||
// thermalSimulation = value;
|
||||
// else if (name == "SimulationProgressBar")
|
||||
// simulationProgressBar = value;
|
||||
// else if (name == "AddressOffset")
|
||||
// addressOffset = value;
|
||||
// else if (name == "UseMalloc")
|
||||
// useMalloc = value;
|
||||
// else if (name == "CheckTLM2Protocol")
|
||||
// checkTLM2Protocol = value;
|
||||
// else if (name == "ECCControllerMode")
|
||||
// {
|
||||
// if (value == "Disabled")
|
||||
// eccMode = ECCMode::Disabled;
|
||||
// else if (value == "Hamming")
|
||||
// eccMode = ECCMode::Hamming;
|
||||
// else
|
||||
// SC_REPORT_FATAL("Configuration", "Unsupported ECC mode!");
|
||||
// }
|
||||
// Specification for ErrorChipSeed, ErrorCSVFile path and StoreMode
|
||||
// else if (name == "ErrorChipSeed")
|
||||
// errorChipSeed = value;
|
||||
// else if (name == "ErrorCSVFile")
|
||||
// errorCSVFile = value;
|
||||
// else if (name == "StoreMode")
|
||||
// {
|
||||
// if (value == "NoStorage")
|
||||
// storeMode = StoreMode::NoStorage;
|
||||
// else if (value == "Store")
|
||||
// storeMode = StoreMode::Store;
|
||||
// else if (value == "ErrorModel")
|
||||
// storeMode = StoreMode::ErrorModel;
|
||||
// else
|
||||
// SC_REPORT_FATAL("Configuration", "Unsupported store mode!");
|
||||
// }
|
||||
//
|
||||
// Temperature Simulation related
|
||||
// else if (name == "TemperatureScale")
|
||||
// {
|
||||
// if (value != "Celsius" && value != "Fahrenheit" && value != "Kelvin")
|
||||
// SC_REPORT_FATAL("Configuration",
|
||||
// ("Invalid value for parameter " + name + ".").c_str());
|
||||
// temperatureSim.temperatureScale = value;
|
||||
// }
|
||||
// else if (name == "StaticTemperatureDefaultValue")
|
||||
// temperatureSim.staticTemperatureDefaultValue = value;
|
||||
// else if (name == "ThermalSimPeriod")
|
||||
// temperatureSim.thermalSimPeriod = value;
|
||||
// else if (name == "ThermalSimUnit")
|
||||
// temperatureSim.thermalSimUnit = string2TimeUnit(value);
|
||||
// else if (name == "PowerInfoFile")
|
||||
// {
|
||||
// temperatureSim.powerInfoFile = value;
|
||||
// temperatureSim.parsePowerInfoFile();
|
||||
// }
|
||||
// else if (name == "IceServerIp")
|
||||
// temperatureSim.iceServerIp = value;
|
||||
// else if (name == "IceServerPort")
|
||||
// temperatureSim.iceServerPort = value;
|
||||
// else if (name == "SimPeriodAdjustFactor")
|
||||
// temperatureSim.simPeriodAdjustFactor = value;
|
||||
// else if (name == "NPowStableCyclesToIncreasePeriod")
|
||||
// temperatureSim.nPowStableCyclesToIncreasePeriod = value;
|
||||
// else if (name == "GenerateTemperatureMap")
|
||||
// temperatureSim.generateTemperatureMap = value;
|
||||
// else if (name == "GeneratePowerMap")
|
||||
// temperatureSim.generatePowerMap = value;
|
||||
// else
|
||||
// SC_REPORT_FATAL("Configuration",
|
||||
// ("Parameter " + name + " not defined in Configuration").c_str());
|
||||
// }
|
||||
|
||||
// Changes the number of bytes depeding on the ECC Controller. This function is needed for modules which get data directly or indirectly from the ECC Controller
|
||||
unsigned int Configuration::adjustNumBytesAfterECC(unsigned nBytes) const
|
||||
@@ -300,73 +289,267 @@ unsigned int Configuration::adjustNumBytesAfterECC(unsigned nBytes) const
|
||||
// Manipulate the number of bytes only if there is an ECC Controller selected
|
||||
if (eccMode == ECCMode::Disabled)
|
||||
return nBytes;
|
||||
else // if (eccMode == ECCMode::Hamming)
|
||||
else // if (eccMode == DRAMSysConfiguration::ECCControllerMode::Hamming)
|
||||
{
|
||||
assert(pECC != nullptr);
|
||||
return pECC->AllocationSize(nBytes);
|
||||
}
|
||||
}
|
||||
|
||||
void Configuration::loadSimConfig(Configuration &config, const std::string &simconfigUri)
|
||||
void Configuration::loadSimConfig(Configuration &config, const DRAMSysConfiguration::SimConfig &simConfig)
|
||||
{
|
||||
json doc = parseJSON(simconfigUri);
|
||||
if (doc["simconfig"].empty())
|
||||
SC_REPORT_FATAL("Configuration", "simconfig is empty.");
|
||||
for (auto& x : doc["simconfig"].items())
|
||||
config.setParameter(x.key(), x.value());
|
||||
// TODO document all default values...
|
||||
|
||||
if (simConfig.addressOffset.isValid())
|
||||
config.addressOffset = simConfig.addressOffset.getValue();
|
||||
|
||||
if (simConfig.addressOffset.isValid())
|
||||
config.checkTLM2Protocol = simConfig.checkTLM2Protocol.getValue();
|
||||
|
||||
if (simConfig.databaseRecording.isValid())
|
||||
config.databaseRecording = simConfig.databaseRecording.getValue();
|
||||
|
||||
if (simConfig.debug.isValid())
|
||||
config.debug = simConfig.debug.getValue();
|
||||
|
||||
if (simConfig.eccControllerMode.isValid())
|
||||
config.eccMode = [=] {
|
||||
auto mode = simConfig.eccControllerMode.getValue();
|
||||
|
||||
if (mode == DRAMSysConfiguration::ECCControllerMode::Disabled)
|
||||
return ECCMode::Disabled;
|
||||
else
|
||||
return ECCMode::Hamming;
|
||||
}();
|
||||
|
||||
if (simConfig.enableWindowing.isValid())
|
||||
config.enableWindowing = simConfig.enableWindowing.getValue();
|
||||
|
||||
if (simConfig.powerAnalysis.isValid())
|
||||
config.powerAnalysis = simConfig.powerAnalysis.getValue();
|
||||
|
||||
if (simConfig.simulationName.isValid())
|
||||
config.simulationName = simConfig.simulationName.getValue();
|
||||
|
||||
if (simConfig.simulationProgressBar.isValid())
|
||||
config.simulationProgressBar = simConfig.simulationProgressBar.getValue();
|
||||
|
||||
if (simConfig.thermalSimulation.isValid())
|
||||
config.thermalSimulation = simConfig.thermalSimulation.getValue();
|
||||
|
||||
if (simConfig.useMalloc.isValid())
|
||||
config.useMalloc = simConfig.useMalloc.getValue();
|
||||
|
||||
if (simConfig.windowSize.isValid())
|
||||
config.windowSize = simConfig.windowSize.getValue();
|
||||
|
||||
|
||||
if (simConfig.errorCsvFile.isValid())
|
||||
config.errorCSVFile = simConfig.errorCsvFile.getValue();
|
||||
|
||||
if (simConfig.errorChipSeed.isValid())
|
||||
config.errorChipSeed = simConfig.errorChipSeed.getValue();
|
||||
|
||||
if (simConfig.storeMode.isValid())
|
||||
config.storeMode = [=] {
|
||||
auto mode = simConfig.storeMode.getValue();
|
||||
|
||||
if (mode == DRAMSysConfiguration::StoreMode::NoStorage)
|
||||
return StoreMode::NoStorage;
|
||||
else if (mode == DRAMSysConfiguration::StoreMode::Store)
|
||||
return StoreMode::Store;
|
||||
else
|
||||
return StoreMode::ErrorModel;
|
||||
}();
|
||||
}
|
||||
|
||||
void Configuration::loadTemperatureSimConfig(Configuration &config, const std::string &thermalsimconfigUri)
|
||||
void Configuration::loadTemperatureSimConfig(Configuration &config, const DRAMSysConfiguration::ThermalConfig &thermalConfig)
|
||||
{
|
||||
json doc = parseJSON(thermalsimconfigUri);
|
||||
if (doc["thermalsimconfig"].empty())
|
||||
SC_REPORT_FATAL("Configuration", "thermalsimconfig is empty.");
|
||||
for (auto& x : doc["thermalsimconfig"].items())
|
||||
config.setParameter(x.key(), x.value());
|
||||
config.temperatureSim.temperatureScale = [=] {
|
||||
if (thermalConfig.temperatureScale == DRAMSysConfiguration::TemperatureScale::Celsius)
|
||||
return TemperatureSimConfig::TemperatureScale::Celsius;
|
||||
else if (thermalConfig.temperatureScale == DRAMSysConfiguration::TemperatureScale::Fahrenheit)
|
||||
return TemperatureSimConfig::TemperatureScale::Fahrenheit;
|
||||
else
|
||||
return TemperatureSimConfig::TemperatureScale::Kelvin;
|
||||
}();
|
||||
|
||||
config.temperatureSim.staticTemperatureDefaultValue = thermalConfig.staticTemperatureDefaultValue;
|
||||
config.temperatureSim.thermalSimPeriod = thermalConfig.thermalSimPeriod;
|
||||
|
||||
config.temperatureSim.thermalSimUnit = [=] {
|
||||
if (thermalConfig.thermalSimUnit == DRAMSysConfiguration::ThermalSimUnit::Seconds)
|
||||
return sc_core::SC_SEC;
|
||||
else if (thermalConfig.thermalSimUnit == DRAMSysConfiguration::ThermalSimUnit::Milliseconds)
|
||||
return sc_core::SC_MS;
|
||||
else if (thermalConfig.thermalSimUnit == DRAMSysConfiguration::ThermalSimUnit::Microseconds)
|
||||
return sc_core::SC_US;
|
||||
else if (thermalConfig.thermalSimUnit == DRAMSysConfiguration::ThermalSimUnit::Nanoseconds)
|
||||
return sc_core::SC_NS;
|
||||
else if (thermalConfig.thermalSimUnit == DRAMSysConfiguration::ThermalSimUnit::Picoseconds)
|
||||
return sc_core::SC_PS;
|
||||
else
|
||||
return sc_core::SC_FS;
|
||||
}();
|
||||
|
||||
for (const auto &channel : thermalConfig.powerInfo.channels)
|
||||
{
|
||||
config.temperatureSim.powerInitialValues.push_back(channel.init_pow);
|
||||
config.temperatureSim.powerThresholds.push_back(channel.threshold);
|
||||
}
|
||||
|
||||
config.temperatureSim.iceServerIp = thermalConfig.iceServerIp;
|
||||
config.temperatureSim.iceServerPort = thermalConfig.iceServerPort;
|
||||
config.temperatureSim.simPeriodAdjustFactor = thermalConfig.simPeriodAdjustFactor;
|
||||
config.temperatureSim.nPowStableCyclesToIncreasePeriod = thermalConfig.nPowStableCyclesToIncreasePeriod;
|
||||
config.temperatureSim.generateTemperatureMap = thermalConfig.generateTemperatureMap;
|
||||
config.temperatureSim.generatePowerMap = thermalConfig.generatePowerMap;
|
||||
|
||||
config.temperatureSim.showTemperatureSimConfig();
|
||||
}
|
||||
|
||||
void Configuration::loadMCConfig(Configuration &config, const std::string &_mcconfigUri)
|
||||
void Configuration::loadMCConfig(Configuration &config, const DRAMSysConfiguration::McConfig &mcConfig)
|
||||
{
|
||||
Configuration::mcconfigUri = _mcconfigUri;
|
||||
json doc = parseJSON(_mcconfigUri);
|
||||
if (doc["mcconfig"].empty())
|
||||
SC_REPORT_FATAL("Configuration", "mcconfig is empty.");
|
||||
for (auto& x : doc["mcconfig"].items())
|
||||
config.setParameter(x.key(), x.value());
|
||||
if (mcConfig.pagePolicy.isValid())
|
||||
config.pagePolicy = [=] {
|
||||
auto policy = mcConfig.pagePolicy.getValue();
|
||||
|
||||
if (policy == DRAMSysConfiguration::PagePolicy::Open)
|
||||
return PagePolicy::Open;
|
||||
else if (policy == DRAMSysConfiguration::PagePolicy::OpenAdaptive)
|
||||
return PagePolicy::OpenAdaptive;
|
||||
else if (policy == DRAMSysConfiguration::PagePolicy::Closed)
|
||||
return PagePolicy::Closed;
|
||||
else
|
||||
return PagePolicy::ClosedAdaptive;
|
||||
}();
|
||||
|
||||
if (mcConfig.scheduler.isValid())
|
||||
config.scheduler = [=] {
|
||||
auto scheduler = mcConfig.scheduler.getValue();
|
||||
|
||||
if (scheduler == DRAMSysConfiguration::Scheduler::Fifo)
|
||||
return Scheduler::Fifo;
|
||||
else if (scheduler == DRAMSysConfiguration::Scheduler::FrFcfs)
|
||||
return Scheduler::FrFcfs;
|
||||
else
|
||||
return Scheduler::FrFcfsGrp;
|
||||
}();
|
||||
|
||||
if (mcConfig.schedulerBuffer.isValid())
|
||||
config.schedulerBuffer = [=] {
|
||||
auto schedulerBuffer = mcConfig.schedulerBuffer.getValue();
|
||||
|
||||
if (schedulerBuffer == DRAMSysConfiguration::SchedulerBuffer::Bankwise)
|
||||
return SchedulerBuffer::Bankwise;
|
||||
else if (schedulerBuffer == DRAMSysConfiguration::SchedulerBuffer::ReadWrite)
|
||||
return SchedulerBuffer::ReadWrite;
|
||||
else
|
||||
return SchedulerBuffer::Shared;
|
||||
}();
|
||||
|
||||
if (mcConfig.requestBufferSize.isValid())
|
||||
config.requestBufferSize = mcConfig.requestBufferSize.getValue();
|
||||
|
||||
if (mcConfig.cmdMux.isValid())
|
||||
config.cmdMux = [=] {
|
||||
auto cmdMux = mcConfig.cmdMux.getValue();
|
||||
|
||||
if (cmdMux == DRAMSysConfiguration::CmdMux::Oldest)
|
||||
return CmdMux::Oldest;
|
||||
else
|
||||
return CmdMux::Strict;
|
||||
}();
|
||||
|
||||
if (mcConfig.respQueue.isValid())
|
||||
config.respQueue = [=] {
|
||||
auto respQueue = mcConfig.respQueue.getValue();
|
||||
|
||||
if (respQueue == DRAMSysConfiguration::RespQueue::Fifo)
|
||||
return RespQueue::Fifo;
|
||||
else
|
||||
return RespQueue::Reorder;
|
||||
}();
|
||||
|
||||
if (mcConfig.refreshPolicy.isValid())
|
||||
config.refreshPolicy = [=] {
|
||||
auto policy = mcConfig.refreshPolicy.getValue();
|
||||
|
||||
if (policy == DRAMSysConfiguration::RefreshPolicy::NoRefresh)
|
||||
return RefreshPolicy::NoRefresh;
|
||||
else if (policy == DRAMSysConfiguration::RefreshPolicy::AllBank)
|
||||
return RefreshPolicy::AllBank;
|
||||
else if (policy == DRAMSysConfiguration::RefreshPolicy::PerBank)
|
||||
return RefreshPolicy::PerBank;
|
||||
else if (policy == DRAMSysConfiguration::RefreshPolicy::Per2Bank)
|
||||
return RefreshPolicy::Per2Bank;
|
||||
else
|
||||
return RefreshPolicy::SameBank;
|
||||
}();
|
||||
|
||||
if (mcConfig.refreshMaxPostponed.isValid())
|
||||
config.refreshMaxPostponed = mcConfig.refreshMaxPostponed.getValue();
|
||||
|
||||
if (mcConfig.refreshMaxPulledin.isValid())
|
||||
config.refreshMaxPulledin = mcConfig.refreshMaxPulledin.getValue();
|
||||
|
||||
if (mcConfig.powerDownPolicy.isValid())
|
||||
config.powerDownPolicy = [=] {
|
||||
auto policy = mcConfig.powerDownPolicy.getValue();
|
||||
|
||||
if (policy == DRAMSysConfiguration::PowerDownPolicy::NoPowerDown)
|
||||
return PowerDownPolicy::NoPowerDown;
|
||||
else
|
||||
return PowerDownPolicy::Staggered;
|
||||
}();
|
||||
|
||||
if (mcConfig.arbiter.isValid())
|
||||
config.arbiter = [=] {
|
||||
auto arbiter = mcConfig.arbiter.getValue();
|
||||
|
||||
if (arbiter == DRAMSysConfiguration::Arbiter::Simple)
|
||||
return Arbiter::Simple;
|
||||
else if (arbiter == DRAMSysConfiguration::Arbiter::Fifo)
|
||||
return Arbiter::Fifo;
|
||||
else
|
||||
return Arbiter::Reorder;
|
||||
}();
|
||||
|
||||
if (mcConfig.maxActiveTransactions.isValid())
|
||||
config.maxActiveTransactions = mcConfig.maxActiveTransactions.getValue();
|
||||
|
||||
if (mcConfig.refreshManagement.isValid())
|
||||
config.refreshManagement = mcConfig.refreshManagement.getValue();
|
||||
}
|
||||
|
||||
void Configuration::loadMemSpec(Configuration &config, const std::string &_memspecUri)
|
||||
void Configuration::loadMemSpec(Configuration &config, const DRAMSysConfiguration::MemSpec &memSpecConfig)
|
||||
{
|
||||
Configuration::memspecUri = _memspecUri;
|
||||
json doc = parseJSON(_memspecUri);
|
||||
json jMemSpec = doc["memspec"];
|
||||
|
||||
std::string memoryType = jMemSpec["memoryType"];
|
||||
std::string memoryType = memSpecConfig.memoryType;
|
||||
|
||||
if (memoryType == "DDR3")
|
||||
memSpec = new MemSpecDDR3(jMemSpec);
|
||||
config.memSpec = new MemSpecDDR3(memSpecConfig);
|
||||
else if (memoryType == "DDR4")
|
||||
memSpec = new MemSpecDDR4(jMemSpec);
|
||||
config.memSpec = new MemSpecDDR4(memSpecConfig);
|
||||
else if (memoryType == "DDR5")
|
||||
memSpec = new MemSpecDDR5(jMemSpec);
|
||||
config.memSpec = new MemSpecDDR5(memSpecConfig);
|
||||
else if (memoryType == "LPDDR4")
|
||||
memSpec = new MemSpecLPDDR4(jMemSpec);
|
||||
config.memSpec = new MemSpecLPDDR4(memSpecConfig);
|
||||
else if (memoryType == "LPDDR5")
|
||||
memSpec = new MemSpecLPDDR5(jMemSpec);
|
||||
config.memSpec = new MemSpecLPDDR5(memSpecConfig);
|
||||
else if (memoryType == "WIDEIO_SDR")
|
||||
memSpec = new MemSpecWideIO(jMemSpec);
|
||||
config.memSpec = new MemSpecWideIO(memSpecConfig);
|
||||
else if (memoryType == "WIDEIO2")
|
||||
memSpec = new MemSpecWideIO2(jMemSpec);
|
||||
config.memSpec = new MemSpecWideIO2(memSpecConfig);
|
||||
else if (memoryType == "HBM2")
|
||||
memSpec = new MemSpecHBM2(jMemSpec);
|
||||
config.memSpec = new MemSpecHBM2(memSpecConfig);
|
||||
else if (memoryType == "GDDR5")
|
||||
memSpec = new MemSpecGDDR5(jMemSpec);
|
||||
config.memSpec = new MemSpecGDDR5(memSpecConfig);
|
||||
else if (memoryType == "GDDR5X")
|
||||
memSpec = new MemSpecGDDR5X(jMemSpec);
|
||||
config.memSpec = new MemSpecGDDR5X(memSpecConfig);
|
||||
else if (memoryType == "GDDR6")
|
||||
memSpec = new MemSpecGDDR6(jMemSpec);
|
||||
config.memSpec = new MemSpecGDDR6(memSpecConfig);
|
||||
else if (memoryType == "STT-MRAM")
|
||||
memSpec = new MemSpecSTTMRAM(jMemSpec);
|
||||
config.memSpec = new MemSpecSTTMRAM(memSpecConfig);
|
||||
else
|
||||
SC_REPORT_FATAL("Configuration", "Unsupported DRAM type");
|
||||
}
|
||||
|
||||
@@ -42,7 +42,7 @@
|
||||
#define CONFIGURATION_H
|
||||
|
||||
#include <string>
|
||||
|
||||
#include <Configuration.h>
|
||||
#include <systemc>
|
||||
#include "memspec/MemSpec.h"
|
||||
#include "../error/eccbaseclass.h"
|
||||
@@ -62,9 +62,6 @@ private:
|
||||
Configuration &operator = (const Configuration &);
|
||||
|
||||
public:
|
||||
static std::string memspecUri;
|
||||
static std::string mcconfigUri;
|
||||
|
||||
// MCConfig:
|
||||
enum class PagePolicy {Open, Closed, OpenAdaptive, ClosedAdaptive} pagePolicy = PagePolicy::Open;
|
||||
enum class Scheduler {Fifo, FrFcfs, FrFcfsGrp} scheduler = Scheduler::FrFcfs;
|
||||
@@ -102,26 +99,23 @@ public:
|
||||
bool useMalloc = false;
|
||||
unsigned long long int addressOffset = 0;
|
||||
|
||||
// MemSpec (from DRAM-Power)
|
||||
const MemSpec *memSpec = nullptr;
|
||||
|
||||
void setParameter(const std::string &name, const nlohmann::json &value);
|
||||
|
||||
//Configs for Seed, csv file and StorageMode
|
||||
unsigned int errorChipSeed = 0;
|
||||
std::string errorCSVFile = "not defined.";
|
||||
enum class StoreMode {NoStorage, Store, ErrorModel} storeMode = StoreMode::NoStorage;
|
||||
|
||||
// MemSpec (from DRAM-Power)
|
||||
const MemSpec *memSpec = nullptr;
|
||||
|
||||
// Temperature Simulation related
|
||||
TemperatureSimConfig temperatureSim;
|
||||
|
||||
unsigned int adjustNumBytesAfterECC(unsigned bytes) const;
|
||||
void setPathToResources(const std::string &path);
|
||||
|
||||
static void loadMCConfig(Configuration &config, const std::string &_mcconfigUri);
|
||||
static void loadSimConfig(Configuration &config, const std::string &simconfigUri);
|
||||
void loadMemSpec(Configuration &config, const std::string &_memspecUri);
|
||||
static void loadTemperatureSimConfig(Configuration &config, const std::string &simconfigUri);
|
||||
static void loadMCConfig(Configuration &config, const DRAMSysConfiguration::McConfig &mcConfig);
|
||||
static void loadSimConfig(Configuration &config, const DRAMSysConfiguration::SimConfig &simConfig);
|
||||
static void loadMemSpec(Configuration &config, const DRAMSysConfiguration::MemSpec &memSpec);
|
||||
static void loadTemperatureSimConfig(Configuration &config, const DRAMSysConfiguration::ThermalConfig &thermalConfig);
|
||||
};
|
||||
|
||||
#endif // CONFIGURATION_H
|
||||
|
||||
@@ -40,7 +40,7 @@
|
||||
|
||||
#include <string>
|
||||
#include <vector>
|
||||
|
||||
#include <Configuration.h>
|
||||
#include <systemc>
|
||||
#include <utility>
|
||||
#include "../common/DebugManager.h"
|
||||
@@ -48,13 +48,7 @@
|
||||
struct TemperatureSimConfig
|
||||
{
|
||||
// Temperature Scale
|
||||
std::string temperatureScale;
|
||||
std::string pathToResources;
|
||||
|
||||
void setPathToResources(std::string path)
|
||||
{
|
||||
pathToResources = std::move(path);
|
||||
}
|
||||
enum class TemperatureScale {Celsius, Fahrenheit, Kelvin} temperatureScale;
|
||||
|
||||
// Static Temperature Simulation parameters
|
||||
int staticTemperatureDefaultValue;
|
||||
@@ -70,47 +64,9 @@ struct TemperatureSimConfig
|
||||
bool generatePowerMap;
|
||||
|
||||
// Power related information
|
||||
std::string powerInfoFile;
|
||||
std::vector<float> powerInitialValues;
|
||||
std::vector<float> powerThresholds;
|
||||
|
||||
void parsePowerInfoFile()
|
||||
{
|
||||
PRINTDEBUGMESSAGE("TemperatureSimConfig", "Power Info File: " + powerInfoFile);
|
||||
|
||||
powerInfoFile = pathToResources
|
||||
+ "/configs/thermalsim/"
|
||||
+ powerInfoFile;
|
||||
|
||||
// Load the JSON file into memory and parse it
|
||||
nlohmann::json powInfoElem = parseJSON(powerInfoFile);
|
||||
|
||||
if (powInfoElem["powerInfo"].empty())
|
||||
{
|
||||
// Invalid file
|
||||
std::string errormsg = "Invalid Power Info File " + powerInfoFile;
|
||||
PRINTDEBUGMESSAGE("TemperatureSimConfig", errormsg);
|
||||
SC_REPORT_FATAL("Temperature Sim Config", errormsg.c_str());
|
||||
}
|
||||
else
|
||||
{
|
||||
for (const auto& it : powInfoElem["powerInfo"].items())
|
||||
{
|
||||
// Load initial power values for all devices
|
||||
auto value = it.value();
|
||||
float pow = value["init_pow"];
|
||||
powerInitialValues.push_back(pow);
|
||||
|
||||
// Load power thresholds for all devices
|
||||
//Changes in power dissipation that exceed the threshods
|
||||
//will make the thermal simulation to be executed more often)
|
||||
float thr = value["threshold"];
|
||||
powerThresholds.push_back(thr);
|
||||
}
|
||||
}
|
||||
showTemperatureSimConfig();
|
||||
}
|
||||
|
||||
void showTemperatureSimConfig()
|
||||
{
|
||||
NDEBUG_UNUSED(int i) = 0;
|
||||
|
||||
@@ -37,9 +37,9 @@
|
||||
|
||||
using namespace sc_core;
|
||||
using namespace tlm;
|
||||
using json = nlohmann::json;
|
||||
|
||||
MemSpec::MemSpec(json &memspec, MemoryType memoryType,
|
||||
MemSpec::MemSpec(const DRAMSysConfiguration::MemSpec &memSpec,
|
||||
MemoryType memoryType,
|
||||
unsigned numberOfChannels,
|
||||
unsigned numberOfRanks, unsigned banksPerRank,
|
||||
unsigned groupsPerRank, unsigned banksPerGroup,
|
||||
@@ -53,16 +53,16 @@ MemSpec::MemSpec(json &memspec, MemoryType memoryType,
|
||||
numberOfBanks(numberOfBanks),
|
||||
numberOfBankGroups(numberOfBankGroups),
|
||||
numberOfDevices(numberOfDevices),
|
||||
numberOfRows(parseUint(memspec["memarchitecturespec"], "nbrOfRows")),
|
||||
numberOfColumns(parseUint(memspec["memarchitecturespec"], "nbrOfColumns")),
|
||||
burstLength(parseUint(memspec["memarchitecturespec"], "burstLength")),
|
||||
dataRate(parseUint(memspec["memarchitecturespec"], "dataRate")),
|
||||
bitWidth(parseUint(memspec["memarchitecturespec"], "width")),
|
||||
numberOfRows(memSpec.memArchitectureSpec.entries.at("nbrOfRows")),
|
||||
numberOfColumns(memSpec.memArchitectureSpec.entries.at("nbrOfColumns")),
|
||||
burstLength(memSpec.memArchitectureSpec.entries.at("burstLength")),
|
||||
dataRate(memSpec.memArchitectureSpec.entries.at("dataRate")),
|
||||
bitWidth(memSpec.memArchitectureSpec.entries.at("width")),
|
||||
dataBusWidth(bitWidth * numberOfDevices),
|
||||
bytesPerBurst((burstLength * dataBusWidth) / 8),
|
||||
fCKMHz(parseUdouble(memspec["memtimingspec"], "clkMhz")),
|
||||
fCKMHz(memSpec.memTimingSpec.entries.at("clkMhz")),
|
||||
tCK(sc_time(1.0 / fCKMHz, SC_US)),
|
||||
memoryId(parseString(memspec, "memoryId")),
|
||||
memoryId(memSpec.memoryId),
|
||||
memoryType(memoryType),
|
||||
burstDuration(tCK * (static_cast<double>(burstLength) / dataRate)),
|
||||
memorySizeBytes(0)
|
||||
|
||||
@@ -40,11 +40,10 @@
|
||||
|
||||
#include <vector>
|
||||
#include <string>
|
||||
|
||||
#include <Configuration.h>
|
||||
#include <systemc>
|
||||
#include <tlm>
|
||||
#include "../../common/utils.h"
|
||||
#include "../../common/third_party/nlohmann/single_include/nlohmann/json.hpp"
|
||||
#include "../../controller/Command.h"
|
||||
|
||||
class MemSpec
|
||||
@@ -96,7 +95,8 @@ public:
|
||||
uint64_t getSimMemSizeInBytes() const;
|
||||
|
||||
protected:
|
||||
MemSpec(nlohmann::json &memspec, MemoryType memoryType,
|
||||
MemSpec(const DRAMSysConfiguration::MemSpec &memSpec,
|
||||
MemoryType memoryType,
|
||||
unsigned numberOfChannels,
|
||||
unsigned numberOfRanks, unsigned banksPerRank,
|
||||
unsigned groupsPerRank, unsigned banksPerGroup,
|
||||
|
||||
@@ -40,63 +40,65 @@
|
||||
|
||||
using namespace sc_core;
|
||||
using namespace tlm;
|
||||
using json = nlohmann::json;
|
||||
|
||||
MemSpecDDR3::MemSpecDDR3(json &memspec)
|
||||
: MemSpec(memspec, MemoryType::DDR3,
|
||||
parseUint(memspec["memarchitecturespec"],"nbrOfChannels"),
|
||||
parseUint(memspec["memarchitecturespec"],"nbrOfRanks"),
|
||||
parseUint(memspec["memarchitecturespec"],"nbrOfBanks"),
|
||||
MemSpecDDR3::MemSpecDDR3(const DRAMSysConfiguration::MemSpec &memSpec)
|
||||
: MemSpec(memSpec, MemoryType::DDR3,
|
||||
memSpec.memArchitectureSpec.entries.at("nbrOfChannels"),
|
||||
memSpec.memArchitectureSpec.entries.at("nbrOfRanks"),
|
||||
memSpec.memArchitectureSpec.entries.at("nbrOfBanks"),
|
||||
1,
|
||||
parseUint(memspec["memarchitecturespec"],"nbrOfBanks"),
|
||||
parseUint(memspec["memarchitecturespec"],"nbrOfBanks")
|
||||
* parseUint(memspec["memarchitecturespec"],"nbrOfRanks"),
|
||||
parseUint(memspec["memarchitecturespec"],"nbrOfRanks"),
|
||||
parseUint(memspec["memarchitecturespec"],"nbrOfDevices")),
|
||||
tCKE (tCK * parseUint(memspec["memtimingspec"], "CKE")),
|
||||
memSpec.memArchitectureSpec.entries.at("nbrOfBanks"),
|
||||
memSpec.memArchitectureSpec.entries.at("nbrOfBanks")
|
||||
* memSpec.memArchitectureSpec.entries.at("nbrOfRanks"),
|
||||
memSpec.memArchitectureSpec.entries.at("nbrOfRanks"),
|
||||
memSpec.memArchitectureSpec.entries.at("nbrOfDevices")),
|
||||
tCKE (tCK * memSpec.memTimingSpec.entries.at("CKE")),
|
||||
tPD (tCKE),
|
||||
tCKESR (tCK * parseUint(memspec["memtimingspec"], "CKESR")),
|
||||
tDQSCK (tCK * parseUint(memspec["memtimingspec"], "DQSCK")),
|
||||
tRAS (tCK * parseUint(memspec["memtimingspec"], "RAS")),
|
||||
tRC (tCK * parseUint(memspec["memtimingspec"], "RC")),
|
||||
tRCD (tCK * parseUint(memspec["memtimingspec"], "RCD")),
|
||||
tRL (tCK * parseUint(memspec["memtimingspec"], "RL")),
|
||||
tRTP (tCK * parseUint(memspec["memtimingspec"], "RTP")),
|
||||
tWL (tCK * parseUint(memspec["memtimingspec"], "WL")),
|
||||
tWR (tCK * parseUint(memspec["memtimingspec"], "WR")),
|
||||
tXP (tCK * parseUint(memspec["memtimingspec"], "XP")),
|
||||
tXS (tCK * parseUint(memspec["memtimingspec"], "XS")),
|
||||
tCCD (tCK * parseUint(memspec["memtimingspec"], "CCD")),
|
||||
tFAW (tCK * parseUint(memspec["memtimingspec"], "FAW")),
|
||||
tREFI (tCK * parseUint(memspec["memtimingspec"], "REFI")),
|
||||
tRFC (tCK * parseUint(memspec["memtimingspec"], "RFC")),
|
||||
tRP (tCK * parseUint(memspec["memtimingspec"], "RP")),
|
||||
tRRD (tCK * parseUint(memspec["memtimingspec"], "RRD")),
|
||||
tWTR (tCK * parseUint(memspec["memtimingspec"], "WTR")),
|
||||
tAL (tCK * parseUint(memspec["memtimingspec"], "AL")),
|
||||
tXPDLL (tCK * parseUint(memspec["memtimingspec"], "XPDLL")),
|
||||
tXSDLL (tCK * parseUint(memspec["memtimingspec"], "XSDLL")),
|
||||
tACTPDEN (tCK * parseUint(memspec["memtimingspec"], "ACTPDEN")),
|
||||
tPRPDEN (tCK * parseUint(memspec["memtimingspec"], "PRPDEN")),
|
||||
tREFPDEN (tCK * parseUint(memspec["memtimingspec"], "REFPDEN")),
|
||||
tRTRS (tCK * parseUint(memspec["memtimingspec"], "RTRS")),
|
||||
iDD0 (parseUdouble(memspec["mempowerspec"], "idd0")),
|
||||
iDD2N (parseUdouble(memspec["mempowerspec"], "idd2n")),
|
||||
iDD3N (parseUdouble(memspec["mempowerspec"], "idd3n")),
|
||||
iDD4R (parseUdouble(memspec["mempowerspec"], "idd4r")),
|
||||
iDD4W (parseUdouble(memspec["mempowerspec"], "idd4w")),
|
||||
iDD5 (parseUdouble(memspec["mempowerspec"], "idd5")),
|
||||
iDD6 (parseUdouble(memspec["mempowerspec"], "idd6")),
|
||||
vDD (parseUdouble(memspec["mempowerspec"], "vdd")),
|
||||
iDD2P0 (parseUdouble(memspec["mempowerspec"], "idd2p0")),
|
||||
iDD2P1 (parseUdouble(memspec["mempowerspec"], "idd2p1")),
|
||||
iDD3P0 (parseUdouble(memspec["mempowerspec"], "idd3p0")),
|
||||
iDD3P1 (parseUdouble(memspec["mempowerspec"], "idd3p1"))
|
||||
tCKESR (tCK * memSpec.memTimingSpec.entries.at("CKESR")),
|
||||
tDQSCK (tCK * memSpec.memTimingSpec.entries.at("DQSCK")),
|
||||
tRAS (tCK * memSpec.memTimingSpec.entries.at("RAS")),
|
||||
tRC (tCK * memSpec.memTimingSpec.entries.at("RC")),
|
||||
tRCD (tCK * memSpec.memTimingSpec.entries.at("RCD")),
|
||||
tRL (tCK * memSpec.memTimingSpec.entries.at("RL")),
|
||||
tRTP (tCK * memSpec.memTimingSpec.entries.at("RTP")),
|
||||
tWL (tCK * memSpec.memTimingSpec.entries.at("WL")),
|
||||
tWR (tCK * memSpec.memTimingSpec.entries.at("WR")),
|
||||
tXP (tCK * memSpec.memTimingSpec.entries.at("XP")),
|
||||
tXS (tCK * memSpec.memTimingSpec.entries.at("XS")),
|
||||
tCCD (tCK * memSpec.memTimingSpec.entries.at("CCD")),
|
||||
tFAW (tCK * memSpec.memTimingSpec.entries.at("FAW")),
|
||||
tREFI (tCK * memSpec.memTimingSpec.entries.at("REFI")),
|
||||
tRFC (tCK * memSpec.memTimingSpec.entries.at("RFC")),
|
||||
tRP (tCK * memSpec.memTimingSpec.entries.at("RP")),
|
||||
tRRD (tCK * memSpec.memTimingSpec.entries.at("RRD")),
|
||||
tWTR (tCK * memSpec.memTimingSpec.entries.at("WTR")),
|
||||
tAL (tCK * memSpec.memTimingSpec.entries.at("AL")),
|
||||
tXPDLL (tCK * memSpec.memTimingSpec.entries.at("XPDLL")),
|
||||
tXSDLL (tCK * memSpec.memTimingSpec.entries.at("XSDLL")),
|
||||
tACTPDEN (tCK * memSpec.memTimingSpec.entries.at("ACTPDEN")),
|
||||
tPRPDEN (tCK * memSpec.memTimingSpec.entries.at("PRPDEN")),
|
||||
tREFPDEN (tCK * memSpec.memTimingSpec.entries.at("REFPDEN")),
|
||||
tRTRS (tCK * memSpec.memTimingSpec.entries.at("RTRS")),
|
||||
iDD0 (memSpec.memPowerSpec.getValue().entries.at("idd0")),
|
||||
iDD2N (memSpec.memPowerSpec.getValue().entries.at("idd2n")),
|
||||
iDD3N (memSpec.memPowerSpec.getValue().entries.at("idd3n")),
|
||||
iDD4R (memSpec.memPowerSpec.getValue().entries.at("idd4r")),
|
||||
iDD4W (memSpec.memPowerSpec.getValue().entries.at("idd4w")),
|
||||
iDD5 (memSpec.memPowerSpec.getValue().entries.at("idd5")),
|
||||
iDD6 (memSpec.memPowerSpec.getValue().entries.at("idd6")),
|
||||
vDD (memSpec.memPowerSpec.getValue().entries.at("vdd")),
|
||||
iDD2P0 (memSpec.memPowerSpec.getValue().entries.at("idd2p0")),
|
||||
iDD2P1 (memSpec.memPowerSpec.getValue().entries.at("idd2p1")),
|
||||
iDD3P0 (memSpec.memPowerSpec.getValue().entries.at("idd3p0")),
|
||||
iDD3P1 (memSpec.memPowerSpec.getValue().entries.at("idd3p1"))
|
||||
{
|
||||
uint64_t deviceSizeBits = static_cast<uint64_t>(banksPerRank) * numberOfRows * numberOfColumns * bitWidth;
|
||||
uint64_t deviceSizeBytes = deviceSizeBits / 8;
|
||||
memorySizeBytes = deviceSizeBytes * numberOfDevices * numberOfRanks * numberOfChannels;
|
||||
|
||||
if (!memSpec.memPowerSpec.isValid())
|
||||
SC_REPORT_FATAL("MemSpec", "No power spec defined!");
|
||||
|
||||
std::cout << headline << std::endl;
|
||||
std::cout << "Memory Configuration:" << std::endl << std::endl;
|
||||
std::cout << " Memory type: " << "DDR3" << std::endl;
|
||||
|
||||
@@ -36,14 +36,15 @@
|
||||
#ifndef MEMSPECDDR3_H
|
||||
#define MEMSPECDDR3_H
|
||||
|
||||
#include <systemc>
|
||||
#include "MemSpec.h"
|
||||
#include "../../common/third_party/nlohmann/single_include/nlohmann/json.hpp"
|
||||
|
||||
#include <systemc>
|
||||
#include <Configuration.h>
|
||||
|
||||
class MemSpecDDR3 final : public MemSpec
|
||||
{
|
||||
public:
|
||||
explicit MemSpecDDR3(nlohmann::json &memspec);
|
||||
explicit MemSpecDDR3(const DRAMSysConfiguration::MemSpec &memSpec);
|
||||
|
||||
// Memspec Variables:
|
||||
const sc_core::sc_time tCKE;
|
||||
|
||||
@@ -40,81 +40,83 @@
|
||||
|
||||
using namespace sc_core;
|
||||
using namespace tlm;
|
||||
using json = nlohmann::json;
|
||||
|
||||
MemSpecDDR4::MemSpecDDR4(json &memspec)
|
||||
: MemSpec(memspec, MemoryType::DDR4,
|
||||
parseUint(memspec["memarchitecturespec"],"nbrOfChannels"),
|
||||
parseUint(memspec["memarchitecturespec"],"nbrOfRanks"),
|
||||
parseUint(memspec["memarchitecturespec"],"nbrOfBanks"),
|
||||
parseUint(memspec["memarchitecturespec"], "nbrOfBankGroups"),
|
||||
parseUint(memspec["memarchitecturespec"],"nbrOfBanks")
|
||||
/ parseUint(memspec["memarchitecturespec"], "nbrOfBankGroups"),
|
||||
parseUint(memspec["memarchitecturespec"],"nbrOfBanks")
|
||||
* parseUint(memspec["memarchitecturespec"],"nbrOfRanks"),
|
||||
parseUint(memspec["memarchitecturespec"], "nbrOfBankGroups")
|
||||
* parseUint(memspec["memarchitecturespec"],"nbrOfRanks"),
|
||||
parseUint(memspec["memarchitecturespec"],"nbrOfDevices")),
|
||||
tCKE (tCK * parseUint(memspec["memtimingspec"], "CKE")),
|
||||
MemSpecDDR4::MemSpecDDR4(const DRAMSysConfiguration::MemSpec &memSpec)
|
||||
: MemSpec(memSpec, MemoryType::DDR4,
|
||||
memSpec.memArchitectureSpec.entries.at("nbrOfChannels"),
|
||||
memSpec.memArchitectureSpec.entries.at("nbrOfRanks"),
|
||||
memSpec.memArchitectureSpec.entries.at("nbrOfBanks"),
|
||||
memSpec.memArchitectureSpec.entries.at("nbrOfBankGroups"),
|
||||
memSpec.memArchitectureSpec.entries.at("nbrOfBanks")
|
||||
/ memSpec.memArchitectureSpec.entries.at("nbrOfBankGroups"),
|
||||
memSpec.memArchitectureSpec.entries.at("nbrOfBanks")
|
||||
* memSpec.memArchitectureSpec.entries.at("nbrOfRanks"),
|
||||
memSpec.memArchitectureSpec.entries.at("nbrOfBankGroups")
|
||||
* memSpec.memArchitectureSpec.entries.at("nbrOfRanks"),
|
||||
memSpec.memArchitectureSpec.entries.at("nbrOfDevices")),
|
||||
tCKE (tCK * memSpec.memTimingSpec.entries.at("CKE")),
|
||||
tPD (tCKE),
|
||||
tCKESR (tCK * parseUint(memspec["memtimingspec"], "CKESR")),
|
||||
tRAS (tCK * parseUint(memspec["memtimingspec"], "RAS")),
|
||||
tRC (tCK * parseUint(memspec["memtimingspec"], "RC")),
|
||||
tRCD (tCK * parseUint(memspec["memtimingspec"], "RCD")),
|
||||
tRL (tCK * parseUint(memspec["memtimingspec"], "RL")),
|
||||
tRPRE (tCK * parseUint(memspec["memtimingspec"], "RPRE")),
|
||||
tRTP (tCK * parseUint(memspec["memtimingspec"], "RTP")),
|
||||
tWL (tCK * parseUint(memspec["memtimingspec"], "WL")),
|
||||
tWPRE (tCK * parseUint(memspec["memtimingspec"], "WPRE")),
|
||||
tWR (tCK * parseUint(memspec["memtimingspec"], "WR")),
|
||||
tXP (tCK * parseUint(memspec["memtimingspec"], "XP")),
|
||||
tXS (tCK * parseUint(memspec["memtimingspec"], "XS")),
|
||||
tREFI ((parseUint(memspec["memtimingspec"], "REFM") == 4) ?
|
||||
(tCK * (static_cast<double>(parseUint(memspec["memtimingspec"], "REFI")) / 4)) :
|
||||
((parseUint(memspec["memtimingspec"], "REFM") == 2) ?
|
||||
(tCK * (static_cast<double>(parseUint(memspec["memtimingspec"], "REFI")) / 2)) :
|
||||
(tCK * parseUint(memspec["memtimingspec"], "REFI")))),
|
||||
tRFC ((parseUint(memspec["memtimingspec"], "REFM") == 4) ?
|
||||
(tCK * parseUint(memspec["memtimingspec"], "RFC4")) :
|
||||
((parseUint(memspec["memtimingspec"], "REFM") == 2) ?
|
||||
(tCK * parseUint(memspec["memtimingspec"], "RFC2")) :
|
||||
(tCK * parseUint(memspec["memtimingspec"], "RFC")))),
|
||||
tRP (tCK * parseUint(memspec["memtimingspec"], "RP")),
|
||||
tDQSCK (tCK * parseUint(memspec["memtimingspec"], "DQSCK")),
|
||||
tCCD_S (tCK * parseUint(memspec["memtimingspec"], "CCD_S")),
|
||||
tCCD_L (tCK * parseUint(memspec["memtimingspec"], "CCD_L")),
|
||||
tFAW (tCK * parseUint(memspec["memtimingspec"], "FAW")),
|
||||
tRRD_S (tCK * parseUint(memspec["memtimingspec"], "RRD_S")),
|
||||
tRRD_L (tCK * parseUint(memspec["memtimingspec"], "RRD_L")),
|
||||
tWTR_S (tCK * parseUint(memspec["memtimingspec"], "WTR_S")),
|
||||
tWTR_L (tCK * parseUint(memspec["memtimingspec"], "WTR_L")),
|
||||
tAL (tCK * parseUint(memspec["memtimingspec"], "AL")),
|
||||
tXPDLL (tCK * parseUint(memspec["memtimingspec"], "XPDLL")),
|
||||
tXSDLL (tCK * parseUint(memspec["memtimingspec"], "XSDLL")),
|
||||
tACTPDEN (tCK * parseUint(memspec["memtimingspec"], "ACTPDEN")),
|
||||
tPRPDEN (tCK * parseUint(memspec["memtimingspec"], "PRPDEN")),
|
||||
tREFPDEN (tCK * parseUint(memspec["memtimingspec"], "REFPDEN")),
|
||||
tRTRS (tCK * parseUint(memspec["memtimingspec"], "RTRS")),
|
||||
iDD0 (parseUdouble(memspec["mempowerspec"], "idd0")),
|
||||
iDD2N (parseUdouble(memspec["mempowerspec"], "idd2n")),
|
||||
iDD3N (parseUdouble(memspec["mempowerspec"], "idd3n")),
|
||||
iDD4R (parseUdouble(memspec["mempowerspec"], "idd4r")),
|
||||
iDD4W (parseUdouble(memspec["mempowerspec"], "idd4w")),
|
||||
iDD5 (parseUdouble(memspec["mempowerspec"], "idd5")),
|
||||
iDD6 (parseUdouble(memspec["mempowerspec"], "idd6")),
|
||||
vDD (parseUdouble(memspec["mempowerspec"], "vdd")),
|
||||
iDD02 (parseUdouble(memspec["mempowerspec"], "idd02")),
|
||||
iDD2P0 (parseUdouble(memspec["mempowerspec"], "idd2p0")),
|
||||
iDD2P1 (parseUdouble(memspec["mempowerspec"], "idd2p1")),
|
||||
iDD3P0 (parseUdouble(memspec["mempowerspec"], "idd3p0")),
|
||||
iDD3P1 (parseUdouble(memspec["mempowerspec"], "idd3p1")),
|
||||
iDD62 (parseUdouble(memspec["mempowerspec"], "idd62")),
|
||||
vDD2 (parseUdouble(memspec["mempowerspec"], "vdd2"))
|
||||
tCKESR (tCK * memSpec.memTimingSpec.entries.at("CKESR")),
|
||||
tRAS (tCK * memSpec.memTimingSpec.entries.at("RAS")),
|
||||
tRC (tCK * memSpec.memTimingSpec.entries.at("RC")),
|
||||
tRCD (tCK * memSpec.memTimingSpec.entries.at("RCD")),
|
||||
tRL (tCK * memSpec.memTimingSpec.entries.at("RL")),
|
||||
tRPRE (tCK * memSpec.memTimingSpec.entries.at("RPRE")),
|
||||
tRTP (tCK * memSpec.memTimingSpec.entries.at("RTP")),
|
||||
tWL (tCK * memSpec.memTimingSpec.entries.at("WL")),
|
||||
tWPRE (tCK * memSpec.memTimingSpec.entries.at("WPRE")),
|
||||
tWR (tCK * memSpec.memTimingSpec.entries.at("WR")),
|
||||
tXP (tCK * memSpec.memTimingSpec.entries.at("XP")),
|
||||
tXS (tCK * memSpec.memTimingSpec.entries.at("XS")),
|
||||
tREFI ((memSpec.memTimingSpec.entries.at("REFM") == 4) ?
|
||||
(tCK * (static_cast<double>(memSpec.memTimingSpec.entries.at("REFI")) / 4)) :
|
||||
((memSpec.memTimingSpec.entries.at("REFM") == 2) ?
|
||||
(tCK * (static_cast<double>(memSpec.memTimingSpec.entries.at("REFI")) / 2)) :
|
||||
(tCK * memSpec.memTimingSpec.entries.at("REFI")))),
|
||||
tRFC ((memSpec.memTimingSpec.entries.at("REFM") == 4) ?
|
||||
(tCK * memSpec.memTimingSpec.entries.at("RFC4")) :
|
||||
((memSpec.memTimingSpec.entries.at("REFM") == 2) ?
|
||||
(tCK * memSpec.memTimingSpec.entries.at("RFC2")) :
|
||||
(tCK * memSpec.memTimingSpec.entries.at("RFC")))),
|
||||
tRP (tCK * memSpec.memTimingSpec.entries.at("RP")),
|
||||
tDQSCK (tCK * memSpec.memTimingSpec.entries.at("DQSCK")),
|
||||
tCCD_S (tCK * memSpec.memTimingSpec.entries.at("CCD_S")),
|
||||
tCCD_L (tCK * memSpec.memTimingSpec.entries.at("CCD_L")),
|
||||
tFAW (tCK * memSpec.memTimingSpec.entries.at("FAW")),
|
||||
tRRD_S (tCK * memSpec.memTimingSpec.entries.at("RRD_S")),
|
||||
tRRD_L (tCK * memSpec.memTimingSpec.entries.at("RRD_L")),
|
||||
tWTR_S (tCK * memSpec.memTimingSpec.entries.at("WTR_S")),
|
||||
tWTR_L (tCK * memSpec.memTimingSpec.entries.at("WTR_L")),
|
||||
tAL (tCK * memSpec.memTimingSpec.entries.at("AL")),
|
||||
tXPDLL (tCK * memSpec.memTimingSpec.entries.at("XPDLL")),
|
||||
tXSDLL (tCK * memSpec.memTimingSpec.entries.at("XSDLL")),
|
||||
tACTPDEN (tCK * memSpec.memTimingSpec.entries.at("ACTPDEN")),
|
||||
tPRPDEN (tCK * memSpec.memTimingSpec.entries.at("PRPDEN")),
|
||||
tREFPDEN (tCK * memSpec.memTimingSpec.entries.at("REFPDEN")),
|
||||
tRTRS (tCK * memSpec.memTimingSpec.entries.at("RTRS")),
|
||||
iDD0 (memSpec.memPowerSpec.getValue().entries.at("idd0")),
|
||||
iDD2N (memSpec.memPowerSpec.getValue().entries.at("idd2n")),
|
||||
iDD3N (memSpec.memPowerSpec.getValue().entries.at("idd3n")),
|
||||
iDD4R (memSpec.memPowerSpec.getValue().entries.at("idd4r")),
|
||||
iDD4W (memSpec.memPowerSpec.getValue().entries.at("idd4w")),
|
||||
iDD5 (memSpec.memPowerSpec.getValue().entries.at("idd5")),
|
||||
iDD6 (memSpec.memPowerSpec.getValue().entries.at("idd6")),
|
||||
vDD (memSpec.memPowerSpec.getValue().entries.at("vdd")),
|
||||
iDD02 (memSpec.memPowerSpec.getValue().entries.at("idd02")),
|
||||
iDD2P0 (memSpec.memPowerSpec.getValue().entries.at("idd2p0")),
|
||||
iDD2P1 (memSpec.memPowerSpec.getValue().entries.at("idd2p1")),
|
||||
iDD3P0 (memSpec.memPowerSpec.getValue().entries.at("idd3p0")),
|
||||
iDD3P1 (memSpec.memPowerSpec.getValue().entries.at("idd3p1")),
|
||||
iDD62 (memSpec.memPowerSpec.getValue().entries.at("idd62")),
|
||||
vDD2 (memSpec.memPowerSpec.getValue().entries.at("vdd2"))
|
||||
{
|
||||
uint64_t deviceSizeBits = static_cast<uint64_t>(banksPerRank) * numberOfRows * numberOfColumns * bitWidth;
|
||||
uint64_t deviceSizeBytes = deviceSizeBits / 8;
|
||||
memorySizeBytes = deviceSizeBytes * numberOfDevices * numberOfRanks * numberOfChannels;
|
||||
|
||||
if (!memSpec.memPowerSpec.isValid())
|
||||
SC_REPORT_FATAL("MemSpec", "No power spec defined!");
|
||||
|
||||
std::cout << headline << std::endl;
|
||||
std::cout << "Memory Configuration:" << std::endl << std::endl;
|
||||
std::cout << " Memory type: " << "DDR4" << std::endl;
|
||||
|
||||
@@ -38,12 +38,11 @@
|
||||
|
||||
#include <systemc>
|
||||
#include "MemSpec.h"
|
||||
#include "../../common/third_party/nlohmann/single_include/nlohmann/json.hpp"
|
||||
|
||||
class MemSpecDDR4 final : public MemSpec
|
||||
{
|
||||
public:
|
||||
explicit MemSpecDDR4(nlohmann::json &memspec);
|
||||
explicit MemSpecDDR4(const DRAMSysConfiguration::MemSpec &memSpec);
|
||||
|
||||
// Memspec Variables:
|
||||
const sc_core::sc_time tCKE;
|
||||
|
||||
@@ -40,84 +40,83 @@
|
||||
|
||||
using namespace sc_core;
|
||||
using namespace tlm;
|
||||
using json = nlohmann::json;
|
||||
|
||||
MemSpecDDR5::MemSpecDDR5(json &memspec)
|
||||
: MemSpec(memspec, MemoryType::DDR5,
|
||||
parseUint(memspec["memarchitecturespec"], "nbrOfChannels"),
|
||||
parseUint(memspec["memarchitecturespec"], "nbrOfRanks"),
|
||||
parseUint(memspec["memarchitecturespec"], "nbrOfBanks"),
|
||||
parseUint(memspec["memarchitecturespec"], "nbrOfBankGroups"),
|
||||
parseUint(memspec["memarchitecturespec"],"nbrOfBanks")
|
||||
/ parseUint(memspec["memarchitecturespec"], "nbrOfBankGroups"),
|
||||
parseUint(memspec["memarchitecturespec"],"nbrOfBanks")
|
||||
* parseUint(memspec["memarchitecturespec"],"nbrOfRanks"),
|
||||
parseUint(memspec["memarchitecturespec"], "nbrOfBankGroups")
|
||||
* parseUint(memspec["memarchitecturespec"],"nbrOfRanks"),
|
||||
parseUint(memspec["memarchitecturespec"],"nbrOfDevices")),
|
||||
numberOfDIMMRanks(parseUint(memspec["memarchitecturespec"], "nbrOfDIMMRanks")),
|
||||
physicalRanksPerDIMMRank(parseUint(memspec["memarchitecturespec"], "nbrOfPhysicalRanks")),
|
||||
MemSpecDDR5::MemSpecDDR5(const DRAMSysConfiguration::MemSpec &memSpec)
|
||||
: MemSpec(memSpec, MemoryType::DDR5,
|
||||
memSpec.memArchitectureSpec.entries.at("nbrOfChannels"),
|
||||
memSpec.memArchitectureSpec.entries.at("nbrOfRanks"),
|
||||
memSpec.memArchitectureSpec.entries.at("nbrOfBanks"),
|
||||
memSpec.memArchitectureSpec.entries.at("nbrOfBankGroups"),
|
||||
memSpec.memArchitectureSpec.entries.at("nbrOfBanks")
|
||||
/ memSpec.memArchitectureSpec.entries.at("nbrOfBankGroups"),
|
||||
memSpec.memArchitectureSpec.entries.at("nbrOfBanks")
|
||||
* memSpec.memArchitectureSpec.entries.at("nbrOfRanks"),
|
||||
memSpec.memArchitectureSpec.entries.at("nbrOfBankGroups")
|
||||
* memSpec.memArchitectureSpec.entries.at("nbrOfRanks"),
|
||||
memSpec.memArchitectureSpec.entries.at("nbrOfDevices")),
|
||||
numberOfDIMMRanks(memSpec.memArchitectureSpec.entries.at("nbrOfDIMMRanks")),
|
||||
physicalRanksPerDIMMRank(memSpec.memArchitectureSpec.entries.at("nbrOfPhysicalRanks")),
|
||||
numberOfPhysicalRanks(physicalRanksPerDIMMRank * numberOfDIMMRanks),
|
||||
logicalRanksPerPhysicalRank(parseUint(memspec["memarchitecturespec"], "nbrOfLogicalRanks")),
|
||||
logicalRanksPerPhysicalRank(memSpec.memArchitectureSpec.entries.at("nbrOfLogicalRanks")),
|
||||
numberOfLogicalRanks(logicalRanksPerPhysicalRank * numberOfPhysicalRanks),
|
||||
cmdMode(parseUint(memspec["memarchitecturespec"], "cmdMode")),
|
||||
refMode(parseUint(memspec["memarchitecturespec"], "refMode")),
|
||||
RAAIMT(parseUint(memspec["memarchitecturespec"], "RAAIMT")),
|
||||
RAAMMT(parseUint(memspec["memarchitecturespec"], "RAAMMT")),
|
||||
RAACDR(parseUint(memspec["memarchitecturespec"], "RAACDR")),
|
||||
tRCD (tCK * parseUint(memspec["memtimingspec"], "RCD")),
|
||||
tPPD (tCK * parseUint(memspec["memtimingspec"], "PPD")),
|
||||
tRP (tCK * parseUint(memspec["memtimingspec"], "RP")),
|
||||
tRAS (tCK * parseUint(memspec["memtimingspec"], "RAS")),
|
||||
cmdMode(memSpec.memArchitectureSpec.entries.at("cmdMode")),
|
||||
refMode(memSpec.memArchitectureSpec.entries.at("refMode")),
|
||||
RAAIMT(memSpec.memArchitectureSpec.entries.at("RAAIMT")),
|
||||
RAAMMT(memSpec.memArchitectureSpec.entries.at("RAAMMT")),
|
||||
RAACDR(memSpec.memArchitectureSpec.entries.at("RAACDR")),
|
||||
tRCD (tCK * memSpec.memTimingSpec.entries.at("RCD")),
|
||||
tPPD (tCK * memSpec.memTimingSpec.entries.at("PPD")),
|
||||
tRP (tCK * memSpec.memTimingSpec.entries.at("RP")),
|
||||
tRAS (tCK * memSpec.memTimingSpec.entries.at("RAS")),
|
||||
tRC (tRAS + tRP),
|
||||
tRL (tCK * parseUint(memspec["memtimingspec"], "RL")),
|
||||
tRTP (tCK * parseUint(memspec["memtimingspec"], "RTP")),
|
||||
tRPRE (tCK * parseUint(memspec["memtimingspec"], "RPRE")),
|
||||
tRPST (tCK * parseUint(memspec["memtimingspec"], "RPST")),
|
||||
tRDDQS (tCK * parseUint(memspec["memtimingspec"], "RDDQS")),
|
||||
tWL (tCK * parseUint(memspec["memtimingspec"], "WL")),
|
||||
tWPRE (tCK * parseUint(memspec["memtimingspec"], "WPRE")),
|
||||
tWPST (tCK * parseUint(memspec["memtimingspec"], "WPST")),
|
||||
tWR (tCK * parseUint(memspec["memtimingspec"], "WR")),
|
||||
tCCD_L_slr (tCK * parseUint(memspec["memtimingspec"], "CCD_L_slr")),
|
||||
tCCD_L_WR_slr (tCK * parseUint(memspec["memtimingspec"], "CCD_L_WR_slr")),
|
||||
tCCD_L_WR2_slr (tCK * parseUint(memspec["memtimingspec"], "CCD_L_WR2_slr")),
|
||||
tCCD_S_slr (tCK * parseUint(memspec["memtimingspec"], "CCD_S_slr")),
|
||||
tCCD_S_WR_slr (tCK * parseUint(memspec["memtimingspec"], "CCD_S_WR_slr")),
|
||||
tCCD_dlr (tCK * parseUint(memspec["memtimingspec"], "CCD_dlr")),
|
||||
tCCD_WR_dlr (tCK * parseUint(memspec["memtimingspec"], "CCD_WR_dlr")),
|
||||
tCCD_WR_dpr (tCK * parseUint(memspec["memtimingspec"], "CCD_WR_dpr")),
|
||||
tRRD_L_slr (tCK * parseUint(memspec["memtimingspec"], "RRD_L_slr")),
|
||||
tRRD_S_slr (tCK * parseUint(memspec["memtimingspec"], "RRD_S_slr")),
|
||||
tRRD_dlr (tCK * parseUint(memspec["memtimingspec"], "RRD_dlr")),
|
||||
tFAW_slr (tCK * parseUint(memspec["memtimingspec"], "FAW_slr")),
|
||||
tFAW_dlr (tCK * parseUint(memspec["memtimingspec"], "FAW_dlr")),
|
||||
tWTR_L (tCK * parseUint(memspec["memtimingspec"], "WTR_L")),
|
||||
tWTR_S (tCK * parseUint(memspec["memtimingspec"], "WTR_S")),
|
||||
tRFC_slr ((refMode == 1) ? tCK * parseUint(memspec["memtimingspec"], "RFC1_slr")
|
||||
: tCK * parseUint(memspec["memtimingspec"], "RFC2_slr")),
|
||||
tRFC_dlr ((refMode == 1) ? tCK * parseUint(memspec["memtimingspec"], "RFC1_dlr")
|
||||
: tCK * parseUint(memspec["memtimingspec"], "RFC2_dlr")),
|
||||
tRFC_dpr ((refMode == 1) ? tCK * parseUint(memspec["memtimingspec"], "RFC1_dpr")
|
||||
: tCK * parseUint(memspec["memtimingspec"], "RFC2_dpr")),
|
||||
tRFCsb_slr (tCK * parseUint(memspec["memtimingspec"], "RFCsb_slr")),
|
||||
tRFCsb_dlr (tCK * parseUint(memspec["memtimingspec"], "RFCsb_dlr")),
|
||||
tREFI ((refMode == 1) ? tCK * parseUint(memspec["memtimingspec"], "REFI1")
|
||||
: tCK * parseUint(memspec["memtimingspec"], "REFI2")),
|
||||
tREFIsb (tCK * parseUint(memspec["memtimingspec"], "REFISB")),
|
||||
tREFSBRD_slr (tCK * parseUint(memspec["memtimingspec"], "REFSBRD_slr")),
|
||||
tREFSBRD_dlr (tCK * parseUint(memspec["memtimingspec"], "REFSBRD_dlr")),
|
||||
tRTRS (tCK * parseUint(memspec["memtimingspec"], "RTRS")),
|
||||
tCPDED (tCK * parseUint(memspec["memtimingspec"], "CPDED")),
|
||||
tPD (tCK * parseUint(memspec["memtimingspec"], "PD")),
|
||||
tXP (tCK * parseUint(memspec["memtimingspec"], "XP")),
|
||||
tACTPDEN (tCK * parseUint(memspec["memtimingspec"], "ACTPDEN")),
|
||||
tPRPDEN (tCK * parseUint(memspec["memtimingspec"], "PRPDEN")),
|
||||
tREFPDEN (tCK * parseUint(memspec["memtimingspec"], "REFPDEN")),
|
||||
tRL (tCK * memSpec.memTimingSpec.entries.at("RL")),
|
||||
tRTP (tCK * memSpec.memTimingSpec.entries.at("RTP")),
|
||||
tRPRE (tCK * memSpec.memTimingSpec.entries.at("RPRE")),
|
||||
tRPST (tCK * memSpec.memTimingSpec.entries.at("RPST")),
|
||||
tRDDQS (tCK * memSpec.memTimingSpec.entries.at("RDDQS")),
|
||||
tWL (tCK * memSpec.memTimingSpec.entries.at("WL")),
|
||||
tWPRE (tCK * memSpec.memTimingSpec.entries.at("WPRE")),
|
||||
tWPST (tCK * memSpec.memTimingSpec.entries.at("WPST")),
|
||||
tWR (tCK * memSpec.memTimingSpec.entries.at("WR")),
|
||||
tCCD_L_slr (tCK * memSpec.memTimingSpec.entries.at("CCD_L_slr")),
|
||||
tCCD_L_WR_slr (tCK * memSpec.memTimingSpec.entries.at("CCD_L_WR_slr")),
|
||||
tCCD_L_WR2_slr (tCK * memSpec.memTimingSpec.entries.at("CCD_L_WR2_slr")),
|
||||
tCCD_S_slr (tCK * memSpec.memTimingSpec.entries.at("CCD_S_slr")),
|
||||
tCCD_S_WR_slr (tCK * memSpec.memTimingSpec.entries.at("CCD_S_WR_slr")),
|
||||
tCCD_dlr (tCK * memSpec.memTimingSpec.entries.at("CCD_dlr")),
|
||||
tCCD_WR_dlr (tCK * memSpec.memTimingSpec.entries.at("CCD_WR_dlr")),
|
||||
tCCD_WR_dpr (tCK * memSpec.memTimingSpec.entries.at("CCD_WR_dpr")),
|
||||
tRRD_L_slr (tCK * memSpec.memTimingSpec.entries.at("RRD_L_slr")),
|
||||
tRRD_S_slr (tCK * memSpec.memTimingSpec.entries.at("RRD_S_slr")),
|
||||
tRRD_dlr (tCK * memSpec.memTimingSpec.entries.at("RRD_dlr")),
|
||||
tFAW_slr (tCK * memSpec.memTimingSpec.entries.at("FAW_slr")),
|
||||
tFAW_dlr (tCK * memSpec.memTimingSpec.entries.at("FAW_dlr")),
|
||||
tWTR_L (tCK * memSpec.memTimingSpec.entries.at("WTR_L")),
|
||||
tWTR_S (tCK * memSpec.memTimingSpec.entries.at("WTR_S")),
|
||||
tRFC_slr ((refMode == 1) ? tCK * memSpec.memTimingSpec.entries.at("RFC1_slr")
|
||||
: tCK * memSpec.memTimingSpec.entries.at("RFC2_slr")),
|
||||
tRFC_dlr ((refMode == 1) ? tCK * memSpec.memTimingSpec.entries.at("RFC1_dlr")
|
||||
: tCK * memSpec.memTimingSpec.entries.at("RFC2_dlr")),
|
||||
tRFC_dpr ((refMode == 1) ? tCK * memSpec.memTimingSpec.entries.at("RFC1_dpr")
|
||||
: tCK * memSpec.memTimingSpec.entries.at("RFC2_dpr")),
|
||||
tRFCsb_slr (tCK * memSpec.memTimingSpec.entries.at("WTR_S")),
|
||||
tRFCsb_dlr (tCK * memSpec.memTimingSpec.entries.at("WTR_S")),
|
||||
tREFI ((refMode == 1) ? tCK * memSpec.memTimingSpec.entries.at("REFI1")
|
||||
: tCK * memSpec.memTimingSpec.entries.at("REFI2")),
|
||||
tREFIsb (tCK * memSpec.memTimingSpec.entries.at("REFISB")),
|
||||
tREFSBRD_slr (tCK * memSpec.memTimingSpec.entries.at("REFSBRD_slr")),
|
||||
tREFSBRD_dlr (tCK * memSpec.memTimingSpec.entries.at("REFSBRD_dlr")),
|
||||
tRTRS (tCK * memSpec.memTimingSpec.entries.at("RTRS")),
|
||||
tCPDED (tCK * memSpec.memTimingSpec.entries.at("CPDED")),
|
||||
tPD (tCK * memSpec.memTimingSpec.entries.at("PD")),
|
||||
tXP (tCK * memSpec.memTimingSpec.entries.at("XP")),
|
||||
tACTPDEN (tCK * memSpec.memTimingSpec.entries.at("ACTPDEN")),
|
||||
tPRPDEN (tCK * memSpec.memTimingSpec.entries.at("PRPDEN")),
|
||||
tREFPDEN (tCK * memSpec.memTimingSpec.entries.at("REFPDEN")),
|
||||
shortCmdOffset (cmdMode == 2 ? 1 * tCK : 0 * tCK),
|
||||
longCmdOffset (cmdMode == 2 ? 3 * tCK : 1 * tCK),
|
||||
tBURST16(tCK * 8),
|
||||
tBURST32(tCK * 16)
|
||||
tBURST16 (tCK * 8),
|
||||
tBURST32 (tCK * 16)
|
||||
{
|
||||
if (cmdMode == 1)
|
||||
{
|
||||
|
||||
@@ -38,12 +38,11 @@
|
||||
|
||||
#include <systemc>
|
||||
#include "MemSpec.h"
|
||||
#include "../../common/third_party/nlohmann/single_include/nlohmann/json.hpp"
|
||||
|
||||
class MemSpecDDR5 final : public MemSpec
|
||||
{
|
||||
public:
|
||||
explicit MemSpecDDR5(nlohmann::json &memspec);
|
||||
explicit MemSpecDDR5(const DRAMSysConfiguration::MemSpec &memSpec);
|
||||
|
||||
const unsigned numberOfDIMMRanks;
|
||||
const unsigned physicalRanksPerDIMMRank;
|
||||
|
||||
@@ -40,55 +40,54 @@
|
||||
|
||||
using namespace sc_core;
|
||||
using namespace tlm;
|
||||
using json = nlohmann::json;
|
||||
|
||||
MemSpecGDDR5::MemSpecGDDR5(json &memspec)
|
||||
: MemSpec(memspec, MemoryType::GDDR5,
|
||||
parseUint(memspec["memarchitecturespec"],"nbrOfChannels"),
|
||||
parseUint(memspec["memarchitecturespec"],"nbrOfRanks"),
|
||||
parseUint(memspec["memarchitecturespec"],"nbrOfBanks"),
|
||||
parseUint(memspec["memarchitecturespec"], "nbrOfBankGroups"),
|
||||
parseUint(memspec["memarchitecturespec"],"nbrOfBanks")
|
||||
/ parseUint(memspec["memarchitecturespec"], "nbrOfBankGroups"),
|
||||
parseUint(memspec["memarchitecturespec"],"nbrOfBanks")
|
||||
* parseUint(memspec["memarchitecturespec"],"nbrOfRanks"),
|
||||
parseUint(memspec["memarchitecturespec"], "nbrOfBankGroups")
|
||||
* parseUint(memspec["memarchitecturespec"],"nbrOfRanks"),
|
||||
parseUint(memspec["memarchitecturespec"],"nbrOfDevices")),
|
||||
tRP (tCK * parseUint(memspec["memtimingspec"], "RP")),
|
||||
tRAS (tCK * parseUint(memspec["memtimingspec"], "RAS")),
|
||||
tRC (tCK * parseUint(memspec["memtimingspec"], "RC")),
|
||||
tRCDRD (tCK * parseUint(memspec["memtimingspec"], "RCDRD")),
|
||||
tRCDWR (tCK * parseUint(memspec["memtimingspec"], "RCDWR")),
|
||||
tRTP (tCK * parseUint(memspec["memtimingspec"], "RTP")),
|
||||
tRRDS (tCK * parseUint(memspec["memtimingspec"], "RRDS")),
|
||||
tRRDL (tCK * parseUint(memspec["memtimingspec"], "RRDL")),
|
||||
tCCDS (tCK * parseUint(memspec["memtimingspec"], "CCDS")),
|
||||
tCCDL (tCK * parseUint(memspec["memtimingspec"], "CCDL")),
|
||||
tCL (tCK * parseUint(memspec["memtimingspec"], "CL")),
|
||||
tWCK2CKPIN (tCK * parseUint(memspec["memtimingspec"], "WCK2CKPIN")),
|
||||
tWCK2CK (tCK * parseUint(memspec["memtimingspec"], "WCK2CK")),
|
||||
tWCK2DQO (tCK * parseUint(memspec["memtimingspec"], "WCK2DQO")),
|
||||
tRTW (tCK * parseUint(memspec["memtimingspec"], "RTW")),
|
||||
tWL (tCK * parseUint(memspec["memtimingspec"], "WL")),
|
||||
tWCK2DQI (tCK * parseUint(memspec["memtimingspec"], "WCK2DQI")),
|
||||
tWR (tCK * parseUint(memspec["memtimingspec"], "WR")),
|
||||
tWTRS (tCK * parseUint(memspec["memtimingspec"], "WTRS")),
|
||||
tWTRL (tCK * parseUint(memspec["memtimingspec"], "WTRL")),
|
||||
tCKE (tCK * parseUint(memspec["memtimingspec"], "CKE")),
|
||||
tPD (tCK * parseUint(memspec["memtimingspec"], "PD")),
|
||||
tXPN (tCK * parseUint(memspec["memtimingspec"], "XPN")),
|
||||
tREFI (tCK * parseUint(memspec["memtimingspec"], "REFI")),
|
||||
tREFIPB (tCK * parseUint(memspec["memtimingspec"], "REFIPB")),
|
||||
tRFC (tCK * parseUint(memspec["memtimingspec"], "RFC")),
|
||||
tRFCPB (tCK * parseUint(memspec["memtimingspec"], "RFCPB")),
|
||||
tRREFD (tCK * parseUint(memspec["memtimingspec"], "RREFD")),
|
||||
tXS (tCK * parseUint(memspec["memtimingspec"], "XS")),
|
||||
tFAW (tCK * parseUint(memspec["memtimingspec"], "FAW")),
|
||||
t32AW (tCK * parseUint(memspec["memtimingspec"], "32AW")),
|
||||
tPPD (tCK * parseUint(memspec["memtimingspec"], "PPD")),
|
||||
tLK (tCK * parseUint(memspec["memtimingspec"], "LK")),
|
||||
tRTRS (tCK * parseUint(memspec["memtimingspec"], "RTRS"))
|
||||
MemSpecGDDR5::MemSpecGDDR5(const DRAMSysConfiguration::MemSpec &memSpec)
|
||||
: MemSpec(memSpec, MemoryType::GDDR5,
|
||||
memSpec.memArchitectureSpec.entries.at("nbrOfChannels"),
|
||||
memSpec.memArchitectureSpec.entries.at("nbrOfRanks"),
|
||||
memSpec.memArchitectureSpec.entries.at("nbrOfBanks"),
|
||||
memSpec.memArchitectureSpec.entries.at("nbrOfBankGroups"),
|
||||
memSpec.memArchitectureSpec.entries.at("nbrOfBanks")
|
||||
/ memSpec.memArchitectureSpec.entries.at("nbrOfBankGroups"),
|
||||
memSpec.memArchitectureSpec.entries.at("nbrOfBanks")
|
||||
* memSpec.memArchitectureSpec.entries.at("nbrOfRanks"),
|
||||
memSpec.memArchitectureSpec.entries.at("nbrOfBankGroups")
|
||||
* memSpec.memArchitectureSpec.entries.at("nbrOfRanks"),
|
||||
memSpec.memArchitectureSpec.entries.at("nbrOfDevices")),
|
||||
tRP (tCK * memSpec.memTimingSpec.entries.at("RP")),
|
||||
tRAS (tCK * memSpec.memTimingSpec.entries.at("RAS")),
|
||||
tRC (tCK * memSpec.memTimingSpec.entries.at("RC")),
|
||||
tRCDRD (tCK * memSpec.memTimingSpec.entries.at("RCDRD")),
|
||||
tRCDWR (tCK * memSpec.memTimingSpec.entries.at("RCDWR")),
|
||||
tRTP (tCK * memSpec.memTimingSpec.entries.at("RTP")),
|
||||
tRRDS (tCK * memSpec.memTimingSpec.entries.at("RRDS")),
|
||||
tRRDL (tCK * memSpec.memTimingSpec.entries.at("RRDL")),
|
||||
tCCDS (tCK * memSpec.memTimingSpec.entries.at("CCDS")),
|
||||
tCCDL (tCK * memSpec.memTimingSpec.entries.at("CCDL")),
|
||||
tCL (tCK * memSpec.memTimingSpec.entries.at("CL")),
|
||||
tWCK2CKPIN (tCK * memSpec.memTimingSpec.entries.at("WCK2CKPIN")),
|
||||
tWCK2CK (tCK * memSpec.memTimingSpec.entries.at("WCK2CK")),
|
||||
tWCK2DQO (tCK * memSpec.memTimingSpec.entries.at("WCK2DQO")),
|
||||
tRTW (tCK * memSpec.memTimingSpec.entries.at("RTW")),
|
||||
tWL (tCK * memSpec.memTimingSpec.entries.at("WL")),
|
||||
tWCK2DQI (tCK * memSpec.memTimingSpec.entries.at("WCK2DQI")),
|
||||
tWR (tCK * memSpec.memTimingSpec.entries.at("WR")),
|
||||
tWTRS (tCK * memSpec.memTimingSpec.entries.at("WTRS")),
|
||||
tWTRL (tCK * memSpec.memTimingSpec.entries.at("WTRL")),
|
||||
tCKE (tCK * memSpec.memTimingSpec.entries.at("CKE")),
|
||||
tPD (tCK * memSpec.memTimingSpec.entries.at("PD")),
|
||||
tXPN (tCK * memSpec.memTimingSpec.entries.at("XPN")),
|
||||
tREFI (tCK * memSpec.memTimingSpec.entries.at("REFI")),
|
||||
tREFIPB (tCK * memSpec.memTimingSpec.entries.at("REFIPB")),
|
||||
tRFC (tCK * memSpec.memTimingSpec.entries.at("RFC")),
|
||||
tRFCPB (tCK * memSpec.memTimingSpec.entries.at("RFCPB")),
|
||||
tRREFD (tCK * memSpec.memTimingSpec.entries.at("RREFD")),
|
||||
tXS (tCK * memSpec.memTimingSpec.entries.at("XS")),
|
||||
tFAW (tCK * memSpec.memTimingSpec.entries.at("FAW")),
|
||||
t32AW (tCK * memSpec.memTimingSpec.entries.at("32AW")),
|
||||
tPPD (tCK * memSpec.memTimingSpec.entries.at("PPD")),
|
||||
tLK (tCK * memSpec.memTimingSpec.entries.at("LK")),
|
||||
tRTRS (tCK * memSpec.memTimingSpec.entries.at("RTRS"))
|
||||
{
|
||||
uint64_t deviceSizeBits = static_cast<uint64_t>(banksPerRank) * numberOfRows * numberOfColumns * bitWidth;
|
||||
uint64_t deviceSizeBytes = deviceSizeBits / 8;
|
||||
|
||||
@@ -38,12 +38,11 @@
|
||||
|
||||
#include <systemc>
|
||||
#include "MemSpec.h"
|
||||
#include "../../common/third_party/nlohmann/single_include/nlohmann/json.hpp"
|
||||
|
||||
class MemSpecGDDR5 final : public MemSpec
|
||||
{
|
||||
public:
|
||||
explicit MemSpecGDDR5(nlohmann::json &memspec);
|
||||
explicit MemSpecGDDR5(const DRAMSysConfiguration::MemSpec &memSpec);
|
||||
|
||||
// Memspec Variables:
|
||||
const sc_core::sc_time tRP;
|
||||
|
||||
@@ -39,55 +39,54 @@
|
||||
|
||||
using namespace sc_core;
|
||||
using namespace tlm;
|
||||
using json = nlohmann::json;
|
||||
|
||||
MemSpecGDDR5X::MemSpecGDDR5X(json &memspec)
|
||||
: MemSpec(memspec, MemoryType::GDDR5X,
|
||||
parseUint(memspec["memarchitecturespec"],"nbrOfChannels"),
|
||||
parseUint(memspec["memarchitecturespec"],"nbrOfRanks"),
|
||||
parseUint(memspec["memarchitecturespec"],"nbrOfBanks"),
|
||||
parseUint(memspec["memarchitecturespec"], "nbrOfBankGroups"),
|
||||
parseUint(memspec["memarchitecturespec"],"nbrOfBanks")
|
||||
/ parseUint(memspec["memarchitecturespec"], "nbrOfBankGroups"),
|
||||
parseUint(memspec["memarchitecturespec"],"nbrOfBanks")
|
||||
* parseUint(memspec["memarchitecturespec"],"nbrOfRanks"),
|
||||
parseUint(memspec["memarchitecturespec"], "nbrOfBankGroups")
|
||||
* parseUint(memspec["memarchitecturespec"],"nbrOfRanks"),
|
||||
parseUint(memspec["memarchitecturespec"],"nbrOfDevices")),
|
||||
tRP (tCK * parseUint(memspec["memtimingspec"], "RP")),
|
||||
tRAS (tCK * parseUint(memspec["memtimingspec"], "RAS")),
|
||||
tRC (tCK * parseUint(memspec["memtimingspec"], "RC")),
|
||||
tRCDRD (tCK * parseUint(memspec["memtimingspec"], "RCDRD")),
|
||||
tRCDWR (tCK * parseUint(memspec["memtimingspec"], "RCDWR")),
|
||||
tRTP (tCK * parseUint(memspec["memtimingspec"], "RTP")),
|
||||
tRRDS (tCK * parseUint(memspec["memtimingspec"], "RRDS")),
|
||||
tRRDL (tCK * parseUint(memspec["memtimingspec"], "RRDL")),
|
||||
tCCDS (tCK * parseUint(memspec["memtimingspec"], "CCDS")),
|
||||
tCCDL (tCK * parseUint(memspec["memtimingspec"], "CCDL")),
|
||||
tRL (tCK * parseUint(memspec["memtimingspec"], "CL")),
|
||||
tWCK2CKPIN (tCK * parseUint(memspec["memtimingspec"], "WCK2CKPIN")),
|
||||
tWCK2CK (tCK * parseUint(memspec["memtimingspec"], "WCK2CK")),
|
||||
tWCK2DQO (tCK * parseUint(memspec["memtimingspec"], "WCK2DQO")),
|
||||
tRTW (tCK * parseUint(memspec["memtimingspec"], "RTW")),
|
||||
tWL (tCK * parseUint(memspec["memtimingspec"], "WL")),
|
||||
tWCK2DQI (tCK * parseUint(memspec["memtimingspec"], "WCK2DQI")),
|
||||
tWR (tCK * parseUint(memspec["memtimingspec"], "WR")),
|
||||
tWTRS (tCK * parseUint(memspec["memtimingspec"], "WTRS")),
|
||||
tWTRL (tCK * parseUint(memspec["memtimingspec"], "WTRL")),
|
||||
tCKE (tCK * parseUint(memspec["memtimingspec"], "CKE")),
|
||||
tPD (tCK * parseUint(memspec["memtimingspec"], "PD")),
|
||||
tXP (tCK * parseUint(memspec["memtimingspec"], "XP")),
|
||||
tREFI (tCK * parseUint(memspec["memtimingspec"], "REFI")),
|
||||
tREFIPB (tCK * parseUint(memspec["memtimingspec"], "REFIPB")),
|
||||
tRFC (tCK * parseUint(memspec["memtimingspec"], "RFC")),
|
||||
tRFCPB (tCK * parseUint(memspec["memtimingspec"], "RFCPB")),
|
||||
tRREFD (tCK * parseUint(memspec["memtimingspec"], "RREFD")),
|
||||
tXS (tCK * parseUint(memspec["memtimingspec"], "XS")),
|
||||
tFAW (tCK * parseUint(memspec["memtimingspec"], "FAW")),
|
||||
t32AW (tCK * parseUint(memspec["memtimingspec"], "32AW")),
|
||||
tPPD (tCK * parseUint(memspec["memtimingspec"], "PPD")),
|
||||
tLK (tCK * parseUint(memspec["memtimingspec"], "LK")),
|
||||
tRTRS (tCK * parseUint(memspec["memtimingspec"], "RTRS"))
|
||||
MemSpecGDDR5X::MemSpecGDDR5X(const DRAMSysConfiguration::MemSpec &memSpec)
|
||||
: MemSpec(memSpec, MemoryType::GDDR5X,
|
||||
memSpec.memArchitectureSpec.entries.at("nbrOfChannels"),
|
||||
memSpec.memArchitectureSpec.entries.at("nbrOfRanks"),
|
||||
memSpec.memArchitectureSpec.entries.at("nbrOfBanks"),
|
||||
memSpec.memArchitectureSpec.entries.at("nbrOfBankGroups"),
|
||||
memSpec.memArchitectureSpec.entries.at("nbrOfBanks")
|
||||
/ memSpec.memArchitectureSpec.entries.at("nbrOfBankGroups"),
|
||||
memSpec.memArchitectureSpec.entries.at("nbrOfBanks")
|
||||
* memSpec.memArchitectureSpec.entries.at("nbrOfRanks"),
|
||||
memSpec.memArchitectureSpec.entries.at("nbrOfBankGroups")
|
||||
* memSpec.memArchitectureSpec.entries.at("nbrOfRanks"),
|
||||
memSpec.memArchitectureSpec.entries.at("nbrOfDevices")),
|
||||
tRP (tCK * memSpec.memTimingSpec.entries.at("RP")),
|
||||
tRAS (tCK * memSpec.memTimingSpec.entries.at("RAS")),
|
||||
tRC (tCK * memSpec.memTimingSpec.entries.at("RC")),
|
||||
tRCDRD (tCK * memSpec.memTimingSpec.entries.at("RCDRD")),
|
||||
tRCDWR (tCK * memSpec.memTimingSpec.entries.at("RCDWR")),
|
||||
tRTP (tCK * memSpec.memTimingSpec.entries.at("RTP")),
|
||||
tRRDS (tCK * memSpec.memTimingSpec.entries.at("RRDS")),
|
||||
tRRDL (tCK * memSpec.memTimingSpec.entries.at("RRDL")),
|
||||
tCCDS (tCK * memSpec.memTimingSpec.entries.at("CCDS")),
|
||||
tCCDL (tCK * memSpec.memTimingSpec.entries.at("CCDL")),
|
||||
tRL (tCK * memSpec.memTimingSpec.entries.at("CL")),
|
||||
tWCK2CKPIN (tCK * memSpec.memTimingSpec.entries.at("WCK2CKPIN")),
|
||||
tWCK2CK (tCK * memSpec.memTimingSpec.entries.at("WCK2CK")),
|
||||
tWCK2DQO (tCK * memSpec.memTimingSpec.entries.at("WCK2DQO")),
|
||||
tRTW (tCK * memSpec.memTimingSpec.entries.at("RTW")),
|
||||
tWL (tCK * memSpec.memTimingSpec.entries.at("WL")),
|
||||
tWCK2DQI (tCK * memSpec.memTimingSpec.entries.at("WCK2DQI")),
|
||||
tWR (tCK * memSpec.memTimingSpec.entries.at("WR")),
|
||||
tWTRS (tCK * memSpec.memTimingSpec.entries.at("WTRS")),
|
||||
tWTRL (tCK * memSpec.memTimingSpec.entries.at("WTRL")),
|
||||
tCKE (tCK * memSpec.memTimingSpec.entries.at("CKE")),
|
||||
tPD (tCK * memSpec.memTimingSpec.entries.at("PD")),
|
||||
tXP (tCK * memSpec.memTimingSpec.entries.at("XP")),
|
||||
tREFI (tCK * memSpec.memTimingSpec.entries.at("REFI")),
|
||||
tREFIPB (tCK * memSpec.memTimingSpec.entries.at("REFIPB")),
|
||||
tRFC (tCK * memSpec.memTimingSpec.entries.at("RFC")),
|
||||
tRFCPB (tCK * memSpec.memTimingSpec.entries.at("RFCPB")),
|
||||
tRREFD (tCK * memSpec.memTimingSpec.entries.at("RREFD")),
|
||||
tXS (tCK * memSpec.memTimingSpec.entries.at("XS")),
|
||||
tFAW (tCK * memSpec.memTimingSpec.entries.at("FAW")),
|
||||
t32AW (tCK * memSpec.memTimingSpec.entries.at("32AW")),
|
||||
tPPD (tCK * memSpec.memTimingSpec.entries.at("PPD")),
|
||||
tLK (tCK * memSpec.memTimingSpec.entries.at("LK")),
|
||||
tRTRS (tCK * memSpec.memTimingSpec.entries.at("TRS"))
|
||||
{
|
||||
uint64_t deviceSizeBits = static_cast<uint64_t>(banksPerRank) * numberOfRows * numberOfColumns * bitWidth;
|
||||
uint64_t deviceSizeBytes = deviceSizeBits / 8;
|
||||
|
||||
@@ -38,12 +38,11 @@
|
||||
|
||||
#include <systemc>
|
||||
#include "MemSpec.h"
|
||||
#include "../../common/third_party/nlohmann/single_include/nlohmann/json.hpp"
|
||||
|
||||
class MemSpecGDDR5X final : public MemSpec
|
||||
{
|
||||
public:
|
||||
explicit MemSpecGDDR5X(nlohmann::json &memspec);
|
||||
explicit MemSpecGDDR5X(const DRAMSysConfiguration::MemSpec &memSpec);
|
||||
|
||||
// Memspec Variables:
|
||||
const sc_core::sc_time tRP;
|
||||
|
||||
@@ -40,58 +40,57 @@
|
||||
|
||||
using namespace sc_core;
|
||||
using namespace tlm;
|
||||
using json = nlohmann::json;
|
||||
|
||||
MemSpecGDDR6::MemSpecGDDR6(json &memspec)
|
||||
: MemSpec(memspec, MemoryType::GDDR6,
|
||||
parseUint(memspec["memarchitecturespec"],"nbrOfChannels"),
|
||||
parseUint(memspec["memarchitecturespec"],"nbrOfRanks"),
|
||||
parseUint(memspec["memarchitecturespec"],"nbrOfBanks"),
|
||||
parseUint(memspec["memarchitecturespec"], "nbrOfBankGroups"),
|
||||
parseUint(memspec["memarchitecturespec"],"nbrOfBanks")
|
||||
/ parseUint(memspec["memarchitecturespec"], "nbrOfBankGroups"),
|
||||
parseUint(memspec["memarchitecturespec"],"nbrOfBanks")
|
||||
* parseUint(memspec["memarchitecturespec"],"nbrOfRanks"),
|
||||
parseUint(memspec["memarchitecturespec"], "nbrOfBankGroups")
|
||||
* parseUint(memspec["memarchitecturespec"],"nbrOfRanks"),
|
||||
parseUint(memspec["memarchitecturespec"],"nbrOfDevices")),
|
||||
per2BankOffset(parseUint(memspec["memarchitecturespec"], "per2BankOffset")),
|
||||
tRP (tCK * parseUint(memspec["memtimingspec"], "RP")),
|
||||
tRAS (tCK * parseUint(memspec["memtimingspec"], "RAS")),
|
||||
tRC (tCK * parseUint(memspec["memtimingspec"], "RC")),
|
||||
tRCDRD (tCK * parseUint(memspec["memtimingspec"], "RCDRD")),
|
||||
tRCDWR (tCK * parseUint(memspec["memtimingspec"], "RCDWR")),
|
||||
tRTP (tCK * parseUint(memspec["memtimingspec"], "RTP")),
|
||||
tRRDS (tCK * parseUint(memspec["memtimingspec"], "RRDS")),
|
||||
tRRDL (tCK * parseUint(memspec["memtimingspec"], "RRDL")),
|
||||
tCCDS (tCK * parseUint(memspec["memtimingspec"], "CCDS")),
|
||||
tCCDL (tCK * parseUint(memspec["memtimingspec"], "CCDL")),
|
||||
tRL (tCK * parseUint(memspec["memtimingspec"], "RL")),
|
||||
tWCK2CKPIN (tCK * parseUint(memspec["memtimingspec"], "WCK2CKPIN")),
|
||||
tWCK2CK (tCK * parseUint(memspec["memtimingspec"], "WCK2CK")),
|
||||
tWCK2DQO (tCK * parseUint(memspec["memtimingspec"], "WCK2DQO")),
|
||||
tRTW (tCK * parseUint(memspec["memtimingspec"], "RTW")),
|
||||
tWL (tCK * parseUint(memspec["memtimingspec"], "WL")),
|
||||
tWCK2DQI (tCK * parseUint(memspec["memtimingspec"], "WCK2DQI")),
|
||||
tWR (tCK * parseUint(memspec["memtimingspec"], "WR")),
|
||||
tWTRS (tCK * parseUint(memspec["memtimingspec"], "WTRS")),
|
||||
tWTRL (tCK * parseUint(memspec["memtimingspec"], "WTRL")),
|
||||
tPD (tCK * parseUint(memspec["memtimingspec"], "PD")),
|
||||
tCKESR (tCK * parseUint(memspec["memtimingspec"], "CKESR")),
|
||||
tXP (tCK * parseUint(memspec["memtimingspec"], "XP")),
|
||||
tREFI (tCK * parseUint(memspec["memtimingspec"], "REFI")),
|
||||
tREFIpb (tCK * parseUint(memspec["memtimingspec"], "REFIpb")),
|
||||
tRFCab (tCK * parseUint(memspec["memtimingspec"], "RFCab")),
|
||||
tRFCpb (tCK * parseUint(memspec["memtimingspec"], "RFCpb")),
|
||||
tRREFD (tCK * parseUint(memspec["memtimingspec"], "RREFD")),
|
||||
tXS (tCK * parseUint(memspec["memtimingspec"], "XS")),
|
||||
tFAW (tCK * parseUint(memspec["memtimingspec"], "FAW")),
|
||||
tPPD (tCK * parseUint(memspec["memtimingspec"], "PPD")),
|
||||
tLK (tCK * parseUint(memspec["memtimingspec"], "LK")),
|
||||
tACTPDE (tCK * parseUint(memspec["memtimingspec"], "ACTPDE")),
|
||||
tPREPDE (tCK * parseUint(memspec["memtimingspec"], "PREPDE")),
|
||||
tREFPDE (tCK * parseUint(memspec["memtimingspec"], "REFPDE")),
|
||||
tRTRS (tCK * parseUint(memspec["memtimingspec"], "RTRS"))
|
||||
MemSpecGDDR6::MemSpecGDDR6(const DRAMSysConfiguration::MemSpec &memSpec)
|
||||
: MemSpec(memSpec, MemoryType::GDDR6,
|
||||
memSpec.memArchitectureSpec.entries.at("nbrOfChannels"),
|
||||
memSpec.memArchitectureSpec.entries.at("nbrOfRanks"),
|
||||
memSpec.memArchitectureSpec.entries.at("nbrOfBanks"),
|
||||
memSpec.memArchitectureSpec.entries.at( "nbrOfBankGroups"),
|
||||
memSpec.memArchitectureSpec.entries.at("nbrOfBanks")
|
||||
/ memSpec.memArchitectureSpec.entries.at( "nbrOfBankGroups"),
|
||||
memSpec.memArchitectureSpec.entries.at("nbrOfBanks")
|
||||
* memSpec.memArchitectureSpec.entries.at("nbrOfRanks"),
|
||||
memSpec.memArchitectureSpec.entries.at( "nbrOfBankGroups")
|
||||
* memSpec.memArchitectureSpec.entries.at("nbrOfRanks"),
|
||||
memSpec.memArchitectureSpec.entries.at("nbrOfDevices")),
|
||||
per2BankOffset(memSpec.memArchitectureSpec.entries.at("per2BankOffset")),
|
||||
tRP (tCK * memSpec.memTimingSpec.entries.at("RP")),
|
||||
tRAS (tCK * memSpec.memTimingSpec.entries.at("RAS")),
|
||||
tRC (tCK * memSpec.memTimingSpec.entries.at("RC")),
|
||||
tRCDRD (tCK * memSpec.memTimingSpec.entries.at("RCDRD")),
|
||||
tRCDWR (tCK * memSpec.memTimingSpec.entries.at("RCDWR")),
|
||||
tRTP (tCK * memSpec.memTimingSpec.entries.at("RTP")),
|
||||
tRRDS (tCK * memSpec.memTimingSpec.entries.at("RRDS")),
|
||||
tRRDL (tCK * memSpec.memTimingSpec.entries.at("RRDL")),
|
||||
tCCDS (tCK * memSpec.memTimingSpec.entries.at("CCDS")),
|
||||
tCCDL (tCK * memSpec.memTimingSpec.entries.at("CCDL")),
|
||||
tRL (tCK * memSpec.memTimingSpec.entries.at("RL")),
|
||||
tWCK2CKPIN (tCK * memSpec.memTimingSpec.entries.at("WCK2CKPIN")),
|
||||
tWCK2CK (tCK * memSpec.memTimingSpec.entries.at("WCK2CK")),
|
||||
tWCK2DQO (tCK * memSpec.memTimingSpec.entries.at("WCK2DQO")),
|
||||
tRTW (tCK * memSpec.memTimingSpec.entries.at("RTW")),
|
||||
tWL (tCK * memSpec.memTimingSpec.entries.at("WL")),
|
||||
tWCK2DQI (tCK * memSpec.memTimingSpec.entries.at("WCK2DQI")),
|
||||
tWR (tCK * memSpec.memTimingSpec.entries.at("WR")),
|
||||
tWTRS (tCK * memSpec.memTimingSpec.entries.at("WTRS")),
|
||||
tWTRL (tCK * memSpec.memTimingSpec.entries.at("WTRL")),
|
||||
tPD (tCK * memSpec.memTimingSpec.entries.at("PD")),
|
||||
tCKESR (tCK * memSpec.memTimingSpec.entries.at("CKESR")),
|
||||
tXP (tCK * memSpec.memTimingSpec.entries.at("XP")),
|
||||
tREFI (tCK * memSpec.memTimingSpec.entries.at("REFI")),
|
||||
tREFIpb (tCK * memSpec.memTimingSpec.entries.at("REFIpb")),
|
||||
tRFCab (tCK * memSpec.memTimingSpec.entries.at("RFCab")),
|
||||
tRFCpb (tCK * memSpec.memTimingSpec.entries.at("RFCpb")),
|
||||
tRREFD (tCK * memSpec.memTimingSpec.entries.at("RREFD")),
|
||||
tXS (tCK * memSpec.memTimingSpec.entries.at("XS")),
|
||||
tFAW (tCK * memSpec.memTimingSpec.entries.at("FAW")),
|
||||
tPPD (tCK * memSpec.memTimingSpec.entries.at("PPD")),
|
||||
tLK (tCK * memSpec.memTimingSpec.entries.at("LK")),
|
||||
tACTPDE (tCK * memSpec.memTimingSpec.entries.at("ACTPDE")),
|
||||
tPREPDE (tCK * memSpec.memTimingSpec.entries.at("PREPDE")),
|
||||
tREFPDE (tCK * memSpec.memTimingSpec.entries.at("REFPDE")),
|
||||
tRTRS (tCK * memSpec.memTimingSpec.entries.at("RTRS"))
|
||||
{
|
||||
uint64_t deviceSizeBits = static_cast<uint64_t>(banksPerRank) * numberOfRows * numberOfColumns * bitWidth;
|
||||
uint64_t deviceSizeBytes = deviceSizeBits / 8;
|
||||
|
||||
@@ -38,12 +38,11 @@
|
||||
|
||||
#include <systemc>
|
||||
#include "MemSpec.h"
|
||||
#include "../../common/third_party/nlohmann/single_include/nlohmann/json.hpp"
|
||||
|
||||
struct MemSpecGDDR6 final : public MemSpec
|
||||
{
|
||||
public:
|
||||
explicit MemSpecGDDR6(nlohmann::json &memspec);
|
||||
explicit MemSpecGDDR6(const DRAMSysConfiguration::MemSpec &memSpec);
|
||||
|
||||
// Memspec Variables:
|
||||
const sc_core::sc_time tRP;
|
||||
|
||||
@@ -40,50 +40,49 @@
|
||||
|
||||
using namespace sc_core;
|
||||
using namespace tlm;
|
||||
using json = nlohmann::json;
|
||||
|
||||
MemSpecHBM2::MemSpecHBM2(json &memspec)
|
||||
: MemSpec(memspec, MemoryType::HBM2,
|
||||
parseUint(memspec["memarchitecturespec"],"nbrOfChannels"),
|
||||
parseUint(memspec["memarchitecturespec"],"nbrOfRanks"),
|
||||
parseUint(memspec["memarchitecturespec"],"nbrOfBanks"),
|
||||
parseUint(memspec["memarchitecturespec"], "nbrOfBankGroups"),
|
||||
parseUint(memspec["memarchitecturespec"],"nbrOfBanks")
|
||||
/ parseUint(memspec["memarchitecturespec"], "nbrOfBankGroups"),
|
||||
parseUint(memspec["memarchitecturespec"],"nbrOfBanks")
|
||||
* parseUint(memspec["memarchitecturespec"],"nbrOfRanks"),
|
||||
parseUint(memspec["memarchitecturespec"], "nbrOfBankGroups")
|
||||
* parseUint(memspec["memarchitecturespec"],"nbrOfRanks"),
|
||||
parseUint(memspec["memarchitecturespec"],"nbrOfDevices")),
|
||||
tDQSCK (tCK * parseUint(memspec["memtimingspec"], "DQSCK")),
|
||||
tRC (tCK * parseUint(memspec["memtimingspec"], "RC")),
|
||||
tRAS (tCK * parseUint(memspec["memtimingspec"], "RAS")),
|
||||
tRCDRD (tCK * parseUint(memspec["memtimingspec"], "RCDRD")),
|
||||
tRCDWR (tCK * parseUint(memspec["memtimingspec"], "RCDWR")),
|
||||
tRRDL (tCK * parseUint(memspec["memtimingspec"], "RRDL")),
|
||||
tRRDS (tCK * parseUint(memspec["memtimingspec"], "RRDS")),
|
||||
tFAW (tCK * parseUint(memspec["memtimingspec"], "FAW")),
|
||||
tRTP (tCK * parseUint(memspec["memtimingspec"], "RTP")),
|
||||
tRP (tCK * parseUint(memspec["memtimingspec"], "RP")),
|
||||
tRL (tCK * parseUint(memspec["memtimingspec"], "RL")),
|
||||
tWL (tCK * parseUint(memspec["memtimingspec"], "WL")),
|
||||
tPL (tCK * parseUint(memspec["memtimingspec"], "PL")),
|
||||
tWR (tCK * parseUint(memspec["memtimingspec"], "WR")),
|
||||
tCCDL (tCK * parseUint(memspec["memtimingspec"], "CCDL")),
|
||||
tCCDS (tCK * parseUint(memspec["memtimingspec"], "CCDS")),
|
||||
tWTRL (tCK * parseUint(memspec["memtimingspec"], "WTRL")),
|
||||
tWTRS (tCK * parseUint(memspec["memtimingspec"], "WTRS")),
|
||||
tRTW (tCK * parseUint(memspec["memtimingspec"], "RTW")),
|
||||
tXP (tCK * parseUint(memspec["memtimingspec"], "XP")),
|
||||
tCKE (tCK * parseUint(memspec["memtimingspec"], "CKE")),
|
||||
MemSpecHBM2::MemSpecHBM2(const DRAMSysConfiguration::MemSpec &memSpec)
|
||||
: MemSpec(memSpec, MemoryType::HBM2,
|
||||
memSpec.memArchitectureSpec.entries.at("nbrOfChannels"),
|
||||
memSpec.memArchitectureSpec.entries.at("nbrOfRanks"),
|
||||
memSpec.memArchitectureSpec.entries.at("nbrOfBanks"),
|
||||
memSpec.memArchitectureSpec.entries.at("nbrOfBankGroups"),
|
||||
memSpec.memArchitectureSpec.entries.at("nbrOfBanks")
|
||||
/ memSpec.memArchitectureSpec.entries.at("nbrOfBankGroups"),
|
||||
memSpec.memArchitectureSpec.entries.at("nbrOfBanks")
|
||||
* memSpec.memArchitectureSpec.entries.at("nbrOfRanks"),
|
||||
memSpec.memArchitectureSpec.entries.at("nbrOfBankGroups")
|
||||
* memSpec.memArchitectureSpec.entries.at("nbrOfRanks"),
|
||||
memSpec.memArchitectureSpec.entries.at("nbrOfDevices")),
|
||||
tDQSCK (tCK * memSpec.memTimingSpec.entries.at("DQSCK")),
|
||||
tRC (tCK * memSpec.memTimingSpec.entries.at("RC")),
|
||||
tRAS (tCK * memSpec.memTimingSpec.entries.at("RAS")),
|
||||
tRCDRD (tCK * memSpec.memTimingSpec.entries.at("RCDRD")),
|
||||
tRCDWR (tCK * memSpec.memTimingSpec.entries.at("RCDWR")),
|
||||
tRRDL (tCK * memSpec.memTimingSpec.entries.at("RRDL")),
|
||||
tRRDS (tCK * memSpec.memTimingSpec.entries.at("RRDS")),
|
||||
tFAW (tCK * memSpec.memTimingSpec.entries.at("FAW")),
|
||||
tRTP (tCK * memSpec.memTimingSpec.entries.at("RTP")),
|
||||
tRP (tCK * memSpec.memTimingSpec.entries.at("RP")),
|
||||
tRL (tCK * memSpec.memTimingSpec.entries.at("RL")),
|
||||
tWL (tCK * memSpec.memTimingSpec.entries.at("WL")),
|
||||
tPL (tCK * memSpec.memTimingSpec.entries.at("PL")),
|
||||
tWR (tCK * memSpec.memTimingSpec.entries.at("WR")),
|
||||
tCCDL (tCK * memSpec.memTimingSpec.entries.at("CCDL")),
|
||||
tCCDS (tCK * memSpec.memTimingSpec.entries.at("CCDS")),
|
||||
tWTRL (tCK * memSpec.memTimingSpec.entries.at("WTRL")),
|
||||
tWTRS (tCK * memSpec.memTimingSpec.entries.at("WTRS")),
|
||||
tRTW (tCK * memSpec.memTimingSpec.entries.at("RTW")),
|
||||
tXP (tCK * memSpec.memTimingSpec.entries.at("XP")),
|
||||
tCKE (tCK * memSpec.memTimingSpec.entries.at("CKE")),
|
||||
tPD (tCKE),
|
||||
tCKESR (tCKE + tCK),
|
||||
tXS (tCK * parseUint(memspec["memtimingspec"], "XS")),
|
||||
tRFC (tCK * parseUint(memspec["memtimingspec"], "RFC")),
|
||||
tRFCSB (tCK * parseUint(memspec["memtimingspec"], "RFCSB")),
|
||||
tRREFD (tCK * parseUint(memspec["memtimingspec"], "RREFD")),
|
||||
tREFI (tCK * parseUint(memspec["memtimingspec"], "REFI")),
|
||||
tREFISB (tCK * parseUint(memspec["memtimingspec"], "REFISB"))
|
||||
tXS (tCK * memSpec.memTimingSpec.entries.at("XS")),
|
||||
tRFC (tCK * memSpec.memTimingSpec.entries.at("RFC")),
|
||||
tRFCSB (tCK * memSpec.memTimingSpec.entries.at("RFCSB")),
|
||||
tRREFD (tCK * memSpec.memTimingSpec.entries.at("RREFD")),
|
||||
tREFI (tCK * memSpec.memTimingSpec.entries.at("REFI")),
|
||||
tREFISB (tCK * memSpec.memTimingSpec.entries.at("REFISB"))
|
||||
{
|
||||
commandLengthInCycles[Command::ACT] = 2;
|
||||
|
||||
|
||||
@@ -38,12 +38,11 @@
|
||||
|
||||
#include <systemc>
|
||||
#include "MemSpec.h"
|
||||
#include "../../common/third_party/nlohmann/single_include/nlohmann/json.hpp"
|
||||
|
||||
class MemSpecHBM2 final : public MemSpec
|
||||
{
|
||||
public:
|
||||
explicit MemSpecHBM2(nlohmann::json &memspec);
|
||||
explicit MemSpecHBM2(const DRAMSysConfiguration::MemSpec &memSpec);
|
||||
|
||||
// Memspec Variables:
|
||||
const sc_core::sc_time tDQSCK;
|
||||
|
||||
@@ -40,50 +40,49 @@
|
||||
|
||||
using namespace sc_core;
|
||||
using namespace tlm;
|
||||
using json = nlohmann::json;
|
||||
|
||||
MemSpecLPDDR4::MemSpecLPDDR4(json &memspec)
|
||||
: MemSpec(memspec, MemoryType::LPDDR4,
|
||||
parseUint(memspec["memarchitecturespec"],"nbrOfChannels"),
|
||||
parseUint(memspec["memarchitecturespec"],"nbrOfRanks"),
|
||||
parseUint(memspec["memarchitecturespec"],"nbrOfBanks"),
|
||||
MemSpecLPDDR4::MemSpecLPDDR4(const DRAMSysConfiguration::MemSpec &memSpec)
|
||||
: MemSpec(memSpec, MemoryType::LPDDR4,
|
||||
memSpec.memArchitectureSpec.entries.at("nbrOfChannels"),
|
||||
memSpec.memArchitectureSpec.entries.at("nbrOfRanks"),
|
||||
memSpec.memArchitectureSpec.entries.at("nbrOfBanks"),
|
||||
1,
|
||||
parseUint(memspec["memarchitecturespec"],"nbrOfBanks"),
|
||||
parseUint(memspec["memarchitecturespec"],"nbrOfBanks")
|
||||
* parseUint(memspec["memarchitecturespec"],"nbrOfRanks"),
|
||||
parseUint(memspec["memarchitecturespec"],"nbrOfRanks"),
|
||||
parseUint(memspec["memarchitecturespec"],"nbrOfDevices")),
|
||||
tREFI (tCK * parseUint(memspec["memtimingspec"], "REFI")),
|
||||
tREFIpb (tCK * parseUint(memspec["memtimingspec"], "REFIPB")),
|
||||
tRFCab (tCK * parseUint(memspec["memtimingspec"], "RFCAB")),
|
||||
tRFCpb (tCK * parseUint(memspec["memtimingspec"], "RFCPB")),
|
||||
tRPab (tCK * parseUint(memspec["memtimingspec"], "RPAB")),
|
||||
tRPpb (tCK * parseUint(memspec["memtimingspec"], "RPPB")),
|
||||
tRCab (tCK * parseUint(memspec["memtimingspec"], "RCAB")),
|
||||
tRCpb (tCK * parseUint(memspec["memtimingspec"], "RCPB")),
|
||||
tPPD (tCK * parseUint(memspec["memtimingspec"], "PPD")),
|
||||
tRAS (tCK * parseUint(memspec["memtimingspec"], "RAS")),
|
||||
tRCD (tCK * parseUint(memspec["memtimingspec"], "RCD")),
|
||||
tFAW (tCK * parseUint(memspec["memtimingspec"], "FAW")),
|
||||
tRRD (tCK * parseUint(memspec["memtimingspec"], "RRD")),
|
||||
tCCD (tCK * parseUint(memspec["memtimingspec"], "CCD")),
|
||||
tRL (tCK * parseUint(memspec["memtimingspec"], "RL")),
|
||||
tRPST (tCK * parseUint(memspec["memtimingspec"], "RPST")),
|
||||
tDQSCK (tCK * parseUint(memspec["memtimingspec"], "DQSCK")),
|
||||
tRTP (tCK * parseUint(memspec["memtimingspec"], "RTP")),
|
||||
tWL (tCK * parseUint(memspec["memtimingspec"], "WL")),
|
||||
tDQSS (tCK * parseUint(memspec["memtimingspec"], "DQSS")),
|
||||
tDQS2DQ (tCK * parseUint(memspec["memtimingspec"], "DQS2DQ")),
|
||||
tWR (tCK * parseUint(memspec["memtimingspec"], "WR")),
|
||||
tWPRE (tCK * parseUint(memspec["memtimingspec"], "WPRE")),
|
||||
tWTR (tCK * parseUint(memspec["memtimingspec"], "WTR")),
|
||||
tXP (tCK * parseUint(memspec["memtimingspec"], "XP")),
|
||||
tSR (tCK * parseUint(memspec["memtimingspec"], "SR")),
|
||||
tXSR (tCK * parseUint(memspec["memtimingspec"], "XSR")),
|
||||
tESCKE (tCK * parseUint(memspec["memtimingspec"], "ESCKE")),
|
||||
tCKE (tCK * parseUint(memspec["memtimingspec"], "CKE")),
|
||||
tCMDCKE (tCK * parseUint(memspec["memtimingspec"], "CMDCKE")),
|
||||
tRTRS (tCK * parseUint(memspec["memtimingspec"], "RTRS"))
|
||||
memSpec.memArchitectureSpec.entries.at("nbrOfBanks"),
|
||||
memSpec.memArchitectureSpec.entries.at("nbrOfBanks")
|
||||
* memSpec.memArchitectureSpec.entries.at("nbrOfRanks"),
|
||||
memSpec.memArchitectureSpec.entries.at("nbrOfRanks"),
|
||||
memSpec.memArchitectureSpec.entries.at("nbrOfDevices")),
|
||||
tREFI (tCK * memSpec.memTimingSpec.entries.at("REFI")),
|
||||
tREFIpb (tCK * memSpec.memTimingSpec.entries.at("REFIPB")),
|
||||
tRFCab (tCK * memSpec.memTimingSpec.entries.at("RFCAB")),
|
||||
tRFCpb (tCK * memSpec.memTimingSpec.entries.at("RFCPB")),
|
||||
tRPab (tCK * memSpec.memTimingSpec.entries.at("RPAB")),
|
||||
tRPpb (tCK * memSpec.memTimingSpec.entries.at("RPPB")),
|
||||
tRCab (tCK * memSpec.memTimingSpec.entries.at("RCAB")),
|
||||
tRCpb (tCK * memSpec.memTimingSpec.entries.at("RCPB")),
|
||||
tPPD (tCK * memSpec.memTimingSpec.entries.at("PPD")),
|
||||
tRAS (tCK * memSpec.memTimingSpec.entries.at("RAS")),
|
||||
tRCD (tCK * memSpec.memTimingSpec.entries.at("RCD")),
|
||||
tFAW (tCK * memSpec.memTimingSpec.entries.at("FAW")),
|
||||
tRRD (tCK * memSpec.memTimingSpec.entries.at("RRD")),
|
||||
tCCD (tCK * memSpec.memTimingSpec.entries.at("CCD")),
|
||||
tRL (tCK * memSpec.memTimingSpec.entries.at("RL")),
|
||||
tRPST (tCK * memSpec.memTimingSpec.entries.at("RPST")),
|
||||
tDQSCK (tCK * memSpec.memTimingSpec.entries.at("DQSCK")),
|
||||
tRTP (tCK * memSpec.memTimingSpec.entries.at("RTP")),
|
||||
tWL (tCK * memSpec.memTimingSpec.entries.at("WL")),
|
||||
tDQSS (tCK * memSpec.memTimingSpec.entries.at("DQSS")),
|
||||
tDQS2DQ (tCK * memSpec.memTimingSpec.entries.at("DQS2DQ")),
|
||||
tWR (tCK * memSpec.memTimingSpec.entries.at("WR")),
|
||||
tWPRE (tCK * memSpec.memTimingSpec.entries.at("WPRE")),
|
||||
tWTR (tCK * memSpec.memTimingSpec.entries.at("WTR")),
|
||||
tXP (tCK * memSpec.memTimingSpec.entries.at("XP")),
|
||||
tSR (tCK * memSpec.memTimingSpec.entries.at("SR")),
|
||||
tXSR (tCK * memSpec.memTimingSpec.entries.at("XSR")),
|
||||
tESCKE (tCK * memSpec.memTimingSpec.entries.at("ESCKE")),
|
||||
tCKE (tCK * memSpec.memTimingSpec.entries.at("CKE")),
|
||||
tCMDCKE (tCK * memSpec.memTimingSpec.entries.at("CMDCKE")),
|
||||
tRTRS (tCK * memSpec.memTimingSpec.entries.at("RTRS"))
|
||||
{
|
||||
commandLengthInCycles[Command::ACT] = 4;
|
||||
commandLengthInCycles[Command::PREPB] = 2;
|
||||
|
||||
@@ -38,12 +38,11 @@
|
||||
|
||||
#include <systemc>
|
||||
#include "MemSpec.h"
|
||||
#include "../../common/third_party/nlohmann/single_include/nlohmann/json.hpp"
|
||||
|
||||
class MemSpecLPDDR4 final : public MemSpec
|
||||
{
|
||||
public:
|
||||
explicit MemSpecLPDDR4(nlohmann::json &memspec);
|
||||
explicit MemSpecLPDDR4(const DRAMSysConfiguration::MemSpec &memSpec);
|
||||
|
||||
// Memspec Variables:
|
||||
const sc_core::sc_time tREFI;
|
||||
|
||||
@@ -40,44 +40,43 @@
|
||||
|
||||
using namespace sc_core;
|
||||
using namespace tlm;
|
||||
using json = nlohmann::json;
|
||||
|
||||
MemSpecLPDDR5::MemSpecLPDDR5(json &memspec)
|
||||
: MemSpec(memspec, MemoryType::LPDDR5,
|
||||
parseUint(memspec["memarchitecturespec"],"nbrOfChannels"),
|
||||
parseUint(memspec["memarchitecturespec"],"nbrOfRanks"),
|
||||
parseUint(memspec["memarchitecturespec"],"nbrOfBanks"),
|
||||
parseUint(memspec["memarchitecturespec"], "nbrOfBankGroups"),
|
||||
parseUint(memspec["memarchitecturespec"],"nbrOfBanks")
|
||||
/ parseUint(memspec["memarchitecturespec"], "nbrOfBankGroups"),
|
||||
parseUint(memspec["memarchitecturespec"],"nbrOfBanks")
|
||||
* parseUint(memspec["memarchitecturespec"],"nbrOfRanks"),
|
||||
parseUint(memspec["memarchitecturespec"], "nbrOfBankGroups")
|
||||
* parseUint(memspec["memarchitecturespec"],"nbrOfRanks"),
|
||||
parseUint(memspec["memarchitecturespec"],"nbrOfDevices")),
|
||||
per2BankOffset(parseUint(memspec["memarchitecturespec"], "per2BankOffset")),
|
||||
tREFI (tCK * parseUint(memspec["memtimingspec"], "REFI")),
|
||||
tREFIpb (tCK * parseUint(memspec["memtimingspec"], "REFIpb")),
|
||||
tRFCab (tCK * parseUint(memspec["memtimingspec"], "RFCab")),
|
||||
tRFCpb (tCK * parseUint(memspec["memtimingspec"], "RFCpb")),
|
||||
tRPab (tCK * parseUint(memspec["memtimingspec"], "RPab")),
|
||||
tRPpb (tCK * parseUint(memspec["memtimingspec"], "RPpb")),
|
||||
tRCab (tCK * parseUint(memspec["memtimingspec"], "RCab")),
|
||||
tRCpb (tCK * parseUint(memspec["memtimingspec"], "RCpb")),
|
||||
tPPD (tCK * parseUint(memspec["memtimingspec"], "PPD")),
|
||||
tRAS (tCK * parseUint(memspec["memtimingspec"], "RAS")),
|
||||
tRCD (tCK * parseUint(memspec["memtimingspec"], "RCD")),
|
||||
tFAW (tCK * parseUint(memspec["memtimingspec"], "FAW")),
|
||||
tRRD (tCK * parseUint(memspec["memtimingspec"], "RRD")),
|
||||
MemSpecLPDDR5::MemSpecLPDDR5(const DRAMSysConfiguration::MemSpec &memSpec)
|
||||
: MemSpec(memSpec, MemoryType::LPDDR5,
|
||||
memSpec.memArchitectureSpec.entries.at("nbrOfChannels"),
|
||||
memSpec.memArchitectureSpec.entries.at("nbrOfRanks"),
|
||||
memSpec.memArchitectureSpec.entries.at("nbrOfBanks"),
|
||||
memSpec.memArchitectureSpec.entries.at("nbrOfBankGroups"),
|
||||
memSpec.memArchitectureSpec.entries.at("nbrOfBanks")
|
||||
/ memSpec.memArchitectureSpec.entries.at("nbrOfBankGroups"),
|
||||
memSpec.memArchitectureSpec.entries.at("nbrOfBanks")
|
||||
* memSpec.memArchitectureSpec.entries.at("nbrOfRanks"),
|
||||
memSpec.memArchitectureSpec.entries.at("nbrOfBankGroups")
|
||||
* memSpec.memArchitectureSpec.entries.at("nbrOfRanks"),
|
||||
memSpec.memArchitectureSpec.entries.at("nbrOfDevices")),
|
||||
per2BankOffset(memSpec.memArchitectureSpec.entries.at("per2BankOffset")),
|
||||
tREFI (tCK * memSpec.memTimingSpec.entries.at("REFI")),
|
||||
tREFIpb (tCK * memSpec.memTimingSpec.entries.at("REFIpb")),
|
||||
tRFCab (tCK * memSpec.memTimingSpec.entries.at("RFCab")),
|
||||
tRFCpb (tCK * memSpec.memTimingSpec.entries.at("RFCpb")),
|
||||
tRPab (tCK * memSpec.memTimingSpec.entries.at("RPab")),
|
||||
tRPpb (tCK * memSpec.memTimingSpec.entries.at("RPpb")),
|
||||
tRCab (tCK * memSpec.memTimingSpec.entries.at("RCab")),
|
||||
tRCpb (tCK * memSpec.memTimingSpec.entries.at("RCpb")),
|
||||
tPPD (tCK * memSpec.memTimingSpec.entries.at("PPD")),
|
||||
tRAS (tCK * memSpec.memTimingSpec.entries.at("RAS")),
|
||||
tRCD (tCK * memSpec.memTimingSpec.entries.at("RCD")),
|
||||
tFAW (tCK * memSpec.memTimingSpec.entries.at("FAW")),
|
||||
tRRD (tCK * memSpec.memTimingSpec.entries.at("RRD")),
|
||||
//tCCD (tCK * parseUint(memspec["memtimingspec"], "CCD")),
|
||||
tRL (tCK * parseUint(memspec["memtimingspec"], "RL")),
|
||||
tRL (tCK * memSpec.memTimingSpec.entries.at("RL")),
|
||||
//tRPST (tCK * parseUint(memspec["memtimingspec"], "RPST")),
|
||||
//tDQSCK (tCK * parseUint(memspec["memtimingspec"], "DQSCK")),
|
||||
tRBTP (tCK * parseUint(memspec["memtimingspec"], "RBTP")),
|
||||
tWL (tCK * parseUint(memspec["memtimingspec"], "WL")),
|
||||
tRBTP (tCK * memSpec.memTimingSpec.entries.at("RBTP")),
|
||||
tWL (tCK * memSpec.memTimingSpec.entries.at("WL")),
|
||||
//tDQSS (tCK * parseUint(memspec["memtimingspec"], "DQSS")),
|
||||
//tDQS2DQ (tCK * parseUint(memspec["memtimingspec"], "DQS2DQ")),
|
||||
tWR (tCK * parseUint(memspec["memtimingspec"], "WR")),
|
||||
tWR (tCK * memSpec.memTimingSpec.entries.at("WR")),
|
||||
//tWPRE (tCK * parseUint(memspec["memtimingspec"], "WPRE")),
|
||||
//tWTR (tCK * parseUint(memspec["memtimingspec"], "WTR")),
|
||||
//tXP (tCK * parseUint(memspec["memtimingspec"] "XP")),
|
||||
@@ -86,20 +85,20 @@ MemSpecLPDDR5::MemSpecLPDDR5(json &memspec)
|
||||
//tESCKE (tCK * parseUint(memspec["memtimingspec"], "ESCKE")),
|
||||
//tCKE (tCK * parseUint(memspec["memtimingspec"], "CKE")),
|
||||
//tCMDCKE (tCK * parseUint(memspec["memtimingspec"], "CMDCKE")),
|
||||
BL_n_min_16(tCK * parseUint(memspec["memtimingspec"], "BL_n_min_16")),
|
||||
BL_n_max_16(tCK * parseUint(memspec["memtimingspec"], "BL_n_max_16")),
|
||||
BL_n_L_16(tCK * parseUint(memspec["memtimingspec"], "BL_n_L_16")),
|
||||
BL_n_S_16(tCK * parseUint(memspec["memtimingspec"], "BL_n_S_16")),
|
||||
BL_n_min_32(tCK * parseUint(memspec["memtimingspec"], "BL_n_min_32")),
|
||||
BL_n_max_32(tCK * parseUint(memspec["memtimingspec"], "BL_n_max_32")),
|
||||
BL_n_L_32(tCK * parseUint(memspec["memtimingspec"], "BL_n_L_32")),
|
||||
BL_n_S_32(tCK * parseUint(memspec["memtimingspec"], "BL_n_S_32")),
|
||||
tWTR_L (tCK * parseUint(memspec["memtimingspec"], "WTR_L")),
|
||||
tWTR_S (tCK * parseUint(memspec["memtimingspec"], "WTR_S")),
|
||||
tWCK2DQO(tCK * parseUint(memspec["memtimingspec"], "WCK2DQO")),
|
||||
tpbR2act(tCK * parseUint(memspec["memtimingspec"], "pbR2act")),
|
||||
tpbR2pbR(tCK * parseUint(memspec["memtimingspec"], "pbR2pbR")),
|
||||
tRTRS (tCK * parseUint(memspec["memtimingspec"], "RTRS"))
|
||||
BL_n_min_16(tCK * memSpec.memTimingSpec.entries.at("BL_n_min_16")),
|
||||
BL_n_max_16(tCK * memSpec.memTimingSpec.entries.at("BL_n_max_16")),
|
||||
BL_n_L_16(tCK * memSpec.memTimingSpec.entries.at("BL_n_L_16")),
|
||||
BL_n_S_16(tCK * memSpec.memTimingSpec.entries.at("BL_n_S_16")),
|
||||
BL_n_min_32(tCK * memSpec.memTimingSpec.entries.at("BL_n_min_32")),
|
||||
BL_n_max_32(tCK * memSpec.memTimingSpec.entries.at("BL_n_max_32")),
|
||||
BL_n_L_32(tCK * memSpec.memTimingSpec.entries.at("BL_n_L_32")),
|
||||
BL_n_S_32(tCK * memSpec.memTimingSpec.entries.at("BL_n_S_32")),
|
||||
tWTR_L (tCK * memSpec.memTimingSpec.entries.at("WTR_L")),
|
||||
tWTR_S (tCK * memSpec.memTimingSpec.entries.at("WTR_S")),
|
||||
tWCK2DQO(tCK * memSpec.memTimingSpec.entries.at("WCK2DQO")),
|
||||
tpbR2act(tCK * memSpec.memTimingSpec.entries.at("pbR2act")),
|
||||
tpbR2pbR(tCK * memSpec.memTimingSpec.entries.at("pbR2pbR")),
|
||||
tRTRS (tCK * memSpec.memTimingSpec.entries.at("RTRS"))
|
||||
{
|
||||
commandLengthInCycles[Command::ACT] = 2;
|
||||
|
||||
|
||||
@@ -43,7 +43,7 @@
|
||||
class MemSpecLPDDR5 final : public MemSpec
|
||||
{
|
||||
public:
|
||||
explicit MemSpecLPDDR5(nlohmann::json &memspec);
|
||||
explicit MemSpecLPDDR5(const DRAMSysConfiguration::MemSpec &memSpec);
|
||||
|
||||
// Memspec Variables:
|
||||
const sc_core::sc_time tREFI;
|
||||
|
||||
@@ -40,43 +40,42 @@
|
||||
|
||||
using namespace sc_core;
|
||||
using namespace tlm;
|
||||
using json = nlohmann::json;
|
||||
|
||||
MemSpecSTTMRAM::MemSpecSTTMRAM(json &memspec)
|
||||
: MemSpec(memspec, MemoryType::STTMRAM,
|
||||
parseUint(memspec["memarchitecturespec"],"nbrOfChannels"),
|
||||
parseUint(memspec["memarchitecturespec"],"nbrOfRanks"),
|
||||
parseUint(memspec["memarchitecturespec"],"nbrOfBanks"),
|
||||
MemSpecSTTMRAM::MemSpecSTTMRAM(const DRAMSysConfiguration::MemSpec &memSpec)
|
||||
: MemSpec(memSpec, MemoryType::STTMRAM,
|
||||
memSpec.memArchitectureSpec.entries.at("nbrOfChannels"),
|
||||
memSpec.memArchitectureSpec.entries.at("nbrOfRanks"),
|
||||
memSpec.memArchitectureSpec.entries.at("nbrOfBanks"),
|
||||
1,
|
||||
parseUint(memspec["memarchitecturespec"],"nbrOfBanks"),
|
||||
parseUint(memspec["memarchitecturespec"],"nbrOfBanks")
|
||||
* parseUint(memspec["memarchitecturespec"],"nbrOfRanks"),
|
||||
parseUint(memspec["memarchitecturespec"],"nbrOfRanks"),
|
||||
parseUint(memspec["memarchitecturespec"],"nbrOfDevices")),
|
||||
tCKE (tCK * parseUint(memspec["memtimingspec"], "CKE")),
|
||||
memSpec.memArchitectureSpec.entries.at("nbrOfBanks"),
|
||||
memSpec.memArchitectureSpec.entries.at("nbrOfBanks")
|
||||
* memSpec.memArchitectureSpec.entries.at("nbrOfRanks"),
|
||||
memSpec.memArchitectureSpec.entries.at("nbrOfRanks"),
|
||||
memSpec.memArchitectureSpec.entries.at("nbrOfDevices")),
|
||||
tCKE (tCK * memSpec.memTimingSpec.entries.at("CKE")),
|
||||
tPD (tCKE),
|
||||
tCKESR (tCK * parseUint(memspec["memtimingspec"], "CKESR")),
|
||||
tDQSCK (tCK * parseUint(memspec["memtimingspec"], "DQSCK")),
|
||||
tRAS (tCK * parseUint(memspec["memtimingspec"], "RAS")),
|
||||
tRC (tCK * parseUint(memspec["memtimingspec"], "RC")),
|
||||
tRCD (tCK * parseUint(memspec["memtimingspec"], "RCD")),
|
||||
tRL (tCK * parseUint(memspec["memtimingspec"], "RL")),
|
||||
tRTP (tCK * parseUint(memspec["memtimingspec"], "RTP")),
|
||||
tWL (tCK * parseUint(memspec["memtimingspec"], "WL")),
|
||||
tWR (tCK * parseUint(memspec["memtimingspec"], "WR")),
|
||||
tXP (tCK * parseUint(memspec["memtimingspec"], "XP")),
|
||||
tXS (tCK * parseUint(memspec["memtimingspec"], "XS")),
|
||||
tCCD (tCK * parseUint(memspec["memtimingspec"], "CCD")),
|
||||
tFAW (tCK * parseUint(memspec["memtimingspec"], "FAW")),
|
||||
tRP (tCK * parseUint(memspec["memtimingspec"], "RP")),
|
||||
tRRD (tCK * parseUint(memspec["memtimingspec"], "RRD")),
|
||||
tWTR (tCK * parseUint(memspec["memtimingspec"], "WTR")),
|
||||
tAL (tCK * parseUint(memspec["memtimingspec"], "AL")),
|
||||
tXPDLL (tCK * parseUint(memspec["memtimingspec"], "XPDLL")),
|
||||
tXSDLL (tCK * parseUint(memspec["memtimingspec"], "XSDLL")),
|
||||
tACTPDEN (tCK * parseUint(memspec["memtimingspec"], "ACTPDEN")),
|
||||
tPRPDEN (tCK * parseUint(memspec["memtimingspec"], "PRPDEN")),
|
||||
tRTRS (tCK * parseUint(memspec["memtimingspec"], "RTRS"))
|
||||
tCKESR (tCK * memSpec.memTimingSpec.entries.at("CKESR")),
|
||||
tDQSCK (tCK * memSpec.memTimingSpec.entries.at("DQSCK")),
|
||||
tRAS (tCK * memSpec.memTimingSpec.entries.at("RAS")),
|
||||
tRC (tCK * memSpec.memTimingSpec.entries.at("RC")),
|
||||
tRCD (tCK * memSpec.memTimingSpec.entries.at("RCD")),
|
||||
tRL (tCK * memSpec.memTimingSpec.entries.at("RL")),
|
||||
tRTP (tCK * memSpec.memTimingSpec.entries.at("RTP")),
|
||||
tWL (tCK * memSpec.memTimingSpec.entries.at("WL")),
|
||||
tWR (tCK * memSpec.memTimingSpec.entries.at("WR")),
|
||||
tXP (tCK * memSpec.memTimingSpec.entries.at("XP")),
|
||||
tXS (tCK * memSpec.memTimingSpec.entries.at("XS")),
|
||||
tCCD (tCK * memSpec.memTimingSpec.entries.at("CCD")),
|
||||
tFAW (tCK * memSpec.memTimingSpec.entries.at("FAW")),
|
||||
tRP (tCK * memSpec.memTimingSpec.entries.at("RP")),
|
||||
tRRD (tCK * memSpec.memTimingSpec.entries.at("RRD")),
|
||||
tWTR (tCK * memSpec.memTimingSpec.entries.at("WTR")),
|
||||
tAL (tCK * memSpec.memTimingSpec.entries.at("AL")),
|
||||
tXPDLL (tCK * memSpec.memTimingSpec.entries.at("XPDLL")),
|
||||
tXSDLL (tCK * memSpec.memTimingSpec.entries.at("XSDLL")),
|
||||
tACTPDEN (tCK * memSpec.memTimingSpec.entries.at("ACTPDEN")),
|
||||
tPRPDEN (tCK * memSpec.memTimingSpec.entries.at("PRPDEN")),
|
||||
tRTRS (tCK * memSpec.memTimingSpec.entries.at("RTRS"))
|
||||
{
|
||||
uint64_t deviceSizeBits = static_cast<uint64_t>(banksPerRank) * numberOfRows * numberOfColumns * bitWidth;
|
||||
uint64_t deviceSizeBytes = deviceSizeBits / 8;
|
||||
|
||||
@@ -38,12 +38,11 @@
|
||||
|
||||
#include <systemc>
|
||||
#include "MemSpec.h"
|
||||
#include "../../common/third_party/nlohmann/single_include/nlohmann/json.hpp"
|
||||
|
||||
class MemSpecSTTMRAM final : public MemSpec
|
||||
{
|
||||
public:
|
||||
explicit MemSpecSTTMRAM(nlohmann::json &memspec);
|
||||
explicit MemSpecSTTMRAM(const DRAMSysConfiguration::MemSpec &memSpec);
|
||||
|
||||
// Memspec Variables:
|
||||
const sc_core::sc_time tCKE;
|
||||
|
||||
@@ -40,69 +40,71 @@
|
||||
|
||||
using namespace sc_core;
|
||||
using namespace tlm;
|
||||
using json = nlohmann::json;
|
||||
|
||||
MemSpecWideIO::MemSpecWideIO(json &memspec)
|
||||
: MemSpec(memspec, MemoryType::WideIO,
|
||||
parseUint(memspec["memarchitecturespec"],"nbrOfChannels"),
|
||||
parseUint(memspec["memarchitecturespec"],"nbrOfRanks"),
|
||||
parseUint(memspec["memarchitecturespec"],"nbrOfBanks"),
|
||||
MemSpecWideIO::MemSpecWideIO(const DRAMSysConfiguration::MemSpec &memSpec)
|
||||
: MemSpec(memSpec, MemoryType::WideIO,
|
||||
memSpec.memArchitectureSpec.entries.at("nbrOfChannels"),
|
||||
memSpec.memArchitectureSpec.entries.at("nbrOfRanks"),
|
||||
memSpec.memArchitectureSpec.entries.at("nbrOfBanks"),
|
||||
1,
|
||||
parseUint(memspec["memarchitecturespec"],"nbrOfBanks"),
|
||||
parseUint(memspec["memarchitecturespec"],"nbrOfBanks")
|
||||
* parseUint(memspec["memarchitecturespec"],"nbrOfRanks"),
|
||||
parseUint(memspec["memarchitecturespec"],"nbrOfRanks"),
|
||||
parseUint(memspec["memarchitecturespec"],"nbrOfDevices")),
|
||||
tCKE (tCK * parseUint(memspec["memtimingspec"], "CKE")),
|
||||
tCKESR (tCK * parseUint(memspec["memtimingspec"], "CKESR")),
|
||||
tDQSCK (tCK * parseUint(memspec["memtimingspec"], "DQSCK")),
|
||||
tAC (tCK * parseUint(memspec["memtimingspec"], "AC")),
|
||||
tRAS (tCK * parseUint(memspec["memtimingspec"], "RAS")),
|
||||
tRC (tCK * parseUint(memspec["memtimingspec"], "RC")),
|
||||
tRCD (tCK * parseUint(memspec["memtimingspec"], "RCD")),
|
||||
tRL (tCK * parseUint(memspec["memtimingspec"], "RL")),
|
||||
tWL (tCK * parseUint(memspec["memtimingspec"], "WL")),
|
||||
tWR (tCK * parseUint(memspec["memtimingspec"], "WR")),
|
||||
tXP (tCK * parseUint(memspec["memtimingspec"], "XP")),
|
||||
tXSR (tCK * parseUint(memspec["memtimingspec"], "XSR")),
|
||||
tCCD_R (tCK * parseUint(memspec["memtimingspec"], "CCD_R")),
|
||||
tCCD_W (tCK * parseUint(memspec["memtimingspec"], "CCD_W")),
|
||||
tREFI (tCK * parseUint(memspec["memtimingspec"], "REFI")),
|
||||
tRFC (tCK * parseUint(memspec["memtimingspec"], "RFC")),
|
||||
tRP (tCK * parseUint(memspec["memtimingspec"], "RP")),
|
||||
tRRD (tCK * parseUint(memspec["memtimingspec"], "RRD")),
|
||||
tTAW (tCK * parseUint(memspec["memtimingspec"], "TAW")),
|
||||
tWTR (tCK * parseUint(memspec["memtimingspec"], "WTR")),
|
||||
tRTRS (tCK * parseUint(memspec["memtimingspec"], "RTRS")),
|
||||
iDD0 (parseUdouble(memspec["mempowerspec"], "idd0")),
|
||||
iDD2N (parseUdouble(memspec["mempowerspec"], "idd2n")),
|
||||
iDD3N (parseUdouble(memspec["mempowerspec"], "idd3n")),
|
||||
iDD4R (parseUdouble(memspec["mempowerspec"], "idd4r")),
|
||||
iDD4W (parseUdouble(memspec["mempowerspec"], "idd4w")),
|
||||
iDD5 (parseUdouble(memspec["mempowerspec"], "idd5")),
|
||||
iDD6 (parseUdouble(memspec["mempowerspec"], "idd6")),
|
||||
vDD (parseUdouble(memspec["mempowerspec"], "vdd")),
|
||||
iDD02 (parseUdouble(memspec["mempowerspec"], "idd02")),
|
||||
iDD2P0 (parseUdouble(memspec["mempowerspec"], "idd2p0")),
|
||||
iDD2P02 (parseUdouble(memspec["mempowerspec"], "idd2p02")),
|
||||
iDD2P1 (parseUdouble(memspec["mempowerspec"], "idd2p1")),
|
||||
iDD2P12 (parseUdouble(memspec["mempowerspec"], "idd2p12")),
|
||||
iDD2N2 (parseUdouble(memspec["mempowerspec"], "idd2n2")),
|
||||
iDD3P0 (parseUdouble(memspec["mempowerspec"], "idd3p0")),
|
||||
iDD3P02 (parseUdouble(memspec["mempowerspec"], "idd3p02")),
|
||||
iDD3P1 (parseUdouble(memspec["mempowerspec"], "idd3p1")),
|
||||
iDD3P12 (parseUdouble(memspec["mempowerspec"], "idd3p12")),
|
||||
iDD3N2 (parseUdouble(memspec["mempowerspec"], "idd3n2")),
|
||||
iDD4R2 (parseUdouble(memspec["mempowerspec"], "idd4r2")),
|
||||
iDD4W2 (parseUdouble(memspec["mempowerspec"], "idd4w2")),
|
||||
iDD52 (parseUdouble(memspec["mempowerspec"], "idd52")),
|
||||
iDD62 (parseUdouble(memspec["mempowerspec"], "idd62")),
|
||||
vDD2 (parseUdouble(memspec["mempowerspec"], "vdd2"))
|
||||
memSpec.memArchitectureSpec.entries.at("nbrOfBanks"),
|
||||
memSpec.memArchitectureSpec.entries.at("nbrOfBanks")
|
||||
* memSpec.memArchitectureSpec.entries.at("nbrOfRanks"),
|
||||
memSpec.memArchitectureSpec.entries.at("nbrOfRanks"),
|
||||
memSpec.memArchitectureSpec.entries.at("nbrOfDevices")),
|
||||
tCKE (tCK * memSpec.memTimingSpec.entries.at("CKE")),
|
||||
tCKESR (tCK * memSpec.memTimingSpec.entries.at("CKESR")),
|
||||
tDQSCK (tCK * memSpec.memTimingSpec.entries.at("DQSCK")),
|
||||
tAC (tCK * memSpec.memTimingSpec.entries.at("AC")),
|
||||
tRAS (tCK * memSpec.memTimingSpec.entries.at("RAS")),
|
||||
tRC (tCK * memSpec.memTimingSpec.entries.at("RC")),
|
||||
tRCD (tCK * memSpec.memTimingSpec.entries.at("RCD")),
|
||||
tRL (tCK * memSpec.memTimingSpec.entries.at("RL")),
|
||||
tWL (tCK * memSpec.memTimingSpec.entries.at("WL")),
|
||||
tWR (tCK * memSpec.memTimingSpec.entries.at("WR")),
|
||||
tXP (tCK * memSpec.memTimingSpec.entries.at("XP")),
|
||||
tXSR (tCK * memSpec.memTimingSpec.entries.at("XSR")),
|
||||
tCCD_R (tCK * memSpec.memTimingSpec.entries.at("CCD_R")),
|
||||
tCCD_W (tCK * memSpec.memTimingSpec.entries.at("CCD_W")),
|
||||
tREFI (tCK * memSpec.memTimingSpec.entries.at("REFI")),
|
||||
tRFC (tCK * memSpec.memTimingSpec.entries.at("RFC")),
|
||||
tRP (tCK * memSpec.memTimingSpec.entries.at("RP")),
|
||||
tRRD (tCK * memSpec.memTimingSpec.entries.at("RRD")),
|
||||
tTAW (tCK * memSpec.memTimingSpec.entries.at("TAW")),
|
||||
tWTR (tCK * memSpec.memTimingSpec.entries.at("WTR")),
|
||||
tRTRS (tCK * memSpec.memTimingSpec.entries.at("RTRS")),
|
||||
iDD0 (memSpec.memPowerSpec.getValue().entries.at("idd0")),
|
||||
iDD2N (memSpec.memPowerSpec.getValue().entries.at("idd2n")),
|
||||
iDD3N (memSpec.memPowerSpec.getValue().entries.at("idd3n")),
|
||||
iDD4R (memSpec.memPowerSpec.getValue().entries.at("idd4r")),
|
||||
iDD4W (memSpec.memPowerSpec.getValue().entries.at("idd4w")),
|
||||
iDD5 (memSpec.memPowerSpec.getValue().entries.at("idd5")),
|
||||
iDD6 (memSpec.memPowerSpec.getValue().entries.at("idd6")),
|
||||
vDD (memSpec.memPowerSpec.getValue().entries.at("vdd")),
|
||||
iDD02 (memSpec.memPowerSpec.getValue().entries.at("idd02")),
|
||||
iDD2P0 (memSpec.memPowerSpec.getValue().entries.at("idd2p0")),
|
||||
iDD2P02 (memSpec.memPowerSpec.getValue().entries.at("idd2p02")),
|
||||
iDD2P1 (memSpec.memPowerSpec.getValue().entries.at("idd2p1")),
|
||||
iDD2P12 (memSpec.memPowerSpec.getValue().entries.at("idd2p12")),
|
||||
iDD2N2 (memSpec.memPowerSpec.getValue().entries.at("idd2n2")),
|
||||
iDD3P0 (memSpec.memPowerSpec.getValue().entries.at("idd3p0")),
|
||||
iDD3P02 (memSpec.memPowerSpec.getValue().entries.at("idd3p02")),
|
||||
iDD3P1 (memSpec.memPowerSpec.getValue().entries.at("idd3p1")),
|
||||
iDD3P12 (memSpec.memPowerSpec.getValue().entries.at("idd3p12")),
|
||||
iDD3N2 (memSpec.memPowerSpec.getValue().entries.at("idd3n2")),
|
||||
iDD4R2 (memSpec.memPowerSpec.getValue().entries.at("idd4r2")),
|
||||
iDD4W2 (memSpec.memPowerSpec.getValue().entries.at("idd4w2")),
|
||||
iDD52 (memSpec.memPowerSpec.getValue().entries.at("idd52")),
|
||||
iDD62 (memSpec.memPowerSpec.getValue().entries.at("idd62")),
|
||||
vDD2 (memSpec.memPowerSpec.getValue().entries.at("vdd2"))
|
||||
{
|
||||
uint64_t deviceSizeBits = static_cast<uint64_t>(banksPerRank) * numberOfRows * numberOfColumns * bitWidth;
|
||||
uint64_t deviceSizeBytes = deviceSizeBits / 8;
|
||||
memorySizeBytes = deviceSizeBytes * numberOfRanks * numberOfChannels;
|
||||
|
||||
if (!memSpec.memPowerSpec.isValid())
|
||||
SC_REPORT_FATAL("MemSpec", "No power spec defined!");
|
||||
|
||||
std::cout << headline << std::endl;
|
||||
std::cout << "Memory Configuration:" << std::endl << std::endl;
|
||||
std::cout << " Memory type: " << "Wide I/O" << std::endl;
|
||||
|
||||
@@ -38,12 +38,11 @@
|
||||
|
||||
#include <systemc>
|
||||
#include "MemSpec.h"
|
||||
#include "../../common/third_party/nlohmann/single_include/nlohmann/json.hpp"
|
||||
|
||||
class MemSpecWideIO final : public MemSpec
|
||||
{
|
||||
public:
|
||||
explicit MemSpecWideIO(nlohmann::json &memspec);
|
||||
explicit MemSpecWideIO(const DRAMSysConfiguration::MemSpec &memSpec);
|
||||
|
||||
// Memspec Variables:
|
||||
const sc_core::sc_time tCKE;
|
||||
|
||||
@@ -40,46 +40,45 @@
|
||||
|
||||
using namespace sc_core;
|
||||
using namespace tlm;
|
||||
using json = nlohmann::json;
|
||||
|
||||
MemSpecWideIO2::MemSpecWideIO2(json &memspec)
|
||||
: MemSpec(memspec, MemoryType::WideIO2,
|
||||
parseUint(memspec["memarchitecturespec"],"nbrOfChannels"),
|
||||
parseUint(memspec["memarchitecturespec"],"nbrOfRanks"),
|
||||
parseUint(memspec["memarchitecturespec"],"nbrOfBanks"),
|
||||
MemSpecWideIO2::MemSpecWideIO2(const DRAMSysConfiguration::MemSpec &memSpec)
|
||||
: MemSpec(memSpec, MemoryType::WideIO2,
|
||||
memSpec.memArchitectureSpec.entries.at("nbrOfChannels"),
|
||||
memSpec.memArchitectureSpec.entries.at("nbrOfRanks"),
|
||||
memSpec.memArchitectureSpec.entries.at("nbrOfBanks"),
|
||||
1,
|
||||
parseUint(memspec["memarchitecturespec"],"nbrOfBanks"),
|
||||
parseUint(memspec["memarchitecturespec"],"nbrOfBanks")
|
||||
* parseUint(memspec["memarchitecturespec"],"nbrOfRanks"),
|
||||
parseUint(memspec["memarchitecturespec"],"nbrOfRanks"),
|
||||
parseUint(memspec["memarchitecturespec"],"nbrOfDevices")),
|
||||
tDQSCK (tCK * parseUint(memspec["memtimingspec"], "DQSCK")),
|
||||
tDQSS (tCK * parseUint(memspec["memtimingspec"], "DQSS")),
|
||||
tCKE (tCK * parseUint(memspec["memtimingspec"], "CKE")),
|
||||
tRL (tCK * parseUint(memspec["memtimingspec"], "RL")),
|
||||
tWL (tCK * parseUint(memspec["memtimingspec"], "WL")),
|
||||
tRCpb (tCK * parseUint(memspec["memtimingspec"], "RCPB")),
|
||||
tRCab (tCK * parseUint(memspec["memtimingspec"], "RCAB")),
|
||||
tCKESR (tCK * parseUint(memspec["memtimingspec"], "CKESR")),
|
||||
tXSR (tCK * parseUint(memspec["memtimingspec"], "XSR")),
|
||||
tXP (tCK * parseUint(memspec["memtimingspec"], "XP")),
|
||||
tCCD (tCK * parseUint(memspec["memtimingspec"], "CCD")),
|
||||
tRTP (tCK * parseUint(memspec["memtimingspec"], "RTP")),
|
||||
tRCD (tCK * parseUint(memspec["memtimingspec"], "RCD")),
|
||||
tRPpb (tCK * parseUint(memspec["memtimingspec"], "RPPB")),
|
||||
tRPab (tCK * parseUint(memspec["memtimingspec"], "RPAB")),
|
||||
tRAS (tCK * parseUint(memspec["memtimingspec"], "RAS")),
|
||||
tWR (tCK * parseUint(memspec["memtimingspec"], "WR")),
|
||||
tWTR (tCK * parseUint(memspec["memtimingspec"], "WTR")),
|
||||
tRRD (tCK * parseUint(memspec["memtimingspec"], "RRD")),
|
||||
tFAW (tCK * parseUint(memspec["memtimingspec"], "FAW")),
|
||||
tREFI (tCK * static_cast<unsigned>(parseUint(memspec["memtimingspec"], "REFI")
|
||||
* parseUdouble(memspec["memtimingspec"], "REFM"))),
|
||||
tREFIpb (tCK * static_cast<unsigned>(parseUint(memspec["memtimingspec"], "REFIPB")
|
||||
* parseUdouble(memspec["memtimingspec"], "REFM"))),
|
||||
tRFCab (tCK * parseUint(memspec["memtimingspec"], "RFCAB")),
|
||||
tRFCpb (tCK * parseUint(memspec["memtimingspec"], "RFCPB")),
|
||||
tRTRS (tCK * parseUint(memspec["memtimingspec"], "RTRS"))
|
||||
memSpec.memArchitectureSpec.entries.at("nbrOfBanks"),
|
||||
memSpec.memArchitectureSpec.entries.at("nbrOfBanks")
|
||||
* memSpec.memArchitectureSpec.entries.at("nbrOfRanks"),
|
||||
memSpec.memArchitectureSpec.entries.at("nbrOfRanks"),
|
||||
memSpec.memArchitectureSpec.entries.at("nbrOfDevices")),
|
||||
tDQSCK (tCK * memSpec.memTimingSpec.entries.at("DQSCK")),
|
||||
tDQSS (tCK * memSpec.memTimingSpec.entries.at("DQSS")),
|
||||
tCKE (tCK * memSpec.memTimingSpec.entries.at("CKE")),
|
||||
tRL (tCK * memSpec.memTimingSpec.entries.at("RL")),
|
||||
tWL (tCK * memSpec.memTimingSpec.entries.at("WL")),
|
||||
tRCpb (tCK * memSpec.memTimingSpec.entries.at("RCPB")),
|
||||
tRCab (tCK * memSpec.memTimingSpec.entries.at("RCAB")),
|
||||
tCKESR (tCK * memSpec.memTimingSpec.entries.at("CKESR")),
|
||||
tXSR (tCK * memSpec.memTimingSpec.entries.at("XSR")),
|
||||
tXP (tCK * memSpec.memTimingSpec.entries.at("XP")),
|
||||
tCCD (tCK * memSpec.memTimingSpec.entries.at("CCD")),
|
||||
tRTP (tCK * memSpec.memTimingSpec.entries.at("RTP")),
|
||||
tRCD (tCK * memSpec.memTimingSpec.entries.at("RCD")),
|
||||
tRPpb (tCK * memSpec.memTimingSpec.entries.at("RPPB")),
|
||||
tRPab (tCK * memSpec.memTimingSpec.entries.at("RPAB")),
|
||||
tRAS (tCK * memSpec.memTimingSpec.entries.at("RAS")),
|
||||
tWR (tCK * memSpec.memTimingSpec.entries.at("WR")),
|
||||
tWTR (tCK * memSpec.memTimingSpec.entries.at("WTR")),
|
||||
tRRD (tCK * memSpec.memTimingSpec.entries.at("RRD")),
|
||||
tFAW (tCK * memSpec.memTimingSpec.entries.at("FAW")),
|
||||
tREFI (tCK * static_cast<unsigned>(memSpec.memTimingSpec.entries.at("REFI")
|
||||
* memSpec.memTimingSpec.entries.at("REFM"))),
|
||||
tREFIpb (tCK * static_cast<unsigned>(memSpec.memTimingSpec.entries.at("REFIPB")
|
||||
* memSpec.memTimingSpec.entries.at("REFM"))),
|
||||
tRFCab (tCK * memSpec.memTimingSpec.entries.at("RFCAB")),
|
||||
tRFCpb (tCK * memSpec.memTimingSpec.entries.at("RFCPB")),
|
||||
tRTRS (tCK * memSpec.memTimingSpec.entries.at("RTRS"))
|
||||
{
|
||||
uint64_t deviceSizeBits = static_cast<uint64_t>(banksPerRank) * numberOfRows * numberOfColumns * bitWidth;
|
||||
uint64_t deviceSizeBytes = deviceSizeBits / 8;
|
||||
|
||||
@@ -38,12 +38,11 @@
|
||||
|
||||
#include <systemc>
|
||||
#include "MemSpec.h"
|
||||
#include "../../common/third_party/nlohmann/single_include/nlohmann/json.hpp"
|
||||
|
||||
class MemSpecWideIO2 final : public MemSpec
|
||||
{
|
||||
public:
|
||||
explicit MemSpecWideIO2(nlohmann::json &memspec);
|
||||
explicit MemSpecWideIO2(const DRAMSysConfiguration::MemSpec &memSpec);
|
||||
|
||||
// Memspec Variables:
|
||||
const sc_core::sc_time tDQSCK;
|
||||
|
||||
@@ -44,87 +44,35 @@
|
||||
#include "../common/utils.h"
|
||||
#include "../configuration/Configuration.h"
|
||||
|
||||
using json = nlohmann::json;
|
||||
|
||||
unsigned int AddressDecoder::getUnsignedAttrFromJson(json &obj, const std::string &strName)
|
||||
AddressDecoder::AddressDecoder(const DRAMSysConfiguration::AddressMapping &addressMapping)
|
||||
{
|
||||
if (!obj[strName].empty())
|
||||
if (addressMapping.channelBits.isValid())
|
||||
{
|
||||
if (obj[strName].is_number_unsigned())
|
||||
{
|
||||
return obj[strName];
|
||||
}
|
||||
else
|
||||
{
|
||||
SC_REPORT_FATAL("AddressDecoder", ("Attribute " + strName + " is not a number.").c_str());
|
||||
return static_cast<unsigned>(-1);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
SC_REPORT_FATAL("AddressDecoder", ("Attribute " + strName + " is empty or not found.").c_str());
|
||||
return static_cast<unsigned>(-1);
|
||||
}
|
||||
}
|
||||
|
||||
std::vector<unsigned> AddressDecoder::getAttrToVectorFromJson(json &obj, const std::string &strName)
|
||||
{
|
||||
std::vector<unsigned> vParameter;
|
||||
if (!obj[strName].empty())
|
||||
{
|
||||
for (const auto& it : obj[strName].items())
|
||||
{
|
||||
auto valor = it.value();
|
||||
if (valor.is_number_unsigned())
|
||||
vParameter.push_back(it.value());
|
||||
else
|
||||
SC_REPORT_FATAL("AddressDecoder", ("Attribute " + strName + " is not a number.").c_str());
|
||||
}
|
||||
}
|
||||
return vParameter;
|
||||
}
|
||||
|
||||
AddressDecoder::AddressDecoder(const std::string &pathToAddressMapping)
|
||||
{
|
||||
json addrFile = parseJSON(pathToAddressMapping);
|
||||
json mapping;
|
||||
if (addrFile["CONGEN"].empty())
|
||||
SC_REPORT_FATAL("AddressDecorder", "Root node name differs from \"CONGEN\". File format not supported.");
|
||||
|
||||
// Load address mapping
|
||||
if (!addrFile["CONGEN"]["SOLUTION"].empty())
|
||||
{
|
||||
bool foundID0 = false;
|
||||
for (const auto& it : addrFile["CONGEN"]["SOLUTION"].items())
|
||||
{
|
||||
if (getUnsignedAttrFromJson(it.value(), "ID") == 0)
|
||||
{
|
||||
foundID0 = true;
|
||||
mapping = it.value();
|
||||
break;
|
||||
}
|
||||
}
|
||||
if (!foundID0)
|
||||
SC_REPORT_FATAL("AddressDecoder", "No mapping with ID 0 was found.");
|
||||
}
|
||||
else
|
||||
mapping = addrFile["CONGEN"];
|
||||
|
||||
for (const auto& xorItem : mapping["XOR"].items())
|
||||
{
|
||||
auto value = xorItem.value();
|
||||
if (!value.empty())
|
||||
vXor.emplace_back(getUnsignedAttrFromJson(value, "FIRST"),
|
||||
getUnsignedAttrFromJson(value, "SECOND"));
|
||||
auto channelBits = addressMapping.channelBits.getValue();
|
||||
std::copy(channelBits.begin(), channelBits.end(), std::back_inserter(vChannelBits));
|
||||
}
|
||||
|
||||
vChannelBits = getAttrToVectorFromJson(mapping,"CHANNEL_BIT");
|
||||
vRankBits = getAttrToVectorFromJson(mapping,"RANK_BIT");
|
||||
vBankGroupBits = getAttrToVectorFromJson(mapping,"BANKGROUP_BIT");
|
||||
vBankBits = getAttrToVectorFromJson(mapping,"BANK_BIT");
|
||||
vRowBits = getAttrToVectorFromJson(mapping,"ROW_BIT");
|
||||
vColumnBits = getAttrToVectorFromJson(mapping,"COLUMN_BIT");
|
||||
vByteBits = getAttrToVectorFromJson(mapping,"BYTE_BIT");
|
||||
if (addressMapping.rankBits.isValid())
|
||||
{
|
||||
auto rankBits = addressMapping.rankBits.getValue();
|
||||
std::copy(rankBits.begin(), rankBits.end(), std::back_inserter(vRankBits));
|
||||
}
|
||||
|
||||
if (addressMapping.bankGroupBits.isValid())
|
||||
{
|
||||
auto bankBroupBits = addressMapping.bankGroupBits.getValue();
|
||||
std::copy(bankBroupBits.begin(), bankBroupBits.end(), std::back_inserter(vBankGroupBits));
|
||||
}
|
||||
|
||||
if (addressMapping.byteBits.isValid())
|
||||
{
|
||||
auto byteBits = addressMapping.byteBits.getValue();
|
||||
std::copy(byteBits.begin(), byteBits.end(), std::back_inserter(vByteBits));
|
||||
}
|
||||
|
||||
std::copy(addressMapping.bankBits.begin(), addressMapping.bankBits.end(), std::back_inserter(vBankBits));
|
||||
std::copy(addressMapping.rowBits.begin(), addressMapping.rowBits.end(), std::back_inserter(vRowBits));
|
||||
std::copy(addressMapping.coloumnBits.begin(), addressMapping.coloumnBits.end(), std::back_inserter(vColumnBits));
|
||||
|
||||
unsigned channels = std::lround(std::pow(2.0, vChannelBits.size()));
|
||||
unsigned ranks = std::lround(std::pow(2.0, vRankBits.size()));
|
||||
|
||||
@@ -40,8 +40,7 @@
|
||||
|
||||
#include <vector>
|
||||
#include <utility>
|
||||
|
||||
#include "../common/third_party/nlohmann/single_include/nlohmann/json.hpp"
|
||||
#include <Configuration.h>
|
||||
|
||||
struct DecodedAddress
|
||||
{
|
||||
@@ -67,14 +66,11 @@ struct DecodedAddress
|
||||
class AddressDecoder
|
||||
{
|
||||
public:
|
||||
explicit AddressDecoder(const std::string &pathToAddressMapping);
|
||||
explicit AddressDecoder(const DRAMSysConfiguration::AddressMapping &addressMapping);
|
||||
DecodedAddress decodeAddress(uint64_t addr);
|
||||
void print();
|
||||
|
||||
private:
|
||||
static std::vector<unsigned> getAttrToVectorFromJson(nlohmann::json &obj, const std::string &strName);
|
||||
static unsigned int getUnsignedAttrFromJson(nlohmann::json &obj, const std::string &strName);
|
||||
|
||||
unsigned banksPerGroup;
|
||||
unsigned bankgroupsPerRank;
|
||||
|
||||
|
||||
@@ -40,10 +40,12 @@
|
||||
#include "AddressDecoder.h"
|
||||
#include "../configuration/Configuration.h"
|
||||
|
||||
#include <Configuration.h>
|
||||
|
||||
using namespace sc_core;
|
||||
using namespace tlm;
|
||||
|
||||
Arbiter::Arbiter(const sc_module_name &name, const std::string &pathToAddressMapping) :
|
||||
Arbiter::Arbiter(const sc_module_name &name, const DRAMSysConfiguration::AddressMapping &addressMapping) :
|
||||
sc_module(name), payloadEventQueue(this, &Arbiter::peqCallback),
|
||||
tCK(Configuration::getInstance().memSpec->tCK),
|
||||
arbitrationDelayFw(Configuration::getInstance().arbitrationDelayFw),
|
||||
@@ -53,21 +55,21 @@ Arbiter::Arbiter(const sc_module_name &name, const std::string &pathToAddressMap
|
||||
tSocket.register_nb_transport_fw(this, &Arbiter::nb_transport_fw);
|
||||
tSocket.register_transport_dbg(this, &Arbiter::transport_dbg);
|
||||
|
||||
addressDecoder = new AddressDecoder(pathToAddressMapping);
|
||||
addressDecoder = new AddressDecoder(addressMapping);
|
||||
addressDecoder->print();
|
||||
|
||||
bytesPerBeat = Configuration::getInstance().memSpec->dataBusWidth / 8;
|
||||
}
|
||||
|
||||
ArbiterSimple::ArbiterSimple(const sc_module_name &name, const std::string &pathToAddressMapping) :
|
||||
Arbiter(name, pathToAddressMapping) {}
|
||||
ArbiterSimple::ArbiterSimple(const sc_module_name &name, const DRAMSysConfiguration::AddressMapping &addressMapping) :
|
||||
Arbiter(name, addressMapping) {}
|
||||
|
||||
ArbiterFifo::ArbiterFifo(const sc_module_name &name, const std::string &pathToAddressMapping) :
|
||||
Arbiter(name, pathToAddressMapping),
|
||||
ArbiterFifo::ArbiterFifo(const sc_module_name &name, const DRAMSysConfiguration::AddressMapping &addressMapping) :
|
||||
Arbiter(name, addressMapping),
|
||||
maxActiveTransactions(Configuration::getInstance().maxActiveTransactions) {}
|
||||
|
||||
ArbiterReorder::ArbiterReorder(const sc_module_name &name, const std::string &pathToAddressMapping) :
|
||||
Arbiter(name, pathToAddressMapping),
|
||||
ArbiterReorder::ArbiterReorder(const sc_module_name &name, const DRAMSysConfiguration::AddressMapping &addressMapping) :
|
||||
Arbiter(name, addressMapping),
|
||||
maxActiveTransactions(Configuration::getInstance().maxActiveTransactions) {}
|
||||
|
||||
Arbiter::~Arbiter()
|
||||
|
||||
@@ -64,7 +64,7 @@ public:
|
||||
~Arbiter() override;
|
||||
|
||||
protected:
|
||||
Arbiter(const sc_core::sc_module_name &name, const std::string &pathToAddressMapping);
|
||||
Arbiter(const sc_core::sc_module_name &name, const DRAMSysConfiguration::AddressMapping &addressMapping);
|
||||
SC_HAS_PROCESS(Arbiter);
|
||||
|
||||
void end_of_elaboration() override;
|
||||
@@ -98,7 +98,7 @@ protected:
|
||||
class ArbiterSimple final : public Arbiter
|
||||
{
|
||||
public:
|
||||
ArbiterSimple(const sc_core::sc_module_name &name, const std::string &pathToAddressMapping);
|
||||
ArbiterSimple(const sc_core::sc_module_name &name, const DRAMSysConfiguration::AddressMapping &addressMapping);
|
||||
SC_HAS_PROCESS(ArbiterSimple);
|
||||
|
||||
private:
|
||||
@@ -111,7 +111,7 @@ private:
|
||||
class ArbiterFifo final : public Arbiter
|
||||
{
|
||||
public:
|
||||
ArbiterFifo(const sc_core::sc_module_name &name, const std::string &pathToAddressMapping);
|
||||
ArbiterFifo(const sc_core::sc_module_name &name, const DRAMSysConfiguration::AddressMapping &addressMapping);
|
||||
SC_HAS_PROCESS(ArbiterFifo);
|
||||
|
||||
private:
|
||||
@@ -131,7 +131,7 @@ private:
|
||||
class ArbiterReorder final : public Arbiter
|
||||
{
|
||||
public:
|
||||
ArbiterReorder(const sc_core::sc_module_name &name, const std::string &pathToAddressMapping);
|
||||
ArbiterReorder(const sc_core::sc_module_name &name, const DRAMSysConfiguration::AddressMapping &addressMapping);
|
||||
SC_HAS_PROCESS(ArbiterReorder);
|
||||
|
||||
private:
|
||||
|
||||
@@ -43,7 +43,6 @@
|
||||
#include <stdexcept>
|
||||
|
||||
#include "DRAMSys.h"
|
||||
#include "../common/third_party/nlohmann/single_include/nlohmann/json.hpp"
|
||||
#include "../common/DebugManager.h"
|
||||
#include "../common/utils.h"
|
||||
#include "../simulation/TemperatureController.h"
|
||||
@@ -63,14 +62,12 @@
|
||||
#include "../controller/Controller.h"
|
||||
|
||||
DRAMSys::DRAMSys(const sc_core::sc_module_name &name,
|
||||
const std::string &simulationToRun,
|
||||
const std::string &pathToResources)
|
||||
: DRAMSys(name, simulationToRun, pathToResources, true)
|
||||
const DRAMSysConfiguration::Configuration &config)
|
||||
: DRAMSys(name, config, true)
|
||||
{}
|
||||
|
||||
DRAMSys::DRAMSys(const sc_core::sc_module_name &name,
|
||||
const std::string &simulationToRun,
|
||||
const std::string &pathToResources,
|
||||
const DRAMSysConfiguration::Configuration &config,
|
||||
bool initAndBind)
|
||||
: sc_module(name), tSocket("DRAMSys_tSocket")
|
||||
{
|
||||
@@ -79,31 +76,13 @@ DRAMSys::DRAMSys(const sc_core::sc_module_name &name,
|
||||
|
||||
logo();
|
||||
|
||||
// Read Configuration Setup:
|
||||
nlohmann::json simulationdoc = parseJSON(simulationToRun);
|
||||
|
||||
Configuration::getInstance().setPathToResources(pathToResources);
|
||||
|
||||
// Load config and initialize modules
|
||||
Configuration::getInstance().loadMemSpec(Configuration::getInstance(),
|
||||
pathToResources
|
||||
+ "configs/memspecs/"
|
||||
+ std::string(simulationdoc["simulation"]["memspec"]));
|
||||
Configuration::getInstance().loadMemSpec(Configuration::getInstance(), config.memSpec);
|
||||
Configuration::loadMCConfig(Configuration::getInstance(), config.mcConfig);
|
||||
Configuration::loadSimConfig(Configuration::getInstance(), config.simConfig);
|
||||
|
||||
Configuration::loadMCConfig(Configuration::getInstance(),
|
||||
pathToResources
|
||||
+ "configs/mcconfigs/"
|
||||
+ std::string(simulationdoc["simulation"]["mcconfig"]));
|
||||
|
||||
Configuration::loadSimConfig(Configuration::getInstance(),
|
||||
pathToResources
|
||||
+ "configs/simulator/"
|
||||
+ std::string(simulationdoc["simulation"]["simconfig"]));
|
||||
|
||||
Configuration::loadTemperatureSimConfig(Configuration::getInstance(),
|
||||
pathToResources
|
||||
+ "configs/thermalsim/"
|
||||
+ std::string(simulationdoc["simulation"]["thermalconfig"]));
|
||||
if (config.thermalConfig.isValid())
|
||||
Configuration::loadTemperatureSimConfig(Configuration::getInstance(), config.thermalConfig.getValue());
|
||||
|
||||
// Setup the debug manager:
|
||||
setupDebugManager(Configuration::getInstance().simulationName);
|
||||
@@ -111,8 +90,7 @@ DRAMSys::DRAMSys(const sc_core::sc_module_name &name,
|
||||
if (initAndBind)
|
||||
{
|
||||
// Instantiate all internal DRAMSys modules:
|
||||
std::string amconfig = simulationdoc["simulation"]["addressmapping"];
|
||||
instantiateModules(pathToResources, amconfig);
|
||||
instantiateModules(config.addressMapping);
|
||||
// Connect all internal DRAMSys modules:
|
||||
bindSockets();
|
||||
report(headline);
|
||||
@@ -174,8 +152,7 @@ void DRAMSys::setupDebugManager(NDEBUG_UNUSED(const std::string &traceName))
|
||||
#endif
|
||||
}
|
||||
|
||||
void DRAMSys::instantiateModules(const std::string &pathToResources,
|
||||
const std::string &amconfig)
|
||||
void DRAMSys::instantiateModules(const DRAMSysConfiguration::AddressMapping &addressMapping)
|
||||
{
|
||||
// The first call to getInstance() creates the Temperature Controller.
|
||||
// The same instance will be accessed by all other modules.
|
||||
@@ -193,11 +170,11 @@ void DRAMSys::instantiateModules(const std::string &pathToResources,
|
||||
|
||||
// Create arbiter
|
||||
if (config.arbiter == Configuration::Arbiter::Simple)
|
||||
arbiter = new ArbiterSimple("arbiter", pathToResources + "configs/amconfigs/" + amconfig);
|
||||
arbiter = new ArbiterSimple("arbiter", addressMapping);
|
||||
else if (config.arbiter == Configuration::Arbiter::Fifo)
|
||||
arbiter = new ArbiterFifo("arbiter", pathToResources + "configs/amconfigs/" + amconfig);
|
||||
arbiter = new ArbiterFifo("arbiter", addressMapping);
|
||||
else if (config.arbiter == Configuration::Arbiter::Reorder)
|
||||
arbiter = new ArbiterReorder("arbiter", pathToResources + "configs/amconfigs/" + amconfig);
|
||||
arbiter = new ArbiterReorder("arbiter", addressMapping);
|
||||
|
||||
// Create controllers and DRAMs
|
||||
MemSpec::MemoryType memoryType = config.memSpec->memoryType;
|
||||
|
||||
@@ -40,18 +40,19 @@
|
||||
#ifndef DRAMSYS_H
|
||||
#define DRAMSYS_H
|
||||
|
||||
#include <string>
|
||||
|
||||
#include <systemc>
|
||||
#include "dram/Dram.h"
|
||||
#include "Arbiter.h"
|
||||
#include "ReorderBuffer.h"
|
||||
#include <tlm_utils/multi_passthrough_target_socket.h>
|
||||
#include <tlm_utils/multi_passthrough_initiator_socket.h>
|
||||
#include "../common/tlm2_base_protocol_checker.h"
|
||||
#include "../error/eccbaseclass.h"
|
||||
#include "../controller/ControllerIF.h"
|
||||
|
||||
#include <Configuration.h>
|
||||
#include <string>
|
||||
#include <systemc>
|
||||
#include <tlm_utils/multi_passthrough_initiator_socket.h>
|
||||
#include <tlm_utils/multi_passthrough_target_socket.h>
|
||||
|
||||
class DRAMSys : public sc_core::sc_module
|
||||
{
|
||||
public:
|
||||
@@ -62,15 +63,13 @@ public:
|
||||
|
||||
SC_HAS_PROCESS(DRAMSys);
|
||||
DRAMSys(const sc_core::sc_module_name &name,
|
||||
const std::string &simulationToRun,
|
||||
const std::string &pathToResources);
|
||||
const DRAMSysConfiguration::Configuration &config);
|
||||
|
||||
~DRAMSys() override;
|
||||
|
||||
protected:
|
||||
DRAMSys(const sc_core::sc_module_name &name,
|
||||
const std::string &simulationToRun,
|
||||
const std::string &pathToResources,
|
||||
const DRAMSysConfiguration::Configuration &config,
|
||||
bool initAndBind);
|
||||
|
||||
//TLM 2.0 Protocol Checkers
|
||||
@@ -97,8 +96,7 @@ protected:
|
||||
private:
|
||||
static void logo();
|
||||
|
||||
void instantiateModules(const std::string &pathToResources,
|
||||
const std::string &amconfig);
|
||||
void instantiateModules(const DRAMSysConfiguration::AddressMapping &addressMapping);
|
||||
void bindSockets();
|
||||
|
||||
static void setupDebugManager(const std::string &traceName);
|
||||
|
||||
@@ -55,27 +55,22 @@
|
||||
using namespace sc_core;
|
||||
|
||||
DRAMSysRecordable::DRAMSysRecordable(const sc_module_name &name,
|
||||
const std::string &simulationToRun,
|
||||
const std::string &pathToResources)
|
||||
: DRAMSys(name, simulationToRun, pathToResources, false)
|
||||
const DRAMSysConfiguration::Configuration &configuration)
|
||||
: DRAMSys(name, configuration, false)
|
||||
{
|
||||
// Read Configuration Setup:
|
||||
nlohmann::json simulationdoc = parseJSON(simulationToRun);
|
||||
|
||||
// If a simulation file is passed as argument to DRAMSys the simulation ID
|
||||
// is prepended to the simulation name if found.
|
||||
std::string traceName;
|
||||
|
||||
if (!simulationdoc["simulation"]["simulationid"].empty())
|
||||
if (!configuration.simulationId.empty())
|
||||
{
|
||||
std::string sid = simulationdoc["simulation"]["simulationid"];
|
||||
std::string sid = configuration.simulationId;
|
||||
traceName = sid + '_' + Configuration::getInstance().simulationName;
|
||||
}
|
||||
else
|
||||
traceName = Configuration::getInstance().simulationName;
|
||||
|
||||
std::string amconfig = simulationdoc["simulation"]["addressmapping"];
|
||||
instantiateModules(traceName, pathToResources, amconfig);
|
||||
instantiateModules(traceName, configuration);
|
||||
bindSockets();
|
||||
report(headline);
|
||||
}
|
||||
@@ -93,7 +88,7 @@ DRAMSysRecordable::~DRAMSysRecordable()
|
||||
delete rec;
|
||||
}
|
||||
|
||||
void DRAMSysRecordable::setupTlmRecorders(const std::string &traceName)
|
||||
void DRAMSysRecordable::setupTlmRecorders(const std::string &traceName, const DRAMSysConfiguration::Configuration &configuration)
|
||||
{
|
||||
// Create TLM Recorders, one per channel.
|
||||
for (std::size_t i = 0; i < Configuration::getInstance().memSpec->numberOfChannels; i++)
|
||||
@@ -104,8 +99,8 @@ void DRAMSysRecordable::setupTlmRecorders(const std::string &traceName)
|
||||
|
||||
TlmRecorder *tlmRecorder =
|
||||
new TlmRecorder(recorderName, dbName);
|
||||
tlmRecorder->recordMcConfig(Configuration::mcconfigUri);
|
||||
tlmRecorder->recordMemspec(Configuration::memspecUri);
|
||||
tlmRecorder->recordMcConfig(DRAMSysConfiguration::dump(configuration.mcConfig));
|
||||
tlmRecorder->recordMemspec(DRAMSysConfiguration::dump(configuration.memSpec));
|
||||
|
||||
std::string traceNames = Configuration::getInstance().simulationName;
|
||||
tlmRecorder->recordTraceNames(traceNames);
|
||||
@@ -115,8 +110,7 @@ void DRAMSysRecordable::setupTlmRecorders(const std::string &traceName)
|
||||
}
|
||||
|
||||
void DRAMSysRecordable::instantiateModules(const std::string &traceName,
|
||||
const std::string &pathToResources,
|
||||
const std::string &amconfig)
|
||||
const DRAMSysConfiguration::Configuration &configuration)
|
||||
{
|
||||
// The first call to getInstance() creates the Temperature Controller.
|
||||
// The same instance will be accessed by all other modules.
|
||||
@@ -126,7 +120,7 @@ void DRAMSysRecordable::instantiateModules(const std::string &traceName,
|
||||
|
||||
// Create and properly initialize TLM recorders.
|
||||
// They need to be ready before creating some modules.
|
||||
setupTlmRecorders(traceName);
|
||||
setupTlmRecorders(traceName, configuration);
|
||||
|
||||
// Create new ECC Controller
|
||||
if (config.eccMode == Configuration::ECCMode::Hamming)
|
||||
@@ -139,11 +133,11 @@ void DRAMSysRecordable::instantiateModules(const std::string &traceName,
|
||||
|
||||
// Create arbiter
|
||||
if (config.arbiter == Configuration::Arbiter::Simple)
|
||||
arbiter = new ArbiterSimple("arbiter", pathToResources + "configs/amconfigs/" + amconfig);
|
||||
arbiter = new ArbiterSimple("arbiter", configuration.addressMapping);
|
||||
else if (config.arbiter == Configuration::Arbiter::Fifo)
|
||||
arbiter = new ArbiterFifo("arbiter", pathToResources + "configs/amconfigs/" + amconfig);
|
||||
arbiter = new ArbiterFifo("arbiter", configuration.addressMapping);
|
||||
else if (config.arbiter == Configuration::Arbiter::Reorder)
|
||||
arbiter = new ArbiterReorder("arbiter", pathToResources + "configs/amconfigs/" + amconfig);
|
||||
arbiter = new ArbiterReorder("arbiter", configuration.addressMapping);
|
||||
|
||||
// Create controllers and DRAMs
|
||||
MemSpec::MemoryType memoryType = config.memSpec->memoryType;
|
||||
|
||||
@@ -39,12 +39,13 @@
|
||||
#include "DRAMSys.h"
|
||||
#include "../common/TlmRecorder.h"
|
||||
|
||||
#include <Configuration.h>
|
||||
|
||||
class DRAMSysRecordable : public DRAMSys
|
||||
{
|
||||
public:
|
||||
DRAMSysRecordable(const sc_core::sc_module_name &name,
|
||||
const std::string &simulationToRun,
|
||||
const std::string &pathToResources);
|
||||
const DRAMSysConfiguration::Configuration &configuration);
|
||||
|
||||
~DRAMSysRecordable() override;
|
||||
|
||||
@@ -53,11 +54,10 @@ private:
|
||||
// They generate the output databases.
|
||||
std::vector<TlmRecorder *> tlmRecorders;
|
||||
|
||||
void setupTlmRecorders(const std::string &traceName);
|
||||
void setupTlmRecorders(const std::string &traceName, const DRAMSysConfiguration::Configuration &configuration);
|
||||
|
||||
void instantiateModules(const std::string &traceName,
|
||||
const std::string &pathToResources,
|
||||
const std::string &amconfig);
|
||||
const DRAMSysConfiguration::Configuration &configuration);
|
||||
|
||||
void bindSockets();
|
||||
};
|
||||
|
||||
@@ -43,9 +43,9 @@ using namespace sc_core;
|
||||
|
||||
double TemperatureController::temperatureConvert(double tKelvin)
|
||||
{
|
||||
if (temperatureScale == "Celsius") {
|
||||
if (temperatureScale == TemperatureSimConfig::TemperatureScale::Celsius) {
|
||||
return tKelvin - 273.15;
|
||||
} else if (temperatureScale == "Fahrenheit") {
|
||||
} else if (temperatureScale == TemperatureSimConfig::TemperatureScale::Fahrenheit) {
|
||||
return (tKelvin - 273.15) * 1.8 + 32;
|
||||
}
|
||||
|
||||
|
||||
@@ -115,7 +115,7 @@ public:
|
||||
double getTemperature(int deviceId, float currentPower);
|
||||
|
||||
private:
|
||||
std::string temperatureScale;
|
||||
TemperatureSimConfig::TemperatureScale temperatureScale;
|
||||
double temperatureConvert(double tKelvin);
|
||||
|
||||
double staticTemperature;
|
||||
|
||||
@@ -43,186 +43,128 @@
|
||||
using namespace sc_core;
|
||||
using namespace tlm;
|
||||
|
||||
TraceSetup::TraceSetup(const std::string &uri,
|
||||
TraceSetup::TraceSetup(const DRAMSysConfiguration::TraceSetup &traceSetup,
|
||||
const std::string &pathToResources,
|
||||
std::vector<TrafficInitiator *> &players)
|
||||
{
|
||||
// Load Simulation:
|
||||
nlohmann::json simulationdoc = parseJSON(uri);
|
||||
if (traceSetup.initiators.empty())
|
||||
SC_REPORT_FATAL("TraceSetup", "No traffic initiators specified");
|
||||
|
||||
if (simulationdoc["simulation"].empty())
|
||||
SC_REPORT_FATAL("TraceSetup",
|
||||
"Cannot load simulation: simulation node expected");
|
||||
|
||||
// Load TrafficInitiators:
|
||||
if (simulationdoc["simulation"]["tracesetup"].empty())
|
||||
SC_REPORT_FATAL("TraceSetup", "tracesetup is empty");
|
||||
for (auto &it : simulationdoc["simulation"]["tracesetup"].items())
|
||||
for (const auto &inititator : traceSetup.initiators)
|
||||
{
|
||||
nlohmann::json value = it.value();
|
||||
if (!value.empty())
|
||||
{
|
||||
sc_time playerClk;
|
||||
if (!value["clkMhz"].is_number() || value["clkMhz"] <= 0)
|
||||
SC_REPORT_FATAL("TraceSetup", "Frequency is not a positive number.");
|
||||
double frequencyMHz = inititator->clkMhz;
|
||||
sc_time playerClk = sc_time(1.0 / frequencyMHz, SC_US);
|
||||
|
||||
double frequencyMHz = value["clkMhz"];
|
||||
playerClk = sc_time(1.0 / frequencyMHz, SC_US);
|
||||
std::string name = inititator->name;
|
||||
|
||||
if (!value["name"].is_string())
|
||||
SC_REPORT_FATAL("TraceSetup", "No trace name defined.");
|
||||
|
||||
std::string name = value["name"];
|
||||
|
||||
unsigned int maxPendingReadRequests = 0;
|
||||
unsigned int maxPendingWriteRequests = 0;
|
||||
|
||||
if (value["maxPendingReadRequests"].is_number_unsigned())
|
||||
maxPendingReadRequests = value["maxPendingReadRequests"];
|
||||
|
||||
if (value["maxPendingWriteRequests"].is_number_unsigned())
|
||||
maxPendingWriteRequests = value["maxPendingWriteRequests"];
|
||||
|
||||
std::string type;
|
||||
|
||||
// Defaulting to type "player" when not specified
|
||||
if (!value["type"].is_string())
|
||||
type = "player";
|
||||
unsigned int maxPendingReadRequests = [=]() -> unsigned int {
|
||||
if (inititator->maxPendingReadRequests.isValid())
|
||||
return inititator->maxPendingReadRequests.getValue();
|
||||
else
|
||||
type = value["type"];
|
||||
return 0;
|
||||
}();
|
||||
|
||||
if (type == "player")
|
||||
{
|
||||
size_t pos = name.rfind('.');
|
||||
if (pos == std::string::npos)
|
||||
throw std::runtime_error("Name of the trace file does not contain a valid extension.");
|
||||
unsigned int maxPendingWriteRequests = [=]() -> unsigned int {
|
||||
if (inititator->maxPendingWriteRequests.isValid())
|
||||
return inititator->maxPendingWriteRequests.getValue();
|
||||
else
|
||||
return 0;
|
||||
}();
|
||||
|
||||
// Get the extension and make it lower case
|
||||
std::string ext = name.substr(pos + 1);
|
||||
std::transform(ext.begin(), ext.end(), ext.begin(), ::tolower);
|
||||
if (std::dynamic_pointer_cast<DRAMSysConfiguration::TracePlayer>(inititator))
|
||||
{
|
||||
size_t pos = name.rfind('.');
|
||||
if (pos == std::string::npos)
|
||||
throw std::runtime_error("Name of the trace file does not contain a valid extension.");
|
||||
|
||||
std::stringstream stlFileStream;
|
||||
stlFileStream << pathToResources << "traces/" << name;
|
||||
std::string stlFile = stlFileStream.str();
|
||||
std::string moduleName = name;
|
||||
// Get the extension and make it lower case
|
||||
std::string ext = name.substr(pos + 1);
|
||||
std::transform(ext.begin(), ext.end(), ext.begin(), ::tolower);
|
||||
|
||||
// replace all '.' to '_'
|
||||
std::replace(moduleName.begin(), moduleName.end(), '.', '_');
|
||||
std::stringstream stlFileStream;
|
||||
stlFileStream << pathToResources << "traces/" << name;
|
||||
std::string stlFile = stlFileStream.str();
|
||||
std::string moduleName = name;
|
||||
|
||||
StlPlayer *player;
|
||||
if (ext == "stl")
|
||||
player = new StlPlayer(moduleName.c_str(), stlFile, playerClk,
|
||||
maxPendingReadRequests, maxPendingWriteRequests, this, false);
|
||||
else if (ext == "rstl")
|
||||
player = new StlPlayer(moduleName.c_str(), stlFile, playerClk,
|
||||
maxPendingReadRequests, maxPendingWriteRequests, this, true);
|
||||
else
|
||||
throw std::runtime_error("Unsupported file extension in " + name);
|
||||
// replace all '.' to '_'
|
||||
std::replace(moduleName.begin(), moduleName.end(), '.', '_');
|
||||
|
||||
players.push_back(player);
|
||||
StlPlayer *player;
|
||||
if (ext == "stl")
|
||||
player = new StlPlayer(moduleName.c_str(), stlFile, playerClk,
|
||||
maxPendingReadRequests, maxPendingWriteRequests, this, false);
|
||||
else if (ext == "rstl")
|
||||
player = new StlPlayer(moduleName.c_str(), stlFile, playerClk,
|
||||
maxPendingReadRequests, maxPendingWriteRequests, this, true);
|
||||
else
|
||||
throw std::runtime_error("Unsupported file extension in " + name);
|
||||
|
||||
totalTransactions += player->getNumberOfLines();
|
||||
}
|
||||
else if (type == "generator")
|
||||
{
|
||||
if (!value["numRequests"].is_number_unsigned())
|
||||
SC_REPORT_FATAL("TraceSetup", "Number of requests is not a number.");
|
||||
|
||||
uint64_t numRequests = value["numRequests"];
|
||||
|
||||
if (!value["rwRatio"].is_number() || value["rwRatio"] < 0 || value["rwRatio"] > 1)
|
||||
SC_REPORT_FATAL("TraceSetup", "Read/Write ratio is not a number between 0 and 1.");
|
||||
|
||||
float rwRatio = value["rwRatio"];
|
||||
|
||||
if (!value["addressDistribution"].is_string())
|
||||
SC_REPORT_FATAL("TraceSetup", "Address distribution not defined.");
|
||||
|
||||
std::string addressDistribution = value["addressDistribution"];
|
||||
if (addressDistribution != "sequential" && addressDistribution != "random")
|
||||
SC_REPORT_FATAL("TraceSetup", "Address distribution must either be sequential or random.");
|
||||
|
||||
unsigned int seed = 0;
|
||||
if (!value["seed"].empty())
|
||||
{
|
||||
if (value["seed"].is_number_unsigned())
|
||||
seed = value["seed"];
|
||||
else
|
||||
SC_REPORT_FATAL("TraceSetup", "Seed is not an unsigned number.");
|
||||
}
|
||||
|
||||
uint64_t minAddress = 0;
|
||||
if (!value["minAddress"].empty())
|
||||
{
|
||||
if (value["minAddress"].is_number_unsigned())
|
||||
{
|
||||
minAddress = value["minAddress"];
|
||||
if (minAddress > Configuration::getInstance().memSpec->getSimMemSizeInBytes() - 1)
|
||||
SC_REPORT_FATAL("TraceSetup", "minAddress is out of range.");
|
||||
}
|
||||
else
|
||||
SC_REPORT_FATAL("TraceSetup", "minAddress is not an unsigned number.");
|
||||
}
|
||||
|
||||
uint64_t maxAddress = Configuration::getInstance().memSpec->getSimMemSizeInBytes() - 1;
|
||||
if (!value["maxAddress"].empty())
|
||||
{
|
||||
if (value["maxAddress"].is_number_unsigned())
|
||||
{
|
||||
maxAddress = value["maxAddress"];
|
||||
if (maxAddress > Configuration::getInstance().memSpec->getSimMemSizeInBytes() - 1)
|
||||
SC_REPORT_FATAL("TraceSetup", "maxAddress is out of range.");
|
||||
}
|
||||
else
|
||||
SC_REPORT_FATAL("TraceSetup", "maxAddress is not an unsigned number.");
|
||||
}
|
||||
|
||||
if (maxAddress < minAddress)
|
||||
SC_REPORT_FATAL("TraceSetup", "maxAddress is smaller than minAddress.");
|
||||
|
||||
TrafficInitiator* generator;
|
||||
|
||||
if (addressDistribution == "sequential")
|
||||
{
|
||||
uint64_t addressIncrement = 0x0;
|
||||
if (!value["addressIncrement"].is_number_unsigned())
|
||||
SC_REPORT_FATAL("TraceSetup", "Address increment is not an unsigned number.");
|
||||
else
|
||||
addressIncrement = value["addressIncrement"];
|
||||
|
||||
generator = new TrafficGeneratorSequential(name.c_str(), playerClk, numRequests,
|
||||
maxPendingReadRequests, maxPendingWriteRequests,
|
||||
minAddress, maxAddress, rwRatio, addressIncrement, seed,
|
||||
this);
|
||||
}
|
||||
else
|
||||
{
|
||||
generator = new TrafficGeneratorRandom(name.c_str(), playerClk, numRequests,
|
||||
maxPendingReadRequests, maxPendingWriteRequests,
|
||||
minAddress, maxAddress, rwRatio, seed, this);
|
||||
}
|
||||
|
||||
players.push_back(generator);
|
||||
|
||||
totalTransactions += numRequests;
|
||||
}
|
||||
else if (type == "hammer")
|
||||
{
|
||||
if (!value["numRequests"].is_number_unsigned())
|
||||
SC_REPORT_FATAL("TraceSetup", "Number of requests is not a number.");
|
||||
uint64_t numRequests = value["numRequests"];
|
||||
|
||||
if (!value["rowIncrement"].is_number_unsigned())
|
||||
SC_REPORT_FATAL("TraceSetup", "Row increment is not a number.");
|
||||
uint64_t rowIncrement = value["rowIncrement"];
|
||||
|
||||
TrafficInitiator* generator = new TrafficGeneratorHammer(name.c_str(), playerClk, numRequests,
|
||||
rowIncrement, this);
|
||||
players.push_back(generator);
|
||||
}
|
||||
players.push_back(player);
|
||||
totalTransactions += player->getNumberOfLines();
|
||||
}
|
||||
else if (auto generator = std::dynamic_pointer_cast<DRAMSysConfiguration::TraceGenerator>(inititator))
|
||||
{
|
||||
uint64_t numRequests = generator->numRequests;
|
||||
double rwRatio = generator->rwRatio;
|
||||
|
||||
if (rwRatio < 0 || rwRatio > 1)
|
||||
SC_REPORT_FATAL("TraceSetup", "Read/Write ratio is not a number between 0 and 1.");
|
||||
|
||||
uint64_t minAddress = [=]() -> uint64_t {
|
||||
if (generator->minAddress.isValid())
|
||||
return generator->minAddress.getValue();
|
||||
else
|
||||
return 0;
|
||||
}();
|
||||
|
||||
uint64_t maxAddress = [=]() -> uint64_t {
|
||||
if (generator->maxAddress.isValid())
|
||||
return generator->maxAddress.getValue();
|
||||
else
|
||||
return 0;
|
||||
}();
|
||||
|
||||
if (maxAddress < minAddress)
|
||||
SC_REPORT_FATAL("TraceSetup", "maxAddress is smaller than minAddress.");
|
||||
|
||||
unsigned int seed = [=]() -> unsigned int {
|
||||
if (generator->seed.isValid())
|
||||
return generator->seed.getValue();
|
||||
else
|
||||
return 0;
|
||||
}();
|
||||
|
||||
if (generator->addressDistribution == DRAMSysConfiguration::AddressDistribution::Sequential)
|
||||
{
|
||||
uint64_t addressIncrement = [=]() -> uint64_t {
|
||||
if (generator->addressIncrement.isValid())
|
||||
return generator->addressIncrement.getValue();
|
||||
else
|
||||
return 0x0;
|
||||
}();
|
||||
|
||||
players.push_back(new TrafficGeneratorSequential(name.c_str(), playerClk, numRequests,
|
||||
maxPendingReadRequests, maxPendingWriteRequests,
|
||||
minAddress, maxAddress, rwRatio, addressIncrement, seed,
|
||||
this));
|
||||
}
|
||||
else if (generator->addressDistribution == DRAMSysConfiguration::AddressDistribution::Random)
|
||||
{
|
||||
players.push_back(new TrafficGeneratorRandom(name.c_str(), playerClk, numRequests,
|
||||
maxPendingReadRequests, maxPendingWriteRequests,
|
||||
minAddress, maxAddress, rwRatio, seed, this));
|
||||
}
|
||||
|
||||
totalTransactions += numRequests;
|
||||
}
|
||||
else if (auto hammer = std::dynamic_pointer_cast<DRAMSysConfiguration::TraceHammer>(inititator))
|
||||
{
|
||||
uint64_t numRequests = hammer->numRequests;
|
||||
uint64_t rowIncrement = hammer->rowIncrement;
|
||||
|
||||
players.push_back(new TrafficGeneratorHammer(name.c_str(), playerClk, numRequests,
|
||||
rowIncrement, this));
|
||||
}
|
||||
else
|
||||
SC_REPORT_FATAL("TraceSetup", "Empty trace setup item.");
|
||||
}
|
||||
|
||||
remainingTransactions = totalTransactions;
|
||||
|
||||
@@ -39,8 +39,9 @@
|
||||
|
||||
#include <vector>
|
||||
#include <string>
|
||||
|
||||
#include <Configuration.h>
|
||||
#include <tlm>
|
||||
|
||||
#include "MemoryManager.h"
|
||||
|
||||
class TrafficInitiator;
|
||||
@@ -48,7 +49,7 @@ class TrafficInitiator;
|
||||
class TraceSetup
|
||||
{
|
||||
public:
|
||||
TraceSetup(const std::string &uri,
|
||||
TraceSetup(const DRAMSysConfiguration::TraceSetup &traceSetup,
|
||||
const std::string &pathToResources,
|
||||
std::vector<TrafficInitiator *> &devices);
|
||||
|
||||
|
||||
@@ -41,15 +41,15 @@
|
||||
#include <utility>
|
||||
#include <vector>
|
||||
#include <chrono>
|
||||
|
||||
#include <Configuration.h>
|
||||
#include <systemc>
|
||||
|
||||
#include "simulation/DRAMSys.h"
|
||||
#include "TraceSetup.h"
|
||||
#include "TrafficInitiator.h"
|
||||
|
||||
#ifdef RECORDING
|
||||
#include "simulation/DRAMSysRecordable.h"
|
||||
#include "common/third_party/nlohmann/single_include/nlohmann/json.hpp"
|
||||
|
||||
using json = nlohmann::json;
|
||||
#endif
|
||||
@@ -97,21 +97,23 @@ int sc_main(int argc, char **argv)
|
||||
|
||||
std::vector<TrafficInitiator *> players;
|
||||
|
||||
DRAMSysConfiguration::Configuration conf = DRAMSysConfiguration::from_path(simulationJson, resources);
|
||||
|
||||
// Instantiate DRAMSys:
|
||||
DRAMSys *dramSys;
|
||||
#ifdef RECORDING
|
||||
json simulationdoc = parseJSON(simulationJson);
|
||||
json simulatordoc = parseJSON(resources + "configs/simulator/"
|
||||
+ std::string(simulationdoc["simulation"]["simconfig"]));
|
||||
|
||||
if (simulatordoc["simconfig"]["DatabaseRecording"])
|
||||
dramSys = new DRAMSysRecordable("DRAMSys", simulationJson, resources);
|
||||
#ifdef RECORDING
|
||||
if (conf.simConfig.databaseRecording.isValid() && conf.simConfig.databaseRecording.getValue())
|
||||
dramSys = new DRAMSysRecordable("DRAMSys", conf);
|
||||
else
|
||||
#endif
|
||||
dramSys = new DRAMSys("DRAMSys", simulationJson, resources);
|
||||
dramSys = new DRAMSys("DRAMSys", conf);
|
||||
|
||||
if (!conf.traceSetup.isValid())
|
||||
SC_REPORT_FATAL("sc_main", "No tracesetup section provided.");
|
||||
|
||||
// Instantiate STL Players:
|
||||
TraceSetup *setup = new TraceSetup(simulationJson, resources, players);
|
||||
TraceSetup *setup = new TraceSetup(conf.traceSetup.getValue(), resources, players);
|
||||
|
||||
// Bind STL Players with DRAMSys:
|
||||
for (size_t i = 0; i < players.size(); i++)
|
||||
|
||||
Reference in New Issue
Block a user