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Rename memconfig to mcconfig

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This commit is contained in:
Felipe S. Prado
2016-10-21 15:15:50 +02:00
parent 8c51cfcb5f
commit cc9345a7ab
37 changed files with 122 additions and 123 deletions
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6
DRAMSys/analyzer/data/tracedb.cpp
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@@ -199,7 +199,7 @@ ID TraceDB::getTransactionIDFromPhaseID(ID phaseID)
GeneralInfo TraceDB::getGeneralInfoFromDB()
{
QSqlQuery query(database);
query.prepare("SELECT NumberOfTransactions,TraceEnd,NumberOfBanks,Clk,UnitOfTime,Traces,Memspec,Memconfig, WindowSize FROM GeneralInfo");
query.prepare("SELECT NumberOfTransactions,TraceEnd,NumberOfBanks,Clk,UnitOfTime,Traces,Memspec,MCconfig, WindowSize FROM GeneralInfo");
executeQuery(query);
if(query.next())
@@ -213,11 +213,11 @@ GeneralInfo TraceDB::getGeneralInfoFromDB()
QString traces = "Traces: " + query.value(5).toString();
QString memspec = "Memspec: " + query.value(6).toString();
QString memconfig = "Memconfig: " + query.value(7).toString();
QString mcconfig = "MCconfig: " + query.value(7).toString();
unsigned int windowSize = query.value(8).toInt();
QString description = (traces + "\n");
description += memconfig + "\n";
description += mcconfig + "\n";
description += memspec + "\n";
description += "Number of Transactions: " + QString::number(numberOfTransactions) + "\n";
description += "Clock period: " + QString::number(clkPeriod) + " " + unitOfTime + "\n";

14
DRAMSys/analyzer/scripts/memUtil.py
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@@ -1,24 +1,24 @@
import xml.etree.ElementTree as ET
class MemConfig(object):
""" Memory Configuration Class
class MCConfig(object):
""" Memory Controller Configuration Class
The format used in memory specification XML files differs from the
format used in memory configuration XML files. Each class uses the
proper format when searching for elements.
format used in memory controller configuration XML files. Each class
uses the proper format when searching for elements.
"""
def getValue(self, id):
return self.xmlMemConfig.findall(id)[0].attrib['value']
return self.xmlMCConfig.findall(id)[0].attrib['value']
def getIntValue(self, id):
return int(self.getValue(id))
def __init__(self, dbconnection):
cursor = dbconnection.cursor()
cursor.execute("SELECT Memconfig FROM GeneralInfo")
cursor.execute("SELECT MCconfig FROM GeneralInfo")
result = cursor.fetchone()
self.xmlMemConfig = ET.parse(result[0])
self.xmlMCConfig = ET.parse(result[0])
class MemSpec(object):

16
DRAMSys/analyzer/scripts/metrics.py
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@@ -371,8 +371,8 @@ def time_in_SREFB_percent(connection):
@metric
def time_in_power_down_states_in_ns(connection):
memconfig = MemConfig(connection)
bankwiseLogic = memconfig.getValue("BankwiseLogic")
mcconfig = MCConfig(connection)
bankwiseLogic = mcconfig.getValue("BankwiseLogic")
if bankwiseLogic == "0":
totalTimeInPDNA = time_in_PDNA_in_ns(connection)
totalTimeInPDNP = time_in_PDNP_in_ns(connection)
@@ -389,8 +389,8 @@ def time_in_power_down_states_in_ns(connection):
@metric
def time_in_power_down_states_percent(connection):
memconfig = MemConfig(connection)
bankwiseLogic = memconfig.getValue("BankwiseLogic")
mcconfig = MCConfig(connection)
bankwiseLogic = mcconfig.getValue("BankwiseLogic")
if bankwiseLogic == "0":
totalTimeAllBanks = trace_length_in_ns(connection)
else:
@@ -447,8 +447,8 @@ def getMetrics(pathToTrace):
selectedMetrics = []
connection = sqlite3.connect(pathToTrace)
memconfig = MemConfig(connection)
bankwiseLogic = memconfig.getValue("BankwiseLogic")
mcconfig = MCConfig(connection)
bankwiseLogic = mcconfig.getValue("BankwiseLogic")
if bankwiseLogic == "0":
pdnMetrics = [time_in_PDNA_in_ns, time_in_PDNA_percent, time_in_PDNP_in_ns, time_in_PDNP_percent, time_in_SREF_in_ns, time_in_SREF_percent]
@@ -481,8 +481,8 @@ def calculateMetrics(pathToTrace, selectedMetrics = []):
calculatedMetrics = []
connection = sqlite3.connect(pathToTrace)
memconfig = MemConfig(connection)
bankwiseLogic = memconfig.getValue("BankwiseLogic")
mcconfig = MCConfig(connection)
bankwiseLogic = mcconfig.getValue("BankwiseLogic")
if bankwiseLogic == "0":
pdnMetrics = [time_in_PDNA_in_ns, time_in_PDNA_percent, time_in_PDNP_in_ns, time_in_PDNP_percent, time_in_SREF_in_ns, time_in_SREF_percent]

6
DRAMSys/analyzer/scripts/tests.py
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@@ -43,15 +43,15 @@ class DramConfig(object):
def readConfigFromFiles(self, connection):
print("Parsing dram configuration")
memconfig = MemConfig(connection)
mcconfig = MCConfig(connection)
memspec = MemSpec(connection)
clkWithUnit = getClock(connection)
self.clk = clkWithUnit[0]
self.unitOfTime = clkWithUnit[1].lower()
self.bankwiseLogic = memconfig.getValue("BankwiseLogic")
self.scheduler = memconfig.getValue("Scheduler")
self.bankwiseLogic = mcconfig.getValue("BankwiseLogic")
self.scheduler = mcconfig.getValue("Scheduler")
self.numberOfBanks = memspec.getIntValue("nbrOfBanks")
self.burstLength = memspec.getIntValue("burstLength")

0
DRAMSys/simulator/resources/configs/memconfigs/.gitignore → DRAMSys/simulator/resources/configs/mcconfigs/.gitignore vendored
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4
DRAMSys/simulator/resources/configs/memconfigs/_old/fr_fcfs_bankwise.xml → DRAMSys/simulator/resources/configs/mcconfigs/_old/fr_fcfs_bankwise.xml
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@@ -1,5 +1,5 @@
<memspec>
<memconfig>
<mcconfig>
<parameter id="bankwiseLogic" type="bool" value="1" />
<parameter id="openPagePolicy" type="bool" value="1" />
<parameter id="adaptiveOpenPagePolicy" type="bool" value="0" />
@@ -11,5 +11,5 @@
<parameter id="powerDownTimeout" type="uint" value="3" />
<parameter id="databaseRecordingEnabled" type="bool" value="1" />
</memconfig>
</mcconfig>
</memspec>

4
DRAMSys/simulator/resources/configs/memconfigs/_old/fr_fcfs_unaware.xml → DRAMSys/simulator/resources/configs/mcconfigs/_old/fr_fcfs_unaware.xml
View File

@@ -1,5 +1,5 @@
<memspec>
<memconfig>
<mcconfig>
<parameter id="bankwiseLogic" type="bool" value="0" />
<parameter id="openPagePolicy" type="bool" value="1" />
<parameter id="adaptiveOpenPagePolicy" type="bool" value="0" />
@@ -11,5 +11,5 @@
<parameter id="powerDownTimeout" type="uint" value="3" />
<parameter id="databaseRecordingEnabled" type="bool" value="1" />
</memconfig>
</mcconfig>
</memspec>

4
DRAMSys/simulator/resources/configs/memconfigs/_old/grouper.xml → DRAMSys/simulator/resources/configs/mcconfigs/_old/grouper.xml
View File

@@ -1,5 +1,5 @@
<memspec>
<memconfig>
<mcconfig>
<parameter id="bankwiseLogic" type="bool" value="0" />
<parameter id="openPagePolicy" type="bool" value="1" />
<parameter id="adaptiveOpenPagePolicy" type="bool" value="0" />
@@ -10,5 +10,5 @@
<parameter id="powerDownMode" type="string" value="Staggered" />
<parameter id="powerDownTimeout" type="uint" value="100" />
<parameter id="databaseRecordingEnabled" type="bool" value="1" />
</memconfig>
</mcconfig>
</memspec>

5
DRAMSys/simulator/resources/configs/memconfigs/_old/par_bs.xml → DRAMSys/simulator/resources/configs/mcconfigs/_old/par_bs.xml
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@@ -1,5 +1,5 @@
<memspec>
<memconfig>
<mcconfig>
<parameter id="bankwiseLogic" type="bool" value="0" />
<parameter id="openPagePolicy" type="bool" value="1" />
<parameter id="adaptiveOpenPagePolicy" type="bool" value="0" />
@@ -9,7 +9,6 @@
<parameter id="capsize" type="uint" value="8" />
<parameter id="powerDownMode" type="string" value="Staggered" />
<parameter id="powerDownTimeout" type="uint" value="3" />
<parameter id="databaseRecordingEnabled" type="bool" value="0" />
</memconfig>
</mcconfig>
</memspec>

7
DRAMSys/simulator/resources/configs/memconfigs/_old/par_bs_unaware.xml → DRAMSys/simulator/resources/configs/mcconfigs/_old/par_bs_unaware.xml
View File

@@ -1,5 +1,5 @@
<memspec>
<memconfig>
<mcconfig>
<parameter id="bankwiseLogic" type="bool" value="0" />
<parameter id="openPagePolicy" type="bool" value="1" />
<parameter id="adaptiveOpenPagePolicy" type="bool" value="0" />
@@ -8,8 +8,7 @@
<parameter id="scheduler" type="string" value="PAR_BS" />
<parameter id="capsize" type="uint" value="8" />
<parameter id="powerDownMode" type="string" value="Staggered" />
<parameter id="powerDownTimeout" type="uint" value="3" />
<parameter id="powerDownTimeout" type="uint" value="3" />
<parameter id="databaseRecordingEnabled" type="bool" value="1" />
</memconfig>
</mcconfig>
</memspec>

4
DRAMSys/simulator/resources/configs/memconfigs/fifo.xml → DRAMSys/simulator/resources/configs/mcconfigs/fifo.xml
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@@ -1,4 +1,4 @@
<memconfig>
<mcconfig>
<BankwiseLogic value="0"/>
<OpenPagePolicy value="1" />
<MaxNrOfTransactions value="8" />
@@ -11,4 +11,4 @@
<ErrorCSVFile value="../../DRAMSys/simulator/src/error/error.csv" />
<!--3 Modes: NoStorage, Store (store data without errormodel), ErrorModel (store data with errormodel)-->
<StoreMode value="NoStorage" />
</memconfig>
</mcconfig>

8
DRAMSys/simulator/resources/configs/memconfigs/fifoStrict.xml → DRAMSys/simulator/resources/configs/mcconfigs/fifoStrict.xml
View File

@@ -1,15 +1,15 @@
<memconfig>
<BankwiseLogic value="0"/>
<mcconfig>
<BankwiseLogic value="1"/>
<OpenPagePolicy value="1" />
<MaxNrOfTransactions value="8" />
<Scheduler value="FIFO_STRICT" />
<Capsize value="5" />
<PowerDownMode value="NoPowerDown" /> <!-- 4 Modes: NoPowerDown, Staggered, TimeoutPDN, TimeoutSREF -->
<PowerDownMode value="Staggered" /> <!-- 4 Modes: NoPowerDown, Staggered, TimeoutPDN, TimeoutSREF -->
<PowerDownTimeout value="100" />
<!-- Error Modelling -->
<ErrorChipSeed value="42" />
<ErrorCSVFile value="../../DRAMSys/simulator/src/error/error.csv" />
<!-- Modes: NoStorage, Store (store data without errormodel), ErrorModel (store data with errormodel) -->
<StoreMode value="NoStorage" />
</memconfig>
</mcconfig>

4
DRAMSys/simulator/resources/configs/memconfigs/fr_fcfs.xml → DRAMSys/simulator/resources/configs/mcconfigs/fr_fcfs.xml
View File

@@ -1,4 +1,4 @@
<memconfig>
<mcconfig>
<BankwiseLogic value="0"/>
<OpenPagePolicy value="1" />
<MaxNrOfTransactions value="8" />
@@ -19,5 +19,5 @@
<ReorderBuffer value="false" />
<DatabaseRecording value="true" />
-->
</memconfig>
</mcconfig>

4
DRAMSys/simulator/resources/configs/memconfigs/par_bs.xml → DRAMSys/simulator/resources/configs/mcconfigs/par_bs.xml
View File

@@ -1,4 +1,4 @@
<memconfig>
<mcconfig>
<BankwiseLogic value="0"/>
<OpenPagePolicy value="1" />
<MaxNrOfTransactions value="8" />
@@ -11,5 +11,5 @@
<ErrorCSVFile value="../../DRAMSys/simulator/src/error/error.csv" />
<!-- Modes: NoStorage, Store (store data without errormodel), ErrorModel (store data with errormodel) -->
<StoreMode value="NoStorage" />
</memconfig>
</mcconfig>

20
DRAMSys/simulator/resources/resources.pri
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@@ -49,16 +49,16 @@ OTHER_FILES += resources/traces/small.stl
OTHER_FILES += resources/traces/chstone-motion_32.stl
OTHER_FILES += resources/traces/mediabench-adpcmdecode_32.stl
# memconfigs
OTHER_FILES += resources/configs/memconfigs/fifoStrict.xml
OTHER_FILES += resources/configs/memconfigs/fifo.xml
OTHER_FILES += resources/configs/memconfigs/_old/par_bs_unaware.xml
OTHER_FILES += resources/configs/memconfigs/_old/fr_fcfs_unaware.xml
OTHER_FILES += resources/configs/memconfigs/_old/grouper.xml
OTHER_FILES += resources/configs/memconfigs/_old/par_bs.xml
OTHER_FILES += resources/configs/memconfigs/_old/fr_fcfs_bankwise.xml
OTHER_FILES += resources/configs/memconfigs/fr_fcfs.xml
OTHER_FILES += resources/configs/memconfigs/par_bs.xml
# mcconfigs
OTHER_FILES += resources/configs/mcconfigs/fifoStrict.xml
OTHER_FILES += resources/configs/mcconfigs/fifo.xml
OTHER_FILES += resources/configs/mcconfigs/_old/par_bs_unaware.xml
OTHER_FILES += resources/configs/mcconfigs/_old/fr_fcfs_unaware.xml
OTHER_FILES += resources/configs/mcconfigs/_old/grouper.xml
OTHER_FILES += resources/configs/mcconfigs/_old/par_bs.xml
OTHER_FILES += resources/configs/mcconfigs/_old/fr_fcfs_bankwise.xml
OTHER_FILES += resources/configs/mcconfigs/fr_fcfs.xml
OTHER_FILES += resources/configs/mcconfigs/par_bs.xml
# memspecs
OTHER_FILES += resources/configs/memspecs/memspec.dtd

2
DRAMSys/simulator/resources/scripts/createTraceDB.sql
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@@ -20,7 +20,7 @@ CREATE TABLE GeneralInfo(
NumberOfBanks INTEGER,
clk INTEGER,
UnitOfTime TEXT,
Memconfig TEXT,
MCconfig TEXT,
Memspec TEXT,
Traces TEXT,
WindowSize INTEGER

6
DRAMSys/simulator/resources/simulations/ddr3-example.xml
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@@ -37,9 +37,9 @@
<addressmapping src="../../DRAMSys/simulator/resources/configs/amconfigs/am_ddr3.xml"></addressmapping>
</addressmappings>
<memconfigs>
<memconfig src="../../DRAMSys/simulator/resources/configs/memconfigs/fifoStrict.xml"/>
</memconfigs>
<mcconfigs>
<mcconfig src="../../DRAMSys/simulator/resources/configs/mcconfigs/fifoStrict.xml"/>
</mcconfigs>
<tracesetups>
<tracesetup id="fifo">

13
DRAMSys/simulator/resources/simulations/sim-batch.xml
View File

@@ -2,17 +2,17 @@
<!-- General Simulator Configuration (used for all simulation setups) -->
<simconfig>
<Debug value="0" />
<DatabaseRecording value="0" />
<DatabaseRecording value="1" />
<PowerAnalysis value="0" />
<EnableWindowing value = "0" />
<WindowSize value="1000" />
<NumberOfTracePlayers value="1"/>
<NumberOfTracePlayers value="2"/>
<NumberOfMemChannels value="4"/>
<ControllerCoreDisableRefresh value="0"/>
<ThermalSimulation value="0"/>
<SimulationProgressBar value="0"/>
<NumberOfDevicesOnDIMM value = "1" />
<CheckTLM2Protocol value = "0" />
<CheckTLM2Protocol value = "1" />
</simconfig>
<!-- Temperature Simulator Configuration (used for all simulation setups) -->
@@ -38,13 +38,14 @@
<addressmapping src="../../DRAMSys/simulator/resources/configs/amconfigs/am_wideio.xml"></addressmapping>
</addressmappings>
<memconfigs>
<memconfig src="../../DRAMSys/simulator/resources/configs/memconfigs/fifoStrict.xml"/>
</memconfigs>
<mcconfigs>
<mcconfig src="../../DRAMSys/simulator/resources/configs/mcconfigs/fifoStrict.xml"/>
</mcconfigs>
<tracesetups>
<tracesetup id="fifo">
<device clkMhz="200">chstone-adpcm_32.stl</device>
<device clkMhz="200">chstone-jpeg_32.stl</device>
</tracesetup>
</tracesetups>

6
DRAMSys/simulator/src/common/TlmRecorder.cpp
View File

@@ -270,8 +270,8 @@ void TlmRecorder::prepareSqlStatements()
updatePhaseString =
"UPDATE Phases SET PhaseEnd = :end WHERE Transact = :trans AND PhaseName = :name";
insertGeneralInfoString =
"INSERT INTO GeneralInfo (NumberOfTransactions,TraceEnd,NumberOfBanks,clk,UnitOfTime,Memconfig,Memspec,Traces, WindowSize) VALUES"
"(:numberOfTransactions,:end,:numberOfBanks,:clk,:unitOfTime,:memconfig,:memspec,:traces,:windowSize)";
"INSERT INTO GeneralInfo (NumberOfTransactions,TraceEnd,NumberOfBanks,clk,UnitOfTime,MCconfig,Memspec,Traces, WindowSize) VALUES"
"(:numberOfTransactions,:end,:numberOfBanks,:clk,:unitOfTime,:mcconfig,:memspec,:traces,:windowSize)";
insertDebugMessageString = "INSERT INTO DebugMessages (Time,Message) Values (:time,:message)";
insertPowerString = "INSERT INTO Power VALUES (:time,:averagePower)";
@@ -301,7 +301,7 @@ void TlmRecorder::insertGeneralInfo()
Configuration::getInstance().memSpec.NumberOfBanks);
sqlite3_bind_int(insertGeneralInfoStatement, 4, Configuration::getInstance().memSpec.clk.value());
sqlite3_bind_text(insertGeneralInfoStatement, 5, "PS", 2, NULL);
sqlite3_bind_text(insertGeneralInfoStatement, 6, memconfig.c_str(), memconfig.length(), NULL);
sqlite3_bind_text(insertGeneralInfoStatement, 6, mcconfig.c_str(), mcconfig.length(), NULL);
sqlite3_bind_text(insertGeneralInfoStatement, 7, memspec.c_str(), memspec.length(), NULL);
sqlite3_bind_text(insertGeneralInfoStatement, 8, traces.c_str(), traces.length(), NULL);
if(!Configuration::getInstance().EnableWindowing)

4
DRAMSys/simulator/src/common/TlmRecorder.h
View File

@@ -64,7 +64,7 @@ public:
TlmRecorder(sc_module_name /*name*/, string uri, string dbname, bool recenable);
~TlmRecorder();
void recordMemconfig(string memconfig){this->memconfig = memconfig;}
void recordMCconfig(string mcconfig){this->mcconfig = mcconfig;}
void recordMemspec(string memspec){this->memspec = memspec;}
void recordTracenames(string traces){this->traces = traces;}
@@ -100,7 +100,7 @@ private:
void setPhaseEnd(string name,sc_time end);
};
std::string memconfig,memspec,traces;
std::string mcconfig,memspec,traces;
void prepareSqlStatements();
void executeSqlCommand(std::string command);

2
DRAMSys/simulator/src/controller/core/configuration/Configuration.cpp
View File

@@ -44,7 +44,7 @@
using namespace std;
string Configuration::memspecUri = "";
string Configuration::memconfigUri = "";
string Configuration::mcconfigUri = "";
Configuration::Configuration()
{

4
DRAMSys/simulator/src/controller/core/configuration/Configuration.h
View File

@@ -53,7 +53,7 @@ enum class EPowerDownMode{NoPowerDown, Staggered, TimeoutPDN, TimeoutSREF};
struct Configuration
{
static std::string memspecUri;
static std::string memconfigUri;
static std::string mcconfigUri;
static inline Configuration& getInstance()
{
@@ -61,7 +61,7 @@ struct Configuration
return configuration;
}
//MemConfig
//MCConfig
bool BankwiseLogic = false;
bool OpenPagePolicy = true;
unsigned int MaxNrOfTransactions = 8;

20
DRAMSys/simulator/src/controller/core/configuration/ConfigurationLoader.cpp
View File

@@ -135,26 +135,26 @@ void ConfigurationLoader::loadMemSpec(Configuration& config, XMLElement* memspec
}
}
void ConfigurationLoader::loadMemConfig(Configuration& config, string memconfigUri)
void ConfigurationLoader::loadMCConfig(Configuration& config, string mcconfigUri)
{
tinyxml2::XMLDocument doc;
loadXML(memconfigUri, doc);
XMLElement* memconfig = doc.FirstChildElement("memconfig");
loadConfig(config, memconfig);
loadXML(mcconfigUri, doc);
XMLElement* mcconfig = doc.FirstChildElement("mcconfig");
loadConfig(config, mcconfig);
}
void ConfigurationLoader::loadMemConfig(Configuration& config, XMLElement* memconfig)
void ConfigurationLoader::loadMCConfig(Configuration& config, XMLElement* mcconfig)
{
if(memconfig->Attribute("src"))
if(mcconfig->Attribute("src"))
{
XMLDocument doc;
string src(memconfig->Attribute("src"));
config.memconfigUri = src;
string src(mcconfig->Attribute("src"));
config.mcconfigUri = src;
loadXML(src, doc);
loadMemConfig(config, doc.FirstChildElement("memconfig"));
loadMCConfig(config, doc.FirstChildElement("mcconfig"));
}
loadConfig(config, memconfig);
loadConfig(config, mcconfig);
}
void ConfigurationLoader::loadDDR3(Configuration& config, XMLElement* memspec)

4
DRAMSys/simulator/src/controller/core/configuration/ConfigurationLoader.h
View File

@@ -45,8 +45,8 @@
class ConfigurationLoader
{
public:
static void loadMemConfig(Configuration& config, std::string memconfigUri);
static void loadMemConfig(Configuration& config, tinyxml2::XMLElement* memconfig);
static void loadMCConfig(Configuration& config, std::string mcconfigUri);
static void loadMCConfig(Configuration& config, tinyxml2::XMLElement* mcconfig);
static void loadSimConfig(Configuration& config, std::string simconfigUri);
static void loadSimConfig(Configuration& config,tinyxml2::XMLElement* simconfig);

4
DRAMSys/simulator/src/simulation/Simulation.cpp
View File

@@ -64,7 +64,7 @@ Simulation::Simulation(sc_module_name __attribute__((unused)) name, string pathT
xmlAddressDecoder::Initialize(setup.addressmapping);
xmlAddressDecoder::getInstance().print();
ConfigurationLoader::loadMemConfig(Configuration::getInstance(), setup.memconfig);
ConfigurationLoader::loadMCConfig(Configuration::getInstance(), setup.mcconfig);
ConfigurationLoader::loadMemSpec(Configuration::getInstance(), setup.memspec);
ConfigurationLoader::loadSimConfig(Configuration::getInstance(), setup.simconfig);
ConfigurationLoader::loadTemperatureSimConfig(Configuration::getInstance(), setup.thermalsimconfig);
@@ -92,7 +92,7 @@ void Simulation::setupTlmRecorders(const string &traceName, const string &pathTo
std::string recorderName = "tlmRecorder" + std::to_string(i);
TlmRecorder *tlmRecorder = new TlmRecorder(recorderName.c_str(), sqlScriptURI.c_str(), dbName.c_str(), Configuration::getInstance().DatabaseRecording);
tlmRecorder->recordMemconfig(Configuration::getInstance().memconfigUri);
tlmRecorder->recordMCconfig(Configuration::getInstance().mcconfigUri);
tlmRecorder->recordMemspec(Configuration::getInstance().memspecUri);
tlmRecorders.push_back(tlmRecorder);

8
DRAMSys/simulator/src/simulation/Simulation.h
View File

@@ -58,11 +58,11 @@
struct DramSetup
{
DramSetup():memspec(NULL),memconfig(NULL),simconfig(NULL),addressmapping(NULL), thermalsimconfig(NULL) {}
DramSetup(tinyxml2::XMLElement* memspec, tinyxml2::XMLElement* memconfig, tinyxml2::XMLElement* simconfig, tinyxml2::XMLElement* addressmapping, tinyxml2::XMLElement *tsc)
: memspec(memspec), memconfig(memconfig), simconfig(simconfig), addressmapping(addressmapping), thermalsimconfig(tsc) {}
DramSetup():memspec(NULL),mcconfig(NULL),simconfig(NULL),addressmapping(NULL), thermalsimconfig(NULL) {}
DramSetup(tinyxml2::XMLElement* memspec, tinyxml2::XMLElement* mcconfig, tinyxml2::XMLElement* simconfig, tinyxml2::XMLElement* addressmapping, tinyxml2::XMLElement *tsc)
: memspec(memspec), mcconfig(mcconfig), simconfig(simconfig), addressmapping(addressmapping), thermalsimconfig(tsc) {}
tinyxml2::XMLElement* memspec;
tinyxml2::XMLElement* memconfig;
tinyxml2::XMLElement* mcconfig;
tinyxml2::XMLElement* simconfig;
tinyxml2::XMLElement* addressmapping;
tinyxml2::XMLElement* thermalsimconfig;

10
DRAMSys/simulator/src/simulation/SimulationManager.cpp
View File

@@ -108,8 +108,8 @@ void SimulationManager::parseSimulationBatch(XMLElement* simulation)
XMLElement* addressmappings = simulation->FirstChildElement("addressmappings");
if(addressmappings == NULL) addressmappings = simulation;
XMLElement* memconfigs = simulation->FirstChildElement("memconfigs");
if(memconfigs == NULL) memconfigs = simulation;
XMLElement* mcconfigs = simulation->FirstChildElement("mcconfigs");
if(mcconfigs == NULL) mcconfigs = simulation;
for (XMLElement* memspec = memspecs->FirstChildElement("memspec"); memspec != NULL;
memspec = memspec->NextSiblingElement("memspec"))
@@ -119,10 +119,10 @@ void SimulationManager::parseSimulationBatch(XMLElement* simulation)
addressmapping = addressmapping->NextSiblingElement("addressmapping"))
{
for (XMLElement* memconfig = memconfigs->FirstChildElement("memconfig");
memconfig != NULL; memconfig = memconfig->NextSiblingElement("memconfig"))
for (XMLElement* mcconfig = mcconfigs->FirstChildElement("mcconfig");
mcconfig != NULL; mcconfig = mcconfig->NextSiblingElement("mcconfig"))
{
batch.dramSetups.push_back(DramSetup(memspec, memconfig, simconfig, addressmapping, thermalsimconfig));
batch.dramSetups.push_back(DramSetup(memspec, mcconfig, simconfig, addressmapping, thermalsimconfig));
}
}
}

4
DRAMSys/tests/TLM_compliance/fifoStrict.xml
View File

@@ -1,4 +1,4 @@
<memconfig>
<mcconfig>
<BankwiseLogic value="0"/>
<OpenPagePolicy value="1" />
<MaxNrOfTransactions value="8" />
@@ -11,5 +11,5 @@
<ErrorCSVFile value="../../DRAMSys/simulator/src/error/error.csv" />
<!-- Modes: NoStorage, Store (store data without errormodel), ErrorModel (store data with errormodel) -->
<StoreMode value="NoStorage"/>
</memconfig>
</mcconfig>

6
DRAMSys/tests/TLM_compliance/sim-batch.xml
View File

@@ -38,9 +38,9 @@
<addressmapping src="../../DRAMSys/simulator/resources/configs/amconfigs/am_wideio.xml"></addressmapping>
</addressmappings>
<memconfigs>
<memconfig src="../../DRAMSys/tests/TLM_compliance/fifoStrict.xml"/>
</memconfigs>
<mcconfigs>
<mcconfig src="../../DRAMSys/tests/TLM_compliance/fifoStrict.xml"/>
</mcconfigs>
<tracesetups>
<tracesetup id="TLM_compliance_test">

4
DRAMSys/tests/error/fr_fcfs.xml
View File

@@ -1,4 +1,4 @@
<memconfig>
<mcconfig>
<BankwiseLogic value="0"/>
<OpenPagePolicy value="1" />
<MaxNrOfTransactions value="8" />
@@ -19,5 +19,5 @@
<ReorderBuffer value="false" />
<DatabaseRecording value="true" />
-->
</memconfig>
</mcconfig>

6
DRAMSys/tests/error/sim-batch.xml
View File

@@ -38,9 +38,9 @@
<addressmapping src="../../DRAMSys/tests/error/am_wideio.xml"></addressmapping>
</addressmappings>
<memconfigs>
<memconfig src="../../DRAMSys/tests/error/fr_fcfs.xml"/>
</memconfigs>
<mcconfigs>
<mcconfig src="../../DRAMSys/tests/error/fr_fcfs.xml"/>
</mcconfigs>
<tracesetups>
<tracesetup id="errorTest_fr_fcfs_test_error.stl">

4
DRAMSys/tests/simple/fifoStrict.xml
View File

@@ -1,4 +1,4 @@
<memconfig>
<mcconfig>
<BankwiseLogic value="0"/>
<OpenPagePolicy value="1" />
<MaxNrOfTransactions value="8" />
@@ -11,5 +11,5 @@
<ErrorCSVFile value="../../DRAMSys/simulator/src/error/error.csv" />
<!-- Modes: NoStorage, Store (store data without errormodel), ErrorModel (store data with errormodel) -->
<StoreMode value="NoStorage" />
</memconfig>
</mcconfig>

6
DRAMSys/tests/simple/sim-batch.xml
View File

@@ -38,9 +38,9 @@
<addressmapping src="../../DRAMSys/simulator/resources/configs/amconfigs/am_wideio.xml"></addressmapping>
</addressmappings>
<memconfigs>
<memconfig src="../../DRAMSys/tests/simple/fifoStrict.xml"/>
</memconfigs>
<mcconfigs>
<mcconfig src="../../DRAMSys/tests/simple/fifoStrict.xml"/>
</mcconfigs>
<tracesetups>
<tracesetup id="simple_test_fifoStrict_chstone-adpcm_32">

4
DRAMSys/tests/timing_compliance/fifoStrict.xml
View File

@@ -1,4 +1,4 @@
<memconfig>
<mcconfig>
<BankwiseLogic value="1"/>
<OpenPagePolicy value="1" />
<MaxNrOfTransactions value="8" />
@@ -11,5 +11,5 @@
<ErrorCSVFile value="../../DRAMSys/simulator/src/error/error.csv" />
<!-- Modes: NoStorage, Store (store data without errormodel), ErrorModel (store data with errormodel) -->
<StoreMode value="NoStorage" />
</memconfig>
</mcconfig>

6
DRAMSys/tests/timing_compliance/sim-batch.xml
View File

@@ -38,9 +38,9 @@
<addressmapping src="../../DRAMSys/simulator/resources/configs/amconfigs/am_wideio.xml"></addressmapping>
</addressmappings>
<memconfigs>
<memconfig src="../../DRAMSys/tests/timing_compliance/fifoStrict.xml"/>
</memconfigs>
<mcconfigs>
<mcconfig src="../../DRAMSys/tests/timing_compliance/fifoStrict.xml"/>
</mcconfigs>
<tracesetups>
<tracesetup id="timing_compliance_test_fifoStrict">

12
DRAMSys/tests/unit/mem_util.py
View File

@@ -35,21 +35,21 @@
import xml.etree.ElementTree as ET
class MemConfig(object):
""" Memory Configuration Class
class MCConfig(object):
""" Memory Controller Configuration Class
The format used in memory specification XML files differs from the
format used in memory configuration XML files. Each class uses the
proper format when searching for elements.
format used in memory controller configuration XML files. Each class
uses the proper format when searching for elements.
"""
def getValue(self, id):
return self.xmlMemConfig.findall(id)[0].attrib['value']
return self.xmlMCConfig.findall(id)[0].attrib['value']
def getIntValue(self, id):
return int(self.getValue(id))
def __init__(self, xmlfile):
self.xmlMemConfig = ET.parse(xmlfile)
self.xmlMCConfig = ET.parse(xmlfile)
class MemSpec(object):

4
DRAMSys/tests/unit/unit_test.py
View File

@@ -49,7 +49,7 @@ tempfile.tempdir = os.getcwd() + '/' + rootdir
builddir = tempfile.mkdtemp()
simdir = builddir + '/simulator'
memConfigPath = rootdir + '/DRAMSys/simulator/resources/configs/memconfigs'
mcConfigPath = rootdir + '/DRAMSys/simulator/resources/configs/mcconfigs'
memSpecsPath = rootdir + '/DRAMSys/simulator/resources/configs/memspecs'
@@ -90,7 +90,7 @@ class TestOutput(unittest.TestCase):
@unittest.skip("skipping this")
class TestDummy(unittest.TestCase):
def test_list_files(self):
for file in os.listdir(memConfigPath):
for file in os.listdir(mcConfigPath):
if file.endswith(".xml"):
print(file)
for file in os.listdir(memSpecsPath):