Add common MemoryManager
This commit is contained in:
36
tests/tests_simulator/cache/ListInitiator.cpp
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36
tests/tests_simulator/cache/ListInitiator.cpp
vendored
@@ -43,7 +43,7 @@
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#include <tlm>
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#include <utility>
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ListInitiator::ListInitiator(const sc_core::sc_module_name& name, MemoryManager& memoryManager) :
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ListInitiator::ListInitiator(const sc_core::sc_module_name& name, DRAMSys::MemoryManager& memoryManager) :
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sc_core::sc_module(name),
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iSocket("iSocket"),
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peq(this, &ListInitiator::peqCallback),
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@@ -64,30 +64,30 @@ void ListInitiator::process()
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? tlm::TLM_WRITE_COMMAND
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: tlm::TLM_READ_COMMAND;
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auto& trans = memoryManager.allocate(testTransactionData.dataLength);
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trans.acquire();
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auto* trans = memoryManager.allocate(testTransactionData.dataLength);
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trans->acquire();
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TestExtension* ext = new TestExtension(testTransactionData);
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trans.set_auto_extension(ext);
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trans->set_auto_extension(ext);
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trans.set_command(command);
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trans.set_address(testTransactionData.address);
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trans.set_data_length(testTransactionData.dataLength);
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trans.set_streaming_width(testTransactionData.dataLength);
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trans.set_byte_enable_ptr(nullptr);
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trans.set_dmi_allowed(false);
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trans.set_response_status(tlm::TLM_INCOMPLETE_RESPONSE);
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trans->set_command(command);
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trans->set_address(testTransactionData.address);
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trans->set_data_length(testTransactionData.dataLength);
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trans->set_streaming_width(testTransactionData.dataLength);
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trans->set_byte_enable_ptr(nullptr);
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trans->set_dmi_allowed(false);
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trans->set_response_status(tlm::TLM_INCOMPLETE_RESPONSE);
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if (trans.is_write())
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if (trans->is_write())
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std::memcpy(
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trans.get_data_ptr(), &testTransactionData.data, testTransactionData.dataLength);
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trans->get_data_ptr(), &testTransactionData.data, testTransactionData.dataLength);
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if (requestInProgress != nullptr)
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{
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wait(endRequest);
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}
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requestInProgress = &trans;
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requestInProgress = trans;
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tlm::tlm_phase phase = tlm::BEGIN_REQ;
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sc_core::sc_time delay = sc_core::SC_ZERO_TIME;
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@@ -99,17 +99,17 @@ void ListInitiator::process()
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<< "0x" << std::setfill('0') << std::setw(8) << std::hex
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<< testTransactionData.data << "(nb_transport) \033[0m" << std::endl;
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tlm::tlm_sync_enum status = iSocket->nb_transport_fw(trans, phase, delay);
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tlm::tlm_sync_enum status = iSocket->nb_transport_fw(*trans, phase, delay);
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if (status == tlm::TLM_UPDATED)
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{
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peq.notify(trans, phase, delay);
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peq.notify(*trans, phase, delay);
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}
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else if (status == tlm::TLM_COMPLETED)
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{
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requestInProgress = nullptr;
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checkTransaction(trans);
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trans.release();
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checkTransaction(*trans);
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trans->release();
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}
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}
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}
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6
tests/tests_simulator/cache/ListInitiator.h
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6
tests/tests_simulator/cache/ListInitiator.h
vendored
@@ -33,7 +33,7 @@
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* Derek Christ
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*/
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#include "simulator/MemoryManager.h"
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#include <DRAMSys/common/MemoryManager.h>
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#include <tlm_utils/peq_with_cb_and_phase.h>
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#include <tlm_utils/simple_initiator_socket.h>
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@@ -44,7 +44,7 @@ public:
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tlm_utils::simple_initiator_socket<ListInitiator> iSocket;
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SC_HAS_PROCESS(ListInitiator);
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ListInitiator(const sc_core::sc_module_name& name, MemoryManager& memoryManager);
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ListInitiator(const sc_core::sc_module_name& name, DRAMSys::MemoryManager& memoryManager);
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struct TestTransactionData
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{
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@@ -102,5 +102,5 @@ private:
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sc_core::sc_event endRequest;
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tlm_utils::peq_with_cb_and_phase<ListInitiator> peq;
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tlm::tlm_generic_payload* requestInProgress = nullptr;
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MemoryManager& memoryManager;
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DRAMSys::MemoryManager& memoryManager;
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};
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4
tests/tests_simulator/cache/tests_cache.cpp
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4
tests/tests_simulator/cache/tests_cache.cpp
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@@ -37,7 +37,7 @@
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#include "TargetMemory.h"
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#include <simulator/Cache.h>
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#include <simulator/MemoryManager.h>
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#include <DRAMSys/common/MemoryManager.h>
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#include <gtest/gtest.h>
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@@ -72,7 +72,7 @@ protected:
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cache.iSocket.bind(target.tSocket);
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}
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MemoryManager memoryManager;
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DRAMSys::MemoryManager memoryManager;
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ListInitiator initiator;
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TargetMemory target;
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Cache cache;
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