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Added configuration python files for etraces

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This commit is contained in:
Matthias Jung
2018-08-28 09:49:44 +02:00
parent a2931df299
commit c4390e1444
4 changed files with 902 additions and 0 deletions
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504
DRAMSys/gem5/configs/singleElasticTraceReplayWithL2.ini Normal file
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[root]
type=Root
children=system
eventq_index=0
full_system=false
sim_quantum=0
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=clk_domain cpu cpu_clk_domain cpu_voltage_domain dvfs_handler l2cache membus physmem tlm tol2bus voltage_domain
boot_osflags=a
cache_line_size=64
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
exit_on_work_items=false
init_param=0
kernel=
kernel_addr_check=true
load_addr_mask=1099511627775
load_offset=0
mem_mode=timing
mem_ranges=0:1073741823:0:0:0:0
memories=system.physmem
mmap_using_noreserve=false
multi_thread=false
num_work_ids=16
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
readfile=
symbolfile=
thermal_components=
thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.membus.slave[0]
[system.clk_domain]
type=SrcClockDomain
clock=1000
domain_id=-1
eventq_index=0
init_perf_level=0
voltage_domain=system.voltage_domain
[system.cpu]
type=TraceCPU
children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb tracer
checker=Null
clk_domain=system.clk_domain
cpu_id=0
dataTraceFile=/Users/myzinsky/EMS/Programming/gem5.traces/2015_09_08/hpc_simpoints/hpcc-gups/l1-base_l2-none_l3-base_mem-simple1/system.cluster.cpu.ElasticTrace.data.itrc.gz
default_p_state=UNDEFINED
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dstage2_mmu=system.cpu.dstage2_mmu
dtb=system.cpu.dtb
enableEarlyExit=false
eventq_index=0
freqMultiplier=1.0
function_trace=false
function_trace_start=0
instTraceFile=/Users/myzinsky/EMS/Programming/gem5.traces/2015_09_08/hpc_simpoints/hpcc-gups/l1-base_l2-none_l3-base_mem-simple1/system.cluster.cpu.ElasticTrace.inst.ptrc.gz
interrupts=system.cpu.interrupts
isa=system.cpu.isa
istage2_mmu=system.cpu.istage2_mmu
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
profile=0
progressMsgInterval=0
progress_interval=0
simpoint_start_insts=
sizeLoadBuffer=16
sizeROB=40
sizeStoreBuffer=16
socket_id=0
switched_out=false
syscallRetryLatency=10000
system=system
tracer=system.cpu.tracer
wait_for_remote_gdb=false
workload=
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
[system.cpu.dcache]
type=Cache
children=tags
addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.clk_domain
clusivity=mostly_incl
data_latency=2
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
is_read_only=false
max_miss_count=0
mshrs=4
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=2
sequential_access=false
size=32768
system=system
tag_latency=2
tags=system.cpu.dcache.tags
tgts_per_mshr=20
write_buffers=8
writeback_clean=false
cpu_side=system.cpu.dcache_port
mem_side=system.tol2bus.slave[1]
[system.cpu.dcache.tags]
type=LRU
assoc=2
block_size=64
clk_domain=system.clk_domain
data_latency=2
default_p_state=UNDEFINED
eventq_index=0
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=32768
tag_latency=2
[system.cpu.dstage2_mmu]
type=ArmStage2MMU
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
sys=system
tlb=system.cpu.dtb
[system.cpu.dstage2_mmu.stage2_tlb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=true
size=32
sys=system
walker=system.cpu.dstage2_mmu.stage2_tlb.walker
[system.cpu.dstage2_mmu.stage2_tlb.walker]
type=ArmTableWalker
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
is_stage2=true
num_squash_per_cycle=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sys=system
[system.cpu.dtb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=false
size=64
sys=system
walker=system.cpu.dtb.walker
[system.cpu.dtb.walker]
type=ArmTableWalker
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
is_stage2=false
num_squash_per_cycle=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sys=system
[system.cpu.icache]
type=Cache
children=tags
addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.clk_domain
clusivity=mostly_incl
data_latency=2
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
is_read_only=true
max_miss_count=0
mshrs=4
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=2
sequential_access=false
size=32768
system=system
tag_latency=2
tags=system.cpu.icache.tags
tgts_per_mshr=20
write_buffers=8
writeback_clean=true
cpu_side=system.cpu.icache_port
mem_side=system.tol2bus.slave[0]
[system.cpu.icache.tags]
type=LRU
assoc=2
block_size=64
clk_domain=system.clk_domain
data_latency=2
default_p_state=UNDEFINED
eventq_index=0
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=32768
tag_latency=2
[system.cpu.interrupts]
type=ArmInterrupts
eventq_index=0
[system.cpu.isa]
type=ArmISA
decoderFlavour=Generic
eventq_index=0
fpsid=1090793632
id_aa64afr0_el1=0
id_aa64afr1_el1=0
id_aa64dfr0_el1=1052678
id_aa64dfr1_el1=0
id_aa64isar0_el1=0
id_aa64isar1_el1=0
id_aa64mmfr0_el1=15728642
id_aa64mmfr1_el1=0
id_isar0=34607377
id_isar1=34677009
id_isar2=555950401
id_isar3=17899825
id_isar4=268501314
id_isar5=0
id_mmfr0=270536963
id_mmfr1=0
id_mmfr2=19070976
id_mmfr3=34611729
midr=1091551472
pmu=Null
system=system
vecRegRenameMode=Full
[system.cpu.istage2_mmu]
type=ArmStage2MMU
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
sys=system
tlb=system.cpu.itb
[system.cpu.istage2_mmu.stage2_tlb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=true
size=32
sys=system
walker=system.cpu.istage2_mmu.stage2_tlb.walker
[system.cpu.istage2_mmu.stage2_tlb.walker]
type=ArmTableWalker
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
is_stage2=true
num_squash_per_cycle=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sys=system
[system.cpu.itb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=false
size=64
sys=system
walker=system.cpu.itb.walker
[system.cpu.itb.walker]
type=ArmTableWalker
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
is_stage2=false
num_squash_per_cycle=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sys=system
[system.cpu.tracer]
type=ExeTracer
eventq_index=0
[system.cpu_clk_domain]
type=SrcClockDomain
clock=1000
domain_id=-1
eventq_index=0
init_perf_level=0
voltage_domain=system.cpu_voltage_domain
[system.cpu_voltage_domain]
type=VoltageDomain
eventq_index=0
voltage=1.000000
[system.dvfs_handler]
type=DVFSHandler
domains=
enable=false
eventq_index=0
sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.l2cache]
type=Cache
children=tags
addr_ranges=0:18446744073709551615:0:0:0:0
assoc=8
clk_domain=system.clk_domain
clusivity=mostly_incl
data_latency=20
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
is_read_only=false
max_miss_count=0
mshrs=20
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=20
sequential_access=false
size=1048576
system=system
tag_latency=20
tags=system.l2cache.tags
tgts_per_mshr=12
write_buffers=8
writeback_clean=false
cpu_side=system.tol2bus.master[0]
mem_side=system.membus.slave[1]
[system.l2cache.tags]
type=LRU
assoc=8
block_size=64
clk_domain=system.clk_domain
data_latency=20
default_p_state=UNDEFINED
eventq_index=0
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=1048576
tag_latency=20
[system.membus]
type=CoherentXBar
children=snoop_filter
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
forward_latency=4
frontend_latency=3
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
point_of_coherency=true
power_model=Null
response_latency=2
snoop_filter=system.membus.snoop_filter
snoop_response_latency=4
system=system
use_default_range=false
width=16
master=system.tlm.port
slave=system.system_port system.l2cache.mem_side
[system.membus.snoop_filter]
type=SnoopFilter
eventq_index=0
lookup_latency=1
max_capacity=8388608
system=system
[system.physmem]
type=SimpleMemory
bandwidth=73.000000
clk_domain=system.clk_domain
conf_table_reported=true
default_p_state=UNDEFINED
eventq_index=0
in_addr_map=true
kvm_map=true
latency=30000
latency_var=0
null=false
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
range=0:134217727:0:0:0:0
[system.tlm]
type=ExternalSlave
addr_ranges=0:4294967295:0:0:0:0
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
port_data=transactor
port_type=tlm_slave
power_model=Null
port=system.membus.master[0]
[system.tol2bus]
type=CoherentXBar
children=snoop_filter
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
forward_latency=0
frontend_latency=1
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
point_of_coherency=false
power_model=Null
response_latency=1
snoop_filter=system.tol2bus.snoop_filter
snoop_response_latency=1
system=system
use_default_range=false
width=32
master=system.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
[system.tol2bus.snoop_filter]
type=SnoopFilter
eventq_index=0
lookup_latency=0
max_capacity=8388608
system=system
[system.voltage_domain]
type=VoltageDomain
eventq_index=0
voltage=1.000000

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DRAMSys/gem5/examples/tlm_elastic_slave.py Normal file
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# Copyright (c) 2016, University of Kaiserslautern
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met:
#
# 1. Redistributions of source code must retain the above copyright notice,
# this list of conditions and the following disclaimer.
#
# 2. Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
#
# 3. Neither the name of the copyright holder nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
# TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
# OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
# PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
# LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors: Matthias Jung
import m5
import optparse
from m5.objects import *
from m5.util import addToPath, fatal
addToPath('../../../configs/common/')
from Caches import *
# This configuration shows a simple setup of a Elastic Trace Player (eTraceCPU)
# and an external TLM port for SystemC co-simulation.
#
# We assume a DRAM size of 512MB and L1 cache sizes of 32KB.
#
# Base System Architecture:
#
# +-----------+ ^
# +-------------+ | eTraceCPU | |
# | System Port | +-----+-----+ |
# +------+------+ | $D1 | $I1 | |
# | +--+--+--+--+ |
# | | | | gem5 World
# | | | | (see this file)
# | | | |
# +------v------------v-----v--+ |
# | Membus | v
# +----------------+-----------+ External Port (see sc_port.*)
# | ^
# +---v---+ | TLM World
# | TLM | | (see sc_target.*)
# +-------+ v
#
#
# Create a system with a Crossbar and an Elastic Trace Player as CPU:
# Setup System:
system = System(cpu=TraceCPU(cpu_id=0),
mem_mode='timing',
mem_ranges = [AddrRange('512MB')],
cache_line_size = 64)
# Create a top-level voltage domain:
system.voltage_domain = VoltageDomain()
# Create a source clock for the system. This is used as the clock period for
# xbar and memory:
system.clk_domain = SrcClockDomain(clock = '1GHz',
voltage_domain = system.voltage_domain)
# Create a CPU voltage domain:
system.cpu_voltage_domain = VoltageDomain()
# Create a separate clock domain for the CPUs. In case of Trace CPUs this clock
# is actually used only by the caches connected to the CPU:
system.cpu_clk_domain = SrcClockDomain(clock = '1GHz',
voltage_domain = system.cpu_voltage_domain)
# Setup CPU and its L1 caches:
system.cpu.createInterruptController()
system.cpu.icache = L1_ICache(size="32kB")
system.cpu.dcache = L1_DCache(size="32kB")
system.cpu.icache.cpu_side = system.cpu.icache_port
system.cpu.dcache.cpu_side = system.cpu.dcache_port
# Assign input trace files to the eTraceCPU:
system.cpu.instTraceFile="system.cpu.traceListener.inst.gz"
system.cpu.dataTraceFile="system.cpu.traceListener.data.gz"
# Setting up L1 BUS:
system.membus = IOXBar(width = 16)
system.physmem = SimpleMemory() # This must be instantiated, even if not needed
# Create a external TLM port:
system.tlm = ExternalSlave()
system.tlm.addr_ranges = [AddrRange('512MB')]
system.tlm.port_type = "tlm_slave"
system.tlm.port_data = "transactor1"
# Connect everything:
system.membus = SystemXBar()
system.system_port = system.membus.slave
system.cpu.icache.mem_side = system.membus.slave
system.cpu.dcache.mem_side = system.membus.slave
system.membus.master = system.tlm.port
# Start the simulation:
root = Root(full_system = False, system = system)
root.system.mem_mode = 'timing'
m5.instantiate()
m5.simulate() #Simulation time specified later on commandline

143
DRAMSys/gem5/examples/tlm_elastic_slave_mc_direct.py Normal file
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# Copyright (c) 2016, University of Kaiserslautern
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met:
#
# 1. Redistributions of source code must retain the above copyright notice,
# this list of conditions and the following disclaimer.
#
# 2. Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
#
# 3. Neither the name of the copyright holder nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
# TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
# OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
# PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
# LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors: Matthias Jung
import m5
import optparse
from m5.objects import *
from m5.util import addToPath, fatal
addToPath('../../../configs/common/')
from Caches import *
# This configuration shows a simple setup of a Elastic Trace Player (eTraceCPU)
# and an external TLM port for SystemC co-simulation.
#
# We assume a DRAM size of 512MB and L1 cache sizes of 32KB.
#
# Base System Architecture:
#
# +--------+ +-----------+ +-----------+ ^
# | System | | eTraceCPU | | eTraceCPU | |
# | Port | +-----+-----+ +-----+-----+ |
# +----+---+ | $D1 | $I1 | | $D1 | $I1 | |
# | +--+--+--+--+ +--+--+--+--+ |
# | | | | | | gem5 World
# | | | | | | (see this file)
# | | | | | |
# +----v--------v-----v--------v-----v-+ |
# | Membus | v
# +----------------+-------------------+ External Port (see sc_port.*)
# | ^
# +---v---+ | TLM World
# | TLM | | (see sc_target.*)
# +-------+ v
#
#
# Create a system with a Crossbar and Elastic Trace Player CPUs:
# Setup System:
system = System(cpu=[TraceCPU(cpu_id=i) for i in xrange(2)],
mem_mode='timing',
mem_ranges = [AddrRange('512MB')],
cache_line_size = 64)
# Create a top-level voltage domain:
system.voltage_domain = VoltageDomain()
# Create a source clock for the system. This is used as the clock period for
# xbar and memory:
system.clk_domain = SrcClockDomain(clock = '1GHz',
voltage_domain = system.voltage_domain)
# Create a CPU voltage domain:
system.cpu_voltage_domain = VoltageDomain()
# Create a separate clock domain for the CPUs. In case of Trace CPUs this clock
# is actually used only by the caches connected to the CPU:
system.cpu_clk_domain = SrcClockDomain(clock = '1GHz',
voltage_domain = system.cpu_voltage_domain)
# Setup CPUs and their L1 caches:
system.cpu[0].createInterruptController()
system.cpu[0].icache = L1_ICache(size="32kB")
system.cpu[0].dcache = L1_DCache(size="32kB")
system.cpu[0].icache.cpu_side = system.cpu[0].icache_port
system.cpu[0].dcache.cpu_side = system.cpu[0].dcache_port
system.cpu[1].createInterruptController()
system.cpu[1].icache = L1_ICache(size="32kB")
system.cpu[1].dcache = L1_DCache(size="32kB")
system.cpu[1].icache.cpu_side = system.cpu[1].icache_port
system.cpu[1].dcache.cpu_side = system.cpu[1].dcache_port
# Assign input trace files to the eTraceCPU:
system.cpu[0].instTraceFile="system.cpu.traceListener.inst.gz"
system.cpu[0].dataTraceFile="system.cpu.traceListener.data.gz"
system.cpu[1].instTraceFile="system.cpu.traceListener.inst.gz"
system.cpu[1].dataTraceFile="system.cpu.traceListener.data.gz"
# Setting up memory BUS:
system.physmem = SimpleMemory() # This must be instantiated, even if not needed
# Create a external TLM port:
system.tlm1 = ExternalSlave()
system.tlm1.addr_ranges = [AddrRange('256MB')]
system.tlm1.port_type = "tlm_slave"
system.tlm1.port_data = "transactor1"
system.tlm2 = ExternalSlave()
system.tlm2.addr_ranges = [AddrRange('256MB')]
system.tlm2.port_type = "tlm_slave"
system.tlm2.port_data = "transactor2"
# Build Helpting Busses:
system.membus1 = SystemXBar()
system.membus2 = SystemXBar()
# Connect everything:
system.system_port = system.membus1.slave
system.cpu[0].icache.mem_side = system.membus1.slave
system.cpu[0].dcache.mem_side = system.membus1.slave
system.cpu[1].icache.mem_side = system.membus2.slave
system.cpu[1].dcache.mem_side = system.membus2.slave
system.membus1.master = system.tlm1.port
system.membus2.master = system.tlm2.port
# Start the simulation:
root = Root(full_system = False, system = system)
root.system.mem_mode = 'timing'
m5.instantiate()
m5.simulate() #Simulation time specified later on commandline

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DRAMSys/gem5/examples/tlm_elastic_slave_with_l2.py Normal file
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# Copyright (c) 2016, University of Kaiserslautern
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met:
#
# 1. Redistributions of source code must retain the above copyright notice,
# this list of conditions and the following disclaimer.
#
# 2. Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
#
# 3. Neither the name of the copyright holder nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
# TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
# OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
# PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
# LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors: Matthias Jung
import m5
import optparse
from m5.objects import *
from m5.util import addToPath, fatal
addToPath('../../../configs/common/')
from Caches import *
# This configuration shows a simple setup of a Elastic Trace Player (eTraceCPU)
# and an external TLM port for SystemC co-simulation.
#
# We assume a DRAM size of 512MB and L1 cache sizes of 32KB.
#
# Base System Architecture:
#
# +-----------+ ^
# +-------------+ | eTraceCPU | |
# | System Port | +-----+-----+ |
# +------+------+ | $D1 | $I1 | |
# | +--+--+--+--+ |
# | | | | gem5 World (see this file)
# | +--v-----v--+ |
# | | toL2Bus | |
# | +-----+-----+ |
# | | |
# | +-----v-----+ |
# | | L2 | |
# | +-----+-----+ |
# | | |
# +------v---------------v-----+ |
# | Membus | v
# +----------------+-----------+ External Port (see sc_port.*)
# | ^
# +---v---+ | TLM World
# | TLM | | (see sc_target.*)
# +-------+ v
#
#
# Create a system with a Crossbar and an Elastic Trace Player as CPU:
# Setup System:
system = System(cpu=TraceCPU(cpu_id=0),
mem_mode='timing',
mem_ranges = [AddrRange('1024MB')],
cache_line_size = 64)
# Create a top-level voltage domain:
system.voltage_domain = VoltageDomain()
# Create a source clock for the system. This is used as the clock period for
# xbar and memory:
system.clk_domain = SrcClockDomain(clock = '1GHz',
voltage_domain = system.voltage_domain)
# Create a CPU voltage domain:
system.cpu_voltage_domain = VoltageDomain()
# Create a separate clock domain for the CPUs. In case of Trace CPUs this clock
# is actually used only by the caches connected to the CPU:
system.cpu_clk_domain = SrcClockDomain(clock = '1GHz',
voltage_domain = system.cpu_voltage_domain)
# Setup CPU and its L1 caches:
system.cpu.createInterruptController()
system.cpu.icache = L1_ICache(size="32kB")
system.cpu.dcache = L1_DCache(size="32kB")
system.cpu.icache.cpu_side = system.cpu.icache_port
system.cpu.dcache.cpu_side = system.cpu.dcache_port
# Assign input trace files to the eTraceCPU:
system.cpu.instTraceFile="system.cpu.traceListener.inst.gz"
system.cpu.dataTraceFile="system.cpu.traceListener.data.gz"
# Setting up L1 BUS:
system.tol2bus = L2XBar()#(width = 16)
system.l2cache = L2Cache(size="1MB")
system.physmem = SimpleMemory() # This must be instantiated, even if not needed
# Create a external TLM port:
system.tlm = ExternalSlave()
system.tlm.addr_ranges = [AddrRange('4024MB')]
system.tlm.port_type = "tlm_slave"
system.tlm.port_data = "transactor1"
# Connect everything:
system.membus = SystemXBar()
system.system_port = system.membus.slave
system.cpu.icache.mem_side = system.tol2bus.slave
system.cpu.dcache.mem_side = system.tol2bus.slave
system.tol2bus.master = system.l2cache.cpu_side
system.l2cache.mem_side = system.membus.slave
system.membus.master = system.tlm.port
# Start the simulation:
root = Root(full_system = False, system = system)
root.system.mem_mode = 'timing'
m5.instantiate()
m5.simulate() #Simulation time specified later on commandline