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Simulation Manager Removed, Cleanups

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This commit is contained in:
Matthias Jung
2017-02-19 01:21:33 +01:00
parent 813708c77e
commit bf0a71748c
41 changed files with 599 additions and 1027 deletions
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15
DRAMSys/simulator/resources/configs/mcconfigs/_old/fr_fcfs_bankwise.xml
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@@ -1,15 +0,0 @@
<memspec>
<mcconfig>
<parameter id="bankwiseLogic" type="bool" value="1" />
<parameter id="openPagePolicy" type="bool" value="1" />
<parameter id="adaptiveOpenPagePolicy" type="bool" value="0" />
<parameter id="refreshAwareScheduling" type="bool" value="0" />
<parameter id="maxNrOfTransactionsInDram" type="uint" value="2000" />
<parameter id="scheduler" type="string" value="FR_FCFS" />
<parameter id="capsize" type="uint" value="5" />
<parameter id="powerDownMode" type="string" value="Staggered" />
<parameter id="powerDownTimeout" type="uint" value="3" />
<parameter id="databaseRecordingEnabled" type="bool" value="1" />
</mcconfig>
</memspec>

15
DRAMSys/simulator/resources/configs/mcconfigs/_old/fr_fcfs_unaware.xml
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@@ -1,15 +0,0 @@
<memspec>
<mcconfig>
<parameter id="bankwiseLogic" type="bool" value="0" />
<parameter id="openPagePolicy" type="bool" value="1" />
<parameter id="adaptiveOpenPagePolicy" type="bool" value="0" />
<parameter id="refreshAwareScheduling" type="bool" value="0" />
<parameter id="maxNrOfTransactionsInDram" type="uint" value="2000" />
<parameter id="scheduler" type="string" value="FR_FCFS" />
<parameter id="capsize" type="uint" value="5" />
<parameter id="powerDownMode" type="string" value="Staggered" />
<parameter id="powerDownTimeout" type="uint" value="3" />
<parameter id="databaseRecordingEnabled" type="bool" value="1" />
</mcconfig>
</memspec>

14
DRAMSys/simulator/resources/configs/mcconfigs/_old/grouper.xml
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@@ -1,14 +0,0 @@
<memspec>
<mcconfig>
<parameter id="bankwiseLogic" type="bool" value="0" />
<parameter id="openPagePolicy" type="bool" value="1" />
<parameter id="adaptiveOpenPagePolicy" type="bool" value="0" />
<parameter id="refreshAwareScheduling" type="bool" value="1" />
<parameter id="maxNrOfTransactionsInDram" type="uint" value="50" />
<parameter id="scheduler" type="string" value="Grouper" />
<parameter id="capsize" type="uint" value="5" />
<parameter id="powerDownMode" type="string" value="Staggered" />
<parameter id="powerDownTimeout" type="uint" value="100" />
<parameter id="databaseRecordingEnabled" type="bool" value="1" />
</mcconfig>
</memspec>

14
DRAMSys/simulator/resources/configs/mcconfigs/_old/par_bs.xml
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@@ -1,14 +0,0 @@
<memspec>
<mcconfig>
<parameter id="bankwiseLogic" type="bool" value="0" />
<parameter id="openPagePolicy" type="bool" value="1" />
<parameter id="adaptiveOpenPagePolicy" type="bool" value="0" />
<parameter id="refreshAwareScheduling" type="bool" value="1" />
<parameter id="maxNrOfTransactionsInDram" type="uint" value="50" />
<parameter id="scheduler" type="string" value="PAR_BS" />
<parameter id="capsize" type="uint" value="8" />
<parameter id="powerDownMode" type="string" value="Staggered" />
<parameter id="powerDownTimeout" type="uint" value="3" />
<parameter id="databaseRecordingEnabled" type="bool" value="0" />
</mcconfig>
</memspec>

14
DRAMSys/simulator/resources/configs/mcconfigs/_old/par_bs_unaware.xml
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@@ -1,14 +0,0 @@
<memspec>
<mcconfig>
<parameter id="bankwiseLogic" type="bool" value="0" />
<parameter id="openPagePolicy" type="bool" value="1" />
<parameter id="adaptiveOpenPagePolicy" type="bool" value="0" />
<parameter id="refreshAwareScheduling" type="bool" value="0" />
<parameter id="maxNrOfTransactionsInDram" type="uint" value="50" />
<parameter id="scheduler" type="string" value="PAR_BS" />
<parameter id="capsize" type="uint" value="8" />
<parameter id="powerDownMode" type="string" value="Staggered" />
<parameter id="powerDownTimeout" type="uint" value="3" />
<parameter id="databaseRecordingEnabled" type="bool" value="1" />
</mcconfig>
</memspec>

7
DRAMSys/simulator/resources/configs/mcconfigs/fifo.xml
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@@ -4,12 +4,17 @@
<MaxNrOfTransactions value="8" />
<Scheduler value="FIFO" />
<Capsize value="5" />
<!-- 4 Modes: NoPowerDown, Staggered, TimeoutPDN, TimeoutSREF -->
<PowerDownMode value="NoPowerDown" />
<PowerDownTimeout value="100" />
<!-- Error Modelling -->
<ErrorChipSeed value="42" />
<ErrorCSVFile value="../../DRAMSys/simulator/src/error/error.csv" />
<!--3 Modes: NoStorage, Store (store data without errormodel), ErrorModel (store data with errormodel)-->
<!-- Modes:
- NoStorage,
- Store (store data without errormodel),
- ErrorModel (store data with errormodel)
-->
<StoreMode value="NoStorage" />
<ControllerCoreDisableRefresh value="0"/>
</mcconfig>

12
DRAMSys/simulator/resources/configs/mcconfigs/fifoStrict.xml
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@@ -4,13 +4,17 @@
<MaxNrOfTransactions value="8" />
<Scheduler value="FIFO_STRICT" />
<Capsize value="5" />
<PowerDownMode value="Staggered" /> <!-- 4 Modes: NoPowerDown, Staggered, TimeoutPDN, TimeoutSREF -->
<!-- 4 Modes: NoPowerDown, Staggered, TimeoutPDN, TimeoutSREF -->
<PowerDownMode value="NoPowerDown" />
<PowerDownTimeout value="100" />
<!-- Error Modelling -->
<ErrorChipSeed value="42" />
<ErrorCSVFile value="../../DRAMSys/simulator/src/error/error.csv" />
<!-- Modes: NoStorage, Store (store data without errormodel), ErrorModel (store data with errormodel) -->
<StoreMode value="Store" />
<!-- Modes:
- NoStorage,
- Store (store data without errormodel),
- ErrorModel (store data with errormodel)
-->
<StoreMode value="NoStorage" />
<ControllerCoreDisableRefresh value="0"/>
</mcconfig>

7
DRAMSys/simulator/resources/configs/mcconfigs/fr_fcfs.xml
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@@ -4,12 +4,17 @@
<MaxNrOfTransactions value="8" />
<Scheduler value="FR_FCFS" />
<Capsize value="5" />
<!-- 4 Modes: NoPowerDown, Staggered, TimeoutPDN, TimeoutSREF -->
<PowerDownMode value="NoPowerDown" />
<PowerDownTimeout value="100" />
<!-- Error Model: -->
<ErrorChipSeed value="42" />
<ErrorCSVFile value="../../DRAMSys/simulator/src/error/error.csv" />
<!-- Modes: NoStorage, Store (store data without errormodel), ErrorModel (store data with errormodel) -->
<!-- Modes:
- NoStorage,
- Store (store data without errormodel),
- ErrorModel (store data with errormodel)
-->
<StoreMode value="NoStorage" />
<ControllerCoreDisableRefresh value="0"/>
</mcconfig>

10
DRAMSys/simulator/resources/configs/mcconfigs/par_bs.xml
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@@ -4,13 +4,17 @@
<MaxNrOfTransactions value="8" />
<Scheduler value="PAR_BS" />
<Capsize value="5" />
<PowerDownMode value="NoPowerDown" /> <!-- 4 Modes: NoPowerDown, Staggered, TimeoutPDN, TimeoutSREF -->
<!-- 4 Modes: NoPowerDown, Staggered, TimeoutPDN, TimeoutSREF -->
<PowerDownMode value="NoPowerDown" />
<PowerDownTimeout value="100" />
<!-- Error Modelling -->
<ErrorChipSeed value="42" />
<ErrorCSVFile value="../../DRAMSys/simulator/src/error/error.csv" />
<!-- Modes: NoStorage, Store (store data without errormodel), ErrorModel (store data with errormodel) -->
<!-- Modes:
- NoStorage,
- Store (store data without errormodel),
- ErrorModel (store data with errormodel)
-->
<StoreMode value="NoStorage" />
<ControllerCoreDisableRefresh value="0"/>
</mcconfig>

12
DRAMSys/simulator/resources/configs/simulator/ddr3-single-device.xml Normal file
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@@ -0,0 +1,12 @@
<simconfig>
<SimulationName value="wideio" />
<Debug value="0" />
<DatabaseRecording value="1" />
<PowerAnalysis value="1" />
<EnableWindowing value = "1" />
<WindowSize value="100" />
<ThermalSimulation value="0"/>
<SimulationProgressBar value="1"/>
<NumberOfMemChannels value="1"/>
<NumberOfDevicesOnDIMM value = "8" />
</simconfig>

2
DRAMSys/simulator/resources/configs/simulator/ddr3.xml
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@@ -1,5 +1,5 @@
<simconfig>
<SimulationName value="wideio" />
<SimulationName value="ddr3" />
<Debug value="0" />
<DatabaseRecording value="1" />
<PowerAnalysis value="1" />

11
DRAMSys/simulator/resources/resources.pri
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@@ -2,7 +2,7 @@
# "DRAMSys/simulator/simulator.pro"
# simulation files
OTHER_FILES += resources/simulations/sim-batch.xml
OTHER_FILES +=
OTHER_FILES += resources/simulations/ddr3-example.xml
OTHER_FILES += resources/simulations/ddr3-single-device.xml
@@ -59,11 +59,6 @@ OTHER_FILES += resources/traces/ddr3_SAMSUNG_M471B5674QH0_DIMM_example.stl
# mcconfigs
OTHER_FILES += resources/configs/mcconfigs/fifoStrict.xml
OTHER_FILES += resources/configs/mcconfigs/fifo.xml
OTHER_FILES += resources/configs/mcconfigs/_old/par_bs_unaware.xml
OTHER_FILES += resources/configs/mcconfigs/_old/fr_fcfs_unaware.xml
OTHER_FILES += resources/configs/mcconfigs/_old/grouper.xml
OTHER_FILES += resources/configs/mcconfigs/_old/par_bs.xml
OTHER_FILES += resources/configs/mcconfigs/_old/fr_fcfs_bankwise.xml
OTHER_FILES += resources/configs/mcconfigs/fr_fcfs.xml
OTHER_FILES += resources/configs/mcconfigs/par_bs.xml
@@ -138,5 +133,7 @@ DISTFILES += \
$$PWD/configs/thermalsim/config.xml \
$$PWD/configs/simulator/wideio.xml \
$$PWD/configs/simulator/ddr3.xml \
$$PWD/configs/memspecs/wideio.xml
$$PWD/configs/memspecs/wideio.xml \
$$PWD/configs/simulator/ddr3-single-device.xml \
$$PWD/simulations/wideio-example.xml

58
DRAMSys/simulator/resources/simulations/ddr3-example.xml
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@@ -1,41 +1,23 @@
<simulation>
<!-- General Simulator Configuration (used for all simulation setups) -->
<simconfig>
</simconfig>
<!-- Temperature Simulator Configuration (used for all simulation setups) -->
<thermalsimconfig>
</thermalsimconfig>
<!-- Memory Device Specification: Which Device is on our simulated DDR3 DIMM -->
<memspecs>
<memspec src="../../DRAMSys/simulator/resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G.xml"></memspec>
</memspecs>
<!-- Configuration for the DRAMSys Simulator -->
<simconfig src="ddr3.xml" />
<!-- Temperature Simulator Configuration -->
<thermalconfig src="config.xml" />
<!-- Memory Device Specification: Which Device is on the DDR3 DIMM -->
<memspec src="MICRON_1Gb_DDR3-1600_8bit_G.xml"></memspec>
<!-- Addressmapping Configuration of the Memory Controller -->
<addressmappings>
<addressmapping src="../../DRAMSys/simulator/resources/configs/amconfigs/am_ddr3_8x1Gbx8_dimm_p1KB_brc.xml"></addressmapping>
</addressmappings>
<!-- Memory Controller Configuration -->
<mcconfigs>
<!-- Without Scheduler FIFO -->
<mcconfig src="../../DRAMSys/simulator/resources/configs/mcconfigs/fifoStrict.xml"/>
<!-- With FR-FCFS Scheduler -->
<!--<mcconfig src="../../DRAMSys/simulator/resources/configs/mcconfigs/fr_fcfs.xml"/>-->
</mcconfigs>
<tracesetups>
<tracesetup id="fifo_scram">
<!--
This device mimics an image processing application
running on an FPGA with 200 Mhz.
-->
<device clkMhz="200">_128x128_64-Pixelgroesse_scram.stl</device>
</tracesetup>
</tracesetups>
<addressmapping src="am_ddr3_8x1Gbx8_dimm_p1KB_brc.xml"></addressmapping>
<!-- Memory Controller Configuration: -->
<mcconfig src="fifoStrict.xml"/>
<!--
The following trace setup is only used in standalone mode.
In library mode e.g. in Platform Architect the trace setup is ignored.
-->
<tracesetup id="fifo_scram">
<!--
This device mimics an image processing application
running on an FPGA with 200 Mhz.
-->
<device clkMhz="200">ddr3_example.stl</device>
</tracesetup>
</simulation>

53
DRAMSys/simulator/resources/simulations/ddr3-single-device.xml
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@@ -1,36 +1,23 @@
<simulation>
<!-- General Simulator Configuration (used for all simulation setups) -->
<simconfig>
</simconfig>
<!-- Temperature Simulator Configuration (used for all simulation setups) -->
<thermalsimconfig>
</thermalsimconfig>
<!-- Memory Device Specification: Which Device is on our simulated DDR3 DIMM -->
<memspecs>
<memspec src="../../DRAMSys/simulator/resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G.xml"></memspec>
</memspecs>
<!-- Configuration for the DRAMSys Simulator -->
<simconfig src="ddr3-single-device.xml" />
<!-- Temperature Simulator Configuration -->
<thermalconfig src="config.xml" />
<!-- Memory Device Specification: Which Device is simulated -->
<memspec src="MICRON_1Gb_DDR3-1600_8bit_G.xml"></memspec>
<!-- Addressmapping Configuration of the Memory Controller -->
<addressmappings>
<addressmapping src="../../DRAMSys/simulator/resources/configs/amconfigs/am_ddr3_1Gbx8_p1KB_brc.xml"></addressmapping>
</addressmappings>
<!-- Memory Controller Configuration -->
<mcconfigs>
<!-- Without Scheduler FIFO -->
<mcconfig src="../../DRAMSys/simulator/resources/configs/mcconfigs/fifoStrict.xml"/>
</mcconfigs>
<tracesetups>
<tracesetup id="ddr3_single_dev_1Gbx8_p1KB_brc">
<!-- The bus master device runs @ 200 MHz -->
<device clkMhz="200">ddr3_single_dev_example.stl</device>
</tracesetup>
</tracesetups>
<addressmapping src="am_ddr3_1Gbx8_p1KB_brc.xml"></addressmapping>
<!-- Memory Controller Configuration: -->
<mcconfig src="fifoStrict.xml"/>
<!--
The following trace setup is only used in standalone mode.
In library mode e.g. in Platform Architect the trace setup is ignored.
-->
<tracesetup id="fifo">
<!--
This device mimics an image processing application
running on an FPGA with 200 Mhz.
-->
<device clkMhz="200">ddr3_single_dev_example.stl</device>
</tracesetup>
</simulation>

28
DRAMSys/simulator/resources/simulations/sim-batch.xml
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@@ -1,28 +0,0 @@
<simulation>
<!-- General Simulator Configuration (used for all simulation setups) -->
<simconfig>
</simconfig>
<memspecs>
<memspec src="../../DRAMSys/simulator/resources/configs/memspecs/WideIO.xml"></memspec>
</memspecs>
<thermalsimconfig>
</thermalsimconfig>
<addressmappings>
<addressmapping src="../../DRAMSys/simulator/resources/configs/amconfigs/am_wideio.xml"></addressmapping>
</addressmappings>
<mcconfigs>
<mcconfig src="../../DRAMSys/simulator/resources/configs/mcconfigs/fifoStrict.xml"/>
</mcconfigs>
<tracesetups>
<tracesetup id="fifo">
<device clkMhz="200">chstone-adpcm_32.stl</device>
</tracesetup>
</tracesetups>
</simulation>

22
DRAMSys/simulator/resources/simulations/wideio-example.xml Normal file
View File

@@ -0,0 +1,22 @@
<simulation>
<!-- Configuration for the DRAMSys Simulator -->
<simconfig src="wideio.xml" />
<!-- Temperature Simulator Configuration -->
<thermalconfig src="config.xml" />
<!-- Memory Device Specification: Which Device is used for Wide I/O -->
<memspec src="WideIO.xml"></memspec>
<!-- Addressmapping Configuration of the Memory Controller -->
<addressmapping src="am_wideio.xml"></addressmapping>
<!-- Memory Controller Configuration -->
<mcconfig src="fifoStrict.xml"/>
<!--
The following trace setup is only used in standalone mode.
In library mode e.g. in Platform Architect the trace setup is ignored.
-->
<tracesetup id="fifo">
<!--
This device mimics an processor running at 1 GHz.
-->
<device clkMhz="1000">chstone-adpcm_32.stl</device>
</tracesetup>
</simulation>

12
DRAMSys/simulator/simulator.pro
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@@ -90,7 +90,6 @@ SOURCES += \
src/controller/core/TimingCalculation.cpp \
src/controller/core/Slots.cpp \
src/controller/core/ControllerCore.cpp \
src/simulation/dramSys.cpp \
src/simulation/MemoryManager.cpp \
src/simulation/main.cpp \
src/simulation/TemperatureController.cpp \
@@ -106,7 +105,10 @@ SOURCES += \
src/controller/Controller.cpp \
src/simulation/TracePlayer.cpp \
src/simulation/StlPlayer.cpp \
src/controller/core/powerdown/PowerDownManagerTimeoutBankwise.cpp
src/controller/core/powerdown/PowerDownManagerTimeoutBankwise.cpp \
src/simulation/TraceSetup.cpp \
src/simulation/DRAMSys.cpp \
src/simulation/Setup.cpp
HEADERS += \
src/common/third_party/tinyxml2/tinyxml2.h \
@@ -143,7 +145,6 @@ HEADERS += \
src/controller/core/Slots.h \
src/controller/core/ControllerCore.h \
src/simulation/TracePlayer.h \
src/simulation/dramSys.h \
src/simulation/MemoryManager.h \
src/simulation/Dram.h \
src/simulation/Arbiter.h \
@@ -167,7 +168,10 @@ HEADERS += \
src/controller/core/configuration/ConfigurationLoader.h \
src/error/errormodel.h \
src/simulation/ExampleInitiator.h \
src/controller/core/powerdown/PowerDownManagerTimeoutBankwise.h
src/controller/core/powerdown/PowerDownManagerTimeoutBankwise.h \
src/simulation/TraceSetup.h \
src/simulation/DRAMSys.h \
src/simulation/Setup.h
thermalsim = $$(THERMALSIM)
isEmpty(thermalsim) {

9
DRAMSys/simulator/src/common/DebugManager.h
View File

@@ -41,15 +41,14 @@
#include <string>
#include <set>
#include "Utils.h"
class DebugManager
{
public:
~DebugManager();
static inline DebugManager& getInstance()
{
static DebugManager manager;
return manager;
}
DEF_SINGLETON(DebugManager);
bool writeToConsole;
bool writeToFile;

5
DRAMSys/simulator/src/common/xmlAddressdecoder.cpp
View File

@@ -44,9 +44,6 @@
using namespace std;
using namespace tinyxml2;
//tinyxml2::XMLElement* xmlAddressDecoder::addressmapping = NULL;
//xmlAddressDecoder* xmlAddressDecoder::decoder = NULL;
xmlAddressDecoder::xmlAddressDecoder()
{
addressmapping = NULL;
@@ -125,7 +122,7 @@ sc_dt::uint64 xmlAddressDecoder::encodeAddress(DecodedAddress n)
void xmlAddressDecoder::print()
{
cout << "Used addressmapping:" << endl;
cout << "====================" << endl;
cout << headline << endl;
for(auto& pair : masks)
{
cout<<pair.first<<"\t:\t" << bitset<32>(pair.second)<<endl;

11
DRAMSys/simulator/src/common/xmlAddressdecoder.h
View File

@@ -50,7 +50,16 @@
struct DecodedAddress
{
DecodedAddress():channel(0),rank(0),bankgroup(0),row(0),bank(0),column(0),bytes(0){}
DecodedAddress() : channel(0),
rank(0),
bankgroup(0),
row(0),
bank(0),
column(0),
bytes(0)
{
}
unsigned int channel;
unsigned int rank;
unsigned int bankgroup;

7
DRAMSys/simulator/src/controller/Controller.cpp
View File

@@ -495,6 +495,11 @@ bool Controller::containsPhase(tlm_phase phase, std::vector<tlm_phase> phases)
return false;
}
void Controller::end_of_simulation()
{
terminateSimulation();
}
void Controller::terminateSimulation()
{
if(Configuration::getInstance().BankwiseLogic)
@@ -508,6 +513,8 @@ void Controller::terminateSimulation()
{
controllerCore->powerDownManager->wakeUp(0, clkAlign(sc_time_stamp()));
}
endTime = sc_time_stamp();
}
void Controller::startBandwidthIdleCollector()

3
DRAMSys/simulator/src/controller/Controller.h
View File

@@ -153,6 +153,9 @@ private:
void startBandwidthIdleCollector();
void endBandwidthIdleCollector();
// SystemC related:
virtual void end_of_simulation() override;
};
#endif /* CONTROLLERWRAPPER_H_ */

5
DRAMSys/simulator/src/controller/core/configuration/Configuration.cpp
View File

@@ -149,8 +149,6 @@ void Configuration::setParameter(std::string name, std::string value)
WindowSize = string2int(value);
else if(name == "Debug")
Debug = string2bool(value);
else if (name == "NumberOfTracePlayers")
NumberOfTracePlayers = string2int(value);
else if (name == "NumberOfMemChannels") {
NumberOfMemChannels = string2int(value);
unsigned int maxNumberofMemChannels = xmlAddressDecoder::getInstance().amount["channel"];
@@ -266,9 +264,6 @@ unsigned int Configuration::getBytesPerBurst()
// offset of the N-byte-wide memory module (DIMM) (a single data word
// or burst element has N bytes. N = 2^(# bits for byte offset)).
unsigned int burstElementSizeInBytes = xmlAddressDecoder::getInstance().amount["bytes"];
cout << "burstElementSizeInBytes:" << burstElementSizeInBytes << endl;
cout << "bytesPerBurst:" << bytesPerBurst << endl;
cout << "BurstLength:" << memSpec.BurstLength << endl;
assert(bytesPerBurst == (burstElementSizeInBytes * memSpec.BurstLength));
}

1
DRAMSys/simulator/src/controller/core/configuration/Configuration.h
View File

@@ -75,7 +75,6 @@ struct Configuration
bool EnableWindowing = false;
unsigned int WindowSize = 1000;
bool Debug = false;
unsigned int NumberOfTracePlayers = 1;
unsigned int NumberOfMemChannels = 1;
bool ControllerCoreDisableRefresh = false;
bool ThermalSimulation = false;

21
DRAMSys/simulator/src/simulation/Arbiter.h
View File

@@ -76,10 +76,6 @@ public:
tSocket.register_nb_transport_fw(this, &Arbiter::nb_transport_fw);
tSocket.register_transport_dbg(this, &Arbiter::transport_dbg);
for (size_t i = 0; i < Configuration::getInstance().NumberOfTracePlayers; ++i) {
receivedResponses.push_back(queue<tlm_generic_payload*>());
}
}
void setTlmRecorders(std::vector<TlmRecorder*> recorders)
@@ -97,7 +93,7 @@ private:
vector<queue<tlm_generic_payload*>> pendingRequests;
//used to account for the response_accept_delay in the initiators (traceplayer,core etc.)
// This is a queue of responses comming from the memory side. The phase of these transactions is BEGIN_RESP.
vector<queue<tlm_generic_payload*>> receivedResponses;
std::map<unsigned int, queue<tlm_generic_payload*>> receivedResponses;
std::vector<TlmRecorder*> tlmRecorders;
@@ -109,7 +105,6 @@ private:
tlm_sync_enum nb_transport_bw(int channelId, tlm_generic_payload &payload, tlm_phase &phase, sc_time &bwDelay)
{
// Check channel ID
assert((unsigned int)channelId < iSocket.size());
if ((unsigned int)channelId != DramExtension::getExtension(payload).getChannel().ID()) {
SC_REPORT_FATAL("Arbiter", "Payload extension was corrupted");
}
@@ -127,8 +122,8 @@ private:
// This function is called when an arbiter's target socket receives a transaction from a device
tlm_sync_enum nb_transport_fw(int id, tlm_generic_payload& payload, tlm_phase& phase, sc_time& fwDelay)
{
assert ((unsigned int)id < tSocket.size());
if (phase == BEGIN_REQ) {
if (phase == BEGIN_REQ)
{
// Map the payload with socket id.
routeMap[&payload] = id;
// In the begin request phase the socket ID is appended to the payload.
@@ -158,7 +153,6 @@ private:
unsigned int channelId = DramExtension::getExtension(payload).getChannel().ID();
// Check the valid range of initiatorSocket ID and channel Id
assert(initiatorSocket < Configuration::getInstance().NumberOfTracePlayers);
assert(channelId < Configuration::getInstance().NumberOfMemChannels);
// Phases initiated by the intiator side from arbiter's point of view (devices performing memory requests to the arbiter)
@@ -210,10 +204,15 @@ private:
if ((int)initiatorSocket != routeMap[&payload]) {
SC_REPORT_FATAL("Arbiter", "Payload extension was corrupted");
}
// The arbiter receives a transaction in BEGIN_RESP phase (that came from the memory side) and forwards it to the requester device
// The arbiter receives a transaction in BEGIN_RESP phase
// (that came from the memory side) and forwards it to the requester
// device
if (receivedResponses[initiatorSocket].empty())
{
sendToInitiator(initiatorSocket, payload, phase, SC_ZERO_TIME);
// Enqueue the transaction in BEGIN_RESP phase until the initiator device acknowledge it (phase changes to END_RESP).
}
// Enqueue the transaction in BEGIN_RESP phase until the initiator
// device acknowledge it (phase changes to END_RESP).
receivedResponses[initiatorSocket].push(&payload);
} else {
SC_REPORT_FATAL(0, "Payload event queue in arbiter was triggered with unknown phase");

61
DRAMSys/simulator/src/simulation/dramSys.cpp → DRAMSys/simulator/src/simulation/DRAMSys.cpp
View File

@@ -41,7 +41,8 @@
#include <fstream>
#include <vector>
#include "dramSys.h"
#include "DRAMSys.h"
#include "Setup.h"
#include "../common/TlmRecorder.h"
#include "../common/DebugManager.h"
#include "../common/xmlAddressdecoder.h"
@@ -54,16 +55,24 @@
using namespace std;
DRAMSys::DRAMSys(sc_module_name __attribute__((unused)) name,
string pathToResources,
string memspec,
string mcconfig,
string amconfig,
string simconfig,
string thermalconfig)
string simulationToRun,
string pathToResources)
{
logo();
SC_THREAD(stop);
// Read Configuration Setup:
string memspec;
string mcconfig;
string amconfig;
string simconfig;
string thermalconfig;
Setup setup(simulationToRun,
memspec,
mcconfig,
amconfig,
simconfig,
thermalconfig);
// The xmlAddressDecoder MUST be initialized before calling the
// ConfigurationLoader because some information from the xmlAddressDecoder
@@ -116,9 +125,7 @@ void DRAMSys::logo()
cout << REDTXT("=| |= ") << BOLDBLUETXT("University of Kaiserslautern")
<< endl;
cout << REDTXT(" +---+ ") << endl;
cout << REDTXT(" ||| ") << "DRAMSys -"
<< " Approximately-Timed TLM Models for DDR and Wide I/0 DRAM -"
<< endl;
cout << REDTXT(" ||| ") << "DRAMSys v3.0" << endl;
cout << endl;
#undef REDTXT
#undef BOLDBLUETXT
@@ -265,38 +272,6 @@ DRAMSys::~DRAMSys()
}
}
void DRAMSys::stop()
{
wait(terminateSimulation);
unsigned int pending_payloads = 0;
do
{
pending_payloads = 0;
for (auto controller : controllers)
{
pending_payloads += controller->getTotalNumberOfPayloadsInSystem();
}
wait(sc_time(200, SC_NS));
}
while(pending_payloads != 0);
for (auto controller : controllers)
{
controller->terminateSimulation();
}
wait(sc_time(200, SC_NS));
for (auto rec : tlmRecorders)
{
rec->closeConnection();
}
sc_stop();
}
void DRAMSys::report(string message)
{
DebugManager::getInstance().printDebugMessage(this->name(), message);

21
DRAMSys/simulator/src/simulation/dramSys.h → DRAMSys/simulator/src/simulation/DRAMSys.h
View File

@@ -59,16 +59,11 @@ public:
SC_HAS_PROCESS(DRAMSys);
DRAMSys(sc_module_name name,
string pathToResources,
string memspec,
string mcconfig,
string amconfig,
string simconfig,
string thermalconfig);
string simulationToRun,
string pathToResources);
~DRAMSys();
void stop();
void logo();
@@ -77,7 +72,8 @@ private:
//DramSetup setup;
//TLM 2.0 Protocol Checkers
std::vector<tlm_utils::tlm2_base_protocol_checker<>*> controllersTlmCheckers;
std::vector<tlm_utils::tlm2_base_protocol_checker<>*>
controllersTlmCheckers;
// All transactions pass through the same arbiter
Arbiter *arbiter;
@@ -91,12 +87,15 @@ private:
// DRAM units
std::vector<Dram*> drams;
// Transaction Recorders (one per channel). They generate the output databases.
// Transaction Recorders (one per channel).
// They generate the output databases.
std::vector<TlmRecorder*> tlmRecorders;
void report(std::string message);
void setupTlmRecorders(const string &traceName, const string &pathToResources);
void instantiateModules(const string &traceName, const string &pathToResources);
void setupTlmRecorders(const string &traceName,
const string &pathToResources);
void instantiateModules(const string &traceName,
const string &pathToResources);
void bindSockets();
void setupDebugManager(const string &traceName);
};

76
DRAMSys/simulator/src/simulation/Dram.h
View File

@@ -212,39 +212,85 @@ struct Dram : sc_module
}
}
virtual void end_of_simulation()
{
}
~Dram()
{
if (powerAnalysis == true) {
// Obtain the residual energy which was not covered by previous windows
if (powerAnalysis == true)
{
// Obtain the residual energy which was not covered by
// previous windows
DRAMPower->calcEnergy();
tlmRecorder->recordPower(sc_time_stamp().to_seconds(), DRAMPower->getPower().window_average_power * Configuration::getInstance().NumberOfDevicesOnDIMM);
tlmRecorder->recordPower(sc_time_stamp().to_seconds(),
DRAMPower->getPower().window_average_power
* Configuration::getInstance().NumberOfDevicesOnDIMM);
// Print the final total energy and the average power for the simulation
cout << name() << string("\tTotal Energy: \t") << fixed <<std::setprecision( 2 )<< DRAMPower->getEnergy().total_energy * Configuration::getInstance().NumberOfDevicesOnDIMM << string(" pJ") << endl;
cout << name() << string("\tAverage Power: \t") << fixed <<std::setprecision( 2 )<< DRAMPower->getPower().average_power * Configuration::getInstance().NumberOfDevicesOnDIMM<< string(" mW") << endl;
// Print the final total energy and the average power for
// the simulation:
cout << name() << string(" Total Energy: ")
<< fixed <<std::setprecision( 2 )
<< DRAMPower->getEnergy().total_energy
* Configuration::getInstance().NumberOfDevicesOnDIMM
<< string(" pJ")
<< endl;
cout << name() << string(" Average Power: ")
<< fixed <<std::setprecision( 2 )
<< DRAMPower->getPower().average_power
* Configuration::getInstance().NumberOfDevicesOnDIMM
<< string(" mW") << endl;
}
// Bandwidth:
sc_time activeTime = numberOfTransactionsServed * Configuration::getInstance().memSpec.BurstLength / Configuration::getInstance().memSpec.DataRate * Configuration::getInstance().memSpec.clk;
sc_time activeTime = numberOfTransactionsServed
* Configuration::getInstance().memSpec.BurstLength
/ Configuration::getInstance().memSpec.DataRate
* Configuration::getInstance().memSpec.clk;
sc_time idleTime = dramController->getIdleTime();
sc_time endTime = dramController->getEndTime();
sc_time startTime = dramController->getStartTime();
double bandwidth = (activeTime/(endTime-startTime)*100);
double bandwidth_IDLE = ((activeTime)/(endTime-startTime-idleTime)*100);
// | clk in Mhz e.g. 800 [MHz] | * | DataRate e.g. 2 | * | BusWidth e.g. 8 | * | Number of devices on a DIMM e.g. 8 | / | 1024 |
double maxBandwidth = ( (1000000/Configuration::getInstance().memSpec.clk.to_double()) * Configuration::getInstance().memSpec.DataRate * Configuration::getInstance().memSpec.bitWidth * Configuration::getInstance().NumberOfDevicesOnDIMM ) / ( 1024 );
cout << name() << string("\tTotal Time: \t") <<(endTime-startTime).to_string() << endl;
//cout << name() << string("\tTotal IDLE: \t") <<idleTime.to_string() << endl;
//cout << name() << string("\tTotal Active DataBus: \t") << activeTime.to_string() << endl;
cout << name() << string("\tAVG BW: \t") <<std::fixed<<std::setprecision(2) << ((bandwidth/100)*maxBandwidth) << " Gibit/s (" << bandwidth << " %)" << endl;
cout << name() << string("\tAVG BW/IDLE: \t") <<std::fixed<<std::setprecision(2) << ((bandwidth_IDLE/100)*maxBandwidth) <<" Gibit/s ("<< (bandwidth_IDLE) << " %)" << endl;
cout << name() << string("\tMAX BW: \t") <<std::fixed<<std::setprecision(2) <<maxBandwidth << " Gibit/s" << endl;
double maxBandwidth = (
// clk in Mhz e.g. 800 [MHz]:
(1000000/Configuration::getInstance().memSpec.clk.to_double())
// DataRate e.g. 2
* Configuration::getInstance().memSpec.DataRate
// BusWidth e.g. 8 or 64
* Configuration::getInstance().memSpec.bitWidth
// Number of devices on a DIMM e.g. 8
* Configuration::getInstance().NumberOfDevicesOnDIMM ) / ( 1024 );
cout << name() << string(" Total Time: ")
<< (endTime-startTime).to_string()
<< endl;
cout << name() << string(" AVG BW: ")
<< std::fixed<<std::setprecision(2)
<< ((bandwidth/100)*maxBandwidth)
<< " Gibit/s (" << bandwidth << " %)"
<< endl;
cout << name() << string(" AVG BW/IDLE: ")
<< std::fixed<<std::setprecision(2)
<< ((bandwidth_IDLE/100)*maxBandwidth)
<< " Gibit/s ("<< (bandwidth_IDLE) << " %)"
<< endl;
cout << name() << string(" MAX BW: ")
<< std::fixed << std::setprecision(2)
<< maxBandwidth << " Gibit/s"
<< endl;
// Clean up:
for (auto e : ememory) {
delete e;
}
tlmRecorder->closeConnection();
}
// When working with floats, we have to decide ourselves what is an

75
DRAMSys/simulator/src/simulation/Setup.cpp Normal file
View File

@@ -0,0 +1,75 @@
/*
* Copyright (c) 2017, University of Kaiserslautern
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
* OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors:
* Matthias Jung
*/
#include "Setup.h"
Setup::Setup(std::string uri,
std::string & memspec,
std::string & mcconfig,
std::string & amconfig,
std::string & simconfig,
std::string & thermalconfig)
{
// Load Simulation:
tinyxml2::XMLDocument simulationdoc;
loadXML(uri, simulationdoc);
tinyxml2::XMLElement* simulation =
simulationdoc.FirstChildElement("simulation");
std::string xmlNodeName(simulation->Name());
if( xmlNodeName != "simulation")
reportFatal("SimulationManager",
"Cannot load simulation: simulation node expected");
// Load all sub-configuration XML files:
tinyxml2::XMLElement* s;
s = simulation->FirstChildElement("memspec");
memspec = s->Attribute("src");
s = simulation->FirstChildElement("mcconfig");
mcconfig = s->Attribute("src");
s = simulation->FirstChildElement("addressmapping");
amconfig = s->Attribute("src");
s = simulation->FirstChildElement("simconfig");
simconfig = s->Attribute("src");
s = simulation->FirstChildElement("thermalconfig");
thermalconfig = s->Attribute("src");
}

58
DRAMSys/simulator/src/simulation/Setup.h Normal file
View File

@@ -0,0 +1,58 @@
/*
* Copyright (c) 2017, University of Kaiserslautern
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
* OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors:
* Matthias Jung
*/
#ifndef SETUP_H
#define SETUP_H
#include <vector>
#include <string>
#include "../common/Utils.h"
#include "TracePlayer.h"
#include "StlPlayer.h"
class Setup
{
public:
Setup(std::string uri,
std::string & memspec,
std::string & mcconfig,
std::string & amconfig,
std::string & simconfig,
std::string & thermalconfig);
};
#endif // SETUP_H

212
DRAMSys/simulator/src/simulation/Simulation.cpp
View File

@@ -1,212 +0,0 @@
/*
* Copyright (c) 2015, University of Kaiserslautern
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
* OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors:
* Janik Schlemminger
* Matthias Jung
* Eder F. Zulian
* Felipe S. Prado
*/
#include <stdlib.h>
#include <iostream>
#include <fstream>
#include <vector>
#include "Simulation.h"
#include "../common/TlmRecorder.h"
#include "../common/DebugManager.h"
#include "../common/xmlAddressdecoder.h"
#include "../controller/core/ControllerCore.h"
#include "../controller/core/configuration/ConfigurationLoader.h"
#include "../common/Utils.h"
#include "../simulation/TemperatureController.h"
#include "../controller/Controller.h"
using namespace std;
Simulation::Simulation(sc_module_name __attribute__((unused)) name, string pathToResources, string traceName, DramSetup setup,
std::vector<Device> devices) : traceName(traceName), dramSetup(setup)
{
SC_THREAD(stop);
// XXX: The xmlAddressDecoder MUST be initialized before calling the
// ConfigurationLoader because some information from the xmlAddressDecoder
// is needed to assure the coherence of the configuration.
xmlAddressDecoder::Initialize(setup.addressmapping);
xmlAddressDecoder::getInstance().print();
ConfigurationLoader::loadMCConfig(Configuration::getInstance(), setup.mcconfig);
ConfigurationLoader::loadMemSpec(Configuration::getInstance(), setup.memspec);
ConfigurationLoader::loadSimConfig(Configuration::getInstance(), setup.simconfig);
ConfigurationLoader::loadTemperatureSimConfig(Configuration::getInstance(), setup.thermalsimconfig);
instantiateModules(traceName, pathToResources, devices);
bindSockets();
setupDebugManager(traceName);
}
void Simulation::setupDebugManager(const string& traceName)
{
auto& dbg = DebugManager::getInstance();
dbg.writeToConsole = true;
dbg.writeToFile = true;
if(dbg.writeToFile)
dbg.openDebugFile(traceName + ".txt");
}
void Simulation::setupTlmRecorders(const string &traceName, const string &pathToResources, const std::vector<Device> &devices)
{
// Create TLM Recorders, one per channel.
for (size_t i = 0; i < Configuration::getInstance().NumberOfMemChannels; i++) {
std::string sqlScriptURI = pathToResources + string("scripts/createTraceDB.sql");
std::string dbName = traceName + string("_channel") + std::to_string(i) + ".tdb";
std::string recorderName = "tlmRecorder" + std::to_string(i);
TlmRecorder *tlmRecorder = new TlmRecorder(recorderName.c_str(), sqlScriptURI.c_str(), dbName.c_str(), Configuration::getInstance().DatabaseRecording);
tlmRecorder->recordMCconfig(Configuration::getInstance().mcconfigUri);
tlmRecorder->recordMemspec(Configuration::getInstance().memspecUri);
tlmRecorders.push_back(tlmRecorder);
std::string traceNames;
for (size_t i = 0; i < devices.size(); i++) {
traceNames.append(devices[i].trace);
if (i == devices.size() - 1)
continue;
traceNames.append(",");
}
tlmRecorder->recordTracenames(traceNames);
}
}
void Simulation::instantiateModules(const string &traceName, const string &pathToResources, const std::vector<Device> &devices)
{
// The first call to getInstance() creates the Temperature Controller.
// The same instance will be accessed by all other modules.
TemperatureController::getInstance();
// Create and properly initialize TLM recorders. They need to be ready before creating some modules.
setupTlmRecorders(traceName, pathToResources, devices);
arbiter = new Arbiter("arbiter");
arbiter->setTlmRecorders(tlmRecorders);
for (size_t i = 0; i < Configuration::getInstance().NumberOfMemChannels; i++) {
std::string str = "controller" + std::to_string(i);
Controller *controller = new Controller(str.c_str(), tlmRecorders[i]);
controllers.push_back(controller);
str = "dram" + std::to_string(i);
Dram *dram = new Dram(str.c_str());
dram->setTlmRecorder(tlmRecorders[i]);
dram->setDramController(controllers[i]);
drams.push_back(dram);
if(Configuration::getInstance().CheckTLM2Protocol) {
str = "TLMCheckerController"+ std::to_string(i);
tlm_utils::tlm2_base_protocol_checker<> * controllerTlmChecker = new tlm_utils::tlm2_base_protocol_checker<>(str.c_str());
controllersTlmCheckers.push_back(controllerTlmChecker);
}
}
}
void Simulation::bindSockets()
{
tSocket.bind(arbiter->tSocket);
if(Configuration::getInstance().CheckTLM2Protocol) {
for (size_t i = 0; i < Configuration::getInstance().NumberOfMemChannels; i++) {
arbiter->iSocket.bind(controllersTlmCheckers[i]->target_socket);
controllersTlmCheckers[i]->initiator_socket.bind(controllers[i]->tSocket);
controllers[i]->iSocket.bind(drams[i]->tSocket);
}
} else {
for (size_t i = 0; i < Configuration::getInstance().NumberOfMemChannels; i++) {
arbiter->iSocket.bind(controllers[i]->tSocket);
controllers[i]->iSocket.bind(drams[i]->tSocket);
}
}
}
Simulation::~Simulation()
{
delete arbiter;
for (auto controller : controllers) {
delete controller;
}
for (auto dram : drams) {
delete dram;
}
for (auto rec : tlmRecorders) {
delete rec;
}
for (auto tlmChecker : controllersTlmCheckers) {
delete tlmChecker;
}
}
void Simulation::stop()
{
wait(terminateSimulation);
unsigned int pending_payloads = 0;
do {
pending_payloads = 0;
for (auto controller : controllers) {
pending_payloads += controller->getTotalNumberOfPayloadsInSystem();
}
wait(sc_time(200, SC_NS));
} while(pending_payloads != 0);
for (auto controller : controllers) {
controller->terminateSimulation();
}
wait(sc_time(200, SC_NS));
for (auto rec : tlmRecorders) {
rec->closeConnection();
}
sc_stop();
}
void Simulation::report(string message)
{
DebugManager::getInstance().printDebugMessage(this->name(), message);
cout << message << endl;
}

117
DRAMSys/simulator/src/simulation/Simulation.h
View File

@@ -1,117 +0,0 @@
/*
* Copyright (c) 2015, University of Kaiserslautern
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
* OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors:
* Janik Schlemminger
* Matthias Jung
* Eder F. Zulian
* Felipe S. Prado
*/
#ifndef SIMULATION_H_
#define SIMULATION_H_
#include <string>
#include <systemc.h>
#include "Dram.h"
#include "Arbiter.h"
#include "TraceGenerator.h"
#include "ReorderBuffer.h"
#include "../controller/Controller.h"
#include "../common/third_party/tinyxml2/tinyxml2.h"
#include "../common/tlm2_base_protocol_checker.h"
struct DramSetup
{
DramSetup():memspec(NULL),mcconfig(NULL),simconfig(NULL),addressmapping(NULL), thermalsimconfig(NULL) {}
DramSetup(tinyxml2::XMLElement* memspec, tinyxml2::XMLElement* mcconfig, tinyxml2::XMLElement* simconfig, tinyxml2::XMLElement* addressmapping, tinyxml2::XMLElement *tsc)
: memspec(memspec), mcconfig(mcconfig), simconfig(simconfig), addressmapping(addressmapping), thermalsimconfig(tsc) {}
tinyxml2::XMLElement* memspec;
tinyxml2::XMLElement* mcconfig;
tinyxml2::XMLElement* simconfig;
tinyxml2::XMLElement* addressmapping;
tinyxml2::XMLElement* thermalsimconfig;
};
struct Device
{
Device():trace("empty.stl"), burstLength(0){}
Device(std::string trace, unsigned int clkMhz, unsigned int burstLength = 8) : trace(trace), clkMhz (clkMhz), burstLength(burstLength)
{
}
std::string trace;
unsigned int clkMhz;
unsigned int burstLength;
};
class Simulation: public sc_module
{
public:
tlm_utils::multi_passthrough_target_socket<Simulation> tSocket;
sc_event terminateSimulation;
SC_HAS_PROCESS(Simulation);
Simulation(sc_module_name name, string pathToResources, string traceName, DramSetup setup,
std::vector<Device> devices);
~Simulation();
void stop();
private:
std::string traceName;
DramSetup dramSetup;
//TLM 2.0 Protocol Checkers
std::vector<tlm_utils::tlm2_base_protocol_checker<>*> controllersTlmCheckers;
// All transactions pass through the same arbiter
Arbiter *arbiter;
// Each DRAM unit has a controller
std::vector<Controller*> controllers;
// TODO: Each DRAM has a reorder buffer (check this!)
ReorderBuffer *reorder;
// DRAM units
std::vector<Dram*> drams;
// Transaction Recorders (one per channel). They generate the output databases.
std::vector<TlmRecorder*> tlmRecorders;
void report(std::string message);
void setupTlmRecorders(const string &traceName, const string &pathToResources, const std::vector<Device> &devices);
void instantiateModules(const string &traceName, const string &pathToResources, const std::vector<Device> &devices);
void bindSockets();
void setupDebugManager(const string &traceName);
};
#endif /* SIMULATIONMANAGER_H_ */

310
DRAMSys/simulator/src/simulation/SimulationManager.cpp
View File

@@ -1,310 +0,0 @@
/*
* Copyright (c) 2015, University of Kaiserslautern
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
* OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors:
* Janik Schlemminger
* Matthias Jung
* Eder F. Zulian
*/
#include <sys/wait.h>
#include <boost/filesystem.hpp>
#include "SimulationManager.h"
#include "../common/Utils.h"
using namespace std;
using namespace tinyxml2;
SimulationManager::SimulationManager(string resources) : resources(resources)
{
}
SimulationManager::~SimulationManager()
{
for (auto player : players) {
delete player;
}
#if USE_EXAMPLE_INITIATOR
delete init;
delete exampleInitiatorTlmChecker;
#endif
for (auto tlmChecker : playersTlmCheckers) {
delete tlmChecker;
}
}
void SimulationManager::loadSimulationsFromXML(string uri)
{
cout << "\n\nload simulation-batch:" << endl;
cout << headline << endl;
exportPath = getFileName(uri);
loadXML(uri, simulationdoc);
cout << "\t-> parsing simulation objects .." << endl;
XMLElement* simulation = simulationdoc.FirstChildElement("simulation");
string xmlNodeName(simulation->Name());
if( xmlNodeName != "simulation")
reportFatal("SimulationManager", "simulation node expected");
parseSimulationBatch(simulation);
cout << "\t-> simulation batches loaded successfully!\n" << endl;
for (auto batch : simulationBatches)
{
batch.print();
}
}
void SimulationManager::runSimulations()
{
for (auto& batch : simulationBatches)
{
boost::filesystem::path dir(exportPath);
boost::filesystem::create_directories(dir);
for (auto& dramSetup : batch.dramSetups)
{
for (auto& traceSetup : batch.traceSetups)
{
string exportname = exportPath + "/" + traceSetup.first;
instantiateModules(exportname, dramSetup, traceSetup.second);
bindSockets();
runSimulation(exportname);
}
}
}
}
void SimulationManager::parseSimulationBatch(XMLElement* simulation)
{
SimulationBatch batch;
XMLElement* simconfig = simulation->FirstChildElement("simconfig");
XMLElement *thermalsimconfig = simulation->FirstChildElement("thermalsimconfig");
XMLElement* memspecs = simulation->FirstChildElement("memspecs");
if(memspecs == NULL) memspecs = simulation;
XMLElement* addressmappings = simulation->FirstChildElement("addressmappings");
if(addressmappings == NULL) addressmappings = simulation;
XMLElement* mcconfigs = simulation->FirstChildElement("mcconfigs");
if(mcconfigs == NULL) mcconfigs = simulation;
for (XMLElement* memspec = memspecs->FirstChildElement("memspec"); memspec != NULL;
memspec = memspec->NextSiblingElement("memspec"))
{
for (XMLElement* addressmapping = addressmappings->FirstChildElement("addressmapping"); addressmapping != NULL;
addressmapping = addressmapping->NextSiblingElement("addressmapping"))
{
for (XMLElement* mcconfig = mcconfigs->FirstChildElement("mcconfig");
mcconfig != NULL; mcconfig = mcconfig->NextSiblingElement("mcconfig"))
{
batch.dramSetups.push_back(DramSetup(memspec, mcconfig, simconfig, addressmapping, thermalsimconfig));
}
}
}
addTraceSetups(batch, simulation);
simulationBatches.push_back(batch);
}
void SimulationManager::instantiateModules(string traceName, DramSetup dramSetup, vector<Device> traceSetup)
{
simulation = new Simulation("sim", resources, traceName, dramSetup, traceSetup);
#if USE_EXAMPLE_INITIATOR
init = new ExampleInitiator("init");
if(Configuration::getInstance().CheckTLM2Protocol) {
string str = "ExampleInitiatorTLMChecker";
exampleInitiatorTlmChecker = new tlm_utils::tlm2_base_protocol_checker<>(str.c_str());
}
#else
for (size_t i = 0; i < Configuration::getInstance().NumberOfTracePlayers; i++) {
std::string playerStr = "tracePlayer" + std::to_string(i);
TracePlayer *player;
sc_time playerClk;
// The clock frequency for the player can be specified in the
// configuration file like in the example below (200 MHz):
//
// <tracesetups>
// <tracesetup id="fifo">
// <device clkMhz="200">chstone-adpcm_32.stl</device>
// </tracesetup>
// </tracesetups>
//
// If it is not specified in the configuration, the player will be
// configured to use the memory clock frequency got from the memory
// specs.
if (traceSetup[i].clkMhz == 0)
playerClk = Configuration::getInstance().memSpec.clk;
else
playerClk = FrequencyToClk(traceSetup[i].clkMhz);
const string pathToResources = resources;
player = new StlPlayer(playerStr.c_str(), pathToResources + string("traces/") + traceSetup[i].trace, playerClk, this);
if(Configuration::getInstance().SimulationProgressBar)
{
totalTransactions += player->getNumberOfLines(pathToResources + string("traces/") + traceSetup[i].trace);
}
players.push_back(player);
if(Configuration::getInstance().CheckTLM2Protocol) {
string str = "TLMCheckerPlayer"+ std::to_string(i);
tlm_utils::tlm2_base_protocol_checker<> * playerTlmChecker = new tlm_utils::tlm2_base_protocol_checker<>(str.c_str());
playersTlmCheckers.push_back(playerTlmChecker);
}
}
remainingTransactions = totalTransactions;
#endif /* USE_EXAMPLE_INITIATOR */
}
void SimulationManager::bindSockets()
{
#if USE_EXAMPLE_INITIATOR
if(Configuration::getInstance().CheckTLM2Protocol) {
init->socket.bind(exampleInitiatorTlmChecker->target_socket);
exampleInitiatorTlmChecker->initiator_socket.bind(simulation->tSocket);
}
else {
init->socket.bind(simulation->tSocket);
#else
if(Configuration::getInstance().CheckTLM2Protocol) {
for (size_t i = 0; i < players.size(); i++) {
players[i]->iSocket.bind(playersTlmCheckers[i]->target_socket);
playersTlmCheckers[i]->initiator_socket.bind(simulation->tSocket);
}
}
else {
for (auto player : players) {
player->iSocket.bind(simulation->tSocket);
}
#endif
}
}
void SimulationManager::runSimulation(string traceName)
{
report("\n\nStarting simulation:");
report(headline);
report(" -> setup: \t\t" + getFileName(traceName));
report(" -> memspec: \t\t" + Configuration::getInstance().memSpec.MemoryId);
cout << endl;
simStartTime = clock();
for (auto player : players) {
player->nextPayload();
}
sc_set_stop_mode(SC_STOP_FINISH_DELTA);
sc_start();
double elapsed_secs = double(clock() - simStartTime) / CLOCKS_PER_SEC;
report("\nSimulation took " + to_string(elapsed_secs) + " seconds\n");
delete simulation;
}
void SimulationManager::startTraceAnalyzer()
{
string p = getenv("trace");
string run_tpr = p + " -f ";
run_tpr += "&";
system(run_tpr.c_str());
}
void SimulationManager::addTraceSetups(SimulationBatch &batch, tinyxml2::XMLElement *simulation)
{
vector<Device> devices;
XMLElement *tracesetups = simulation->FirstChildElement("tracesetups");
XMLElement *simconfig = simulation->FirstChildElement("simconfig");
unsigned int numberOfTracePlayers = 1;
XMLElement *ntp = simconfig->FirstChildElement("NumberOfTracePlayers");
if (ntp != NULL)
ntp->QueryUnsignedAttribute("value", &numberOfTracePlayers);
for (XMLElement *tracesetup = tracesetups->FirstChildElement("tracesetup"); tracesetup != NULL; tracesetup = tracesetup->NextSiblingElement("tracesetup")) {
for (XMLElement *device = tracesetup->FirstChildElement("device"); device != NULL; device = device->NextSiblingElement("device")) {
devices.push_back(Device(device->GetText(), device->IntAttribute("clkMhz"), device->IntAttribute("bl")));
}
// This step is done here to add a default device in case the user haven't specified a trace file to be executed by one or more trace players.
while (devices.size() < numberOfTracePlayers) {
devices.push_back(Device());
}
batch.traceSetups.emplace(tracesetup->Attribute("id"), devices);
devices.clear();
}
}
void inline SimulationManager::tracePlayerTerminates()
{
static unsigned int finishedTracePlayers = 0;
finishedTracePlayers++;
if (finishedTracePlayers == Configuration::getInstance().NumberOfTracePlayers)
simulation->terminateSimulation.notify();
}
void inline SimulationManager::transactionFinished()
{
remainingTransactions--;
loadbar(totalTransactions - remainingTransactions, totalTransactions);
if (remainingTransactions == 0)
{
cout << endl;
}
}
void SimulationManager::report(string message)
{
cout << message << endl;
}
void SimulationBatch::print()
{
for (auto& s : traceSetups)
{
cout << "trace-setup " + s.first + ":\n";
for (Device d : s.second)
cout << "\t(" << d.burstLength << ") " << d.trace << ";" << endl;
cout << endl;
}
}

16
DRAMSys/simulator/src/simulation/StlPlayer.cpp
View File

@@ -39,7 +39,12 @@
#include "StlPlayer.h"
StlPlayer::StlPlayer(sc_module_name, string pathToTrace, sc_time playerClk, TracePlayerListener *listener) : TracePlayer(listener), file(pathToTrace)
StlPlayer::StlPlayer(sc_module_name,
string pathToTrace,
sc_time playerClk,
TracePlayerListener *listener) :
TracePlayer(listener),
file(pathToTrace)
{
if (!file.is_open())
SC_REPORT_FATAL(0, (string("Could not open trace ") + pathToTrace).c_str());
@@ -62,11 +67,16 @@ void StlPlayer::nextPayload()
line.clear();
}
if (!file) {
if (!file)
{
// The file is empty. Nothing more to do.
this->terminate();
this->finish();
return;
}
else
{
numberOfTransactions++;
}
// Allocate a generic payload for this request.
gp *payload = this->allocatePayload();

5
DRAMSys/simulator/src/simulation/StlPlayer.h
View File

@@ -49,7 +49,10 @@ using namespace tlm;
struct StlPlayer: public TracePlayer
{
public:
StlPlayer(sc_module_name /*name*/, string pathToTrace, sc_time playerClk, TracePlayerListener *listener);
StlPlayer(sc_module_name /*name*/,
string pathToTrace,
sc_time playerClk,
TracePlayerListener *listener);
void nextPayload();

32
DRAMSys/simulator/src/simulation/TraceGenerator.h
View File

@@ -60,25 +60,25 @@ public:
virtual void nextPayload() override
{
if(transCounter >= 1000) // TODO set limit!
{
this->terminate();
}
if(transCounter >= 1000) // TODO set limit!
{
this->terminate();
}
gp* payload = this->allocatePayload();
gp* payload = this->allocatePayload();
unsigned char * dataElement = new unsigned char[16]; // TODO: column / burst breite
unsigned char * dataElement = new unsigned char[16]; // TODO: column / burst breite
payload->set_address(0x0);
payload->set_response_status(TLM_INCOMPLETE_RESPONSE);
payload->set_dmi_allowed(false);
payload->set_byte_enable_length(0);
payload->set_streaming_width(this->burstlenght);
payload->set_data_ptr(dataElement);
payload->set_data_length(16);
payload->set_command(TLM_READ_COMMAND);
transCounter++;
this->payloadEventQueue.notify(*payload, BEGIN_REQ, SC_ZERO_TIME);
payload->set_address(0x0);
payload->set_response_status(TLM_INCOMPLETE_RESPONSE);
payload->set_dmi_allowed(false);
payload->set_byte_enable_length(0);
payload->set_streaming_width(this->burstlenght);
payload->set_data_ptr(dataElement);
payload->set_data_length(16);
payload->set_command(TLM_READ_COMMAND);
transCounter++;
this->payloadEventQueue.notify(*payload, BEGIN_REQ, SC_ZERO_TIME);
}
private:

25
DRAMSys/simulator/src/simulation/TracePlayer.cpp
View File

@@ -39,7 +39,12 @@
#include "TracePlayer.h"
TracePlayer::TracePlayer(TracePlayerListener* listener) :
payloadEventQueue(this, &TracePlayer::peqCallback), transactionsSent(0), listener(listener)
payloadEventQueue(this, &TracePlayer::peqCallback),
transactionsSent(0),
transactionsReceived(0),
listener(listener),
numberOfTransactions(0),
finished(false)
{
iSocket.register_nb_transport_bw(this, &TracePlayer::nb_transport_bw);
}
@@ -49,6 +54,11 @@ gp *TracePlayer::allocatePayload()
return memoryManager.allocate();
}
void TracePlayer::finish()
{
finished = true;
}
void TracePlayer::terminate()
{
cout << sc_time_stamp() << " " << this->name() << " terminated " << std::endl;
@@ -87,6 +97,14 @@ void TracePlayer::peqCallback(tlm_generic_payload &payload, const tlm_phase &pha
payload.release();
if(Configuration::getInstance().SimulationProgressBar)
listener->transactionFinished();
transactionsReceived++;
// If all answers were received:
if(finished == true && numberOfTransactions == transactionsReceived)
{
this->terminate();
}
}
else if (phase == END_RESP)
{
@@ -97,6 +115,11 @@ void TracePlayer::peqCallback(tlm_generic_payload &payload, const tlm_phase &pha
}
}
void TracePlayer::setNumberOfTransactions(unsigned int n)
{
numberOfTransactions = n;
}
unsigned int TracePlayer::getNumberOfLines(string pathToTrace)
{
ifstream newFile;

5
DRAMSys/simulator/src/simulation/TracePlayer.h
View File

@@ -67,8 +67,11 @@ public:
protected:
gp* allocatePayload();
tlm_utils::peq_with_cb_and_phase<TracePlayer> payloadEventQueue;
void finish();
void terminate();
void printDebugMessage(std::string message);
void setNumberOfTransactions(unsigned int n);
unsigned int numberOfTransactions;
private:
tlm_sync_enum nb_transport_bw(tlm_generic_payload& payload, tlm_phase& phase, sc_time& bwDelay);
@@ -81,7 +84,9 @@ private:
}
MemoryManager memoryManager;
unsigned int transactionsSent;
unsigned int transactionsReceived;
TracePlayerListener* listener;
bool finished;
};
#endif /* TRACEPLAYER_H_ */

122
DRAMSys/simulator/src/simulation/TraceSetup.cpp Normal file
View File

@@ -0,0 +1,122 @@
/*
* Copyright (c) 2017, University of Kaiserslautern
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
* OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors:
* Matthias Jung
*/
#include "TraceSetup.h"
traceSetup::traceSetup(std::string uri,
std::string pathToResources,
std::vector<StlPlayer *> * devices)
{
// Load Simulation:
tinyxml2::XMLDocument simulationdoc;
loadXML(uri, simulationdoc);
tinyxml2::XMLElement* simulation =
simulationdoc.FirstChildElement("simulation");
std::string xmlNodeName(simulation->Name());
if( xmlNodeName != "simulation")
reportFatal("traceSetup",
"Cannot load simulation: simulation node expected");
// Load TracePlayers:
tinyxml2::XMLElement *tracesetup =
simulation->FirstChildElement("tracesetup");
for (tinyxml2::XMLElement *device =
tracesetup->FirstChildElement("device");
device != NULL;
device = device->NextSiblingElement("device"))
{
sc_time playerClk;
unsigned int frequency = device->IntAttribute("clkMhz");
if (frequency == 0)
{
reportFatal("traceSetup","No Frequency Defined");
}
else
{
playerClk = FrequencyToClk(frequency);
}
std::string name = device->GetText();
std::string stlFile = pathToResources + string("traces/") + name;
std::string moduleName = name;
// replace all '.' to '_'
std::replace( moduleName.begin(), moduleName.end(), '.', '_');
StlPlayer * player = new StlPlayer(moduleName.c_str(),
stlFile,
playerClk,
this);
devices->push_back(player);
if(Configuration::getInstance().SimulationProgressBar)
{
totalTransactions += player->getNumberOfLines(stlFile);
}
}
remainingTransactions = totalTransactions;
NumberOfTracePlayers = devices->size();
cout << "NumberOfTracePlayers: " << NumberOfTracePlayers << endl;
cout << "totalTransactions: " << totalTransactions << endl;
}
void traceSetup::tracePlayerTerminates()
{
finishedTracePlayers++;
if (finishedTracePlayers == NumberOfTracePlayers)
{
//simulation->terminateSimulation.notify();
sc_stop();
}
}
void traceSetup::transactionFinished()
{
remainingTransactions--;
loadbar(totalTransactions - remainingTransactions, totalTransactions);
if (remainingTransactions == 0)
{
cout << endl;
}
}

69
DRAMSys/simulator/src/simulation/SimulationManager.h → DRAMSys/simulator/src/simulation/TraceSetup.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2015, University of Kaiserslautern
* Copyright (c) 2017, University of Kaiserslautern
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -30,80 +30,35 @@
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors:
* Janik Schlemminger
* Matthias Jung
* Eder F. Zulian
*/
#ifndef SIMULATIONMANAGER_H_
#define SIMULATIONMANAGER_H_
#ifndef TRACESETUP_H
#define TRACESETUP_H
#include <vector>
#include <string>
#include <map>
#include "Simulation.h"
#include "../common/Utils.h"
#include "TracePlayer.h"
#include "StlPlayer.h"
#include "../controller/core/configuration/ConfigurationLoader.h"
#include "../common/third_party/tinyxml2/tinyxml2.h"
#include "ExampleInitiator.h"
#include "../common/tlm2_base_protocol_checker.h"
#define USE_EXAMPLE_INITIATOR 0
struct SimulationBatch
{
std::vector<DramSetup> dramSetups;
std::map<std::string, std::vector<Device>> traceSetups;
void print();
};
class SimulationManager: public TracePlayerListener
class traceSetup : public TracePlayerListener
{
public:
SimulationManager(std::string resources);
~SimulationManager();
void loadSimulationsFromXML(std::string uri);
void runSimulations();
void startTraceAnalyzer();
traceSetup(std::string uri,
std::string pathToResources,
std::vector<StlPlayer*> * devices);
virtual void tracePlayerTerminates() override;
virtual void transactionFinished() override;
private:
std::string resources;
std::string exportPath;
std::string basePath;
tinyxml2::XMLDocument simulationdoc;
std::vector<SimulationBatch> simulationBatches;
// A vector of pointers to all trace player (devices which acquire the bus
// and initiate transactions targeting the memory)
std::vector<TracePlayer*> players;
Simulation* simulation;
clock_t simStartTime;
//TLM 2.0 Protocol Checkers
std::vector<tlm_utils::tlm2_base_protocol_checker<>*> playersTlmCheckers;
unsigned int NumberOfTracePlayers;
unsigned int totalTransactions = 0;
unsigned int remainingTransactions;
#if USE_EXAMPLE_INITIATOR
ExampleInitiator *init;
tlm_utils::tlm2_base_protocol_checker<>* exampleInitiatorTlmChecker;
#endif
void instantiateModules(std::string traceName, DramSetup dramSetup, std::vector<Device> traceSetup);
void bindSockets();
void runSimulation(string traceName);
void parseSimulationBatch(tinyxml2::XMLElement* simulation);
void addTraceSetups(SimulationBatch &batch, tinyxml2::XMLElement *element);
void report(std::string message);
unsigned int finishedTracePlayers = 0;
};
#endif /* SIMULATIONMANAGER_H_ */
#endif // TRACESETUP_H

54
DRAMSys/simulator/src/simulation/main.cpp
View File

@@ -40,12 +40,10 @@
#include <utility>
#include <vector>
//XXX
//#include "SimulationManager.h"
#include "dramSys.h"
#include "DRAMSys.h"
#include "TraceSetup.h"
#include "ExampleInitiator.h"
using namespace std;
string resources;
@@ -60,8 +58,6 @@ int main(int argc, char **argv)
return sc_main(argc, argv);
}
int sc_main(int argc, char **argv)
{
sc_set_time_resolution(1, SC_PS);
@@ -70,31 +66,45 @@ int sc_main(int argc, char **argv)
resources = pathOfFile(argv[0])
+ string("/../../DRAMSys/simulator/resources/");
string simulationToRun;
string SimulationXML;
if(argc > 1)
simulationToRun = argv[1];
{
SimulationXML = argv[1];
}
else
simulationToRun = resources + "simulations/sim-batch.xml";
{
SimulationXML = resources + "simulations/ddr3-example.xml";
}
std::vector<StlPlayer*> players;
DRAMSys dramSystem("dramSystem",
"../../DRAMSys/simulator/resources/",
"wideio.xml",
"fifoStrict.xml",
"am_wideio.xml",
"wideio.xml",
"config.xml");
// Instantiate DRAMSys:
DRAMSys dramSys("DRAMSys", SimulationXML, resources);
ExampleInitiator trageGenerator("traceGenerator");
// Instantiate STL Players:
traceSetup setup = traceSetup(SimulationXML, resources, &players);
trageGenerator.socket.bind(dramSystem.tSocket);
// Bind STL Players with DRAMSys:
for(auto& p : players)
{
p->iSocket.bind(dramSys.tSocket);
}
SC_REPORT_INFO("sc_main", "Start of Simulation");
// Store the starting of the simulation in wallclock time:
clock_t simStartTime = clock();
sc_core::sc_start();
// Kickstart the players:
for (auto& p : players)
{
p->nextPayload();
}
SC_REPORT_INFO("sc_main", "End of Simulation");
// Start SystemC Simulation:
sc_set_stop_mode(SC_STOP_FINISH_DELTA);
sc_start();
double elapsed_secs = double(clock() - simStartTime) / CLOCKS_PER_SEC;
cout << "Simulation took " + to_string(elapsed_secs) + " seconds" << endl;
return 0;
}