derek/DRAMSys
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Deserialize std::variant without throwing exception

Browse Source
This commit is contained in:
marcomoerz
2024-07-04 10:54:04 +02:00
committed by Derek Christ
parent 4120e9c35b
commit bc8274433a
21 changed files with 71 additions and 23 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
configs/ddr3-example.json
View File

@@ -7,6 +7,7 @@
"simulationid": "ddr3-example",
"tracesetup": [
{
"type": "player",
"clkMhz": 800,
"name": "traces/example.stl"
}

1
configs/ddr4-example.json
View File

@@ -7,6 +7,7 @@
"simulationid": "ddr4-example",
"tracesetup": [
{
"type": "player",
"clkMhz": 200,
"name": "traces/example.stl"
}

1
configs/ddr4-full-example.json
View File

@@ -210,6 +210,7 @@
"simulationid": "ddr4-example",
"tracesetup": [
{
"type": "player",
"clkMhz": 200,
"name": "traces/example.stl"
}

1
configs/ddr5-example.json
View File

@@ -7,6 +7,7 @@
"simulationid": "ddr5-example",
"tracesetup": [
{
"type": "player",
"clkMhz": 2000,
"name": "traces/example.stl"
}

1
configs/hbm2-example.json
View File

@@ -7,6 +7,7 @@
"simulationid": "hbm2-example",
"tracesetup": [
{
"type": "player",
"clkMhz": 1000,
"name": "traces/example.stl"
}

1
configs/lpddr4-example.json
View File

@@ -7,6 +7,7 @@
"simulationid": "lpddr4-example",
"tracesetup": [
{
"type": "player",
"clkMhz": 200,
"name": "traces/example.stl"
}

1
configs/lpddr5-example.json
View File

@@ -7,6 +7,7 @@
"simulationid": "lpddr5-example",
"tracesetup": [
{
"type": "player",
"clkMhz": 200,
"name": "traces/example.stl"
}

3
src/configuration/DRAMSys/config/AddressMapping.h
View File

@@ -37,6 +37,7 @@
#define DRAMSYSCONFIGURATION_ADDRESSMAPPING_H
#include <DRAMUtils/util/json_utils.h>
#include <DRAMUtils/util/collapsingvector.h>
#include <optional>
@@ -47,7 +48,7 @@ struct AddressMapping
{
static constexpr std::string_view KEY = "addressmapping";
using BitEntry = std::variant<unsigned int, std::vector<unsigned int>>;
using BitEntry = DRAMUtils::util::CollapsingVector<unsigned int>;
std::optional<std::vector<BitEntry>> BYTE_BIT;
std::optional<std::vector<BitEntry>> COLUMN_BIT;

21
src/configuration/DRAMSys/config/TraceSetup.h
View File

@@ -37,7 +37,10 @@
#define DRAMSYSCONFIGURATION_TRACESETUP_H
#include <DRAMUtils/util/json_utils.h>
#include <DRAMUtils/util/id_variant.h>
#include <DRAMUtils/util/types.h>
#include <string_view>
#include <optional>
#include <variant>
@@ -72,6 +75,8 @@ NLOHMANN_JSON_SERIALIZE_ENUM(AddressDistribution,
struct TracePlayer
{
static constexpr inline const std::string_view id = "player";
uint64_t clkMhz{};
std::string name;
std::optional<unsigned int> maxPendingReadRequests;
@@ -122,6 +127,8 @@ NLOHMANN_JSONIFY_ALL_THINGS(TrafficGeneratorStateTransition, from, to, probabili
struct TrafficGenerator
{
static constexpr inline const std::string_view id = "generator";
uint64_t clkMhz{};
std::string name;
std::optional<unsigned int> maxPendingReadRequests;
@@ -158,6 +165,8 @@ NLOHMANN_JSONIFY_ALL_THINGS(TrafficGenerator,
struct TrafficGeneratorStateMachine
{
static constexpr inline const std::string_view id = "statemachine";
uint64_t clkMhz{};
std::string name;
std::optional<unsigned int> maxPendingReadRequests;
@@ -185,6 +194,8 @@ NLOHMANN_JSONIFY_ALL_THINGS(TrafficGeneratorStateMachine,
struct RowHammer
{
static constexpr inline const std::string_view id = "rowhammer";
uint64_t clkMhz{};
std::string name;
std::optional<unsigned int> maxPendingReadRequests;
@@ -207,8 +218,14 @@ struct TraceSetupConstants
static constexpr std::string_view KEY = "tracesetup";
};
using Initiator =
std::variant<TracePlayer, TrafficGenerator, TrafficGeneratorStateMachine, RowHammer>;
using InitiatorTypes = DRAMUtils::util::type_sequence<
TracePlayer,
TrafficGenerator,
TrafficGeneratorStateMachine,
RowHammer
>;
DRAMUTILS_DECLARE_IDVARIANT(Initiator, "type", InitiatorTypes)
} // namespace DRAMSys::Config

22
src/libdramsys/DRAMSys/simulation/AddressDecoder.cpp
View File

@@ -37,6 +37,7 @@
*/
#include "AddressDecoder.h"
#include "DRAMSys/config/AddressMapping.h"
#include <bitset>
#include <cmath>
@@ -50,23 +51,14 @@ static void addMapping(std::vector<Config::AddressMapping::BitEntry> const& mapp
std::vector<unsigned>& bitVector,
std::vector<std::vector<unsigned>>& xorVector)
{
for (const auto& bitEntry : mappingVector)
for (const Config::AddressMapping::BitEntry& bitEntry : mappingVector)
{
std::visit(
[&bitVector, &xorVector](auto&& arg)
{
using T = std::decay_t<decltype(arg)>;
if constexpr (std::is_same_v<T, unsigned>)
{
bitVector.push_back(arg);
if (bitEntry.get_type() == Config::AddressMapping::BitEntry::Type::SINGLE) {
bitVector.push_back(bitEntry.at(0));
} else {
bitVector.push_back(bitEntry.at(0));
xorVector.push_back(bitEntry);
}
else if constexpr (std::is_same_v<T, std::vector<unsigned>>)
{
bitVector.push_back(arg.at(0));
xorVector.push_back(arg);
}
},
bitEntry);
}
}

2
src/simulator/simulator/Simulator.cpp
View File

@@ -148,7 +148,7 @@ Simulator::instantiateInitiator(const DRAMSys::Config::Initiator& initiator)
std::move(hammer));
}
},
initiator);
initiator.getVariant());
}
void Simulator::run()

4
tests/tests_configuration/reference.json
View File

@@ -213,10 +213,12 @@
"simulationid": "std::string_simulationId",
"tracesetup": [
{
"type": "player",
"clkMhz": 100,
"name": "mytrace.stl"
},
{
"type": "generator",
"addressDistribution": "random",
"clkMhz": 100,
"name": "MyTestGen",
@@ -224,6 +226,7 @@
"rwRatio": 0.5
},
{
"type": "statemachine",
"clkMhz": 100,
"maxPendingReadRequests": 8,
"name": "MyTestGen",
@@ -255,6 +258,7 @@
]
},
{
"type": "rowhammer",
"clkMhz": 100,
"name": "MyTestHammer",
"numRequests": 4000,

3
tests/tests_configuration/resources/tracesetup/ddr5-trace.json
View File

@@ -1,10 +1,12 @@
{
"tracesetup": [
{
"type": "player",
"clkMhz": 2000,
"name": "ddr3_example.stl"
},
{
"type": "generator",
"clkMhz": 2000,
"name": "gen0",
"numRequests": 2000,
@@ -15,6 +17,7 @@
"maxPendingWriteRequests": 8
},
{
"type": "generator",
"clkMhz": 2000,
"name": "gen1",
"numRequests": 2000,

17
tests/tests_configuration/test_configuration.cpp
View File

@@ -68,7 +68,18 @@ protected:
static DRAMSys::Config::RowHammer createTraceHammer();
static std::vector<DRAMSys::Config::AddressMapping::BitEntry>
addressMapBitVector(std::vector<unsigned> bits)
addressMapBitVector(std::initializer_list<std::vector<unsigned int>> bits)
{
auto result = std::vector<DRAMSys::Config::AddressMapping::BitEntry>();
for (const auto& bit : bits)
{
result.push_back(DRAMSys::Config::AddressMapping::BitEntry({bit.begin(), bit.end()}));
}
return result;
};
static std::vector<DRAMSys::Config::AddressMapping::BitEntry>
addressMapBitVector(std::vector<unsigned int> bits)
{
return {bits.begin(), bits.end()};
};
@@ -707,10 +718,12 @@ TEST_F(ConfigurationTest, TraceSetup)
{
"tracesetup": [
{
"type": "player",
"clkMhz": 100,
"name": "mytrace.stl"
},
{
"type": "generator",
"addressDistribution": "random",
"clkMhz": 100,
"name": "MyTestGen",
@@ -718,6 +731,7 @@ TEST_F(ConfigurationTest, TraceSetup)
"rwRatio": 0.5
},
{
"type": "statemachine",
"clkMhz": 100,
"maxPendingReadRequests": 8,
"name": "MyTestGen",
@@ -749,6 +763,7 @@ TEST_F(ConfigurationTest, TraceSetup)
]
},
{
"type": "rowhammer",
"clkMhz": 100,
"name": "MyTestHammer",
"numRequests": 4000,

1
tests/tests_regression/DDR3/ddr3-example.json
View File

@@ -135,6 +135,7 @@
"simulationid": "ddr3-dual-rank",
"tracesetup": [
{
"type": "player",
"clkMhz": 533,
"name": "traces/trace_test2.stl"
}

1
tests/tests_regression/DDR4/ddr4-example.json
View File

@@ -211,6 +211,7 @@
"simulationid": "ddr4-bankgrp",
"tracesetup": [
{
"type": "player",
"clkMhz": 933,
"name": "traces/trace_test3.stl"
}

1
tests/tests_regression/DDR5/ddr5-example.json
View File

@@ -218,6 +218,7 @@
"simulationid": "ddr5-example",
"tracesetup": [
{
"type": "player",
"clkMhz": 1600,
"name": "traces/trace_test3.stl"
}

2
tests/tests_regression/HBM2/hbm2-example.json
View File

@@ -126,10 +126,12 @@
"simulationid": "hbm2-example",
"tracesetup": [
{
"type": "player",
"clkMhz": 1000,
"name": "traces/trace1_test4.stl"
},
{
"type": "player",
"clkMhz": 1000,
"name": "traces/trace2_test4.stl"
}

2
tests/tests_regression/HBM3/hbm3-example.json
View File

@@ -129,10 +129,12 @@
"simulationid": "hbm3-example",
"tracesetup": [
{
"type": "player",
"clkMhz": 1600,
"name": "traces/trace1_test4.stl"
},
{
"type": "player",
"clkMhz": 1600,
"name": "traces/trace2_test4.stl"
}

1
tests/tests_regression/LPDDR4/lpddr4-example.json
View File

@@ -181,6 +181,7 @@
"simulationid": "lpddr4-example",
"tracesetup": [
{
"type": "player",
"clkMhz": 1600,
"name": "traces/trace_lpddr4.stl"
}

1
tests/tests_regression/LPDDR5/lpddr5-example.json
View File

@@ -203,6 +203,7 @@
"simulationid": "lpddr5-example",
"tracesetup": [
{
"type": "player",
"clkMhz": 1600,
"name": "traces/trace_lpddr5.stl"
}