191 lines
5.2 KiB
JSON
191 lines
5.2 KiB
JSON
{
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"simulation": {
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"addressmapping": {
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"BANK_BIT": [
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27,
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28,
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29
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],
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"BYTE_BIT": [
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0
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],
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"COLUMN_BIT": [
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1,
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2,
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3,
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4,
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5,
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6,
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7,
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8,
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9,
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10
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],
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"ROW_BIT": [
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11,
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12,
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13,
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14,
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15,
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16,
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17,
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18,
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19,
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20,
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21,
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22,
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23,
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24,
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25,
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26
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]
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},
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"mcconfig": {
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"PagePolicy": "OpenAdaptive",
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"Scheduler": "Fifo",
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"RequestBufferSize": 8,
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"CmdMux": "Oldest",
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"RespQueue": "Fifo",
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"RefreshPolicy": "Bankwise",
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"RefreshMaxPostponed": 8,
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"RefreshMaxPulledin": 8,
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"PowerDownPolicy": "NoPowerDown",
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"PowerDownTimeout": 100
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},
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"memspec": {
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"memarchitecturespec": {
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"nbrOfBankGroups": 1,
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"burstLength": 16,
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"dataRate": 2,
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"nbrOfBanks": 8,
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"nbrOfColumns": 1024,
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"nbrOfRanks": 1,
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"nbrOfChannels": 1,
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"nbrOfDevices": 1,
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"nbrOfRows": 65536,
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"width": 16,
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"maxBurstLength": 16
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},
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"memoryId": "JEDEC_8Gb_LPDDR4-3200_16bit",
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"memoryType": "LPDDR4",
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"memtimingspec": {
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"CCD": 8,
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"CCDMW": 32,
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"CKE": 12,
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"CMDCKE": 3,
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"DQS2DQ": 2,
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"DQSCK": 6,
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"DQSS": 1,
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"ESCKE": 3,
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"FAW": 64,
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"PPD": 4,
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"RAS": 68,
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"RCD": 29,
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"REFI": 6246,
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"REFIpb": 780,
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"RFCab": 448,
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"RFCpb": 224,
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"RL": 28,
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"RPab": 34,
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"RPpb": 29,
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"RCab": 102,
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"RCpb": 97,
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"RPST": 0,
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"RRD": 16,
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"RTP": 12,
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"SR": 24,
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"WL": 14,
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"WPRE": 2,
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"WR": 29,
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"WTR": 16,
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"XP": 12,
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"XSR": 460,
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"RTRS": 1,
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"REFM": 0,
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"tCK": 625e-12
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},
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"mempowerspec": {
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"vdd1": 0.0,
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"idd01": 0.0,
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"idd2n1": 0.0,
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"idd3n1": 0.0,
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"idd4r1": 0.0,
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"idd4w1": 0.0,
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"idd51": 0.0,
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"idd5pb1": 0.0,
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"idd61": 0.0,
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"idd2p1": 0.0,
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"idd3p1": 0.0,
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"vdd2": 0.0,
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"idd02": 0.0,
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"idd2n2": 0.0,
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"idd3n2": 0.0,
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"idd4r2": 0.0,
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"idd4w2": 0.0,
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"idd52": 0.0,
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"idd5pb2": 0.0,
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"idd62": 0.0,
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"idd2p2": 0.0,
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"idd3p2": 0.0,
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"vddq": 0.0,
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"iBeta_vdd1": 0.0,
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"iBeta_vdd2": 0.0
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},
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"memimpedancespec": {
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"ck_termination": true,
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"ck_R_eq": 1e6,
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"ck_dyn_E": 1e-12,
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"ca_termination": true,
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"ca_R_eq": 1e6,
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"ca_dyn_E": 1e-12,
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"rdq_termination": true,
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"rdq_R_eq": 1e6,
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"rdq_dyn_E": 1e-12,
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"wdq_termination": true,
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"wdq_R_eq": 1e6,
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"wdq_dyn_E": 1e-12,
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"wdqs_termination": true,
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"wdqs_R_eq": 1e6,
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"wdqs_dyn_E": 1e-12,
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"rdqs_termination": true,
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"rdqs_R_eq": 1e6,
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"rdqs_dyn_E": 1e-12
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},
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"bankwisespec": {
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"factRho": 1.0,
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"factSigma": 1.0,
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"pasrMode": 0,
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"hasPASR": false
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}
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},
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"simconfig": {
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"AddressOffset": 0,
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"CheckTLM2Protocol": false,
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"DatabaseRecording": true,
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"Debug": false,
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"ECCControllerMode": "Disabled",
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"EnableWindowing": false,
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"ErrorCSVFile": "",
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"ErrorChipSeed": 42,
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"PowerAnalysis": false,
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"SimulationName": "lpddr4",
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"SimulationProgressBar": true,
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"StoreMode": "NoStorage",
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"ThermalSimulation": false,
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"UseMalloc": false,
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"WindowSize": 1000
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},
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"simulationid": "lpddr4-example",
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"tracesetup": [
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{
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"type": "player",
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"clkMhz": 1600,
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"name": "traces/trace_lpddr4.stl"
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}
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]
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}
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}
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