Added references to papers that describe some concepts for the first time

README.md

@@ -1,7 +1,7 @@
 de.uni-kl.ems.dram.vp.system
 ============================
 
-Generic DRAM controller simulator and related tools.
+Generic DRAM controller simulator **DRAMSys** [1] and related tools.
 
 ## Basic Setup
 
@@ -26,7 +26,7 @@ $ git clone --recursive https://<user>@git.rhrk.uni-kl.de/EIT-Wehn/dram.vp.syste
 ```
 
 The *--recursive* flag tells git to initialize all submodules within the
-repository. **DRAMPower** and **tinyxml** are examples third party
+repository. **DRAMPower** [2] and **tinyxml** are examples third party
 repositories that were embedded within the source tree as submodules.
 
 It is possible to work with a copy of the official codebase. The copy is
@@ -211,7 +211,7 @@ Below are listed the configuration sections and configuration fields.
   ```
 
   - *BankwiseLogic* (boolean)
-    - "1": perform bankwise operations such as bankwise-refresh and bankwise-powerdown
+    - "1": perform bankwise-refresh [3] and bankwise-powerdown [4]
     - "0": do not perform bankwise operations
   - *OpenPagePolicy* (boolean)
     - "1": use open page precharge policy
@@ -219,14 +219,14 @@ Below are listed the configuration sections and configuration fields.
   - *MaxNrOfTransactions* (unsigned int)
     - Maximum number of transactions.
   - *Scheduler* (string)
-    - Scheduler algorithm to be applied on memory transactions. Different
+    - "FIFO": first in, first out
-      schedulers can order transactions based on different factors such as
+    - "FIFO_STRICT": out-of-order treatment of queue elements not allowed
-      latency, power savings, etc.
+    - "FR_FCFS": first-come, first-served
   - *Capsize* (unsigned int)
     - Capacitor cell size.
   - *PowerDownMode* (enum EPowerDownMode)
     - "NoPowerDown": no power down mode (active idle)
-    - "Staggered": staggered power down policy
+    - "Staggered": staggered power down policy [5]
     - "TimeoutPDN": precharge idle
     - "TimeoutSREF": self refresh
   - *Buswidth* (unsigned int)
@@ -244,22 +244,21 @@ Below are listed the configuration sections and configuration fields.
   - *ErrorStoreMode* (enum ErrorStorageMode)
     - "NoStorage": no storage
     - "Store": store data without error model
-    - "ErrorModel": store data with error model
+    - "ErrorModel": store data with error model [6]
-
-[1]: http://google.com
-[2]: http://google.com
 
 - **Trace setups**
   - *id*
+    - trace setup id
   - *clkMhz*
+    - speed of the trace player
 
 Some attributes are self-explanatory while others require some previous
 knowhow of memory technologies or some knowledge of the simulator source code.
 
-Some resources of the simulator are available in the **resources** directory
+Resources of the simulator are available in the **resources** directory its
-its sub-directories.
+sub-directories.
 
-``` xml
+``` bash
 $ cd /projects/dram.vp.system/dram/resources
 ```
 
@@ -277,3 +276,27 @@ A description of the content each directory follows.
   - **traces**: trace files for simulations. They contain accesses to memory
     in certain known scenarios.
 
+#### References
+
+[1] TLM Modelling of 3D Stacked Wide I/O DRAM Subsystems, A Virtual Platform for Memory Controller Design Space Exploration
+M. Jung, C. Weis, N. Wehn, K. Chandrasekar. International Conference on High-Performance and Embedded Architectures and Compilers 2013 (HiPEAC), Workshop on: Rapid Simulation and Performance Evaluation: Methods and Tools (RAPIDO), January, 2013, Berlin.
+
+[2] DRAMPower: Open-source DRAM Power & Energy Estimation Tool
+Karthik Chandrasekar, Christian Weis, Yonghui Li, Sven Goossens, Matthias Jung, Omar Naji, Benny Akesson, Norbert Wehn, and Kees Goossens
+URL: http://www.drampower.info
+
+[3] Energy Optimization in 3D MPSoCs with Wide-I/O DRAM
+M. Sadri, M. Jung, C. Weis, N. Wehn, L. Benini. Conference Design, Automation and Test in Europe (DATE), March, 2014, Dresden, Germany.
+
+[4] DRAMSys: A flexible DRAM Subsystem Design Space Exploration Framework
+M. Jung, C. Weis, N. Wehn. Accepted for publication, IPSJ Transactions on System LSI Design Methodology (T-SLDM), October, 2015.
+
+[5] Optimized Active and Power-Down Mode Refresh Control in 3D-DRAMs
+M. Jung, M. Sadri, C. Weis, N. Wehn, L. Benini., VLSI-SoC, October, 2014, Playa del Carmen, Mexico.
+
+[6] Retention Time Measurements and Modelling of Bit Error Rates of WIDE-I/O DRAM in MPSoCs
+C. Weis, M. Jung, P. Ehses, C. Santos, P. Vivet, S. Goossens, M. Koedam, N. Wehn. Accepted for publication, IEEE Conference Design, Automation and Test in Europe (DATE), March, 2015, Grenoble, France
+
+[7] http://www.uni-kl.de/3d-dram/publications/
+
+