Use tCCDMW for masked write in LPDDR4

2023-08-21 09:26:05 +02:00
parent b3937cf63a
commit b30df49d67
21 changed files with 31 additions and 0 deletions
--- a/configs/memspec/JEDEC_1Gbx16_LPDDR4-0533.json
+++ b/configs/memspec/JEDEC_1Gbx16_LPDDR4-0533.json
@@ -15,6 +15,7 @@
        "memoryType": "LPDDR4",
        "memtimingspec": {
            "CCD": 8,
+            "CCDMW": 32,
            "CKE": 4,
            "CMDCKE": 3,
            "DQS2DQ": 0,
--- a/configs/memspec/JEDEC_1Gbx16_LPDDR4-1066.json
+++ b/configs/memspec/JEDEC_1Gbx16_LPDDR4-1066.json
@@ -15,6 +15,7 @@
        "memoryType": "LPDDR4",
        "memtimingspec": {
            "CCD": 8,
+            "CCDMW": 32,
            "CKE": 4,
            "CMDCKE": 3,
            "DQS2DQ": 0,
--- a/configs/memspec/JEDEC_1Gbx16_LPDDR4-1600.json
+++ b/configs/memspec/JEDEC_1Gbx16_LPDDR4-1600.json
@@ -15,6 +15,7 @@
        "memoryType": "LPDDR4",
        "memtimingspec": {
            "CCD": 8,
+            "CCDMW": 32,
            "CKE": 6,
            "CMDCKE": 3,
            "DQS2DQ": 0,
--- a/configs/memspec/JEDEC_1Gbx16_LPDDR4-2133.json
+++ b/configs/memspec/JEDEC_1Gbx16_LPDDR4-2133.json
@@ -15,6 +15,7 @@
        "memoryType": "LPDDR4",
        "memtimingspec": {
            "CCD": 8,
+            "CCDMW": 32,
            "CKE": 9,
            "CMDCKE": 3,
            "DQS2DQ": 0,
--- a/configs/memspec/JEDEC_1Gbx16_LPDDR4-2666.json
+++ b/configs/memspec/JEDEC_1Gbx16_LPDDR4-2666.json
@@ -15,6 +15,7 @@
        "memoryType": "LPDDR4",
        "memtimingspec": {
            "CCD": 8,
+            "CCDMW": 32,
            "CKE": 10,
            "CMDCKE": 3,
            "DQS2DQ": 0,
--- a/configs/memspec/JEDEC_1Gbx16_LPDDR4-3200.json
+++ b/configs/memspec/JEDEC_1Gbx16_LPDDR4-3200.json
@@ -15,6 +15,7 @@
        "memoryType": "LPDDR4",
        "memtimingspec": {
            "CCD": 8,
+            "CCDMW": 32,
            "CKE": 12,
            "CMDCKE": 3,
            "DQS2DQ": 0,
--- a/configs/memspec/JEDEC_1Gbx16_LPDDR4-3733.json
+++ b/configs/memspec/JEDEC_1Gbx16_LPDDR4-3733.json
@@ -15,6 +15,7 @@
        "memoryType": "LPDDR4",
        "memtimingspec": {
            "CCD": 8,
+            "CCDMW": 32,
            "CKE": 15,
            "CMDCKE": 4,
            "DQS2DQ": 0,
--- a/configs/memspec/JEDEC_1Gbx16_LPDDR4-4266.json
+++ b/configs/memspec/JEDEC_1Gbx16_LPDDR4-4266.json
@@ -15,6 +15,7 @@
        "memoryType": "LPDDR4",
        "memtimingspec": {
            "CCD": 8,
+            "CCDMW": 32,
            "CKE": 17,
            "CMDCKE": 4,
            "DQS2DQ": 0,
--- a/configs/memspec/JEDEC_512Mbx16_LPDDR4-0533.json
+++ b/configs/memspec/JEDEC_512Mbx16_LPDDR4-0533.json
@@ -15,6 +15,7 @@
        "memoryType": "LPDDR4",
        "memtimingspec": {
            "CCD": 8,
+            "CCDMW": 32,
            "CKE": 4,
            "CMDCKE": 3,
            "DQS2DQ": 0,
--- a/configs/memspec/JEDEC_512Mbx16_LPDDR4-1066.json
+++ b/configs/memspec/JEDEC_512Mbx16_LPDDR4-1066.json
@@ -15,6 +15,7 @@
        "memoryType": "LPDDR4",
        "memtimingspec": {
            "CCD": 8,
+            "CCDMW": 32,
            "CKE": 4,
            "CMDCKE": 3,
            "DQS2DQ": 0,
--- a/configs/memspec/JEDEC_512Mbx16_LPDDR4-1600.json
+++ b/configs/memspec/JEDEC_512Mbx16_LPDDR4-1600.json
@@ -15,6 +15,7 @@
        "memoryType": "LPDDR4",
        "memtimingspec": {
            "CCD": 8,
+            "CCDMW": 32,
            "CKE": 6,
            "CMDCKE": 3,
            "DQS2DQ": 0,
--- a/configs/memspec/JEDEC_512Mbx16_LPDDR4-2133.json
+++ b/configs/memspec/JEDEC_512Mbx16_LPDDR4-2133.json
@@ -15,6 +15,7 @@
        "memoryType": "LPDDR4",
        "memtimingspec": {
            "CCD": 8,
+            "CCDMW": 32,
            "CKE": 9,
            "CMDCKE": 3,
            "DQS2DQ": 0,
--- a/configs/memspec/JEDEC_512Mbx16_LPDDR4-2666.json
+++ b/configs/memspec/JEDEC_512Mbx16_LPDDR4-2666.json
@@ -15,6 +15,7 @@
        "memoryType": "LPDDR4",
        "memtimingspec": {
            "CCD": 8,
+            "CCDMW": 32,
            "CKE": 10,
            "CMDCKE": 3,
            "DQS2DQ": 0,
--- a/configs/memspec/JEDEC_512Mbx16_LPDDR4-3200.json
+++ b/configs/memspec/JEDEC_512Mbx16_LPDDR4-3200.json
@@ -15,6 +15,7 @@
        "memoryType": "LPDDR4",
        "memtimingspec": {
            "CCD": 8,
+            "CCDMW": 32,
            "CKE": 12,
            "CMDCKE": 3,
            "DQS2DQ": 0,
--- a/configs/memspec/JEDEC_512Mbx16_LPDDR4-3733.json
+++ b/configs/memspec/JEDEC_512Mbx16_LPDDR4-3733.json
@@ -15,6 +15,7 @@
        "memoryType": "LPDDR4",
        "memtimingspec": {
            "CCD": 8,
+            "CCDMW": 32,
            "CKE": 15,
            "CMDCKE": 4,
            "DQS2DQ": 0,
--- a/configs/memspec/JEDEC_512Mbx16_LPDDR4-4266.json
+++ b/configs/memspec/JEDEC_512Mbx16_LPDDR4-4266.json
@@ -15,6 +15,7 @@
        "memoryType": "LPDDR4",
        "memtimingspec": {
            "CCD": 8,
+            "CCDMW": 32,
            "CKE": 17,
            "CMDCKE": 4,
            "DQS2DQ": 0,
--- a/configs/memspec/JEDEC_8Gb_LPDDR4-3200_16bit.json
+++ b/configs/memspec/JEDEC_8Gb_LPDDR4-3200_16bit.json
@@ -65,6 +65,7 @@
        },
        "memtimingspec": {
            "CCD": 8,
+            "CCDMW": 32,
            "CKE": 12,
            "CMDCKE": 3,
            "DQS2DQ": 2,
--- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecLPDDR4.cpp
+++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecLPDDR4.cpp
@@ -72,6 +72,7 @@ MemSpecLPDDR4::MemSpecLPDDR4(const DRAMSys::Config::MemSpec &memSpec)
      tFAW    (tCK * memSpec.memtimingspec.entries.at("FAW")),
      tRRD    (tCK * memSpec.memtimingspec.entries.at("RRD")),
      tCCD    (tCK * memSpec.memtimingspec.entries.at("CCD")),
+      tCCDMW  (tCK * memSpec.memtimingspec.entries.at("CCDMW")),
      tRL     (tCK * memSpec.memtimingspec.entries.at("RL")),
      tRPST   (tCK * memSpec.memtimingspec.entries.at("RPST")),
      tDQSCK  (tCK * memSpec.memtimingspec.entries.at("DQSCK")),
--- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecLPDDR4.h
+++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecLPDDR4.h
@@ -65,6 +65,7 @@ public:
    const sc_core::sc_time tFAW;
    const sc_core::sc_time tRRD;
    const sc_core::sc_time tCCD;
+    const sc_core::sc_time tCCDMW;
    const sc_core::sc_time tRL;
    const sc_core::sc_time tRPST;
    const sc_core::sc_time tDQSCK;
--- a/src/libdramsys/DRAMSys/controller/checker/CheckerLPDDR4.cpp
+++ b/src/libdramsys/DRAMSys/controller/checker/CheckerLPDDR4.cpp
@@ -178,6 +178,17 @@ sc_time CheckerLPDDR4::timeToSatisfyConstraints(Command command, const tlm_gener
        if (lastCommandStart != scMaxTime)
            earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tBURST + memSpec->tRTRS);

+        if (command == Command::MWR || command == Command::MWRA)
+        {
+            lastCommandStart = lastScheduledByCommandAndBank[Command::WR][bank];
+            if (lastCommandStart != scMaxTime)
+                earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDMW);
+
+            lastCommandStart = lastScheduledByCommandAndBank[Command::WRA][bank];
+            if (lastCommandStart != scMaxTime)
+                earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDMW);
+        }
+
        lastCommandStart = lastScheduledByCommandAndRank[Command::PDXA][rank];
        if (lastCommandStart != scMaxTime)
            earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXP);
--- a/tests/tests_regression/LPDDR4/lpddr4-example.json
+++ b/tests/tests_regression/LPDDR4/lpddr4-example.json
@@ -68,6 +68,7 @@
            "memoryType": "LPDDR4",
            "memtimingspec": {
                "CCD": 8,
+                "CCDMW": 32,
                "CKE": 12,
                "CMDCKE": 3,
                "DQS2DQ": 2,