From b30df49d671894ca80a2adf966f0138be6ee8d59 Mon Sep 17 00:00:00 2001 From: Derek Christ Date: Mon, 21 Aug 2023 09:26:05 +0200 Subject: [PATCH] Use tCCDMW for masked write in LPDDR4 --- configs/memspec/JEDEC_1Gbx16_LPDDR4-0533.json | 1 + configs/memspec/JEDEC_1Gbx16_LPDDR4-1066.json | 1 + configs/memspec/JEDEC_1Gbx16_LPDDR4-1600.json | 1 + configs/memspec/JEDEC_1Gbx16_LPDDR4-2133.json | 1 + configs/memspec/JEDEC_1Gbx16_LPDDR4-2666.json | 1 + configs/memspec/JEDEC_1Gbx16_LPDDR4-3200.json | 1 + configs/memspec/JEDEC_1Gbx16_LPDDR4-3733.json | 1 + configs/memspec/JEDEC_1Gbx16_LPDDR4-4266.json | 1 + configs/memspec/JEDEC_512Mbx16_LPDDR4-0533.json | 1 + configs/memspec/JEDEC_512Mbx16_LPDDR4-1066.json | 1 + configs/memspec/JEDEC_512Mbx16_LPDDR4-1600.json | 1 + configs/memspec/JEDEC_512Mbx16_LPDDR4-2133.json | 1 + configs/memspec/JEDEC_512Mbx16_LPDDR4-2666.json | 1 + configs/memspec/JEDEC_512Mbx16_LPDDR4-3200.json | 1 + configs/memspec/JEDEC_512Mbx16_LPDDR4-3733.json | 1 + configs/memspec/JEDEC_512Mbx16_LPDDR4-4266.json | 1 + configs/memspec/JEDEC_8Gb_LPDDR4-3200_16bit.json | 1 + .../DRAMSys/configuration/memspec/MemSpecLPDDR4.cpp | 1 + .../DRAMSys/configuration/memspec/MemSpecLPDDR4.h | 1 + .../DRAMSys/controller/checker/CheckerLPDDR4.cpp | 11 +++++++++++ tests/tests_regression/LPDDR4/lpddr4-example.json | 1 + 21 files changed, 31 insertions(+) diff --git a/configs/memspec/JEDEC_1Gbx16_LPDDR4-0533.json b/configs/memspec/JEDEC_1Gbx16_LPDDR4-0533.json index 05bc63a6..5ac5d841 100644 --- a/configs/memspec/JEDEC_1Gbx16_LPDDR4-0533.json +++ b/configs/memspec/JEDEC_1Gbx16_LPDDR4-0533.json @@ -15,6 +15,7 @@ "memoryType": "LPDDR4", "memtimingspec": { "CCD": 8, + "CCDMW": 32, "CKE": 4, "CMDCKE": 3, "DQS2DQ": 0, diff --git a/configs/memspec/JEDEC_1Gbx16_LPDDR4-1066.json b/configs/memspec/JEDEC_1Gbx16_LPDDR4-1066.json index 8d90868e..0a59c8f0 100644 --- a/configs/memspec/JEDEC_1Gbx16_LPDDR4-1066.json +++ b/configs/memspec/JEDEC_1Gbx16_LPDDR4-1066.json @@ -15,6 +15,7 @@ "memoryType": "LPDDR4", "memtimingspec": { "CCD": 8, + "CCDMW": 32, "CKE": 4, "CMDCKE": 3, "DQS2DQ": 0, diff --git a/configs/memspec/JEDEC_1Gbx16_LPDDR4-1600.json b/configs/memspec/JEDEC_1Gbx16_LPDDR4-1600.json index 15dbf8a0..2582a665 100644 --- a/configs/memspec/JEDEC_1Gbx16_LPDDR4-1600.json +++ b/configs/memspec/JEDEC_1Gbx16_LPDDR4-1600.json @@ -15,6 +15,7 @@ "memoryType": "LPDDR4", "memtimingspec": { "CCD": 8, + "CCDMW": 32, "CKE": 6, "CMDCKE": 3, "DQS2DQ": 0, diff --git a/configs/memspec/JEDEC_1Gbx16_LPDDR4-2133.json b/configs/memspec/JEDEC_1Gbx16_LPDDR4-2133.json index 243b0b30..ddab725f 100644 --- a/configs/memspec/JEDEC_1Gbx16_LPDDR4-2133.json +++ b/configs/memspec/JEDEC_1Gbx16_LPDDR4-2133.json @@ -15,6 +15,7 @@ "memoryType": "LPDDR4", "memtimingspec": { "CCD": 8, + "CCDMW": 32, "CKE": 9, "CMDCKE": 3, "DQS2DQ": 0, diff --git a/configs/memspec/JEDEC_1Gbx16_LPDDR4-2666.json b/configs/memspec/JEDEC_1Gbx16_LPDDR4-2666.json index 906d69bf..6a2d68d4 100644 --- a/configs/memspec/JEDEC_1Gbx16_LPDDR4-2666.json +++ b/configs/memspec/JEDEC_1Gbx16_LPDDR4-2666.json @@ -15,6 +15,7 @@ "memoryType": "LPDDR4", "memtimingspec": { "CCD": 8, + "CCDMW": 32, "CKE": 10, "CMDCKE": 3, "DQS2DQ": 0, diff --git a/configs/memspec/JEDEC_1Gbx16_LPDDR4-3200.json b/configs/memspec/JEDEC_1Gbx16_LPDDR4-3200.json index 7e89bb85..d8da9906 100644 --- a/configs/memspec/JEDEC_1Gbx16_LPDDR4-3200.json +++ b/configs/memspec/JEDEC_1Gbx16_LPDDR4-3200.json @@ -15,6 +15,7 @@ "memoryType": "LPDDR4", "memtimingspec": { "CCD": 8, + "CCDMW": 32, "CKE": 12, "CMDCKE": 3, "DQS2DQ": 0, diff --git a/configs/memspec/JEDEC_1Gbx16_LPDDR4-3733.json b/configs/memspec/JEDEC_1Gbx16_LPDDR4-3733.json index 34bf2c0d..5de3ab04 100644 --- a/configs/memspec/JEDEC_1Gbx16_LPDDR4-3733.json +++ b/configs/memspec/JEDEC_1Gbx16_LPDDR4-3733.json @@ -15,6 +15,7 @@ "memoryType": "LPDDR4", "memtimingspec": { "CCD": 8, + "CCDMW": 32, "CKE": 15, "CMDCKE": 4, "DQS2DQ": 0, diff --git a/configs/memspec/JEDEC_1Gbx16_LPDDR4-4266.json b/configs/memspec/JEDEC_1Gbx16_LPDDR4-4266.json index 2c32c685..8ddccb5f 100644 --- a/configs/memspec/JEDEC_1Gbx16_LPDDR4-4266.json +++ b/configs/memspec/JEDEC_1Gbx16_LPDDR4-4266.json @@ -15,6 +15,7 @@ "memoryType": "LPDDR4", "memtimingspec": { "CCD": 8, + "CCDMW": 32, "CKE": 17, "CMDCKE": 4, "DQS2DQ": 0, diff --git a/configs/memspec/JEDEC_512Mbx16_LPDDR4-0533.json b/configs/memspec/JEDEC_512Mbx16_LPDDR4-0533.json index 8a9e7336..0ca4fb42 100644 --- a/configs/memspec/JEDEC_512Mbx16_LPDDR4-0533.json +++ b/configs/memspec/JEDEC_512Mbx16_LPDDR4-0533.json @@ -15,6 +15,7 @@ "memoryType": "LPDDR4", "memtimingspec": { "CCD": 8, + "CCDMW": 32, "CKE": 4, "CMDCKE": 3, "DQS2DQ": 0, diff --git a/configs/memspec/JEDEC_512Mbx16_LPDDR4-1066.json b/configs/memspec/JEDEC_512Mbx16_LPDDR4-1066.json index b3d92da6..0bcec5c4 100644 --- a/configs/memspec/JEDEC_512Mbx16_LPDDR4-1066.json +++ b/configs/memspec/JEDEC_512Mbx16_LPDDR4-1066.json @@ -15,6 +15,7 @@ "memoryType": "LPDDR4", "memtimingspec": { "CCD": 8, + "CCDMW": 32, "CKE": 4, "CMDCKE": 3, "DQS2DQ": 0, diff --git a/configs/memspec/JEDEC_512Mbx16_LPDDR4-1600.json b/configs/memspec/JEDEC_512Mbx16_LPDDR4-1600.json index ab996263..b89a8be8 100644 --- a/configs/memspec/JEDEC_512Mbx16_LPDDR4-1600.json +++ b/configs/memspec/JEDEC_512Mbx16_LPDDR4-1600.json @@ -15,6 +15,7 @@ "memoryType": "LPDDR4", "memtimingspec": { "CCD": 8, + "CCDMW": 32, "CKE": 6, "CMDCKE": 3, "DQS2DQ": 0, diff --git a/configs/memspec/JEDEC_512Mbx16_LPDDR4-2133.json b/configs/memspec/JEDEC_512Mbx16_LPDDR4-2133.json index 9b19b8e3..c4b96735 100644 --- a/configs/memspec/JEDEC_512Mbx16_LPDDR4-2133.json +++ b/configs/memspec/JEDEC_512Mbx16_LPDDR4-2133.json @@ -15,6 +15,7 @@ "memoryType": "LPDDR4", "memtimingspec": { "CCD": 8, + "CCDMW": 32, "CKE": 9, "CMDCKE": 3, "DQS2DQ": 0, diff --git a/configs/memspec/JEDEC_512Mbx16_LPDDR4-2666.json b/configs/memspec/JEDEC_512Mbx16_LPDDR4-2666.json index bf4c87ee..d1b856f8 100644 --- a/configs/memspec/JEDEC_512Mbx16_LPDDR4-2666.json +++ b/configs/memspec/JEDEC_512Mbx16_LPDDR4-2666.json @@ -15,6 +15,7 @@ "memoryType": "LPDDR4", "memtimingspec": { "CCD": 8, + "CCDMW": 32, "CKE": 10, "CMDCKE": 3, "DQS2DQ": 0, diff --git a/configs/memspec/JEDEC_512Mbx16_LPDDR4-3200.json b/configs/memspec/JEDEC_512Mbx16_LPDDR4-3200.json index bc238774..cea28e05 100644 --- a/configs/memspec/JEDEC_512Mbx16_LPDDR4-3200.json +++ b/configs/memspec/JEDEC_512Mbx16_LPDDR4-3200.json @@ -15,6 +15,7 @@ "memoryType": "LPDDR4", "memtimingspec": { "CCD": 8, + "CCDMW": 32, "CKE": 12, "CMDCKE": 3, "DQS2DQ": 0, diff --git a/configs/memspec/JEDEC_512Mbx16_LPDDR4-3733.json b/configs/memspec/JEDEC_512Mbx16_LPDDR4-3733.json index 3f7a0a9e..92ed0476 100644 --- a/configs/memspec/JEDEC_512Mbx16_LPDDR4-3733.json +++ b/configs/memspec/JEDEC_512Mbx16_LPDDR4-3733.json @@ -15,6 +15,7 @@ "memoryType": "LPDDR4", "memtimingspec": { "CCD": 8, + "CCDMW": 32, "CKE": 15, "CMDCKE": 4, "DQS2DQ": 0, diff --git a/configs/memspec/JEDEC_512Mbx16_LPDDR4-4266.json b/configs/memspec/JEDEC_512Mbx16_LPDDR4-4266.json index 84f3c5a3..6c075009 100644 --- a/configs/memspec/JEDEC_512Mbx16_LPDDR4-4266.json +++ b/configs/memspec/JEDEC_512Mbx16_LPDDR4-4266.json @@ -15,6 +15,7 @@ "memoryType": "LPDDR4", "memtimingspec": { "CCD": 8, + "CCDMW": 32, "CKE": 17, "CMDCKE": 4, "DQS2DQ": 0, diff --git a/configs/memspec/JEDEC_8Gb_LPDDR4-3200_16bit.json b/configs/memspec/JEDEC_8Gb_LPDDR4-3200_16bit.json index 12094ae4..33ba7767 100644 --- a/configs/memspec/JEDEC_8Gb_LPDDR4-3200_16bit.json +++ b/configs/memspec/JEDEC_8Gb_LPDDR4-3200_16bit.json @@ -65,6 +65,7 @@ }, "memtimingspec": { "CCD": 8, + "CCDMW": 32, "CKE": 12, "CMDCKE": 3, "DQS2DQ": 2, diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecLPDDR4.cpp b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecLPDDR4.cpp index f01099a2..bcdf6124 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecLPDDR4.cpp +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecLPDDR4.cpp @@ -72,6 +72,7 @@ MemSpecLPDDR4::MemSpecLPDDR4(const DRAMSys::Config::MemSpec &memSpec) tFAW (tCK * memSpec.memtimingspec.entries.at("FAW")), tRRD (tCK * memSpec.memtimingspec.entries.at("RRD")), tCCD (tCK * memSpec.memtimingspec.entries.at("CCD")), + tCCDMW (tCK * memSpec.memtimingspec.entries.at("CCDMW")), tRL (tCK * memSpec.memtimingspec.entries.at("RL")), tRPST (tCK * memSpec.memtimingspec.entries.at("RPST")), tDQSCK (tCK * memSpec.memtimingspec.entries.at("DQSCK")), diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecLPDDR4.h b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecLPDDR4.h index 1daa2ab9..9025a87f 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecLPDDR4.h +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecLPDDR4.h @@ -65,6 +65,7 @@ public: const sc_core::sc_time tFAW; const sc_core::sc_time tRRD; const sc_core::sc_time tCCD; + const sc_core::sc_time tCCDMW; const sc_core::sc_time tRL; const sc_core::sc_time tRPST; const sc_core::sc_time tDQSCK; diff --git a/src/libdramsys/DRAMSys/controller/checker/CheckerLPDDR4.cpp b/src/libdramsys/DRAMSys/controller/checker/CheckerLPDDR4.cpp index b6667e66..97fbe7df 100644 --- a/src/libdramsys/DRAMSys/controller/checker/CheckerLPDDR4.cpp +++ b/src/libdramsys/DRAMSys/controller/checker/CheckerLPDDR4.cpp @@ -178,6 +178,17 @@ sc_time CheckerLPDDR4::timeToSatisfyConstraints(Command command, const tlm_gener if (lastCommandStart != scMaxTime) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tBURST + memSpec->tRTRS); + if (command == Command::MWR || command == Command::MWRA) + { + lastCommandStart = lastScheduledByCommandAndBank[Command::WR][bank]; + if (lastCommandStart != scMaxTime) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDMW); + + lastCommandStart = lastScheduledByCommandAndBank[Command::WRA][bank]; + if (lastCommandStart != scMaxTime) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDMW); + } + lastCommandStart = lastScheduledByCommandAndRank[Command::PDXA][rank]; if (lastCommandStart != scMaxTime) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXP); diff --git a/tests/tests_regression/LPDDR4/lpddr4-example.json b/tests/tests_regression/LPDDR4/lpddr4-example.json index 5aa31ec2..674c1f6b 100644 --- a/tests/tests_regression/LPDDR4/lpddr4-example.json +++ b/tests/tests_regression/LPDDR4/lpddr4-example.json @@ -68,6 +68,7 @@ "memoryType": "LPDDR4", "memtimingspec": { "CCD": 8, + "CCDMW": 32, "CKE": 12, "CMDCKE": 3, "DQS2DQ": 2,