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Use tCCDMW for masked write in LPDDR4

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This commit is contained in:
Derek Christ
2023-08-21 09:26:05 +02:00
parent b3937cf63a
commit b30df49d67
21 changed files with 31 additions and 0 deletions
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1
configs/memspec/JEDEC_1Gbx16_LPDDR4-0533.json
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@@ -15,6 +15,7 @@
"memoryType": "LPDDR4", "memoryType": "LPDDR4",
"memtimingspec": { "memtimingspec": {
"CCD": 8, "CCD": 8,
"CCDMW": 32,
"CKE": 4, "CKE": 4,
"CMDCKE": 3, "CMDCKE": 3,
"DQS2DQ": 0, "DQS2DQ": 0,

1
configs/memspec/JEDEC_1Gbx16_LPDDR4-1066.json
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@@ -15,6 +15,7 @@
"memoryType": "LPDDR4", "memoryType": "LPDDR4",
"memtimingspec": { "memtimingspec": {
"CCD": 8, "CCD": 8,
"CCDMW": 32,
"CKE": 4, "CKE": 4,
"CMDCKE": 3, "CMDCKE": 3,
"DQS2DQ": 0, "DQS2DQ": 0,

1
configs/memspec/JEDEC_1Gbx16_LPDDR4-1600.json
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@@ -15,6 +15,7 @@
"memoryType": "LPDDR4", "memoryType": "LPDDR4",
"memtimingspec": { "memtimingspec": {
"CCD": 8, "CCD": 8,
"CCDMW": 32,
"CKE": 6, "CKE": 6,
"CMDCKE": 3, "CMDCKE": 3,
"DQS2DQ": 0, "DQS2DQ": 0,

1
configs/memspec/JEDEC_1Gbx16_LPDDR4-2133.json
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@@ -15,6 +15,7 @@
"memoryType": "LPDDR4", "memoryType": "LPDDR4",
"memtimingspec": { "memtimingspec": {
"CCD": 8, "CCD": 8,
"CCDMW": 32,
"CKE": 9, "CKE": 9,
"CMDCKE": 3, "CMDCKE": 3,
"DQS2DQ": 0, "DQS2DQ": 0,

1
configs/memspec/JEDEC_1Gbx16_LPDDR4-2666.json
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@@ -15,6 +15,7 @@
"memoryType": "LPDDR4", "memoryType": "LPDDR4",
"memtimingspec": { "memtimingspec": {
"CCD": 8, "CCD": 8,
"CCDMW": 32,
"CKE": 10, "CKE": 10,
"CMDCKE": 3, "CMDCKE": 3,
"DQS2DQ": 0, "DQS2DQ": 0,

1
configs/memspec/JEDEC_1Gbx16_LPDDR4-3200.json
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@@ -15,6 +15,7 @@
"memoryType": "LPDDR4", "memoryType": "LPDDR4",
"memtimingspec": { "memtimingspec": {
"CCD": 8, "CCD": 8,
"CCDMW": 32,
"CKE": 12, "CKE": 12,
"CMDCKE": 3, "CMDCKE": 3,
"DQS2DQ": 0, "DQS2DQ": 0,

1
configs/memspec/JEDEC_1Gbx16_LPDDR4-3733.json
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@@ -15,6 +15,7 @@
"memoryType": "LPDDR4", "memoryType": "LPDDR4",
"memtimingspec": { "memtimingspec": {
"CCD": 8, "CCD": 8,
"CCDMW": 32,
"CKE": 15, "CKE": 15,
"CMDCKE": 4, "CMDCKE": 4,
"DQS2DQ": 0, "DQS2DQ": 0,

1
configs/memspec/JEDEC_1Gbx16_LPDDR4-4266.json
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@@ -15,6 +15,7 @@
"memoryType": "LPDDR4", "memoryType": "LPDDR4",
"memtimingspec": { "memtimingspec": {
"CCD": 8, "CCD": 8,
"CCDMW": 32,
"CKE": 17, "CKE": 17,
"CMDCKE": 4, "CMDCKE": 4,
"DQS2DQ": 0, "DQS2DQ": 0,

1
configs/memspec/JEDEC_512Mbx16_LPDDR4-0533.json
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@@ -15,6 +15,7 @@
"memoryType": "LPDDR4", "memoryType": "LPDDR4",
"memtimingspec": { "memtimingspec": {
"CCD": 8, "CCD": 8,
"CCDMW": 32,
"CKE": 4, "CKE": 4,
"CMDCKE": 3, "CMDCKE": 3,
"DQS2DQ": 0, "DQS2DQ": 0,

1
configs/memspec/JEDEC_512Mbx16_LPDDR4-1066.json
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@@ -15,6 +15,7 @@
"memoryType": "LPDDR4", "memoryType": "LPDDR4",
"memtimingspec": { "memtimingspec": {
"CCD": 8, "CCD": 8,
"CCDMW": 32,
"CKE": 4, "CKE": 4,
"CMDCKE": 3, "CMDCKE": 3,
"DQS2DQ": 0, "DQS2DQ": 0,

1
configs/memspec/JEDEC_512Mbx16_LPDDR4-1600.json
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@@ -15,6 +15,7 @@
"memoryType": "LPDDR4", "memoryType": "LPDDR4",
"memtimingspec": { "memtimingspec": {
"CCD": 8, "CCD": 8,
"CCDMW": 32,
"CKE": 6, "CKE": 6,
"CMDCKE": 3, "CMDCKE": 3,
"DQS2DQ": 0, "DQS2DQ": 0,

1
configs/memspec/JEDEC_512Mbx16_LPDDR4-2133.json
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@@ -15,6 +15,7 @@
"memoryType": "LPDDR4", "memoryType": "LPDDR4",
"memtimingspec": { "memtimingspec": {
"CCD": 8, "CCD": 8,
"CCDMW": 32,
"CKE": 9, "CKE": 9,
"CMDCKE": 3, "CMDCKE": 3,
"DQS2DQ": 0, "DQS2DQ": 0,

1
configs/memspec/JEDEC_512Mbx16_LPDDR4-2666.json
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@@ -15,6 +15,7 @@
"memoryType": "LPDDR4", "memoryType": "LPDDR4",
"memtimingspec": { "memtimingspec": {
"CCD": 8, "CCD": 8,
"CCDMW": 32,
"CKE": 10, "CKE": 10,
"CMDCKE": 3, "CMDCKE": 3,
"DQS2DQ": 0, "DQS2DQ": 0,

1
configs/memspec/JEDEC_512Mbx16_LPDDR4-3200.json
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@@ -15,6 +15,7 @@
"memoryType": "LPDDR4", "memoryType": "LPDDR4",
"memtimingspec": { "memtimingspec": {
"CCD": 8, "CCD": 8,
"CCDMW": 32,
"CKE": 12, "CKE": 12,
"CMDCKE": 3, "CMDCKE": 3,
"DQS2DQ": 0, "DQS2DQ": 0,

1
configs/memspec/JEDEC_512Mbx16_LPDDR4-3733.json
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@@ -15,6 +15,7 @@
"memoryType": "LPDDR4", "memoryType": "LPDDR4",
"memtimingspec": { "memtimingspec": {
"CCD": 8, "CCD": 8,
"CCDMW": 32,
"CKE": 15, "CKE": 15,
"CMDCKE": 4, "CMDCKE": 4,
"DQS2DQ": 0, "DQS2DQ": 0,

1
configs/memspec/JEDEC_512Mbx16_LPDDR4-4266.json
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@@ -15,6 +15,7 @@
"memoryType": "LPDDR4", "memoryType": "LPDDR4",
"memtimingspec": { "memtimingspec": {
"CCD": 8, "CCD": 8,
"CCDMW": 32,
"CKE": 17, "CKE": 17,
"CMDCKE": 4, "CMDCKE": 4,
"DQS2DQ": 0, "DQS2DQ": 0,

1
configs/memspec/JEDEC_8Gb_LPDDR4-3200_16bit.json
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@@ -65,6 +65,7 @@
}, },
"memtimingspec": { "memtimingspec": {
"CCD": 8, "CCD": 8,
"CCDMW": 32,
"CKE": 12, "CKE": 12,
"CMDCKE": 3, "CMDCKE": 3,
"DQS2DQ": 2, "DQS2DQ": 2,

1
src/libdramsys/DRAMSys/configuration/memspec/MemSpecLPDDR4.cpp
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@@ -72,6 +72,7 @@ MemSpecLPDDR4::MemSpecLPDDR4(const DRAMSys::Config::MemSpec &memSpec)
tFAW (tCK * memSpec.memtimingspec.entries.at("FAW")), tFAW (tCK * memSpec.memtimingspec.entries.at("FAW")),
tRRD (tCK * memSpec.memtimingspec.entries.at("RRD")), tRRD (tCK * memSpec.memtimingspec.entries.at("RRD")),
tCCD (tCK * memSpec.memtimingspec.entries.at("CCD")), tCCD (tCK * memSpec.memtimingspec.entries.at("CCD")),
tCCDMW (tCK * memSpec.memtimingspec.entries.at("CCDMW")),
tRL (tCK * memSpec.memtimingspec.entries.at("RL")), tRL (tCK * memSpec.memtimingspec.entries.at("RL")),
tRPST (tCK * memSpec.memtimingspec.entries.at("RPST")), tRPST (tCK * memSpec.memtimingspec.entries.at("RPST")),
tDQSCK (tCK * memSpec.memtimingspec.entries.at("DQSCK")), tDQSCK (tCK * memSpec.memtimingspec.entries.at("DQSCK")),

1
src/libdramsys/DRAMSys/configuration/memspec/MemSpecLPDDR4.h
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@@ -65,6 +65,7 @@ public:
const sc_core::sc_time tFAW; const sc_core::sc_time tFAW;
const sc_core::sc_time tRRD; const sc_core::sc_time tRRD;
const sc_core::sc_time tCCD; const sc_core::sc_time tCCD;
const sc_core::sc_time tCCDMW;
const sc_core::sc_time tRL; const sc_core::sc_time tRL;
const sc_core::sc_time tRPST; const sc_core::sc_time tRPST;
const sc_core::sc_time tDQSCK; const sc_core::sc_time tDQSCK;

11
src/libdramsys/DRAMSys/controller/checker/CheckerLPDDR4.cpp
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@@ -178,6 +178,17 @@ sc_time CheckerLPDDR4::timeToSatisfyConstraints(Command command, const tlm_gener
if (lastCommandStart != scMaxTime) if (lastCommandStart != scMaxTime)
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tBURST + memSpec->tRTRS); earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tBURST + memSpec->tRTRS);
if (command == Command::MWR || command == Command::MWRA)
{
lastCommandStart = lastScheduledByCommandAndBank[Command::WR][bank];
if (lastCommandStart != scMaxTime)
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDMW);
lastCommandStart = lastScheduledByCommandAndBank[Command::WRA][bank];
if (lastCommandStart != scMaxTime)
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDMW);
}
lastCommandStart = lastScheduledByCommandAndRank[Command::PDXA][rank]; lastCommandStart = lastScheduledByCommandAndRank[Command::PDXA][rank];
if (lastCommandStart != scMaxTime) if (lastCommandStart != scMaxTime)
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXP); earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXP);

1
tests/tests_regression/LPDDR4/lpddr4-example.json
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@@ -68,6 +68,7 @@
"memoryType": "LPDDR4", "memoryType": "LPDDR4",
"memtimingspec": { "memtimingspec": {
"CCD": 8, "CCD": 8,
"CCDMW": 32,
"CKE": 12, "CKE": 12,
"CMDCKE": 3, "CMDCKE": 3,
"DQS2DQ": 2, "DQS2DQ": 2,