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Fix issuance of commands in half-cylces in HBM3

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This commit is contained in:
Derek Christ
2022-05-23 17:08:32 +02:00
parent f66a98b911
commit a944d0eeff
2 changed files with 12 additions and 0 deletions
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10
DRAMSys/library/src/controller/checker/CheckerHBM3.cpp
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@@ -760,6 +760,10 @@ sc_time CheckerHBM3::timeToSatisfyConstraints(Command command, const tlm_generic
SC_REPORT_FATAL("CheckerHBM3", "Unknown command!"); SC_REPORT_FATAL("CheckerHBM3", "Unknown command!");
} }
// Don't issue commands at half cycles.
if (command != Command::PREAB && command != Command::PREPB && !isFullCycle(earliestTimeToStart))
earliestTimeToStart += memSpec->tCK / 2;
return earliestTimeToStart; return earliestTimeToStart;
} }
@@ -794,3 +798,9 @@ void CheckerHBM3::insert(Command command, const tlm_generic_payload &payload)
if (command == Command::REFPB) if (command == Command::REFPB)
bankwiseRefreshCounter[rank.ID()] = (bankwiseRefreshCounter[rank.ID()] + 1) % memSpec->banksPerRank; bankwiseRefreshCounter[rank.ID()] = (bankwiseRefreshCounter[rank.ID()] + 1) % memSpec->banksPerRank;
} }
bool CheckerHBM3::isFullCycle(const sc_core::sc_time& time) const
{
sc_time aligedAtHalfCycle = std::floor((time * 2 / memSpec->tCK + 0.5)) / 2 * memSpec->tCK;
return aligedAtHalfCycle % memSpec->tCK == SC_ZERO_TIME;
}

2
DRAMSys/library/src/controller/checker/CheckerHBM3.h
View File

@@ -50,6 +50,8 @@ public:
void insert(Command command, const tlm::tlm_generic_payload& payload) override; void insert(Command command, const tlm::tlm_generic_payload& payload) override;
private: private:
bool isFullCycle(const sc_core::sc_time& time) const;
const MemSpecHBM3 *memSpec; const MemSpecHBM3 *memSpec;
std::vector<std::vector<sc_core::sc_time>> lastScheduledByCommandAndBank; std::vector<std::vector<sc_core::sc_time>> lastScheduledByCommandAndBank;