ECC Controller umgebaut. Testumgebung angepasst. Weak cells manuell gesetzt.

2017-03-02 20:18:36 +01:00
parent 25015d3dd1
commit a11276c876
12 changed files with 221 additions and 48 deletions
--- a/DRAMSys/simulator/library.pro
+++ b/DRAMSys/simulator/library.pro
@@ -163,7 +163,8 @@ HEADERS += \
    src/controller/core/powerdown/PowerDownManagerTimeoutBankwise.h \
    src/simulation/TraceSetup.h \
    src/simulation/DRAMSys.h \
-    src/simulation/Setup.h
+    src/simulation/Setup.h \
+    src/error/controllerECC.h

 thermalsim = $$(THERMALSIM)
 isEmpty(thermalsim) {
--- a/DRAMSys/simulator/resources/configs/mcconfigs/fifo_ecc.xml
+++ b/DRAMSys/simulator/resources/configs/mcconfigs/fifo_ecc.xml
@@ -0,0 +1,20 @@
+<mcconfig>
+    <BankwiseLogic value="0"/>
+    <OpenPagePolicy value="1" />
+    <MaxNrOfTransactions value="8" />
+    <Scheduler value="FIFO" />
+    <Capsize value="5" />
+    <!-- 4 Modes: NoPowerDown, Staggered, TimeoutPDN, TimeoutSREF -->
+    <PowerDownMode value="NoPowerDown" />
+    <PowerDownTimeout value="100" />
+    <!-- Error Modelling -->
+    <ErrorChipSeed value="42" />
+    <ErrorCSVFile value="../../DRAMSys/simulator/src/error/error.csv" />
+    <!-- Modes:
+        - NoStorage,
+        - Store (store data without errormodel),
+        - ErrorModel (store data with errormodel)
+    -->
+    <StoreMode value="ErrorModel" />
+    <ControllerCoreDisableRefresh value="0"/>
+</mcconfig>
--- a/DRAMSys/simulator/resources/configs/memspecs/wideio_less_refresh.xml
+++ b/DRAMSys/simulator/resources/configs/memspecs/wideio_less_refresh.xml
@@ -0,0 +1,61 @@
+<!DOCTYPE memspec SYSTEM "memspec.dtd">
+<memspec>
+  <parameter id="memoryId" type="string" value="wideio_less_refresh" />
+  <parameter id="memoryType" type="string" value="WIDEIO_SDR" />
+  <memarchitecturespec>
+    <parameter id="width" type="uint" value="128" />
+    <parameter id="nbrOfBanks" type="uint" value="8" />
+    <parameter id="nbrOfColumns" type="uint" value="128" />
+     <parameter id="nbrOfRows" type="uint" value="8192" />
+     <parameter id="dataRate" type="uint" value="1" />
+    <parameter id="burstLength" type="uint" value="4" />
+  </memarchitecturespec>
+  <memtimingspec>
+      <parameter id="clkMhz" type="double" value="166" />
+      <parameter id="RC" type="uint" value="9" /><!--tRP+tRAS-->
+      <parameter id="RCD" type="uint" value="3" />
+      <parameter id="RL" type="uint" value="3" />
+      <parameter id="RP" type="uint" value="3" />
+      <parameter id="RFC" type="uint" value="22" />
+      <parameter id="RAS" type="uint" value="6" />
+      <parameter id="WL" type="uint" value="1" />
+      <parameter id="AL" type="uint" value="0" /> 
+      <parameter id="RTP" type="uint" value="4" />
+      <parameter id="WR" type="uint" value="2" />
+      <parameter id="XP" type="uint" value="2" />
+      <parameter id="XS" type="uint" value="20" /><!--tRFC+2clk-->
+      <parameter id="REFI" type="uint" value="166000000000" />
+      <parameter id="TAW" type="uint" value="10" />
+      <parameter id="RRD" type="uint" value="2" />
+      <parameter id="CCD" type="uint" value="1" />
+      <parameter id="WTR" type="uint" value="3" />
+      <parameter id="CKE" type="uint" value="3" />
+      <parameter id="CKESR" type="uint" value="3" />
+  </memtimingspec>
+  <mempowerspec>
+      <parameter id="idd0" type="double" value="5.88" />
+      <parameter id="idd02" type="double" value="21.18" />
+      <parameter id="idd2p0" type="double" value="0.05" />
+      <parameter id="idd2p02" type="double" value="0.17" />
+      <parameter id="idd2p1" type="double" value="0.05" />
+      <parameter id="idd2p12" type="double" value="0.17" />
+      <parameter id="idd2n" type="double" value="0.13" />
+      <parameter id="idd2n2" type="double" value="4.04" />
+      <parameter id="idd3p0" type="double" value="0.25" />
+      <parameter id="idd3p02" type="double" value="1.49" />
+      <parameter id="idd3p1" type="double" value="0.25" />
+      <parameter id="idd3p12" type="double" value="1.49" />
+      <parameter id="idd3n" type="double" value="0.52" />
+      <parameter id="idd3n2" type="double" value="6.55" />
+      <parameter id="idd4r" type="double" value="1.41" />
+      <parameter id="idd4r2" type="double" value="85.73" />
+      <parameter id="idd4w" type="double" value="1.42" />
+      <parameter id="idd4w2" type="double" value="60.79" />
+      <parameter id="idd5" type="double" value="14.43" />
+      <parameter id="idd52" type="double" value="48.17" />
+      <parameter id="idd6" type="double" value="0.07" />
+      <parameter id="idd62" type="double" value="0.27" />
+      <parameter id="vdd" type="double" value="1.8" />
+      <parameter id="vdd2" type="double" value="1.2" />
+  </mempowerspec>
+</memspec>
--- a/DRAMSys/simulator/resources/configs/simulator/wideio_ecc.xml
+++ b/DRAMSys/simulator/resources/configs/simulator/wideio_ecc.xml
@@ -0,0 +1,15 @@
+<simconfig>
+    <SimulationName value="wideio_ecc" />
+    <Debug value="0" />
+    <DatabaseRecording value="1" />
+    <PowerAnalysis value="1" />
+    <EnableWindowing value = "1" />
+    <WindowSize value="1000" />
+    <ThermalSimulation value="0"/>
+    <SimulationProgressBar value="1"/>
+    <NumberOfMemChannels value="1"/>
+    <NumberOfDevicesOnDIMM value = "1" />
+    <CheckTLM2Protocol value = "0" />
+    <EnableControllerECC value = "1" />
+</simconfig>
+
--- a/DRAMSys/simulator/resources/resources.pri
+++ b/DRAMSys/simulator/resources/resources.pri
@@ -134,3 +134,10 @@ OTHER_FILES += resources/configs/thermalsim/mem.flp
 OTHER_FILES += resources/configs/thermalsim/powerInfo.xml
 OTHER_FILES += resources/configs/thermalsim/stack.stk
 OTHER_FILES += resources/configs/thermalsim/config.xml
+
+DISTFILES += \
+    $$PWD/configs/simulator/wideio_ecc.xml \
+    $$PWD/configs/mcconfigs/fifo_ecc.xml \
+    $$PWD/simulations/wideio-ecc.xml \
+    $$PWD/traces/test_ecc.stl \
+    $$PWD/configs/memspecs/wideio_less_refresh.xml
--- a/DRAMSys/simulator/resources/simulations/wideio-ecc.xml
+++ b/DRAMSys/simulator/resources/simulations/wideio-ecc.xml
@@ -0,0 +1,22 @@
+<simulation>
+    <!-- Configuration for the DRAMSys Simulator -->
+    <simconfig src="wideio_ecc.xml" />
+    <!-- Temperature Simulator Configuration -->
+    <thermalconfig src="config.xml" />
+    <!-- Memory Device Specification: Which Device is used for Wide I/O -->
+    <memspec src="wideio_less_refresh.xml"></memspec>
+    <!-- Addressmapping Configuration of the Memory Controller -->
+    <addressmapping src="am_wideio.xml"></addressmapping>
+    <!-- Memory Controller Configuration -->
+    <mcconfig src="fifo_ecc.xml"/>
+    <!--
+    The following trace setup is only used in standalone mode.
+    In library mode e.g. in Platform Architect the trace setup is ignored.
+    -->
+    <tracesetup>
+        <!--
+        This device mimics an processor running at 1 GHz.
+        -->
+        <device clkMhz="1000">test_ecc.stl</device>
+    </tracesetup>
+</simulation>
--- a/DRAMSys/simulator/src/controller/core/configuration/Configuration.cpp
+++ b/DRAMSys/simulator/src/controller/core/configuration/Configuration.cpp
@@ -187,6 +187,8 @@ void Configuration::setParameter(std::string name, std::string value)
        NumberOfDevicesOnDIMM = string2int(value);
    else if(name == "CheckTLM2Protocol")
        CheckTLM2Protocol = string2bool(value);
+    else if(name == "EnableControllerECC")
+        EnableControllerECC = string2bool(value);
    // Specification for ErrorChipSeed, ErrorCSVFile path and StoreMode
    else if(name == "ErrorChipSeed")
        ErrorChipSeed = string2int(value);
--- a/DRAMSys/simulator/src/controller/core/configuration/Configuration.h
+++ b/DRAMSys/simulator/src/controller/core/configuration/Configuration.h
@@ -81,6 +81,7 @@ struct  Configuration
    bool SimulationProgressBar = false;
    unsigned int NumberOfDevicesOnDIMM = 1;
    bool CheckTLM2Protocol = false;
+    bool EnableControllerECC = false;

    // MemSpec (from DRAM-Power XML)
    MemSpec memSpec;
--- a/DRAMSys/simulator/src/error/controllerECC.h
+++ b/DRAMSys/simulator/src/error/controllerECC.h
@@ -12,7 +12,7 @@ using namespace tlm;
 struct ControllerECC: sc_module
 {
 private:
-	map<sc_dt::uint64, uint8_t> m_mBuffer;
+    map<sc_dt::uint64, vector<uint8_t>> m_mBuffer;

 public:
 	tlm_utils::multi_passthrough_target_socket<ControllerECC>    t_socket;
@@ -29,38 +29,45 @@ public:
 	// Forward interface
 	virtual tlm::tlm_sync_enum nb_transport_fw( int id, tlm::tlm_generic_payload& trans, tlm::tlm_phase& phase, sc_time& delay )
 	{
-		if(trans.get_command() == TLM_WRITE_COMMAND)
-		{
-			// Save all Bytes
-			for(unsigned i = 0; i < trans.get_data_length(); i++)
-			{
-				m_mBuffer[trans.get_address() + i] = *(trans.get_data_ptr() + i);
-			}
-		}
-		return i_socket[id]->nb_transport_fw( trans, phase, delay );
+        if(trans.get_command() == TLM_WRITE_COMMAND)
+        {
+            // Allocate memory if necessary
+            if(m_mBuffer[trans.get_address()].size() != trans.get_data_length())
+                m_mBuffer[trans.get_address()].resize(trans.get_data_length());
+
+            // Copy data
+            memcpy(m_mBuffer[trans.get_address()].data(), trans.get_data_ptr(), trans.get_data_length());
+        }
+        return i_socket[id]->nb_transport_fw( trans, phase, delay );
 	}


 	// Backward interface
 	virtual tlm::tlm_sync_enum nb_transport_bw( int id, tlm::tlm_generic_payload& trans, tlm::tlm_phase& phase, sc_time& delay )
 	{
-		if(trans.get_command() == TLM_WRITE_COMMAND)
-		{
-			// Compare all Bytes
-			for(unsigned i = 0; i < trans.get_data_length(); i++)
-			{
-				if(m_mBuffer[trans.get_address() + i] != *(trans.get_data_ptr() + i))
-				{
-					std::stringstream msg;
-					msg << "Error Detected: Address: 0x" << hex << trans.get_address() + i
-						<< "\n\t\tData Read: 0x" << hex << (int)*(trans.get_data_ptr() + i)
-						<< "\n\t\tData original: 0x" << hex << (int)m_mBuffer[trans.get_address() + i];
-
-					DebugManager::getInstance().printDebugMessage(name(), msg.str());
-				}
-			}
-		}
+        if(trans.get_command() == TLM_READ_COMMAND && phase == 3)
+        {
+            if(m_mBuffer[trans.get_address()].size() == trans.get_data_length())
+            {
+                // Data can be compared, they got the same size
+                int error = memcmp(m_mBuffer[trans.get_address()].data(), trans.get_data_ptr(), trans.get_data_length());
+                if(error)
+                {
+                    // Data not equal
+                    cout << "\nError Detected: Address: 0x" << hex << trans.get_address();

+                    for(unsigned n = 0; n < trans.get_data_length(); n++)
+                    {
+                        if(m_mBuffer[trans.get_address()].data()[n] !=  trans.get_data_ptr()[n])
+                        {
+                            cout << "\n\t\tError Byte " << dec << n << " Orig: 0x" << hex << (int)m_mBuffer[trans.get_address()].data()[n]
+                                                                    << " Read: 0x" << hex << (int)trans.get_data_ptr()[n];
+                        }
+                    }
+                    cout << endl;
+                }
+            }
+        }
 		return t_socket[id]->nb_transport_bw( trans, phase, delay );
 	}
 };
--- a/DRAMSys/simulator/src/error/errormodel.cpp
+++ b/DRAMSys/simulator/src/error/errormodel.cpp
@@ -105,6 +105,26 @@ void errorModel::init()
    //weakCells[0].row = 0;
    //weakCells[0].dependent = true;

+    weakCells[0].bit = 0;
+    weakCells[0].col = 0;
+    weakCells[0].row = 0;
+    weakCells[0].dependent = false;
+
+    weakCells[0].bit = 5;
+    weakCells[0].col = 0;
+    weakCells[0].row = 0;
+    weakCells[0].dependent = false;
+
+    weakCells[0].bit = 12;
+    weakCells[0].col = 0;
+    weakCells[0].row = 0;
+    weakCells[0].dependent = false;
+
+    weakCells[0].bit = 22;
+    weakCells[0].col = 0;
+    weakCells[0].row = 0;
+    weakCells[0].dependent = false;
+
    markBitFlips();
 }

--- a/DRAMSys/simulator/src/simulation/DRAMSys.cpp
+++ b/DRAMSys/simulator/src/simulation/DRAMSys.cpp
@@ -58,6 +58,9 @@ DRAMSys::DRAMSys(sc_module_name __attribute__((unused)) name,
                 string simulationToRun,
                 string pathToResources) : tSocket("DRAMSys_tSocket")
 {
+    // Initialize ecc pointer
+    ecc = 0;
+
    logo();

    // Read Configuration Setup:
@@ -185,6 +188,10 @@ void DRAMSys::instantiateModules(const string &traceName,
    // They need to be ready before creating some modules.
    setupTlmRecorders(traceName, pathToResources);

+    // Initialize ECC Controller is enabled
+    if(Configuration::getInstance().EnableControllerECC)
+        ecc = new ControllerECC("ControllerECC");
+
    arbiter = new Arbiter("arbiter");
    arbiter->setTlmRecorders(tlmRecorders);

@@ -214,35 +221,45 @@ void DRAMSys::instantiateModules(const string &traceName,

 void DRAMSys::bindSockets()
 {
-    tSocket.bind(arbiter->tSocket);
+    // If ECC Controller enabled, put it between Trace and arbiter
+    if(Configuration::getInstance().EnableControllerECC)
+    {
+        tSocket.bind(ecc->t_socket);
+        ecc->i_socket.bind(arbiter->tSocket);
+    }
+    else
+    {
+        tSocket.bind(arbiter->tSocket);
+    }

-        if(Configuration::getInstance().CheckTLM2Protocol)
+    if(Configuration::getInstance().CheckTLM2Protocol)
+    {
+        for (size_t i = 0;
+             i < Configuration::getInstance().NumberOfMemChannels;
+             i++)
        {
-            for (size_t i = 0;
-                 i < Configuration::getInstance().NumberOfMemChannels;
-                 i++)
-            {
-                arbiter->iSocket.bind(controllersTlmCheckers[i]->target_socket);
-                controllersTlmCheckers[i]->initiator_socket.bind(
-                            controllers[i]->tSocket);
-                controllers[i]->iSocket.bind(drams[i]->tSocket);
-            }
+            arbiter->iSocket.bind(controllersTlmCheckers[i]->target_socket);
+            controllersTlmCheckers[i]->initiator_socket.bind(
+                        controllers[i]->tSocket);
+            controllers[i]->iSocket.bind(drams[i]->tSocket);
        }
-        else
+    }
+    else
+    {
+        for (size_t i = 0;
+             i < Configuration::getInstance().NumberOfMemChannels;
+             i++)
        {
-            for (size_t i = 0;
-                 i < Configuration::getInstance().NumberOfMemChannels;
-                 i++)
-            {
-                arbiter->iSocket.bind(controllers[i]->tSocket);
-                controllers[i]->iSocket.bind(drams[i]->tSocket);
-            }
+            arbiter->iSocket.bind(controllers[i]->tSocket);
+            controllers[i]->iSocket.bind(drams[i]->tSocket);
        }
+    }
 }

 DRAMSys::~DRAMSys()
 {
-
+    if(ecc)
+        delete ecc;
    delete arbiter;

    for (auto controller : controllers)
--- a/DRAMSys/simulator/src/simulation/main.cpp
+++ b/DRAMSys/simulator/src/simulation/main.cpp
@@ -72,7 +72,7 @@ int sc_main(int argc, char **argv)
    }
    else
    {
-        SimulationXML = resources + "simulations/ddr3-example.xml";
+        SimulationXML = resources + "simulations/wideio-ecc.xml";
    }

    std::vector<StlPlayer*> players;