derek/DRAMSys
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

ECC implemented. Error trace created which produces many errors.

Browse Source
This commit is contained in:
Johannes Feldmann
2017-02-27 10:46:48 +01:00
parent af20dcb647
commit a0daa34bf1
5 changed files with 57 additions and 28 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
DRAMSys/simulator/resources/configs/mcconfigs/fifo.xml
View File

@@ -10,5 +10,5 @@
<ErrorChipSeed value="42" />
<ErrorCSVFile value="../../DRAMSys/simulator/src/error/error.csv" />
<!--3 Modes: NoStorage, Store (store data without errormodel), ErrorModel (store data with errormodel)-->
<StoreMode value="NoStorage" />
<StoreMode value="ErrorModel" />
</mcconfig>

2
DRAMSys/simulator/resources/configs/memspecs/WideIO.xml
View File

@@ -24,7 +24,7 @@
<parameter id="WR" type="uint" value="2" />
<parameter id="XP" type="uint" value="2" />
<parameter id="XS" type="uint" value="20" /><!--tRFC+2clk-->
<parameter id="REFI" type="uint" value="1300" />
<parameter id="REFI" type="uint" value="1660000000" />
<parameter id="TAW" type="uint" value="10" />
<parameter id="RRD" type="uint" value="2" />
<parameter id="CCD" type="uint" value="1" />

8
DRAMSys/simulator/resources/simulations/sim-batch.xml
View File

@@ -1,8 +1,8 @@
<simulation>
<!-- General Simulator Configuration (used for all simulation setups) -->
<simconfig>
<Debug value="0" />
<DatabaseRecording value="0" />
<Debug value="1" />
<DatabaseRecording value="1" />
<PowerAnalysis value="0" />
<EnableWindowing value = "0" />
<WindowSize value="1000" />
@@ -39,12 +39,12 @@
</addressmappings>
<mcconfigs>
<mcconfig src="../../DRAMSys/simulator/resources/configs/mcconfigs/fifoStrict.xml"/>
<mcconfig src="../../DRAMSys/simulator/resources/configs/mcconfigs/fifo.xml"/>
</mcconfigs>
<tracesetups>
<tracesetup id="fifo">
<device clkMhz="200">chstone-adpcm_32.stl</device>
<device clkMhz="200">test.stl</device>
</tracesetup>
</tracesetups>

70
DRAMSys/simulator/src/error/controllerECC.h
View File

@@ -3,38 +3,66 @@
#include <systemc.h>
#include "../common/xmlAddressdecoder.h"
#include "../common/DebugManager.h"
using namespace std;
using namespace tlm;
struct ControllerECC: sc_module
{
tlm_utils::multi_passthrough_target_socket<ControllerECC> t_socket;
tlm_utils::multi_passthrough_initiator_socket<ControllerECC> i_socket;
private:
map<sc_dt::uint64, uint8_t> m_mBuffer;
SC_CTOR(ControllerECC)
: t_socket("t_socket")
, i_socket("i_socket")
{
t_socket.register_nb_transport_fw (this, &ControllerECC::nb_transport_fw);
i_socket.register_nb_transport_bw (this, &ControllerECC::nb_transport_bw);
}
public:
tlm_utils::multi_passthrough_target_socket<ControllerECC> t_socket;
tlm_utils::multi_passthrough_initiator_socket<ControllerECC> i_socket;
// Forward interface
SC_CTOR(ControllerECC)
: t_socket("t_socket")
, i_socket("i_socket")
{
t_socket.register_nb_transport_fw(this, &ControllerECC::nb_transport_fw);
i_socket.register_nb_transport_bw(this, &ControllerECC::nb_transport_bw);
}
virtual tlm::tlm_sync_enum nb_transport_fw( int id, tlm::tlm_generic_payload& trans,
tlm::tlm_phase& phase, sc_time& delay )
{
return i_socket[id]->nb_transport_fw( trans, phase, delay );
}
// Forward interface
virtual tlm::tlm_sync_enum nb_transport_fw( int id, tlm::tlm_generic_payload& trans, tlm::tlm_phase& phase, sc_time& delay )
{
if(trans.get_command() == TLM_WRITE_COMMAND)
{
// Save all Bytes
for(unsigned i = 0; i < trans.get_data_length(); i++)
{
m_mBuffer[trans.get_address() + i] = *(trans.get_data_ptr() + i);
}
}
return i_socket[id]->nb_transport_fw( trans, phase, delay );
}
// Backward interface
// Backward interface
virtual tlm::tlm_sync_enum nb_transport_bw( int id, tlm::tlm_generic_payload& trans, tlm::tlm_phase& phase, sc_time& delay )
{
if(trans.get_command() == TLM_WRITE_COMMAND)
{
// Compare all Bytes
for(unsigned i = 0; i < trans.get_data_length(); i++)
{
if(m_mBuffer[trans.get_address() + i] != *(trans.get_data_ptr() + i))
{
std::stringstream msg;
msg << "Error Detected: Address: 0x" << hex << trans.get_address() + i
<< "\n\t\tData Read: 0x" << hex << (int)*(trans.get_data_ptr() + i)
<< "\n\t\tData original: 0x" << hex << (int)m_mBuffer[trans.get_address() + i];
virtual tlm::tlm_sync_enum nb_transport_bw( int id, tlm::tlm_generic_payload& trans,
tlm::tlm_phase& phase, sc_time& delay )
{
return t_socket[id]->nb_transport_bw( trans, phase, delay );
}
DebugManager::getInstance().printDebugMessage(name(), msg.str());
}
}
}
return t_socket[id]->nb_transport_bw( trans, phase, delay );
}
};
#endif // CONTROLLERECC_H

3
DRAMSys/simulator/src/simulation/SimulationManager.cpp
View File

@@ -92,7 +92,7 @@ void SimulationManager::runSimulations()
for (auto& batch : simulationBatches)
{
boost::filesystem::path dir(exportPath);
boost::filesystem::create_directories(dir);
boost::filesystem::create_directory(dir);
for (auto& dramSetup : batch.dramSetups)
{
@@ -238,6 +238,7 @@ void SimulationManager::runSimulation(string traceName)
sc_set_stop_mode(SC_STOP_FINISH_DELTA);
sc_start();
double elapsed_secs = double(clock() - simStartTime) / CLOCKS_PER_SEC;
report("\nSimulation took " + to_string(elapsed_secs) + " seconds\n");
delete simulation;