Created a section for address decoding with json files.

README.md

@@ -503,6 +503,10 @@ Below, the sub-configurations are listed and explained.
 
 - **Address Mapping**
 
+  There are currently two different file formats to describe the address mapping. This software automatically chooses the correct interpreter using the file extension as selection criterion. So please make sure that all files have the correct extension.
+
+- **XML file format**
+
   XML files describe the address mapping to be used in the simulation.
 
   Example for 1GB x64 DIMM with: 8 x 1 Gbit x8 Devices (Micron MT41J128M8) with Page Size: 1KB
@@ -568,6 +572,71 @@ Below, the sub-configurations are listed and explained.
 
   ![Address Mapping Sample 2](DRAMSys/docs/images/am_wideio_brc.png)
 
+- **JSON file format**
+
+  This file format is generated by ConGen. It does not have an unambiguous assignment of the address lines.
+
+  The format delivers more information than needed for an address mapping.
+  Unused data:
+  - Block "Config": Gives you information about the ConGen configuration
+  - Key "Name": Name of the trace file which was used by ConGen
+  - All items of the array "Solutions" but the first one: Alternative solution with same result.
+  - Key "costs": Number of row misses which this configuration produces while playing the trace.
+  
+  Used data:
+  - First item of array "Solution":
+    - "XOR": Array of row and bank bits which are connected with an xor. Order of the bit: bank1, bank2, ..., row1, row2, ...
+    - "bank_bits": Number of the addres bits which are connected to a bank bit
+    - "row_bits": Number of the addres bits which are connected to a row bit
+
+  ```json
+  {
+    "Config": {
+      "numberOfBankBits": 3,
+      "numberOfRowBits": 14,
+      "numberOfColumnBits": 10,
+      "numberOfByteBits": 3,
+      "numberOfBLBits": 3
+    },
+    "Name": "trace_name",
+    "Solutions": [
+      {
+        "XOR": [
+        ],
+        "Banks Rows": [
+          {
+            "bank_bits": [
+              27,
+              28,
+              29
+            ],
+            "rows": {
+              "row_bits": [
+                13,
+                14,
+                15,
+                16,
+                17,
+                18,
+                19,
+                20,
+                21,
+                22,
+                23,
+                24,
+                25,
+                26
+              ],
+              "costs": 477468
+            },
+            "costs": 477468
+          }
+        ]
+      }
+    ]
+  }
+```
+
 - **Memory Configuration**
 
   The content of [fifo.xml](DRAMSys/library/resources/configs/memconfigs/fifo.xml) is