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Created a section for address decoding with json files.

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Johannes Feldmann
2018-03-30 16:47:43 +02:00
parent 454e77eba8
commit 9ed217c01d
1 changed files with 96 additions and 27 deletions
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README.md
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@@ -23,7 +23,7 @@ Configure git on your machine. Some basic configurations follow. Replace
$ git config --global user.name "FirstName OtherNames LastName"
$ git config --global user.email rhrkuser@rhrk.uni-kl.de
$ git config --global credential.helper ’cache --timeout=3600’
$ git config --global color.ui auto
$ git config --global color.ui auto
```
Login using your **git.rhrk** account. Fork the repository by clicking in
@@ -239,17 +239,17 @@ ln -s lib/ lib-macosx64
$ brew install python3
```
Python3 (via homebrew) will be installed in
Python3 (via homebrew) will be installed in
```
/usr/local/Cellar/python3/3.5.2_2/Frameworks/Python.framework
```
or you can install manually using official package provided in [link](https://www.python.org/downloads/)
**Note:** Official Python Package will be installed in
**Note:** Official Python Package will be installed in
```
/Library/Frameworks/Python.framework
```
```
- Install the QtCreator using offical setup file from [link](https://www.qt.io/download-open-source/#section-2)
@@ -292,7 +292,7 @@ export LIBQWT_HEADERS=/opt/qwt-6.1.4/lib/qwt.framework/Headers
- For the trace analyzer the file:
```
/opt/local/Library/Frameworks/Python.framework/Versions/3.5/include/python3.4m/pyport.h
/opt/local/Library/Frameworks/Python.framework/Versions/3.5/include/python3.4m/pyport.h
```
has to be changed like [this](https://trac.macports.org/attachment/ticket/44288/issue10910-workaround.txt)
@@ -431,13 +431,13 @@ Below, the sub-configurations are listed and explained.
- "1": enables thermal simulation
- "0": static temperature during simulation
- *SimulationProgressBar* (boolean)
- "1": enables the simulation progress bar
- "1": enables the simulation progress bar
- "0": disables the simulation progress bar
- *NumberOfDevicesOnDIMM* (unsigned int)
- Number of devices on dual inline memory module
- *CheckTLM2Protocol* (boolean)
- "1": enables the TLM 2.0 Protocol Checking
- "0": disables the TLM 2.0 Protocol Checking
- "1": enables the TLM 2.0 Protocol Checking
- "0": disables the TLM 2.0 Protocol Checking
- *ECCControllerMode* (string)
- "Disabled": No ECC Controller is used
- "Hamming": Enables an ECC Controller with classic SECDED implementation using Hamming Code
@@ -503,6 +503,10 @@ Below, the sub-configurations are listed and explained.
- **Address Mapping**
There are currently two different file formats to describe the address mapping. This software automatically chooses the correct interpreter using the file extension as selection criterion. So please make sure that all files have the correct extension.
- **XML file format**
XML files describe the address mapping to be used in the simulation.
Example for 1GB x64 DIMM with: 8 x 1 Gbit x8 Devices (Micron MT41J128M8) with Page Size: 1KB
@@ -510,23 +514,23 @@ Below, the sub-configurations are listed and explained.
[am_ddr3_8x1Gbx8_dimm_p1KB_brc.xml](DRAMSys/library/resources/configs/amconfigs/am_ddr3_8x1Gbx8_dimm_p1KB_brc.xml)
``` xml
<!--
<!--
DDR3 Example:
1GB x64 DIMM with: 8 * 1 Gb x8 Devices (e.g. Micron MT41J128M8) with Page Size: 1KB
Device Characteristics:
Rows: 16 K [13:0] -> 14 bit
Bank: 8 [2:0] -> 3 bit
Cols: 1 K [9:0] -> 10 bit
Due to the DIMM we have a Byte Offset Y
2 2 2 | 2 2 2 2 2 2 2 1 1 1 1 1 1 1 | 1 1 1
2 2 2 | 2 2 2 2 2 2 2 1 1 1 1 1 1 1 | 1 1 1
9 8 7 | 6 5 4 3 2 1 0 9 8 7 6 5 4 3 | 2 1 0 9 8 7 6 5 4 3 | 2 1 0
B B B | R R R R R R R R R R R R R R | C C C C C C C C C C | Y Y Y
-->
<addressmapping>
<channel from="128" to="128" /> <!-- only one channel -->
<bank from="27" to="29" />
@@ -537,18 +541,18 @@ Below, the sub-configurations are listed and explained.
```
Some more examples with graphical representation follow:
[am_wideio.xml](DRAMSys/library/resources/configs/amconfigs/am_wideio.xml)
``` xml
<!-- Row Bank Column -->
<addressmapping>
<channel from="27" to="28" />
<row from="14" to="26" />
<bank from="11" to="13" />
<column from="4" to="10" />
<bytes from="0" to="3" />
<bytes from="0" to="3" />
</addressmapping>
```
@@ -568,6 +572,71 @@ Below, the sub-configurations are listed and explained.
![Address Mapping Sample 2](DRAMSys/docs/images/am_wideio_brc.png)
- **JSON file format**
This file format is generated by ConGen. It does not have an unambiguous assignment of the address lines.
The format delivers more information than needed for an address mapping.
Unused data:
- Block "Config": Gives you information about the ConGen configuration
- Key "Name": Name of the trace file which was used by ConGen
- All items of the array "Solutions" but the first one: Alternative solution with same result.
- Key "costs": Number of row misses which this configuration produces while playing the trace.
Used data:
- First item of array "Solution":
- "XOR": Array of row and bank bits which are connected with an xor. Order of the bit: bank1, bank2, ..., row1, row2, ...
- "bank_bits": Number of the addres bits which are connected to a bank bit
- "row_bits": Number of the addres bits which are connected to a row bit
```json
{
"Config": {
"numberOfBankBits": 3,
"numberOfRowBits": 14,
"numberOfColumnBits": 10,
"numberOfByteBits": 3,
"numberOfBLBits": 3
},
"Name": "trace_name",
"Solutions": [
{
"XOR": [
],
"Banks Rows": [
{
"bank_bits": [
27,
28,
29
],
"rows": {
"row_bits": [
13,
14,
15,
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26
],
"costs": 477468
},
"costs": 477468
}
]
}
]
}
```
- **Memory Configuration**
The content of [fifo.xml](DRAMSys/library/resources/configs/memconfigs/fifo.xml) is
@@ -676,7 +745,7 @@ A description of the content each directory follows.
- **scripts**: useful tools.
- **simulations**: main configuration files.
- **traces**: pre-recorded trace files that may be used as stimuli in simulations.
#### Log Collector Script
Users can profit of running multiple simulations automatically with
@@ -741,28 +810,28 @@ For more information check the documentation in [DRAMSylva folder](DRAMSys/libra
the socket id (thread) of a payload. It is added in the Arbiter and is sent
to the Controller.
![Payload Extension information](DRAMSys/docs/images/PayloadExtension.png)
- **Transaction object with Memory Manager**
The TracePlayer allocates the memory for the transaction object by calling allocatePayload method.
The acquire method is called before passing the transaction object in TracePlayer, Arbiter and Controller.
The release method is called after each component is done with the transaction object. After the final call of release method, the free method of the memory manager is called to free the transaction object.
![Payload Memory Manager](DRAMSys/docs/images/PayloadMemoryManager.png)
- **Architecture of the backend TLM model**
The below figure shows our custom TLM protocol between the Controller and the Dram. A new transaction enters the Controller with the BEGIN_REQ phase is stored in frontendPEQ. The callback function of the frontendPEQ is called and send the payload to the Scheduler.
The Scheduler checks the address of payload and the current state to determine proper command (Active, Precharge, Read or Write). Then the ControllerCore sends the payload with the corresponding phase (BEGIN_ACT, BEGIN_PRE, BEGIN_RD or BEGIN_WR) to the Dram by calling nb_transport_fw method.
The Dram receives the transaction then send back to the Controller by calling nb_transport_bw with appropriate END phase (END_ACT, END_PRE, END_RD or END_WR).
The Dram receives the transaction then send back to the Controller by calling nb_transport_bw with appropriate END phase (END_ACT, END_PRE, END_RD or END_WR).
![Architecture backend TLM](DRAMSys/docs/images/TransactionPhase.png)
### DRAMSys Thermal Simulation
### DRAMSys Thermal Simulation
The thermal simulation is performed by a **3D-ICE** [8] server accessed
through the network. Therefore users interested in thermal simulation during