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Code formatting.

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This commit is contained in:
Lukas Steiner
2021-06-15 18:48:57 +02:00
parent 1cf97f7187
commit 9b135948e6
18 changed files with 81 additions and 84 deletions
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2
DRAMSys/library/src/common/TlmRecorder.cpp
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@@ -112,7 +112,7 @@ void TlmRecorder::recordBandwidth(double timeInSeconds, double averageBandwidth)
}
void TlmRecorder::recordPhase(tlm_generic_payload &trans,
tlm_phase phase, const sc_time &time)
const tlm_phase &phase, const sc_time &time)
{
if (currentTransactionsInSystem.find(&trans) == currentTransactionsInSystem.end())
introduceTransactionSystem(trans);

3
DRAMSys/library/src/common/TlmRecorder.h
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@@ -72,8 +72,7 @@ public:
traces = _traces;
}
void recordPhase(tlm::tlm_generic_payload &trans, tlm::tlm_phase phase,
const sc_time &time);
void recordPhase(tlm::tlm_generic_payload &trans, const tlm::tlm_phase &phase, const sc_time &time);
void recordPower(double timeInSeconds, double averagePower);
void recordBufferDepth(double timeInSeconds, const std::vector<double> &averageBufferDepth);
void recordBandwidth(double timeInSeconds, double averageBandwidth);

2
DRAMSys/library/src/common/utils.cpp
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@@ -65,7 +65,7 @@ sc_time TimeInterval::getLength() const
return start - end;
}
std::string getPhaseName(tlm_phase phase)
std::string getPhaseName(const tlm_phase &phase)
{
std::ostringstream oss;
oss << phase;

2
DRAMSys/library/src/common/utils.h
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@@ -65,7 +65,7 @@ public:
constexpr const char headline[] =
"===========================================================================";
std::string getPhaseName(tlm::tlm_phase phase);
std::string getPhaseName(const tlm::tlm_phase &phase);
nlohmann::json parseJSON(const std::string &path);
bool parseBool(nlohmann::json &obj, const std::string &name);

8
DRAMSys/library/src/controller/Controller.cpp
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@@ -158,8 +158,8 @@ Controller::Controller(const sc_module_name &name) :
for (unsigned rankID = 0; rankID < memSpec->numberOfRanks; rankID++)
{
bankMachinesOnRank.push_back(std::vector<BankMachine *>(bankMachines.begin() + rankID * memSpec->banksPerRank,
bankMachines.begin() + (rankID + 1) * memSpec->banksPerRank));
bankMachinesOnRank.emplace_back(bankMachines.begin() + rankID * memSpec->banksPerRank,
bankMachines.begin() + (rankID + 1) * memSpec->banksPerRank);
}
// instantiate power-down managers (one per rank)
@@ -289,9 +289,7 @@ void Controller::controllerMethod()
if (command != Command::NOP) // can happen with FIFO strict
{
Rank rank = DramExtension::getRank(payload);
BankGroup bankgroup = DramExtension::getBankGroup(payload);
Bank bank = DramExtension::getBank(payload);
unsigned burstLength = DramExtension::getBurstLength(payload);
if (command.isRankCommand())
{
@@ -396,7 +394,7 @@ unsigned int Controller::transport_dbg(tlm_generic_payload &trans)
return iSocket->transport_dbg(trans);
}
void Controller::manageRequests(sc_time delay)
void Controller::manageRequests(const sc_time &delay)
{
if (transToAcquire.payload != nullptr && transToAcquire.time <= sc_time_stamp())
{

8
DRAMSys/library/src/controller/Controller.h
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@@ -65,9 +65,9 @@ public:
~Controller() override;
protected:
tlm::tlm_sync_enum nb_transport_fw(tlm::tlm_generic_payload &, tlm::tlm_phase &, sc_time &) override;
tlm::tlm_sync_enum nb_transport_bw(tlm::tlm_generic_payload &, tlm::tlm_phase &, sc_time &) override;
unsigned int transport_dbg(tlm::tlm_generic_payload &) override;
tlm::tlm_sync_enum nb_transport_fw(tlm::tlm_generic_payload &trans, tlm::tlm_phase &phase, sc_time &delay) override;
tlm::tlm_sync_enum nb_transport_bw(tlm::tlm_generic_payload &trans, tlm::tlm_phase &phase, sc_time &delay) override;
unsigned int transport_dbg(tlm::tlm_generic_payload &trans) override;
virtual void sendToFrontend(tlm::tlm_generic_payload *, tlm::tlm_phase, sc_time);
virtual void sendToDram(Command, tlm::tlm_generic_payload *, sc_time);
@@ -102,7 +102,7 @@ private:
} transToAcquire, transToRelease;
void manageResponses();
void manageRequests(sc_time);
void manageRequests(const sc_time &delay);
sc_event beginReqEvent, endRespEvent, controllerEvent, dataResponseEvent;
};

2
DRAMSys/library/src/controller/ControllerRecordable.cpp
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@@ -84,7 +84,7 @@ void ControllerRecordable::sendToDram(Command command, tlm_generic_payload *payl
iSocket->nb_transport_fw(*payload, phase, delay);
}
void ControllerRecordable::recordPhase(tlm_generic_payload &trans, tlm_phase phase, sc_time delay)
void ControllerRecordable::recordPhase(tlm_generic_payload &trans, const tlm_phase &phase, const sc_time &delay)
{
sc_time recTime = delay + sc_time_stamp();

2
DRAMSys/library/src/controller/ControllerRecordable.h
View File

@@ -56,7 +56,7 @@ protected:
void controllerMethod() override;
private:
void recordPhase(tlm::tlm_generic_payload &trans, tlm::tlm_phase phase, sc_time delay);
void recordPhase(tlm::tlm_generic_payload &trans, const tlm::tlm_phase &phase, const sc_time &delay);
TlmRecorder *tlmRecorder;
sc_event windowEvent;

50
DRAMSys/library/src/simulation/AddressDecoder.cpp
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@@ -44,7 +44,7 @@
using json = nlohmann::json;
unsigned int AddressDecoder::getUnsignedAttrFromJson(nlohmann::json obj, std::string strName)
unsigned int AddressDecoder::getUnsignedAttrFromJson(const nlohmann::json &obj, const std::string &strName)
{
if (!obj[strName].empty())
{
@@ -65,12 +65,12 @@ unsigned int AddressDecoder::getUnsignedAttrFromJson(nlohmann::json obj, std::st
}
}
std::vector<unsigned> AddressDecoder::getAttrToVectorFromJson(nlohmann::json obj, std::string strName)
std::vector<unsigned> AddressDecoder::getAttrToVectorFromJson(const nlohmann::json &obj, const std::string &strName)
{
std::vector<unsigned> vParameter;
if (!obj[strName].empty())
{
for (auto it : obj[strName].items())
for (const auto& it : obj[strName].items())
{
auto valor = it.value();
if (valor.is_number_unsigned())
@@ -82,7 +82,7 @@ std::vector<unsigned> AddressDecoder::getAttrToVectorFromJson(nlohmann::json obj
return vParameter;
}
AddressDecoder::AddressDecoder(std::string pathToAddressMapping)
AddressDecoder::AddressDecoder(const std::string &pathToAddressMapping)
{
json addrFile = parseJSON(pathToAddressMapping);
json mapping;
@@ -93,7 +93,7 @@ AddressDecoder::AddressDecoder(std::string pathToAddressMapping)
if (!addrFile["CONGEN"]["SOLUTION"].empty())
{
bool foundID0 = false;
for (auto it : addrFile["CONGEN"]["SOLUTION"].items())
for (const auto& it : addrFile["CONGEN"]["SOLUTION"].items())
{
if (getUnsignedAttrFromJson(it.value(), "ID") == 0)
{
@@ -108,12 +108,12 @@ AddressDecoder::AddressDecoder(std::string pathToAddressMapping)
else
mapping = addrFile["CONGEN"];
for (auto xorItem : mapping["XOR"].items())
for (const auto& xorItem : mapping["XOR"].items())
{
auto value = xorItem.value();
if (!value.empty())
vXor.push_back(std::pair<unsigned, unsigned>(getUnsignedAttrFromJson(value, "FIRST"),
getUnsignedAttrFromJson(value, "SECOND")));
vXor.emplace_back(getUnsignedAttrFromJson(value, "FIRST"),
getUnsignedAttrFromJson(value, "SECOND"));
}
vChannelBits = getAttrToVectorFromJson(mapping,"CHANNEL_BIT");
@@ -124,28 +124,28 @@ AddressDecoder::AddressDecoder(std::string pathToAddressMapping)
vColumnBits = getAttrToVectorFromJson(mapping,"COLUMN_BIT");
vByteBits = getAttrToVectorFromJson(mapping,"BYTE_BIT");
unsigned channels = static_cast<unsigned>(pow(2.0, vChannelBits.size()) + 0.5);
unsigned ranks = static_cast<unsigned>(pow(2.0, vRankBits.size()) + 0.5);
unsigned bankgroups = static_cast<unsigned>(pow(2.0, vBankGroupBits.size()) + 0.5);
unsigned banks = static_cast<unsigned>(pow(2.0, vBankBits.size()) + 0.5);
unsigned rows = static_cast<unsigned>(pow(2.0, vRowBits.size()) + 0.5);
unsigned columns = static_cast<unsigned>(pow(2.0, vColumnBits.size()) + 0.5);
unsigned bytes = static_cast<unsigned>(pow(2.0, vByteBits.size()) + 0.5);
unsigned channels = std::lround(std::pow(2.0, vChannelBits.size()));
unsigned ranks = std::lround(std::pow(2.0, vRankBits.size()));
unsigned bankGroups = std::lround(std::pow(2.0, vBankGroupBits.size()));
unsigned banks = std::lround(std::pow(2.0, vBankBits.size()));
unsigned rows = std::lround(std::pow(2.0, vRowBits.size()));
unsigned columns = std::lround(std::pow(2.0, vColumnBits.size()));
unsigned bytes = std::lround(std::pow(2.0, vByteBits.size()));
maximumAddress = static_cast<uint64_t>(bytes) * columns * rows * banks * bankgroups * ranks * channels - 1;
maximumAddress = static_cast<uint64_t>(bytes) * columns * rows * banks * bankGroups * ranks * channels - 1;
banksPerGroup = banks;
banks = banksPerGroup * bankgroups * ranks;
banks = banksPerGroup * bankGroups * ranks;
bankgroupsPerRank = bankgroups;
bankgroups = bankgroupsPerRank * ranks;
bankgroupsPerRank = bankGroups;
bankGroups = bankgroupsPerRank * ranks;
Configuration &config = Configuration::getInstance();
const MemSpec *memSpec = config.memSpec;
if (memSpec->numberOfChannels != channels || memSpec->numberOfRanks != ranks
|| memSpec->numberOfBankGroups != bankgroups || memSpec->numberOfBanks != banks
|| memSpec->numberOfRows != rows || memSpec->numberOfColumns != columns
|| memSpec->numberOfBankGroups != bankGroups || memSpec->numberOfBanks != banks
|| memSpec->numberOfRows != rows || memSpec->numberOfColumns != columns
|| memSpec->numberOfDevicesOnDIMM * memSpec->bitWidth != bytes * 8)
SC_REPORT_FATAL("AddressDecoder", "Memspec and address mapping do not match");
}
@@ -158,12 +158,12 @@ DecodedAddress AddressDecoder::decodeAddress(uint64_t encAddr)
// Apply XOR
// For each used xor:
// Get the first bit and second bit. Apply a bitwise xor operator and save it back to the first bit.
for (auto it = vXor.begin(); it != vXor.end(); it++)
for (auto &it : vXor)
{
uint64_t xoredBit;
xoredBit = (((encAddr >> it->first) & UINT64_C(1)) ^ ((encAddr >> it->second) & UINT64_C(1)));
encAddr &= ~(UINT64_C(1) << it->first);
encAddr |= xoredBit << it->first;
xoredBit = (((encAddr >> it.first) & UINT64_C(1)) ^ ((encAddr >> it.second) & UINT64_C(1)));
encAddr &= ~(UINT64_C(1) << it.first);
encAddr |= xoredBit << it.first;
}
DecodedAddress decAddr;

6
DRAMSys/library/src/simulation/AddressDecoder.h
View File

@@ -70,13 +70,13 @@ struct DecodedAddress
class AddressDecoder
{
public:
AddressDecoder(std::string);
explicit AddressDecoder(const std::string &pathToAddressMapping);
DecodedAddress decodeAddress(uint64_t addr);
void print();
private:
std::vector<unsigned> getAttrToVectorFromJson(nlohmann::json obj, std::string strName);
unsigned int getUnsignedAttrFromJson(nlohmann::json obj, std::string strName);
static std::vector<unsigned> getAttrToVectorFromJson(const nlohmann::json &obj, const std::string &strName);
static unsigned int getUnsignedAttrFromJson(const nlohmann::json &obj, const std::string &strName);
unsigned banksPerGroup;
unsigned bankgroupsPerRank;

8
DRAMSys/library/src/simulation/Arbiter.cpp
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@@ -42,7 +42,7 @@
using namespace tlm;
Arbiter::Arbiter(sc_module_name name, std::string pathToAddressMapping) :
Arbiter::Arbiter(const sc_module_name &name, const std::string &pathToAddressMapping) :
sc_module(name), payloadEventQueue(this, &Arbiter::peqCallback),
tCK(Configuration::getInstance().memSpec->tCK),
arbitrationDelayFw(Configuration::getInstance().arbitrationDelayFw),
@@ -58,14 +58,14 @@ Arbiter::Arbiter(sc_module_name name, std::string pathToAddressMapping) :
bytesPerBeat = Configuration::getInstance().memSpec->dataBusWidth / 8;
}
ArbiterSimple::ArbiterSimple(sc_module_name name, std::string pathToAddressMapping) :
ArbiterSimple::ArbiterSimple(const sc_module_name &name, const std::string &pathToAddressMapping) :
Arbiter(name, pathToAddressMapping) {}
ArbiterFifo::ArbiterFifo(sc_module_name name, std::string pathToAddressMapping) :
ArbiterFifo::ArbiterFifo(const sc_module_name &name, const std::string &pathToAddressMapping) :
Arbiter(name, pathToAddressMapping),
maxActiveTransactions(Configuration::getInstance().maxActiveTransactions) {}
ArbiterReorder::ArbiterReorder(sc_module_name name, std::string pathToAddressMapping) :
ArbiterReorder::ArbiterReorder(const sc_module_name &name, const std::string &pathToAddressMapping) :
Arbiter(name, pathToAddressMapping),
maxActiveTransactions(Configuration::getInstance().maxActiveTransactions) {}

24
DRAMSys/library/src/simulation/Arbiter.h
View File

@@ -57,13 +57,13 @@ public:
tlm_utils::multi_passthrough_initiator_socket<Arbiter> iSocket;
tlm_utils::multi_passthrough_target_socket<Arbiter> tSocket;
virtual ~Arbiter() override;
~Arbiter() override;
protected:
Arbiter(sc_module_name, std::string);
Arbiter(const sc_module_name &name, const std::string &pathToAddressMapping);
SC_HAS_PROCESS(Arbiter);
virtual void end_of_elaboration() override;
void end_of_elaboration() override;
AddressDecoder *addressDecoder;
@@ -94,12 +94,12 @@ protected:
class ArbiterSimple final : public Arbiter
{
public:
ArbiterSimple(sc_module_name, std::string);
ArbiterSimple(const sc_module_name &name, const std::string &pathToAddressMapping);
SC_HAS_PROCESS(ArbiterSimple);
private:
virtual void end_of_elaboration() override;
virtual void peqCallback(tlm::tlm_generic_payload &payload, const tlm::tlm_phase &phase) override;
void end_of_elaboration() override;
void peqCallback(tlm::tlm_generic_payload &payload, const tlm::tlm_phase &phase) override;
std::vector<std::queue<tlm::tlm_generic_payload *>> pendingResponses;
};
@@ -107,12 +107,12 @@ private:
class ArbiterFifo final : public Arbiter
{
public:
ArbiterFifo(sc_module_name, std::string);
ArbiterFifo(const sc_module_name &name, const std::string &pathToAddressMapping);
SC_HAS_PROCESS(ArbiterFifo);
private:
virtual void end_of_elaboration() override;
virtual void peqCallback(tlm::tlm_generic_payload &payload, const tlm::tlm_phase &phase) override;
void end_of_elaboration() override;
void peqCallback(tlm::tlm_generic_payload &payload, const tlm::tlm_phase &phase) override;
std::vector<unsigned int> activeTransactions;
const unsigned maxActiveTransactions;
@@ -127,12 +127,12 @@ private:
class ArbiterReorder final : public Arbiter
{
public:
ArbiterReorder(sc_module_name, std::string);
ArbiterReorder(const sc_module_name &name, const std::string &pathToAddressMapping);
SC_HAS_PROCESS(ArbiterReorder);
private:
virtual void end_of_elaboration() override;
virtual void peqCallback(tlm::tlm_generic_payload &payload, const tlm::tlm_phase &phase) override;
void end_of_elaboration() override;
void peqCallback(tlm::tlm_generic_payload &payload, const tlm::tlm_phase &phase) override;
std::vector<unsigned int> activeTransactions;
const unsigned maxActiveTransactions;

16
DRAMSys/library/src/simulation/DRAMSys.cpp
View File

@@ -37,7 +37,7 @@
* Lukas Steiner
*/
#include <stdlib.h>
#include <cstdlib>
#include <iostream>
#include <fstream>
#include <vector>
@@ -62,15 +62,15 @@
#include "dram/DramSTTMRAM.h"
#include "../controller/Controller.h"
DRAMSys::DRAMSys(sc_module_name name,
std::string simulationToRun,
std::string pathToResources)
DRAMSys::DRAMSys(const sc_module_name &name,
const std::string &simulationToRun,
const std::string &pathToResources)
: DRAMSys(name, simulationToRun, pathToResources, true)
{}
DRAMSys::DRAMSys(sc_module_name name,
std::string simulationToRun,
std::string pathToResources,
DRAMSys::DRAMSys(const sc_module_name &name,
const std::string &simulationToRun,
const std::string &pathToResources,
bool initAndBind)
: sc_module(name), tSocket("DRAMSys_tSocket")
{
@@ -279,7 +279,7 @@ void DRAMSys::bindSockets()
}
}
void DRAMSys::report(std::string message)
void DRAMSys::report(const std::string &message)
{
PRINTDEBUGMESSAGE(name(), message);
std::cout << message << std::endl;

16
DRAMSys/library/src/simulation/DRAMSys.h
View File

@@ -61,16 +61,16 @@ public:
playersTlmCheckers;
SC_HAS_PROCESS(DRAMSys);
DRAMSys(sc_module_name name,
std::string simulationToRun,
std::string pathToResources);
DRAMSys(const sc_module_name &name,
const std::string &simulationToRun,
const std::string &pathToResources);
~DRAMSys() override;
protected:
DRAMSys(sc_module_name name,
std::string simulationToRun,
std::string pathToResources,
DRAMSys(const sc_module_name &name,
const std::string &simulationToRun,
const std::string &pathToResources,
bool initAndBind);
//TLM 2.0 Protocol Checkers
@@ -92,7 +92,7 @@ protected:
// DRAM units
std::vector<Dram *> drams;
void report(std::string message);
void report(const std::string &message);
private:
static void logo();
@@ -101,7 +101,7 @@ private:
const std::string &amconfig);
void bindSockets();
void setupDebugManager(const std::string &traceName);
static void setupDebugManager(const std::string &traceName);
};
#endif // DRAMSYS_H

6
DRAMSys/library/src/simulation/DRAMSysRecordable.cpp
View File

@@ -51,9 +51,9 @@
#include "../simulation/TemperatureController.h"
#include "../error/ecchamming.h"
DRAMSysRecordable::DRAMSysRecordable(sc_module_name name,
std::string simulationToRun,
std::string pathToResources)
DRAMSysRecordable::DRAMSysRecordable(const sc_module_name &name,
const std::string &simulationToRun,
const std::string &pathToResources)
: DRAMSys(name, simulationToRun, pathToResources, false)
{
// Read Configuration Setup:

6
DRAMSys/library/src/simulation/DRAMSysRecordable.h
View File

@@ -42,9 +42,9 @@
class DRAMSysRecordable : public DRAMSys
{
public:
DRAMSysRecordable(sc_module_name name,
std::string simulationToRun,
std::string pathToResources);
DRAMSysRecordable(const sc_module_name &name,
const std::string &simulationToRun,
const std::string &pathToResources);
~DRAMSysRecordable() override;

2
DRAMSys/library/src/simulation/dram/DramRecordable.cpp
View File

@@ -82,7 +82,7 @@ tlm_sync_enum DramRecordable<BaseDram>::nb_transport_fw(tlm_generic_payload &pay
}
template<class BaseDram>
void DramRecordable<BaseDram>::recordPhase(tlm_generic_payload &trans, tlm_phase phase, sc_time delay)
void DramRecordable<BaseDram>::recordPhase(tlm_generic_payload &trans, const tlm_phase &phase, const sc_time &delay)
{
sc_time recTime = sc_time_stamp() + delay;

2
DRAMSys/library/src/simulation/dram/DramRecordable.h
View File

@@ -55,7 +55,7 @@ private:
tlm::tlm_sync_enum nb_transport_fw(tlm::tlm_generic_payload &payload,
tlm::tlm_phase &phase, sc_time &delay) override;
void recordPhase(tlm::tlm_generic_payload &trans, tlm::tlm_phase phase, sc_time delay);
void recordPhase(tlm::tlm_generic_payload &trans, const tlm::tlm_phase &phase, const sc_time &delay);
TlmRecorder *tlmRecorder;