derek/DRAMSys
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

new error model skeleton integrated

Browse Source
This commit is contained in:
Matthias Jung
2015-07-29 22:57:19 +02:00
parent 4767ae2267
commit 979f4a0db4
4 changed files with 214 additions and 22 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
DRAMSys/dramSys/dramSys.pro
View File

@@ -69,7 +69,8 @@ SOURCES += \
src/controller/scheduler/IScheduler.cpp \
src/controller/scheduler/FifoStrict.cpp \
src/error/nest_map.cpp \
src/error/flip_memory.cpp
src/error/flip_memory.cpp \
src/error/errormodel.cpp
HEADERS += \
src/common/third_party/tinyxml2/tinyxml2.h \
@@ -128,5 +129,6 @@ HEADERS += \
src/controller/IController.h \
src/controller/core/configuration/ConfigurationLoader.h \
src/error/nest_map.h \
src/error/flip_memory.h
src/error/flip_memory.h \
src/error/errormodel.h

134
DRAMSys/dramSys/src/error/errormodel.cpp
View File

@@ -1,5 +1,139 @@
/*
* Copyright (c) 2015, University of Kaiserslautern
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
* OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors:
* Matthias Jung
*/
#include "errormodel.h"
errorModel::errorModel()
{
// Get Configuration parameters:
busWidth = Configuration::getInstance().Buswidth;
burstLenght = Configuration::getInstance().memSpec.BurstLength;
numberOfColumns = Configuration::getInstance().memSpec.NumberOfColumns;
bytesPerColumn = xmlAddressDecoder::getInstance().amount["bytes"];
}
errorModel::~errorModel()
{
// Remove all data from the dataMap:
for (std::map<DecodedAddress, unsigned char*>::iterator it = dataMap.begin(); it != dataMap.end(); ++it )
{
delete it->second;
}
// Delete all elements from the dataMap:
dataMap.clear();
}
void errorModel::store(tlm::tlm_generic_payload &trans)
{
// Get the key for the dataMap from the transaction's address:
DecodedAddress key = xmlAddressDecoder::getInstance().decodeAddress(trans.get_address());
// Check if the provided data length is correct:
assert((bytesPerColumn * burstLenght) == trans.get_data_length());
// Handle the DRAM burst,
for (unsigned int i = 0; i < trans.get_data_length(); i+=bytesPerColumn)
{
unsigned char * data;
// Check if address is not already stored:
if(dataMap.count(key) == 0)
{
// Generate a new data entry
data = new unsigned char[bytesPerColumn];
}
else // In case the address was stored before:
{
data = dataMap[key];
}
// Copy the data from the transaction to the data pointer
memcpy(data, trans.get_data_ptr()+i, bytesPerColumn);
// Save part of the burst in the dataMap
dataMap.insert(std::pair<DecodedAddress, unsigned char*>(key,data));
// The next burst element is handled, therfore the column address must be increased
key.column++;
// Check that there is no column overfow:
assert(key.column <= numberOfColumns);
// Reset flipped weak cells in this area, since they are rewritten now
// TODO
}
//trans.set_response_status(TLM_OK_RESPONSE);
}
void errorModel::load(tlm::tlm_generic_payload &trans)
{
// Get the key for the dataMap from the transaction's address:
DecodedAddress key = xmlAddressDecoder::getInstance().decodeAddress(trans.get_address());
// Check if the provided data length is correct:
assert((bytesPerColumn * burstLenght) == trans.get_data_length());
// Handle the DRAM burst:
for (unsigned int i = 0; i < trans.get_data_length(); i+=bytesPerColumn)
{
// Check if address is not stored:
if(dataMap.count(key) == 0)
{
SC_REPORT_FATAL("errormodel","Reading from an empty memory location");
}
// Copy the data from the transaction to the data pointer
memcpy(trans.get_data_ptr()+i, dataMap[key], bytesPerColumn);
// The next burst element is handled, therfore the column address must be increased
key.column++;
// Check that there is no column overfow:
assert(key.column <= numberOfColumns);
}
}
void errorModel::refresh(unsigned int row)
{
// A refresh is internally composed of PRE and ACT that are executed
// on all banks, therefore we call the activate method:
activate(row);
}
void errorModel::activate(unsigned int row)
{
// TODO
}

66
DRAMSys/dramSys/src/error/errormodel.h
View File

@@ -1,10 +1,74 @@
/*
* Copyright (c) 2015, University of Kaiserslautern
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
* OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors:
* Matthias Jung
*/
#ifndef ERRORMODEL_H
#define ERRORMODEL_H
#include "../controller/core/configuration/Configuration.h"
#include "../common/xmlAddressdecoder.h"
#include <map>
class errorModel
{
public:
public:
errorModel();
~errorModel();
// Access Methods:
void store(tlm::tlm_generic_payload &trans);
void load(tlm::tlm_generic_payload &trans);
void refresh(unsigned int row);
void activate(unsigned int row);
// Configuration Parameters:
unsigned int busWidth;
unsigned int burstLenght;
unsigned int numberOfColumns;
unsigned int bytesPerColumn;
struct DecodedAddressComparer
{
bool operator()( const DecodedAddress& first , const DecodedAddress& second) const
{
sc_dt::uint64 addrFirst = xmlAddressDecoder::getInstance().encodeAddress(first);
sc_dt::uint64 addrSecond = xmlAddressDecoder::getInstance().encodeAddress(second);
return addrFirst < addrSecond;
}
};
private:
std::map<DecodedAddress, unsigned char *, DecodedAddressComparer> dataMap;
};
#endif // ERRORMODEL_H

30
DRAMSys/dramSys/src/simulation/Dram.h
View File

@@ -51,7 +51,7 @@
#include "../common/Utils.h"
#include "../common/TlmRecorder.h"
#include "../common/third_party/DRAMPower/src/libdrampower/LibDRAMPower.h"
#include "../error/flip_memory.h"
#include "../error/errormodel.h"
using namespace std;
using namespace tlm;
@@ -69,7 +69,7 @@ struct Dram : sc_module
// Error Model related:
ErrorStorageMode ErrorStoreMode = Configuration::getInstance().ErrorStoreMode;
flip_memory * fmemory;
errorModel ememory;
// Data Storage:
map< unsigned long int, unsigned char[BUSWIDTH/2] > memory;
@@ -165,11 +165,6 @@ struct Dram : sc_module
}
printDebugMessage(string("ErrorStorageMode: ") + EnumToString(ErrorStoreMode));
if(ErrorStoreMode == ErrorStorageMode::ErrorModel)
{
fmemory = new flip_memory[Configuration::getInstance().memSpec.NumberOfBanks];
}
}
~Dram()
@@ -183,10 +178,7 @@ struct Dram : sc_module
}
if(ErrorStoreMode == ErrorStorageMode::ErrorModel)
{
for(int b = 0; b < 8; b++)
{
cout << "BIT_ERRORS Bank: " <<b <<"="<< fmemory[b].BIT_ERR << endl;
}
//cout << "BIT_ERRORS Bank: " <<b <<"="<< fmemory[b].BIT_ERR << endl;
}
// TODO Aufrauemen!
//delete fmemory; // TODO Testen!
@@ -223,7 +215,7 @@ struct Dram : sc_module
if (ErrorStoreMode == ErrorStorageMode::ErrorModel)
{
fmemory[bank].refresh(row);
ememory.activate(row);
}
}
else if (phase == BEGIN_WR)
@@ -241,7 +233,7 @@ struct Dram : sc_module
}
else // == 2 Use Storage with Error Model
{
fmemory[bank].store(payload);
ememory.store(payload);
}
sendToController(payload, END_WR, delay + getExecutionTime(Command::Write, payload));
}
@@ -263,7 +255,7 @@ struct Dram : sc_module
}
else if(ErrorStoreMode == ErrorStorageMode::ErrorModel)// use ErrorStorageMode with errormodel
{
fmemory[bank].load(payload);
ememory.load(payload);
}
sendToController(payload, END_RD, delay + getExecutionTime(Command::Read, payload));
@@ -283,7 +275,7 @@ struct Dram : sc_module
}
else // == 2 Use Storage with Error Model
{
fmemory[bank].store(payload);
ememory.store(payload);
}
sendToController(payload, END_WRA, delay + getExecutionTime(Command::WriteA, payload));
}
@@ -305,7 +297,7 @@ struct Dram : sc_module
}
else if(ErrorStoreMode == ErrorStorageMode::ErrorModel)// use ErrorStorageMode with errormodel
{
fmemory[bank].load(payload);
ememory.load(payload);
}
sendToController(payload, END_RDA, delay + getExecutionTime(Command::ReadA, payload));
@@ -318,7 +310,7 @@ struct Dram : sc_module
if (ErrorStoreMode == ErrorStorageMode::ErrorModel)
{
fmemory[bank].refresh(row);
ememory.refresh(row);
}
}
@@ -407,7 +399,7 @@ struct Dram : sc_module
}
else
{
fmemory[bank].load(trans);
ememory.load(trans);
}
}
else if ( cmd == tlm::TLM_WRITE_COMMAND )
@@ -418,7 +410,7 @@ struct Dram : sc_module
}
else
{
fmemory[bank].store(trans);
ememory.store(trans);
}
}
return len;