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Example initiator changed to send 64 bytes at a time and only 2 transactions to keep it simple

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This commit is contained in:
Éder F. Zulian
2016-07-07 10:34:05 +02:00
parent 73a42589c0
commit 944328b20b
2 changed files with 47 additions and 61 deletions
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88
DRAMSys/simulator/src/simulation/ExampleInitiator.h
View File

@@ -31,44 +31,15 @@ struct ExampleInitiator: sc_module
tlm::tlm_phase phase;
sc_time delay;
for (int i = 0; i < 64; i++)
data[i] = 0x55;
#if 0
// Make a call to b_transport
trans = m_mm.allocate();
trans->acquire();
int adr = 0;
data[0] = adr;
trans->set_command( tlm::TLM_WRITE_COMMAND );
trans->set_address( adr );
trans->set_data_ptr( reinterpret_cast<unsigned char*>(&data[0]) );
trans->set_data_length( 4 );
trans->set_streaming_width( 4 );
trans->set_byte_enable_ptr( 0 );
trans->set_dmi_allowed( false );
trans->set_response_status( tlm::TLM_INCOMPLETE_RESPONSE );
socket->b_transport( *trans, delay );
trans->release();
#endif
#if 1
for (unsigned i = 0; i < 16; i++) {
data[i] = 0xaa55aa55;
}
#endif
// Generate a sequence of random transactions
for (int i = 0; i < 1000; i++)
// Generate 2 write transactions
for (int i = 0; i < 2; i++)
{
//int adr = rand();
int adr = i % 256;
//tlm::tlm_command cmd = static_cast<tlm::tlm_command>(rand() % 2);
//tlm::tlm_command cmd = tlm::TLM_READ_COMMAND;
int adr = i * 64;
tlm::tlm_command cmd = tlm::TLM_WRITE_COMMAND;
//if (cmd == tlm::TLM_WRITE_COMMAND) data[i % 16] = adr;
// Grab a new transaction from the memory manager
trans = m_mm.allocate();
@@ -77,7 +48,7 @@ struct ExampleInitiator: sc_module
trans->set_command( cmd );
trans->set_address( adr );
trans->set_data_ptr( reinterpret_cast<unsigned char*>(&data[0]) );
trans->set_data_length( 4 );
trans->set_data_length( 64 );
trans->set_streaming_width( 4 );
trans->set_byte_enable_ptr( 0 );
trans->set_dmi_allowed( false );
@@ -90,10 +61,9 @@ struct ExampleInitiator: sc_module
phase = tlm::BEGIN_REQ;
// Timing annotation models processing time of initiator prior to call
//delay = sc_time(rand_ps(), SC_PS);
delay = sc_time(100000, SC_PS);
cout << hex << adr << " new, cmd=" << (cmd ? "write" : "read")
cout << "Address " << hex << adr << " new, cmd=" << (cmd ? "write" : "read")
<< ", data=" << hex << data[0] << " at time " << sc_time_stamp()
<< " in " << name() << endl;
@@ -123,29 +93,48 @@ struct ExampleInitiator: sc_module
trans->release();
}
dump_memories();
wait( sc_time(500, SC_NS) );
//wait( sc_time(rand_ps(), SC_PS) );
wait( sc_time(50000, SC_PS) );
dump_mem();
}
wait( sc_time(500, SC_NS) );
sc_stop();
}
void dump_memories()
#if 0
void init_mem()
{
for (sc_dt::uint64 addr = 0; addr <= 256; addr += 256)
for (int addr = 0; addr < 256; addr += 256)
{
int buffer[64];
int buffer[64] = {0, };
tlm::tlm_generic_payload trans;
trans.set_command( tlm::TLM_WRITE_COMMAND );
trans.set_address( addr );
trans.set_data_ptr( reinterpret_cast<unsigned char*>(buffer) );
trans.set_data_length( 256 );
socket->transport_dbg( trans );
}
}
#endif
void dump_mem()
{
for (int addr = 0; addr < 128; addr += 64)
{
unsigned char buffer[64];
tlm::tlm_generic_payload trans;
trans.set_command( tlm::TLM_READ_COMMAND );
trans.set_address( addr );
trans.set_data_ptr( reinterpret_cast<unsigned char*>(buffer) );
trans.set_data_length( 16 );
trans.set_data_ptr( buffer );
trans.set_data_length( 64 );
socket->transport_dbg( trans );
cout << "\nMemory dump\n";
for (int i = 0; i < 64; i++)
cout << "mem[" << addr + i*4 << "] = " << buffer[i] << endl;
cout << "mem[" << addr + i << "] = " << hex << (int)buffer[i] << endl;
}
}
@@ -178,7 +167,6 @@ struct ExampleInitiator: sc_module
// Send final phase transition to target
tlm::tlm_phase fw_phase = tlm::END_RESP;
//sc_time delay = sc_time(rand_ps(), SC_PS);
sc_time delay = sc_time(60000, SC_PS);
socket->nb_transport_fw( trans, fw_phase, delay );
// Ignore return value
@@ -211,8 +199,8 @@ struct ExampleInitiator: sc_module
assert( *ptr == -int(adr) );
}
MemoryManager m_mm;
int data[16];
MemoryManager m_mm;
unsigned char data[64];
tlm::tlm_generic_payload* request_in_progress;
sc_event end_request_event;
tlm_utils::peq_with_cb_and_phase<ExampleInitiator> m_peq;

20
DRAMSys/simulator/src/simulation/Simulation.cpp
View File

@@ -114,7 +114,7 @@ void Simulation::instantiateModules(const string &traceName, const string &pathT
// The same instance will be accessed by all other modules.
TemperatureController::getInstance();
#if 0
#if 1
for (size_t i = 0; i < Configuration::getInstance().NumberOfTracePlayers; i++) {
std::string playerStr = "tracePlayer" + std::to_string(i);
TracePlayer *player;
@@ -138,8 +138,6 @@ void Simulation::instantiateModules(const string &traceName, const string &pathT
players.push_back(player);
}
remainingTransactions = totalTransactions;
player->remainingTransactions = player->totalTransactions;
#endif
// Create and properly initialize TLM recorders. They need to be ready before creating some modules.
@@ -148,7 +146,7 @@ void Simulation::instantiateModules(const string &traceName, const string &pathT
arbiter = new Arbiter("arbiter");
arbiter->setTlmRecorders(tlmRecorders);
init = new ExampleInitiator("init");
//init = new ExampleInitiator("init");
for (size_t i = 0; i < Configuration::getInstance().NumberOfMemChannels; i++) {
std::string str = "controller" + std::to_string(i);
@@ -165,11 +163,11 @@ void Simulation::instantiateModules(const string &traceName, const string &pathT
void Simulation::bindSockets()
{
//for (auto player : players) {
// player->iSocket.bind(arbiter->tSocket);
//}
for (auto player : players) {
player->iSocket.bind(arbiter->tSocket);
}
init->socket.bind(arbiter->tSocket);
//init->socket.bind(arbiter->tSocket);
for (size_t i = 0; i < Configuration::getInstance().NumberOfMemChannels; i++) {
arbiter->iSocket.bind(controllers[i]->tSocket);
@@ -179,9 +177,9 @@ void Simulation::bindSockets()
Simulation::~Simulation()
{
//for (auto player : players) {
// delete player;
//}
for (auto player : players) {
delete player;
}
delete arbiter;