Integrated LibDRAMPower. Before you start you have to run the install_prerequisites.sh

.gitignore

@@ -11,3 +11,5 @@
 /dram/src/common/third_party/DRAMPower/*
 *.*~
 dram/build-*/
+._.DS_Store
+.DS_Store

dram/dramSys/dramSys.pro

@@ -5,14 +5,16 @@ CONFIG -= qt
 
 
 LIBS += -L/opt/systemc/lib-linux64 -lsystemc
-LIBS += -L/opt/boost/lib -lboost_filesystem  -lboost_system
+LIBS += -L/opt/boost/lib -lboost_filesystem -lboost_system
 LIBS += -L/opt/sqlite3/lib -lsqlite3
 LIBS += -lpthread
-LIBS += -L ../src/common/third_party/DRAMPower/src -ldrampower
+LIBS += -lxerces-c
-INCLUDEPATH += ../src/common/third_party/DRAMPower/src
+LIBS += -L../src/common/third_party/DRAMPower/src -ldrampower
+
 INCLUDEPATH += /opt/systemc/include
 INCLUDEPATH += /opt/boost/include
 INCLUDEPATH += /opt/sqlite3/include
+INCLUDEPATH += ../src/common/third_party/DRAMPower/src
 
 DEFINES += TIXML_USE_STL
 DEFINES += SC_INCLUDE_DYNAMIC_PROCESSES
@@ -58,7 +60,6 @@ SOURCES += \
     ../src/simulation/Simulation.cpp \
     ../src/simulation/MemoryManager.cpp \
     ../src/simulation/main.cpp \
-    ../src/common/libDRAMPower.cpp \
     ../src/controller/core/RowBufferStates.cpp \
     ../src/controller/scheduler/Scheduler.cpp \
     ../src/controller/scheduler/readwritegrouper.cpp
@@ -113,9 +114,8 @@ HEADERS += \
     ../src/simulation/MemoryManager.h \
     ../src/simulation/ISimulation.h \
     ../src/simulation/Dram.h \
-    ../src/simulation/Arbiter.h
+    ../src/simulation/Arbiter.h \
     ../src/common/libDRAMPower.h \
     ../src/controller/core/RowBufferStates.h \
     ../src/controller/scheduler/readwritegrouper.h
 
-

dram/resources/configs/memspecs/WideIO.xml

@@ -5,7 +5,7 @@
   <memarchitecturespec>
     <parameter id="width" type="uint" value="128" />
     <parameter id="nbrOfBanks" type="uint" value="8" />
-    <parameter id="nbrOfColumns" type="uint" value="128" />-
+    <parameter id="nbrOfColumns" type="uint" value="128" />
      <parameter id="nbrOfRows" type="uint" value="8192" />
      <parameter id="dataRate" type="uint" value="1" />
     <parameter id="burstLength" type="uint" value="4" />
@@ -33,7 +33,7 @@
       <parameter id="CKESR" type="uint" value="3" />
   </memtimingspec>
   <mempowerspec>
-     <!-- <parameter id="idd0" type="double" value="5.88" />
+      <parameter id="idd0" type="double" value="5.88" />
       <parameter id="idd02" type="double" value="21.18" />
       <parameter id="idd2p0" type="double" value="0.05" />
       <parameter id="idd2p02" type="double" value="0.17" />
@@ -56,6 +56,6 @@
       <parameter id="idd6" type="double" value="0.07" />
       <parameter id="idd62" type="double" value="0.27" />
       <parameter id="vdd" type="double" value="1.8" />
-      <parameter id="vdd2" type="double" value="1.2" />-->
+      <parameter id="vdd2" type="double" value="1.2" />
   </mempowerspec>
 </memspec>

dram/resources/configs/memspecs/memspec.dtd

@@ -0,0 +1,13 @@
+<!ELEMENT memspec (parameter*,memarchitecturespec,memtimingspec,mempowerspec)>
+
+<!ELEMENT parameter EMPTY>
+<!ATTLIST parameter id CDATA #REQUIRED>
+<!ATTLIST parameter type CDATA #REQUIRED>
+<!ATTLIST parameter value CDATA #REQUIRED>
+<!ATTLIST parameter unit CDATA #IMPLIED>
+
+<!ELEMENT memarchitecturespec (parameter*)>
+
+<!ELEMENT memtimingspec (parameter*)>
+
+<!ELEMENT mempowerspec (parameter*)>

dram/src/simulation/Dram.h

@@ -13,11 +13,14 @@
 #include <tlm_utils/peq_with_cb_and_phase.h>
 #include <tlm_utils/simple_target_socket.h>
 #include "../common/DebugManager.h"
+#include "../common/dramExtension.h"
 #include "../controller/core/TimingCalculation.h"
+#include "../controller/core/configuration/Configuration.h"
 #include "../common/protocol.h"
 #include "../common/Utils.h"
 #include "../common/TlmRecorder.h"
-#include <LibDRAMPower.h>
+#include "../common/third_party/DRAMPower/src/LibDRAMPower.h"
+
 
 using namespace std;
 using namespace tlm;
@@ -35,74 +38,86 @@ struct Dram: sc_module
             tSocket("socket")
     {
         tSocket.register_nb_transport_fw(this, &Dram::nb_transport_fw);
-        DRAMPower.doCommand(347);
     }
 
     ~Dram()
     {
+        DRAMPower.getEnergy(Configuration::getInstance().memspecUri);
     }
 
     virtual tlm::tlm_sync_enum nb_transport_fw(tlm::tlm_generic_payload& payload, tlm::tlm_phase& phase, sc_time& delay)
     {
         TlmRecorder::getInstance().recordPhase(payload, phase, sc_time_stamp() + delay);
 
+        // This is only needed for power simulation:
+        unsigned long long cycle = sc_time_stamp().value()/Configuration::getInstance().Timings.clk.value();
+        unsigned int bank = DramExtension::getExtension(payload).getBank().ID();
+
         if (phase == BEGIN_PRE)
         {
+            DRAMPower.doCommand(MemCommand::PRE, bank, cycle);
             sendToController(payload, END_PRE, delay + getExecutionTime(Command::Precharge, payload));
         }
         else if (phase == BEGIN_PRE_ALL)
         {
+            DRAMPower.doCommand(MemCommand::PREA, bank, cycle);
             sendToController(payload, END_PRE_ALL,delay +  getExecutionTime(Command::PrechargeAll, payload));
         }
         else if (phase == BEGIN_ACT)
         {
+            DRAMPower.doCommand(MemCommand::ACT, bank, cycle);
             sendToController(payload, END_ACT, delay +  getExecutionTime(Command::Activate, payload));
         }
         else if (phase == BEGIN_WR)
         {
+            DRAMPower.doCommand(MemCommand::WR, bank, cycle);
             sendToController(payload, END_WR, delay +  getExecutionTime(Command::Write, payload));
         }
         else if (phase == BEGIN_RD)
         {
+            DRAMPower.doCommand(MemCommand::RD, bank, cycle);
             sendToController(payload, END_RD, delay +  getExecutionTime(Command::Read, payload));
         }
         else if (phase == BEGIN_WRA)
         {
+            DRAMPower.doCommand(MemCommand::WRA, bank, cycle);
             sendToController(payload, END_WRA, delay +  getExecutionTime(Command::WriteA, payload));
         }
         else if (phase == BEGIN_RDA)
         {
+            DRAMPower.doCommand(MemCommand::RDA, bank, cycle);
             sendToController(payload, END_RDA, delay +  getExecutionTime(Command::ReadA, payload));
         }
         else if (phase == BEGIN_AUTO_REFRESH)
         {
+            DRAMPower.doCommand(MemCommand::REF, bank, cycle);
             sendToController(payload, END_AUTO_REFRESH, delay +  getExecutionTime(Command::AutoRefresh, payload));
         }
 
         //Powerdown phases have to be started and ended by the controller, because they do not have a fixed length
         else if (phase == BEGIN_PDNP)
         {
-
+            DRAMPower.doCommand(MemCommand::PDN_S_PRE, bank, cycle);
         }
         else if (phase == END_PDNP)
         {
-
+            DRAMPower.doCommand(MemCommand::PUP_PRE, bank, cycle);
         }
         else if (phase == BEGIN_PDNA)
         {
-
+            DRAMPower.doCommand(MemCommand::PDN_S_ACT, bank, cycle);
         }
         else if (phase == END_PDNA)
         {
-
+            DRAMPower.doCommand(MemCommand::PUP_PRE, bank, cycle);
         }
         else if (phase == BEGIN_SREF)
         {
-
+            DRAMPower.doCommand(MemCommand::SREN, bank, cycle);
         }
         else if (phase == END_SREF)
         {
-
+            DRAMPower.doCommand(MemCommand::SREX, bank, cycle);
         }
         else
         {

install_prerequisites.sh

@@ -1,8 +1,5 @@
 #!/bin/bash
-mkdir -p dram/src/common/third_party/DRAMPower
+cd dram/src/common/third_party/
-cd dram/src/common/third_party/DRAMPower
+git clone https://github.com/myzinsky/DRAMPower.git
-wget "http://www.es.ele.tue.nl/drampower/DRAMPower3.1.zip"
+cd DRAMPower
-unzip DRAMPower3.1.zip
+make lib
-mv DRAMPower3.1/* .
-rm -r DRAMPower3.1
-rm -r DRAMPower3.1.zip