diff --git a/.gitignore b/.gitignore index 8bf9a499..f6cc4740 100644 --- a/.gitignore +++ b/.gitignore @@ -11,3 +11,5 @@ /dram/src/common/third_party/DRAMPower/* *.*~ dram/build-*/ +._.DS_Store +.DS_Store diff --git a/dram/dramSys/dramSys.pro b/dram/dramSys/dramSys.pro index c9c33314..27b6a71d 100644 --- a/dram/dramSys/dramSys.pro +++ b/dram/dramSys/dramSys.pro @@ -5,14 +5,16 @@ CONFIG -= qt LIBS += -L/opt/systemc/lib-linux64 -lsystemc -LIBS += -L/opt/boost/lib -lboost_filesystem -lboost_system +LIBS += -L/opt/boost/lib -lboost_filesystem -lboost_system LIBS += -L/opt/sqlite3/lib -lsqlite3 LIBS += -lpthread -LIBS += -L ../src/common/third_party/DRAMPower/src -ldrampower -INCLUDEPATH += ../src/common/third_party/DRAMPower/src +LIBS += -lxerces-c +LIBS += -L../src/common/third_party/DRAMPower/src -ldrampower + INCLUDEPATH += /opt/systemc/include INCLUDEPATH += /opt/boost/include INCLUDEPATH += /opt/sqlite3/include +INCLUDEPATH += ../src/common/third_party/DRAMPower/src DEFINES += TIXML_USE_STL DEFINES += SC_INCLUDE_DYNAMIC_PROCESSES @@ -58,7 +60,6 @@ SOURCES += \ ../src/simulation/Simulation.cpp \ ../src/simulation/MemoryManager.cpp \ ../src/simulation/main.cpp \ - ../src/common/libDRAMPower.cpp \ ../src/controller/core/RowBufferStates.cpp \ ../src/controller/scheduler/Scheduler.cpp \ ../src/controller/scheduler/readwritegrouper.cpp @@ -113,9 +114,8 @@ HEADERS += \ ../src/simulation/MemoryManager.h \ ../src/simulation/ISimulation.h \ ../src/simulation/Dram.h \ - ../src/simulation/Arbiter.h + ../src/simulation/Arbiter.h \ ../src/common/libDRAMPower.h \ ../src/controller/core/RowBufferStates.h \ ../src/controller/scheduler/readwritegrouper.h - diff --git a/dram/resources/configs/memspecs/WideIO.xml b/dram/resources/configs/memspecs/WideIO.xml index e71d27c6..fbe252d6 100644 --- a/dram/resources/configs/memspecs/WideIO.xml +++ b/dram/resources/configs/memspecs/WideIO.xml @@ -5,7 +5,7 @@ - - + @@ -33,7 +33,7 @@ - + diff --git a/dram/resources/configs/memspecs/memspec.dtd b/dram/resources/configs/memspecs/memspec.dtd new file mode 100644 index 00000000..f94ed9e9 --- /dev/null +++ b/dram/resources/configs/memspecs/memspec.dtd @@ -0,0 +1,13 @@ + + + + + + + + + + + + + diff --git a/dram/src/simulation/Dram.h b/dram/src/simulation/Dram.h index 8cc87159..a73051b4 100644 --- a/dram/src/simulation/Dram.h +++ b/dram/src/simulation/Dram.h @@ -13,11 +13,14 @@ #include #include #include "../common/DebugManager.h" +#include "../common/dramExtension.h" #include "../controller/core/TimingCalculation.h" +#include "../controller/core/configuration/Configuration.h" #include "../common/protocol.h" #include "../common/Utils.h" #include "../common/TlmRecorder.h" -#include +#include "../common/third_party/DRAMPower/src/LibDRAMPower.h" + using namespace std; using namespace tlm; @@ -35,74 +38,86 @@ struct Dram: sc_module tSocket("socket") { tSocket.register_nb_transport_fw(this, &Dram::nb_transport_fw); - DRAMPower.doCommand(347); } ~Dram() { + DRAMPower.getEnergy(Configuration::getInstance().memspecUri); } virtual tlm::tlm_sync_enum nb_transport_fw(tlm::tlm_generic_payload& payload, tlm::tlm_phase& phase, sc_time& delay) { TlmRecorder::getInstance().recordPhase(payload, phase, sc_time_stamp() + delay); + // This is only needed for power simulation: + unsigned long long cycle = sc_time_stamp().value()/Configuration::getInstance().Timings.clk.value(); + unsigned int bank = DramExtension::getExtension(payload).getBank().ID(); + if (phase == BEGIN_PRE) { + DRAMPower.doCommand(MemCommand::PRE, bank, cycle); sendToController(payload, END_PRE, delay + getExecutionTime(Command::Precharge, payload)); } else if (phase == BEGIN_PRE_ALL) { + DRAMPower.doCommand(MemCommand::PREA, bank, cycle); sendToController(payload, END_PRE_ALL,delay + getExecutionTime(Command::PrechargeAll, payload)); } else if (phase == BEGIN_ACT) { + DRAMPower.doCommand(MemCommand::ACT, bank, cycle); sendToController(payload, END_ACT, delay + getExecutionTime(Command::Activate, payload)); } else if (phase == BEGIN_WR) { + DRAMPower.doCommand(MemCommand::WR, bank, cycle); sendToController(payload, END_WR, delay + getExecutionTime(Command::Write, payload)); } else if (phase == BEGIN_RD) { + DRAMPower.doCommand(MemCommand::RD, bank, cycle); sendToController(payload, END_RD, delay + getExecutionTime(Command::Read, payload)); } else if (phase == BEGIN_WRA) { + DRAMPower.doCommand(MemCommand::WRA, bank, cycle); sendToController(payload, END_WRA, delay + getExecutionTime(Command::WriteA, payload)); } else if (phase == BEGIN_RDA) { + DRAMPower.doCommand(MemCommand::RDA, bank, cycle); sendToController(payload, END_RDA, delay + getExecutionTime(Command::ReadA, payload)); } else if (phase == BEGIN_AUTO_REFRESH) { + DRAMPower.doCommand(MemCommand::REF, bank, cycle); sendToController(payload, END_AUTO_REFRESH, delay + getExecutionTime(Command::AutoRefresh, payload)); } //Powerdown phases have to be started and ended by the controller, because they do not have a fixed length else if (phase == BEGIN_PDNP) { - + DRAMPower.doCommand(MemCommand::PDN_S_PRE, bank, cycle); } else if (phase == END_PDNP) { - + DRAMPower.doCommand(MemCommand::PUP_PRE, bank, cycle); } else if (phase == BEGIN_PDNA) { - + DRAMPower.doCommand(MemCommand::PDN_S_ACT, bank, cycle); } else if (phase == END_PDNA) { - + DRAMPower.doCommand(MemCommand::PUP_PRE, bank, cycle); } else if (phase == BEGIN_SREF) { - + DRAMPower.doCommand(MemCommand::SREN, bank, cycle); } else if (phase == END_SREF) { - + DRAMPower.doCommand(MemCommand::SREX, bank, cycle); } else { diff --git a/install_prerequisites.sh b/install_prerequisites.sh index 7fb677b3..c0c59f4f 100755 --- a/install_prerequisites.sh +++ b/install_prerequisites.sh @@ -1,8 +1,5 @@ #!/bin/bash -mkdir -p dram/src/common/third_party/DRAMPower -cd dram/src/common/third_party/DRAMPower -wget "http://www.es.ele.tue.nl/drampower/DRAMPower3.1.zip" -unzip DRAMPower3.1.zip -mv DRAMPower3.1/* . -rm -r DRAMPower3.1 -rm -r DRAMPower3.1.zip +cd dram/src/common/third_party/ +git clone https://github.com/myzinsky/DRAMPower.git +cd DRAMPower +make lib