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Integrated LibDRAMPower. Before you start you have to run the install_prerequisites.sh

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This commit is contained in:
Matthias Jung
2014-07-15 22:47:02 +02:00
parent a2c757e347
commit 8b4e3fa4bf
6 changed files with 51 additions and 24 deletions
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31
dram/src/simulation/Dram.h
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@@ -13,11 +13,14 @@
#include <tlm_utils/peq_with_cb_and_phase.h>
#include <tlm_utils/simple_target_socket.h>
#include "../common/DebugManager.h"
#include "../common/dramExtension.h"
#include "../controller/core/TimingCalculation.h"
#include "../controller/core/configuration/Configuration.h"
#include "../common/protocol.h"
#include "../common/Utils.h"
#include "../common/TlmRecorder.h"
#include <LibDRAMPower.h>
#include "../common/third_party/DRAMPower/src/LibDRAMPower.h"
using namespace std;
using namespace tlm;
@@ -35,74 +38,86 @@ struct Dram: sc_module
tSocket("socket")
{
tSocket.register_nb_transport_fw(this, &Dram::nb_transport_fw);
DRAMPower.doCommand(347);
}
~Dram()
{
DRAMPower.getEnergy(Configuration::getInstance().memspecUri);
}
virtual tlm::tlm_sync_enum nb_transport_fw(tlm::tlm_generic_payload& payload, tlm::tlm_phase& phase, sc_time& delay)
{
TlmRecorder::getInstance().recordPhase(payload, phase, sc_time_stamp() + delay);
// This is only needed for power simulation:
unsigned long long cycle = sc_time_stamp().value()/Configuration::getInstance().Timings.clk.value();
unsigned int bank = DramExtension::getExtension(payload).getBank().ID();
if (phase == BEGIN_PRE)
{
DRAMPower.doCommand(MemCommand::PRE, bank, cycle);
sendToController(payload, END_PRE, delay + getExecutionTime(Command::Precharge, payload));
}
else if (phase == BEGIN_PRE_ALL)
{
DRAMPower.doCommand(MemCommand::PREA, bank, cycle);
sendToController(payload, END_PRE_ALL,delay + getExecutionTime(Command::PrechargeAll, payload));
}
else if (phase == BEGIN_ACT)
{
DRAMPower.doCommand(MemCommand::ACT, bank, cycle);
sendToController(payload, END_ACT, delay + getExecutionTime(Command::Activate, payload));
}
else if (phase == BEGIN_WR)
{
DRAMPower.doCommand(MemCommand::WR, bank, cycle);
sendToController(payload, END_WR, delay + getExecutionTime(Command::Write, payload));
}
else if (phase == BEGIN_RD)
{
DRAMPower.doCommand(MemCommand::RD, bank, cycle);
sendToController(payload, END_RD, delay + getExecutionTime(Command::Read, payload));
}
else if (phase == BEGIN_WRA)
{
DRAMPower.doCommand(MemCommand::WRA, bank, cycle);
sendToController(payload, END_WRA, delay + getExecutionTime(Command::WriteA, payload));
}
else if (phase == BEGIN_RDA)
{
DRAMPower.doCommand(MemCommand::RDA, bank, cycle);
sendToController(payload, END_RDA, delay + getExecutionTime(Command::ReadA, payload));
}
else if (phase == BEGIN_AUTO_REFRESH)
{
DRAMPower.doCommand(MemCommand::REF, bank, cycle);
sendToController(payload, END_AUTO_REFRESH, delay + getExecutionTime(Command::AutoRefresh, payload));
}
//Powerdown phases have to be started and ended by the controller, because they do not have a fixed length
else if (phase == BEGIN_PDNP)
{
DRAMPower.doCommand(MemCommand::PDN_S_PRE, bank, cycle);
}
else if (phase == END_PDNP)
{
DRAMPower.doCommand(MemCommand::PUP_PRE, bank, cycle);
}
else if (phase == BEGIN_PDNA)
{
DRAMPower.doCommand(MemCommand::PDN_S_ACT, bank, cycle);
}
else if (phase == END_PDNA)
{
DRAMPower.doCommand(MemCommand::PUP_PRE, bank, cycle);
}
else if (phase == BEGIN_SREF)
{
DRAMPower.doCommand(MemCommand::SREN, bank, cycle);
}
else if (phase == END_SREF)
{
DRAMPower.doCommand(MemCommand::SREX, bank, cycle);
}
else
{