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added support for debug_transport in Controller and DRAM

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This commit is contained in:
Matthias Jung
2015-06-08 14:53:39 +02:00
parent f47097d914
commit 8819f9b39c
2 changed files with 50 additions and 0 deletions
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8
dram/src/controller/Controller.h
View File

@@ -82,6 +82,7 @@ public:
buildScheduler();
iSocket.register_nb_transport_bw(this, &Controller<BUSWIDTH>::nb_transport_bw);
tSocket.register_nb_transport_fw(this, &Controller<BUSWIDTH>::nb_transport_fw);
tSocket.register_transport_dbg(this, &Controller<BUSWIDTH>::transport_dbg);
}
~Controller()
@@ -108,6 +109,7 @@ private:
// --- FRONTEND ------
tlm_sync_enum nb_transport_fw(tlm_generic_payload& payload, tlm_phase& phase, sc_time& fwDelay);
virtual unsigned int transport_dbg(tlm::tlm_generic_payload& trans);
void frontendPEQCallback(tlm_generic_payload& payload, const tlm_phase& phase);
void sendToFrontend(tlm_generic_payload& payload, const tlm_phase& phase, const sc_time& delay);
@@ -363,6 +365,12 @@ tlm_sync_enum Controller<BUSWIDTH>::nb_transport_fw(tlm_generic_payload &payload
return TLM_ACCEPTED;
}
template<unsigned int BUSWIDTH>
unsigned int Controller<BUSWIDTH>::transport_dbg(tlm::tlm_generic_payload& trans)
{
return iSocket->transport_dbg(trans);
}
template<unsigned int BUSWIDTH>
void Controller<BUSWIDTH>::frontendPEQCallback(tlm_generic_payload &payload, const tlm_phase &phase)
{

42
dram/src/simulation/Dram.h
View File

@@ -86,6 +86,7 @@ struct Dram: sc_module
SC_CTOR(Dram) : tSocket("socket")
{
tSocket.register_nb_transport_fw(this, &Dram::nb_transport_fw);
tSocket.register_transport_dbg(this,&Dram::transport_dbg);
if(powerAnalysis == true)
{
@@ -312,6 +313,47 @@ struct Dram: sc_module
return tlm::TLM_ACCEPTED;
}
virtual unsigned int transport_dbg(tlm::tlm_generic_payload& trans)
{
// TODO: This part is not tested yet, neither with traceplayers neither with GEM5 coupling
if (ErrorStoreMode == ErrorStorageMode::NoStorage)
{
SC_REPORT_FATAL("DRAM", "Debug Transport is used in combination with NoStorage");
}
else
{
tlm::tlm_command cmd = trans.get_command();
sc_dt::uint64 adr = trans.get_address(); // TODO: - offset;
unsigned char* ptr = trans.get_data_ptr();
unsigned int len = trans.get_data_length();
unsigned int bank = DramExtension::getExtension(trans).getBank().ID();
if ( cmd == tlm::TLM_READ_COMMAND )
{
if (ErrorStoreMode == ErrorStorageMode::Store) // Use Storage
{
memcpy(ptr,&memory[adr], len);
}
else
{
fmemory[bank].load(trans);
}
}
else if ( cmd == tlm::TLM_WRITE_COMMAND )
{
if (ErrorStoreMode == ErrorStorageMode::Store) // Use Storage
{
memcpy(&memory[adr], ptr, len);
}
else
{
fmemory[bank].store(trans);
}
}
return len;
}
}
void sendToController(tlm_generic_payload& payload, const tlm_phase& phase, const sc_time& delay)
{
tlm_phase TPhase = phase;