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Rename RAACDR to RAADEC

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This commit is contained in:
Derek Christ
2023-04-21 11:10:09 +02:00
parent 515962e7ae
commit 85f944fe58
31 changed files with 39 additions and 39 deletions
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2
configs/memspec/HBM3.json
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@@ -13,7 +13,7 @@
"nbrOfChannels": 1, "nbrOfChannels": 1,
"RAAIMT" : 16, "RAAIMT" : 16,
"RAAMMT" : 96, "RAAMMT" : 96,
"RAACDR" : 16 "RAADEC" : 16
}, },
"memoryId": "", "memoryId": "",
"memoryType": "HBM3", "memoryType": "HBM3",

2
configs/memspec/JEDEC_2x2x8x4Gbx4_DDR5-3200A.json
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@@ -18,7 +18,7 @@
"refMode": 1, "refMode": 1,
"RAAIMT" : 16, "RAAIMT" : 16,
"RAAMMT" : 96, "RAAMMT" : 96,
"RAACDR" : 16 "RAADEC" : 16
}, },
"memoryId": "JEDEC_2x8x2Gbx4_DDR5-3200A", "memoryId": "JEDEC_2x8x2Gbx4_DDR5-3200A",
"memoryType": "DDR5", "memoryType": "DDR5",

2
configs/memspec/JEDEC_2x4x1Gbx8_DDR5-3200A.json
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@@ -18,7 +18,7 @@
"refMode": 1, "refMode": 1,
"RAAIMT" : 16, "RAAIMT" : 16,
"RAAMMT" : 96, "RAAMMT" : 96,
"RAACDR" : 16 "RAADEC" : 16
}, },
"memoryId": "JEDEC_2x4x1Gbx8_DDR5-3200A", "memoryId": "JEDEC_2x4x1Gbx8_DDR5-3200A",
"memoryType": "DDR5", "memoryType": "DDR5",

2
configs/memspec/JEDEC_2x4x1Gbx8_DDR5-3600A.json
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@@ -18,7 +18,7 @@
"refMode": 1, "refMode": 1,
"RAAIMT" : 16, "RAAIMT" : 16,
"RAAMMT" : 96, "RAAMMT" : 96,
"RAACDR" : 16 "RAADEC" : 16
}, },
"memoryId": "JEDEC_2x4x1Gbx8_DDR5-3600A", "memoryId": "JEDEC_2x4x1Gbx8_DDR5-3600A",
"memoryType": "DDR5", "memoryType": "DDR5",

2
configs/memspec/JEDEC_2x4x1Gbx8_DDR5-4000A.json
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@@ -18,7 +18,7 @@
"refMode": 1, "refMode": 1,
"RAAIMT" : 16, "RAAIMT" : 16,
"RAAMMT" : 96, "RAAMMT" : 96,
"RAACDR" : 16 "RAADEC" : 16
}, },
"memoryId": "JEDEC_2x4x1Gbx8_DDR5-4000A", "memoryId": "JEDEC_2x4x1Gbx8_DDR5-4000A",
"memoryType": "DDR5", "memoryType": "DDR5",

2
configs/memspec/JEDEC_2x4x1Gbx8_DDR5-4400A.json
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@@ -18,7 +18,7 @@
"refMode": 1, "refMode": 1,
"RAAIMT" : 16, "RAAIMT" : 16,
"RAAMMT" : 96, "RAAMMT" : 96,
"RAACDR" : 16 "RAADEC" : 16
}, },
"memoryId": "JEDEC_2x4x1Gbx8_DDR5-4400A", "memoryId": "JEDEC_2x4x1Gbx8_DDR5-4400A",
"memoryType": "DDR5", "memoryType": "DDR5",

2
configs/memspec/JEDEC_2x4x1Gbx8_DDR5-4800A.json
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@@ -18,7 +18,7 @@
"refMode": 1, "refMode": 1,
"RAAIMT" : 16, "RAAIMT" : 16,
"RAAMMT" : 96, "RAAMMT" : 96,
"RAACDR" : 16 "RAADEC" : 16
}, },
"memoryId": "JEDEC_2x4x1Gbx8_DDR5-4800A", "memoryId": "JEDEC_2x4x1Gbx8_DDR5-4800A",
"memoryType": "DDR5", "memoryType": "DDR5",

2
configs/memspec/JEDEC_2x4x1Gbx8_DDR5-5200A.json
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@@ -18,7 +18,7 @@
"refMode": 1, "refMode": 1,
"RAAIMT" : 16, "RAAIMT" : 16,
"RAAMMT" : 96, "RAAMMT" : 96,
"RAACDR" : 16 "RAADEC" : 16
}, },
"memoryId": "JEDEC_2x4x1Gbx8_DDR5-5200A", "memoryId": "JEDEC_2x4x1Gbx8_DDR5-5200A",
"memoryType": "DDR5", "memoryType": "DDR5",

2
configs/memspec/JEDEC_2x4x1Gbx8_DDR5-5600A.json
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@@ -18,7 +18,7 @@
"refMode": 1, "refMode": 1,
"RAAIMT" : 16, "RAAIMT" : 16,
"RAAMMT" : 96, "RAAMMT" : 96,
"RAACDR" : 16 "RAADEC" : 16
}, },
"memoryId": "JEDEC_2x4x1Gbx8_DDR5-5600A", "memoryId": "JEDEC_2x4x1Gbx8_DDR5-5600A",
"memoryType": "DDR5", "memoryType": "DDR5",

2
configs/memspec/JEDEC_2x4x1Gbx8_DDR5-6000A.json
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@@ -18,7 +18,7 @@
"refMode": 1, "refMode": 1,
"RAAIMT" : 16, "RAAIMT" : 16,
"RAAMMT" : 96, "RAAMMT" : 96,
"RAACDR" : 16 "RAADEC" : 16
}, },
"memoryId": "JEDEC_2x4x1Gbx8_DDR5-6000A", "memoryId": "JEDEC_2x4x1Gbx8_DDR5-6000A",
"memoryType": "DDR5", "memoryType": "DDR5",

2
configs/memspec/JEDEC_2x4x1Gbx8_DDR5-6400A.json
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@@ -18,7 +18,7 @@
"refMode": 1, "refMode": 1,
"RAAIMT" : 16, "RAAIMT" : 16,
"RAAMMT" : 96, "RAAMMT" : 96,
"RAACDR" : 16 "RAADEC" : 16
}, },
"memoryId": "JEDEC_2x4x1Gbx8_DDR5-6400A", "memoryId": "JEDEC_2x4x1Gbx8_DDR5-6400A",
"memoryType": "DDR5", "memoryType": "DDR5",

2
configs/memspec/JEDEC_2x8x2Gbx4_DDR5-3200A.json
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@@ -18,7 +18,7 @@
"refMode": 1, "refMode": 1,
"RAAIMT" : 32, "RAAIMT" : 32,
"RAAMMT" : 96, "RAAMMT" : 96,
"RAACDR" : 16 "RAADEC" : 16
}, },
"memoryId": "JEDEC_2x8x2Gbx4_DDR5-3200A", "memoryId": "JEDEC_2x8x2Gbx4_DDR5-3200A",
"memoryType": "DDR5", "memoryType": "DDR5",

2
configs/memspec/JEDEC_2x8x2Gbx4_DDR5-3600A.json
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@@ -18,7 +18,7 @@
"refMode": 1, "refMode": 1,
"RAAIMT" : 16, "RAAIMT" : 16,
"RAAMMT" : 96, "RAAMMT" : 96,
"RAACDR" : 16 "RAADEC" : 16
}, },
"memoryId": "JEDEC_2x8x2Gbx4_DDR5-3600A", "memoryId": "JEDEC_2x8x2Gbx4_DDR5-3600A",
"memoryType": "DDR5", "memoryType": "DDR5",

2
configs/memspec/JEDEC_2x8x2Gbx4_DDR5-4000A.json
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@@ -18,7 +18,7 @@
"refMode": 1, "refMode": 1,
"RAAIMT" : 16, "RAAIMT" : 16,
"RAAMMT" : 96, "RAAMMT" : 96,
"RAACDR" : 16 "RAADEC" : 16
}, },
"memoryId": "JEDEC_2x8x2Gbx4_DDR5-4000A", "memoryId": "JEDEC_2x8x2Gbx4_DDR5-4000A",
"memoryType": "DDR5", "memoryType": "DDR5",

2
configs/memspec/JEDEC_2x8x2Gbx4_DDR5-4400A.json
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@@ -18,7 +18,7 @@
"refMode": 1, "refMode": 1,
"RAAIMT" : 16, "RAAIMT" : 16,
"RAAMMT" : 96, "RAAMMT" : 96,
"RAACDR" : 16 "RAADEC" : 16
}, },
"memoryId": "JEDEC_2x8x2Gbx4_DDR5-4400A", "memoryId": "JEDEC_2x8x2Gbx4_DDR5-4400A",
"memoryType": "DDR5", "memoryType": "DDR5",

2
configs/memspec/JEDEC_2x8x2Gbx4_DDR5-4800A.json
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@@ -18,7 +18,7 @@
"refMode": 1, "refMode": 1,
"RAAIMT" : 16, "RAAIMT" : 16,
"RAAMMT" : 96, "RAAMMT" : 96,
"RAACDR" : 16 "RAADEC" : 16
}, },
"memoryId": "JEDEC_2x8x2Gbx4_DDR5-4800A", "memoryId": "JEDEC_2x8x2Gbx4_DDR5-4800A",
"memoryType": "DDR5", "memoryType": "DDR5",

2
configs/memspec/JEDEC_2x8x2Gbx4_DDR5-5200A.json
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@@ -18,7 +18,7 @@
"refMode": 1, "refMode": 1,
"RAAIMT" : 16, "RAAIMT" : 16,
"RAAMMT" : 96, "RAAMMT" : 96,
"RAACDR" : 16 "RAADEC" : 16
}, },
"memoryId": "JEDEC_2x8x2Gbx4_DDR5-5200A", "memoryId": "JEDEC_2x8x2Gbx4_DDR5-5200A",
"memoryType": "DDR5", "memoryType": "DDR5",

2
configs/memspec/JEDEC_2x8x2Gbx4_DDR5-5600A.json
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@@ -18,7 +18,7 @@
"refMode": 1, "refMode": 1,
"RAAIMT" : 16, "RAAIMT" : 16,
"RAAMMT" : 96, "RAAMMT" : 96,
"RAACDR" : 16 "RAADEC" : 16
}, },
"memoryId": "JEDEC_2x8x2Gbx4_DDR5-5600A", "memoryId": "JEDEC_2x8x2Gbx4_DDR5-5600A",
"memoryType": "DDR5", "memoryType": "DDR5",

2
configs/memspec/JEDEC_2x8x2Gbx4_DDR5-6000A.json
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@@ -18,7 +18,7 @@
"refMode": 1, "refMode": 1,
"RAAIMT" : 16, "RAAIMT" : 16,
"RAAMMT" : 96, "RAAMMT" : 96,
"RAACDR" : 16 "RAADEC" : 16
}, },
"memoryId": "JEDEC_2x8x2Gbx4_DDR5-6000A", "memoryId": "JEDEC_2x8x2Gbx4_DDR5-6000A",
"memoryType": "DDR5", "memoryType": "DDR5",

2
configs/memspec/JEDEC_2x8x2Gbx4_DDR5-6400A.json
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@@ -18,7 +18,7 @@
"refMode": 1, "refMode": 1,
"RAAIMT" : 16, "RAAIMT" : 16,
"RAAMMT" : 96, "RAAMMT" : 96,
"RAACDR" : 16 "RAADEC" : 16
}, },
"memoryId": "JEDEC_2x8x2Gbx4_DDR5-6400A", "memoryId": "JEDEC_2x8x2Gbx4_DDR5-6400A",
"memoryType": "DDR5", "memoryType": "DDR5",

2
configs/memspec/JEDEC_2x8x8x2Gbx4_DDR5-3200A.json
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@@ -18,7 +18,7 @@
"refMode": 1, "refMode": 1,
"RAAIMT" : 16, "RAAIMT" : 16,
"RAAMMT" : 96, "RAAMMT" : 96,
"RAACDR" : 16 "RAADEC" : 16
}, },
"memoryId": "JEDEC_2x8x8x8Gbx4_DDR5-3200A_4bit", "memoryId": "JEDEC_2x8x8x8Gbx4_DDR5-3200A_4bit",
"memoryType": "DDR5", "memoryType": "DDR5",

6
extensions/standards/DDR5/DRAMSys/configuration/memspec/MemSpecDDR5.cpp
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@@ -66,7 +66,7 @@ MemSpecDDR5::MemSpecDDR5(const DRAMSys::Config::MemSpec &memSpec)
refMode(memSpec.memarchitecturespec.entries.at("refMode")), refMode(memSpec.memarchitecturespec.entries.at("refMode")),
RAAIMT(memSpec.memarchitecturespec.entries.at("RAAIMT")), RAAIMT(memSpec.memarchitecturespec.entries.at("RAAIMT")),
RAAMMT(memSpec.memarchitecturespec.entries.at("RAAMMT")), RAAMMT(memSpec.memarchitecturespec.entries.at("RAAMMT")),
RAACDR(memSpec.memarchitecturespec.entries.at("RAACDR")), RAADEC(memSpec.memarchitecturespec.entries.at("RAADEC")),
tRCD (tCK * memSpec.memtimingspec.entries.at("RCD")), tRCD (tCK * memSpec.memtimingspec.entries.at("RCD")),
tPPD (tCK * memSpec.memtimingspec.entries.at("PPD")), tPPD (tCK * memSpec.memtimingspec.entries.at("PPD")),
tRP (tCK * memSpec.memtimingspec.entries.at("RP")), tRP (tCK * memSpec.memtimingspec.entries.at("RP")),
@@ -196,9 +196,9 @@ sc_time MemSpecDDR5::getRefreshIntervalSB() const
return tREFIsb; return tREFIsb;
} }
unsigned MemSpecDDR5::getRAACDR() const unsigned MemSpecDDR5::getRAADEC() const
{ {
return RAACDR; return RAADEC;
} }
unsigned MemSpecDDR5::getRAAIMT() const unsigned MemSpecDDR5::getRAAIMT() const

4
extensions/standards/DDR5/DRAMSys/configuration/memspec/MemSpecDDR5.h
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@@ -54,7 +54,7 @@ public:
const unsigned refMode; const unsigned refMode;
const unsigned RAAIMT; const unsigned RAAIMT;
const unsigned RAAMMT; const unsigned RAAMMT;
const unsigned RAACDR; const unsigned RAADEC;
// Memspec Variables: // Memspec Variables:
const sc_core::sc_time tRCD; const sc_core::sc_time tRCD;
@@ -119,7 +119,7 @@ public:
sc_core::sc_time getRefreshIntervalAB() const override; sc_core::sc_time getRefreshIntervalAB() const override;
sc_core::sc_time getRefreshIntervalSB() const override; sc_core::sc_time getRefreshIntervalSB() const override;
unsigned getRAACDR() const override; unsigned getRAADEC() const override;
unsigned getRAAIMT() const override; unsigned getRAAIMT() const override;
unsigned getRAAMMT() const override; unsigned getRAAMMT() const override;

6
extensions/standards/HBM3/DRAMSys/configuration/memspec/MemSpecHBM3.cpp
View File

@@ -58,7 +58,7 @@ MemSpecHBM3::MemSpecHBM3(const DRAMSys::Config::MemSpec &memSpec)
memSpec.memarchitecturespec.entries.at("nbrOfDevices")), memSpec.memarchitecturespec.entries.at("nbrOfDevices")),
RAAIMT(memSpec.memarchitecturespec.entries.at("RAAIMT")), RAAIMT(memSpec.memarchitecturespec.entries.at("RAAIMT")),
RAAMMT(memSpec.memarchitecturespec.entries.at("RAAMMT")), RAAMMT(memSpec.memarchitecturespec.entries.at("RAAMMT")),
RAACDR(memSpec.memarchitecturespec.entries.at("RAACDR")), RAADEC(memSpec.memarchitecturespec.entries.at("RAADEC")),
tDQSCK (tCK * memSpec.memtimingspec.entries.at("DQSCK")), tDQSCK (tCK * memSpec.memtimingspec.entries.at("DQSCK")),
tRC (tCK * memSpec.memtimingspec.entries.at("RC")), tRC (tCK * memSpec.memtimingspec.entries.at("RC")),
tRAS (tCK * memSpec.memtimingspec.entries.at("RAS")), tRAS (tCK * memSpec.memtimingspec.entries.at("RAS")),
@@ -179,9 +179,9 @@ TimeInterval MemSpecHBM3::getIntervalOnDataStrobe(Command command, const tlm_gen
} }
} }
unsigned MemSpecHBM3::getRAACDR() const unsigned MemSpecHBM3::getRAADEC() const
{ {
return RAACDR; return RAADEC;
} }
unsigned MemSpecHBM3::getRAAIMT() const unsigned MemSpecHBM3::getRAAIMT() const

4
extensions/standards/HBM3/DRAMSys/configuration/memspec/MemSpecHBM3.h
View File

@@ -47,7 +47,7 @@ public:
const unsigned RAAIMT; const unsigned RAAIMT;
const unsigned RAAMMT; const unsigned RAAMMT;
const unsigned RAACDR; const unsigned RAADEC;
// Memspec Variables: // Memspec Variables:
const sc_core::sc_time tDQSCK; const sc_core::sc_time tDQSCK;
@@ -89,7 +89,7 @@ public:
sc_core::sc_time getRefreshIntervalAB() const override; sc_core::sc_time getRefreshIntervalAB() const override;
sc_core::sc_time getRefreshIntervalPB() const override; sc_core::sc_time getRefreshIntervalPB() const override;
unsigned getRAACDR() const override; unsigned getRAADEC() const override;
unsigned getRAAIMT() const override; unsigned getRAAIMT() const override;
unsigned getRAAMMT() const override; unsigned getRAAMMT() const override;

2
src/libdramsys/DRAMSys/configuration/memspec/MemSpec.cpp
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@@ -122,7 +122,7 @@ unsigned MemSpec::getPer2BankOffset() const
return 0; return 0;
} }
unsigned MemSpec::getRAACDR() const unsigned MemSpec::getRAADEC() const
{ {
SC_REPORT_FATAL("MemSpec", "Refresh Management not supported"); SC_REPORT_FATAL("MemSpec", "Refresh Management not supported");
return 0; return 0;

2
src/libdramsys/DRAMSys/configuration/memspec/MemSpec.h
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@@ -92,7 +92,7 @@ public:
virtual unsigned getRAAIMT() const; virtual unsigned getRAAIMT() const;
virtual unsigned getRAAMMT() const; virtual unsigned getRAAMMT() const;
virtual unsigned getRAACDR() const; virtual unsigned getRAADEC() const;
virtual bool hasRasAndCasBus() const; virtual bool hasRasAndCasBus() const;

4
src/libdramsys/DRAMSys/controller/BankMachine.cpp
View File

@@ -85,8 +85,8 @@ void BankMachine::update(Command command)
if (refreshManagement) if (refreshManagement)
{ {
if (refreshManagementCounter > memSpec.getRAACDR()) if (refreshManagementCounter > memSpec.getRAADEC())
refreshManagementCounter -= memSpec.getRAACDR(); refreshManagementCounter -= memSpec.getRAADEC();
else else
refreshManagementCounter = 0; refreshManagementCounter = 0;
} }

2
tests/tests_configuration/reference.json
View File

@@ -66,7 +66,7 @@
}, },
"memspec": { "memspec": {
"memarchitecturespec": { "memarchitecturespec": {
"RAACDR": 1, "RAADEC": 1,
"RAAIMT": 32, "RAAIMT": 32,
"RAAMMT": 96, "RAAMMT": 96,
"burstLength": 16, "burstLength": 16,

2
tests/tests_configuration/resources/memspec/JEDEC_2x8x2Gbx4_DDR5-3200A.json
View File

@@ -18,7 +18,7 @@
"refMode": 1, "refMode": 1,
"RAAIMT" : 32, "RAAIMT" : 32,
"RAAMMT" : 96, "RAAMMT" : 96,
"RAACDR" : 16 "RAADEC" : 16
}, },
"memoryId": "JEDEC_2x8x2Gbx4_DDR5-3200A", "memoryId": "JEDEC_2x8x2Gbx4_DDR5-3200A",
"memoryType": "DDR5", "memoryType": "DDR5",

4
tests/tests_configuration/test_configuration.cpp
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@@ -141,7 +141,7 @@ DRAMSys::Config::MemSpec ConfigurationTest::createMemSpec()
{"refMode", 1}, {"refMode", 1},
{"RAAIMT", 32}, {"RAAIMT", 32},
{"RAAMMT", 96}, {"RAAMMT", 96},
{"RAACDR", 1}}}; {"RAADEC", 1}}};
MemTimingSpecType memTimingSpec{{{ MemTimingSpecType memTimingSpec{{{
{"RCD", 22}, {"PPD", 2}, {"RP", 22}, {"RAS", 52}, {"RCD", 22}, {"PPD", 2}, {"RP", 22}, {"RAS", 52},
@@ -352,7 +352,7 @@ TEST_F(ConfigurationTest, MemSpec)
{ {
"memspec": { "memspec": {
"memarchitecturespec": { "memarchitecturespec": {
"RAACDR": 1, "RAADEC": 1,
"RAAIMT": 32, "RAAIMT": 32,
"RAAMMT": 96, "RAAMMT": 96,
"burstLength": 16, "burstLength": 16,