81 lines
2.1 KiB
JSON
81 lines
2.1 KiB
JSON
{
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"memspec": {
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"memarchitecturespec": {
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"burstLength": 16,
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"dataRate": 2,
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"nbrOfBankGroups": 8,
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"nbrOfBanks": 16,
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"nbrOfColumns": 2048,
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"nbrOfRanks": 1,
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"nbrOfDIMMRanks": 1,
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"nbrOfPhysicalRanks": 1,
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"nbrOfLogicalRanks": 1,
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"nbrOfRows": 65536,
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"width": 4,
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"nbrOfDevices": 8,
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"nbrOfChannels": 2,
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"cmdMode": 1,
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"refMode": 1,
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"RAAIMT" : 16,
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"RAAMMT" : 96,
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"RAADEC" : 16
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},
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"memoryId": "JEDEC_2x8x2Gbx4_DDR5-3600A",
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"memoryType": "DDR5",
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"memtimingspec": {
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"RCD": 26,
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"PPD": 2,
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"RP": 26,
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"RAS": 58,
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"RL": 26,
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"RTP": 14,
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"RPRE": 1,
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"RPST": 0,
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"RDDQS": 0,
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"WL": 24,
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"WPRE": 2,
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"WPST": 0,
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"WR": 54,
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"CCD_L_slr": 9,
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"CCD_L_WR_slr": 36,
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"CCD_L_WR2_slr": 18,
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"CCD_M_slr": 9,
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"CCD_M_WR_slr": 36,
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"CCD_S_slr": 8,
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"CCD_S_WR_slr": 8,
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"CCD_dlr": 0,
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"CCD_WR_dlr": 0,
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"CCD_WR_dpr": 0,
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"RRD_L_slr": 9,
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"RRD_S_slr": 8,
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"RRD_dlr": 0,
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"FAW_slr": 32,
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"FAW_dlr": 0,
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"WTR_L": 18,
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"WTR_M": 18,
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"WTR_S": 5,
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"RFC1_slr": 351,
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"RFC2_slr": 234,
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"RFC1_dlr": 0,
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"RFC2_dlr": 0,
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"RFC1_dpr": 0,
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"RFC2_dpr": 0,
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"RFCsb_slr": 207,
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"RFCsb_dlr": 0,
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"REFI1": 7020,
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"REFI2": 3510,
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"REFISB": 1755,
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"REFSBRD_slr": 54,
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"REFSBRD_dlr": 0,
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"RTRS": 2,
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"CPDED": 9,
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"PD": 14,
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"XP": 14,
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"ACTPDEN": 2,
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"PRPDEN": 2,
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"REFPDEN": 2,
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"clkMhz": 1800
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}
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}
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}
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