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Refactoring and command bus pooling.

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This commit is contained in:
Iron Prando da Silva
2022-02-16 10:55:57 +01:00
parent 8c3f4349ba
commit 7e7b2097f9
10 changed files with 65 additions and 39 deletions
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8
DRAMSys/traceAnalyzer/CMakeLists.txt
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@@ -113,14 +113,16 @@ add_executable(TraceAnalyzer
businessObjects/dependencymodels.cpp
businessObjects/dramTimeDependencies/common/common.cpp
businessObjects/dramTimeDependencies/dbEntries/DDR3dbphaseentry.cpp
businessObjects/dramTimeDependencies/deviceDependencies/poolcontroller.cpp
businessObjects/dramTimeDependencies/deviceDependencies/poolcontrollermap.cpp
businessObjects/dramTimeDependencies/deviceDependencies/dramtimedependenciesIF.cpp
businessObjects/dramTimeDependencies/deviceDependencies/DDR3TimeDependencies.cpp
businessObjects/dramTimeDependencies/configurations/configurationfactory.cpp
businessObjects/dramTimeDependencies/configurations/configurationIF.cpp
businessObjects/dramTimeDependencies/configurations/DDR3Configuration.cpp
businessObjects/dramTimeDependencies/dbEntries/specialized/DDR3dbphaseentry.cpp
businessObjects/dramTimeDependencies/deviceDependencies/specialized/DDR3TimeDependencies.cpp
businessObjects/dramTimeDependencies/configurations/specialized/DDR3Configuration.cpp
businessObjects/dramTimeDependencies/phasedependenciestracker.cpp
businessObjects/dramTimeDependencies/dramtimedependenciesIF.cpp

2
DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/configurationfactory.h
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@@ -38,7 +38,7 @@
#include <memory>
#include "configurationIF.h"
#include "DDR3Configuration.h"
#include "specialized/DDR3Configuration.h"
#include "data/tracedb.h"
class ConfigurationFactory {

0
DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/DDR3Configuration.cpp → DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/DDR3Configuration.cpp
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6
DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/DDR3Configuration.h → DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/DDR3Configuration.h
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@@ -1,9 +1,9 @@
#pragma once
#include "configurationIF.h"
#include "businessObjects/dramTimeDependencies/deviceDependencies/DDR3TimeDependencies.h"
#include "businessObjects/dramTimeDependencies/dbEntries/DDR3dbphaseentry.h"
#include "businessObjects/dramTimeDependencies/configurations/configurationIF.h"
#include "businessObjects/dramTimeDependencies/deviceDependencies/specialized/DDR3TimeDependencies.h"
#include "businessObjects/dramTimeDependencies/dbEntries/specialized/DDR3dbphaseentry.h"
class DDR3Configuration : public ConfigurationIF {
public:

2
DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/dbphaseentryTypes.h
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@@ -2,4 +2,4 @@
#pragma once
#include "dbphaseentryIF.h"
#include "DDR3dbphaseentry.h"
#include "specialized/DDR3dbphaseentry.h"

3
DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/DDR3dbphaseentry.cpp → DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/DDR3dbphaseentry.cpp
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@@ -16,6 +16,8 @@ bool DDR3DBPhaseEntry::potentialDependency(const TimeDependency& dep, const std:
auto other = std::dynamic_pointer_cast<DDR3DBPhaseEntry>(otherPhase);
if (!other) return false;
bool isCmdPool = dep.phaseDep == "CMD_BUS_POOL";
bool const skipOnIntraBankAndDifferentBanks = {
dep.depType == DependencyType::IntraBank
&& tBank != other->tBank
@@ -27,6 +29,7 @@ bool DDR3DBPhaseEntry::potentialDependency(const TimeDependency& dep, const std:
bool const skipOnInterRankAndSameRank = {
dep.depType == DependencyType::InterRank
&& tRank == other->tRank
&& !isCmdPool
};
return !(skipOnIntraBankAndDifferentBanks || skipOnIntraRankAndDifferentRanks || skipOnInterRankAndSameRank);

2
DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/DDR3dbphaseentry.h → DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/DDR3dbphaseentry.h
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@@ -1,7 +1,7 @@
#pragma once
#include "dbphaseentryIF.h"
#include "businessObjects/dramTimeDependencies/dbEntries/dbphaseentryIF.h"
class DDR3DBPhaseEntry : public DBPhaseEntryIF {
public:

64
DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/DDR3TimeDependencies.cpp → DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/DDR3TimeDependencies.cpp
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@@ -45,7 +45,27 @@ void DDR3TimeDependencies::mInitializeValues() {
burstLength = mMemspecJson["memarchitecturespec"].toObject()["burstLength"].toInt();
dataRate = mMemspecJson["memarchitecturespec"].toObject()["dataRate"].toInt();
mPools.insert({"FAW", {4, {"ACT"}}});
mPools.insert({
"CMD_BUS", {
1, {
"ACT",
"RD",
"WR",
"PREPB",
"RDA",
"WRA",
"REFAB",
"PREAB",
"PDEP",
"PDXP",
"SREFEN",
"SREFEX",
"PDEA",
"PDXA",
}
}
});
mPools.insert({"NAW", {4, {"ACT"}}});
tRP = tCK * mMemspecJson["memtimingspec"].toObject()["RP"].toInt();
tRAS = tCK * mMemspecJson["memtimingspec"].toObject()["RAS"].toInt();
@@ -123,7 +143,8 @@ DependencyMap DDR3TimeDependencies::mSpecializedGetDependencies() const {
{tXP, "PDXP", DependencyType::IntraRank, "tXP"},
{tRFC, "REFAB", DependencyType::IntraRank, "tRFC"},
{tXS, "SREFEX", DependencyType::IntraRank, "tXS"},
{tFAW, "FAW_POOL", DependencyType::IntraRank, "tFAW"}
{tCK, "CMD_BUS_POOL", DependencyType::InterRank, "CMD_BUS"},
{tFAW, "NAW_POOL", DependencyType::IntraRank, "tFAW"},
}
)
);
@@ -143,7 +164,8 @@ DependencyMap DDR3TimeDependencies::mSpecializedGetDependencies() const {
{tBURST + tRTRS, "RD", DependencyType::InterRank, "tBURST + tRTRS"},
{tBURST + tRTRS, "RDA", DependencyType::InterRank, "tBURST + tRTRS"},
{tWRRD_R, "WR", DependencyType::InterRank, "tWRRD_R"},
{tWRRD_R, "WRA", DependencyType::InterRank, "tWRRD_R"}
{tWRRD_R, "WRA", DependencyType::InterRank, "tWRRD_R"},
{tCK, "CMD_BUS_POOL", DependencyType::InterRank, "CMD_BUS"},
}
)
);
@@ -164,7 +186,8 @@ DependencyMap DDR3TimeDependencies::mSpecializedGetDependencies() const {
{tBURST + tRTRS, "RD", DependencyType::InterRank, "tBURST + tRTRS"},
{tBURST + tRTRS, "RDA", DependencyType::InterRank, "tBURST + tRTRS"},
{tWRRD_R, "WR", DependencyType::InterRank, "tWRRD_R"},
{tWRRD_R, "WRA", DependencyType::InterRank, "tWRRD_R"}
{tWRRD_R, "WRA", DependencyType::InterRank, "tWRRD_R"},
{tCK, "CMD_BUS_POOL", DependencyType::InterRank, "CMD_BUS"},
}
)
);
@@ -184,7 +207,8 @@ DependencyMap DDR3TimeDependencies::mSpecializedGetDependencies() const {
{tRDWR_R, "RD", DependencyType::InterRank, "tRDWR_R"},
{tRDWR_R, "RDA", DependencyType::InterRank, "tRDWR_R"},
{tBURST + tRTRS, "WR", DependencyType::InterRank, "tBURST + tRTRS"},
{tBURST + tRTRS, "WRA", DependencyType::InterRank, "tBURST + tRTRS"}
{tBURST + tRTRS, "WRA", DependencyType::InterRank, "tBURST + tRTRS"},
{tCK, "CMD_BUS_POOL", DependencyType::InterRank, "CMD_BUS"},
}
)
);
@@ -204,7 +228,8 @@ DependencyMap DDR3TimeDependencies::mSpecializedGetDependencies() const {
{tRDWR_R, "RD", DependencyType::InterRank, "tRDWR_R"},
{tRDWR_R, "RDA", DependencyType::InterRank, "tRDWR_R"},
{tBURST + tRTRS, "WR", DependencyType::InterRank, "tBURST + tRTRS"},
{tBURST + tRTRS, "WRA", DependencyType::InterRank, "tBURST + tRTRS"}
{tBURST + tRTRS, "WRA", DependencyType::InterRank, "tBURST + tRTRS"},
{tCK, "CMD_BUS_POOL", DependencyType::InterRank, "CMD_BUS"},
}
)
);
@@ -217,7 +242,8 @@ DependencyMap DDR3TimeDependencies::mSpecializedGetDependencies() const {
{tRAS, "ACT", DependencyType::IntraBank, "tRAS"},
{tAL + tRTP, "RD", DependencyType::IntraBank, "tAL + tRTP"},
{tWRPRE, "WR", DependencyType::IntraBank, "tWRPRE"},
{tXP, "PDXA", DependencyType::IntraRank, "tXP"}
{tXP, "PDXA", DependencyType::IntraRank, "tXP"},
{tCK, "CMD_BUS_POOL", DependencyType::InterRank, "CMD_BUS"},
}
)
);
@@ -232,7 +258,8 @@ DependencyMap DDR3TimeDependencies::mSpecializedGetDependencies() const {
{tAL + tRTP, "RDA", DependencyType::IntraRank, "tAL + tRTP"},
{tWRPRE, "WR", DependencyType::IntraRank, "tWRPRE"},
{tWRPRE, "WRA", DependencyType::IntraRank, "tWRPRE"},
{tXP, "PDXA", DependencyType::IntraRank, "tXP"}
{tXP, "PDXA", DependencyType::IntraRank, "tXP"},
{tCK, "CMD_BUS_POOL", DependencyType::InterRank, "CMD_BUS"},
}
)
);
@@ -249,7 +276,8 @@ DependencyMap DDR3TimeDependencies::mSpecializedGetDependencies() const {
{tRP, "PREAB", DependencyType::IntraRank, "tRP"},
{tXP, "PDXP", DependencyType::IntraRank, "tXP"},
{tRFC, "REFAB", DependencyType::IntraRank, "tRFC"},
{tXS, "SREFEX", DependencyType::IntraRank, "tXS"}
{tXS, "SREFEX", DependencyType::IntraRank, "tXS"},
{tCK, "CMD_BUS_POOL", DependencyType::InterRank, "CMD_BUS"},
}
)
);
@@ -265,7 +293,8 @@ DependencyMap DDR3TimeDependencies::mSpecializedGetDependencies() const {
{tWRPDEN, "WR", DependencyType::IntraRank, "tWRPDEN"},
{tWRAPDEN, "WRA", DependencyType::IntraRank, "tWRAPDEN"},
{tPRPDEN, "PREPB", DependencyType::IntraRank, "tPRPDEN"},
{tCKE, "PDXA", DependencyType::IntraRank, "tCKE"}
{tCKE, "PDXA", DependencyType::IntraRank, "tCKE"},
{tCK, "CMD_BUS_POOL", DependencyType::InterRank, "CMD_BUS"},
}
)
);
@@ -275,7 +304,8 @@ DependencyMap DDR3TimeDependencies::mSpecializedGetDependencies() const {
forward_as_tuple("PDXA"),
forward_as_tuple(
initializer_list<TimeDependency>{
{tPD, "PDEA", DependencyType::IntraRank, "tPD"}
{tPD, "PDEA", DependencyType::IntraRank, "tPD"},
{tCK, "CMD_BUS_POOL", DependencyType::InterRank, "CMD_BUS"},
}
)
);
@@ -292,7 +322,8 @@ DependencyMap DDR3TimeDependencies::mSpecializedGetDependencies() const {
{tPRPDEN, "PREAB", DependencyType::IntraRank, "tPRPDEN"},
{tCKE, "PDXP", DependencyType::IntraRank, "tCKE"},
{tREFPDEN, "REFAB", DependencyType::IntraRank, "tREFPDEN"},
{tXS, "SREFEX", DependencyType::IntraRank, "tXS"}
{tXS, "SREFEX", DependencyType::IntraRank, "tXS"},
{tCK, "CMD_BUS_POOL", DependencyType::InterRank, "CMD_BUS"},
}
)
);
@@ -302,7 +333,8 @@ DependencyMap DDR3TimeDependencies::mSpecializedGetDependencies() const {
forward_as_tuple("PDXP"),
forward_as_tuple(
initializer_list<TimeDependency>{
{tPD, "PDEP", DependencyType::IntraRank, "tPD"}
{tPD, "PDEP", DependencyType::IntraRank, "tPD"},
{tCK, "CMD_BUS_POOL", DependencyType::InterRank, "CMD_BUS"},
}
)
);
@@ -319,7 +351,8 @@ DependencyMap DDR3TimeDependencies::mSpecializedGetDependencies() const {
{tRP, "PREAB", DependencyType::IntraRank, "tRP"},
{tXP, "PDXP", DependencyType::IntraRank, "tXP"},
{tRFC, "REFAB", DependencyType::IntraRank, "tRFC"},
{tXS, "SREFEX", DependencyType::IntraRank, "tXS"}
{tXS, "SREFEX", DependencyType::IntraRank, "tXS"},
{tCK, "CMD_BUS_POOL", DependencyType::InterRank, "CMD_BUS"},
}
)
);
@@ -329,7 +362,8 @@ DependencyMap DDR3TimeDependencies::mSpecializedGetDependencies() const {
forward_as_tuple("SREFEX"),
forward_as_tuple(
initializer_list<TimeDependency>{
{tCKESR, "SREFEN", DependencyType::IntraRank, "tCKESR"}
{tCKESR, "SREFEN", DependencyType::IntraRank, "tCKESR"},
{tCK, "CMD_BUS_POOL", DependencyType::InterRank, "CMD_BUS"},
}
)
);

2
DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/DDR3TimeDependencies.h → DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/DDR3TimeDependencies.h
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@@ -35,7 +35,7 @@
#pragma once
#include "dramtimedependenciesIF.h"
#include "businessObjects/dramTimeDependencies/deviceDependencies/dramtimedependenciesIF.h"
class DDR3TimeDependencies final : public DRAMTimeDependenciesIF {
public:

15
DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/phasedependenciestracker.cpp
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@@ -187,7 +187,7 @@ PhaseDependenciesTracker::mCalculateDependencies(const std::shared_ptr<Configura
// Tries to find all timing dependencies for each phase on the trace
PoolControllerMap poolController = deviceConfig->getPools();
for (size_t i = 1; i < phases.size(); i++) {
// NAW dependencies variables reset
// Pool dependencies variables reset
poolController.clear();
// Auxiliary variables
@@ -257,19 +257,6 @@ PhaseDependenciesTracker::mCalculateDependencies(const std::shared_ptr<Configura
}
// TODO remove this - must be substituted by the pool controller
// Capture command bus dependencies
if (timeDiff == deviceConfig->getClk()) {
entries.emplace_back(DBDependencyEntry{
phase->id,
phase->phaseName,
PhaseDependency::dependencyTypeName(DependencyType::InterRank),
"CommandBus",
otherPhase->id,
otherPhase->phaseName
});
}
}
poolController.merge(entries);