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Made timings const.

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This commit is contained in:
Lukas Steiner
2020-05-29 17:38:55 +02:00
parent fdf4ce913e
commit 7d0f001763
21 changed files with 811 additions and 881 deletions
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30
DRAMSys/library/src/common/TlmRecorder.cpp
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@@ -363,21 +363,21 @@ void TlmRecorder::insertCommandLengths()
{
MemSpec *memSpec = Configuration::getInstance().memSpec;
sqlite3_bind_int(insertCommandLengthsStatement, 1, memSpec->commandLengthInCycles[Command::ACT]);
sqlite3_bind_int(insertCommandLengthsStatement, 2, memSpec->commandLengthInCycles[Command::PRE]);
sqlite3_bind_int(insertCommandLengthsStatement, 3, memSpec->commandLengthInCycles[Command::PREA]);
sqlite3_bind_int(insertCommandLengthsStatement, 4, memSpec->commandLengthInCycles[Command::RD]);
sqlite3_bind_int(insertCommandLengthsStatement, 5, memSpec->commandLengthInCycles[Command::RDA]);
sqlite3_bind_int(insertCommandLengthsStatement, 6, memSpec->commandLengthInCycles[Command::WR]);
sqlite3_bind_int(insertCommandLengthsStatement, 7, memSpec->commandLengthInCycles[Command::WRA]);
sqlite3_bind_int(insertCommandLengthsStatement, 8, memSpec->commandLengthInCycles[Command::REFA]);
sqlite3_bind_int(insertCommandLengthsStatement, 9, memSpec->commandLengthInCycles[Command::REFB]);
sqlite3_bind_int(insertCommandLengthsStatement, 10, memSpec->commandLengthInCycles[Command::PDEA]);
sqlite3_bind_int(insertCommandLengthsStatement, 11, memSpec->commandLengthInCycles[Command::PDXA]);
sqlite3_bind_int(insertCommandLengthsStatement, 12, memSpec->commandLengthInCycles[Command::PDEP]);
sqlite3_bind_int(insertCommandLengthsStatement, 13, memSpec->commandLengthInCycles[Command::PDXP]);
sqlite3_bind_int(insertCommandLengthsStatement, 14, memSpec->commandLengthInCycles[Command::SREFEN]);
sqlite3_bind_int(insertCommandLengthsStatement, 15, memSpec->commandLengthInCycles[Command::SREFEX]);
sqlite3_bind_int(insertCommandLengthsStatement, 1, memSpec->getCommandLength(Command::ACT) / memSpec->tCK);
sqlite3_bind_int(insertCommandLengthsStatement, 2, memSpec->getCommandLength(Command::PRE) / memSpec->tCK);
sqlite3_bind_int(insertCommandLengthsStatement, 3, memSpec->getCommandLength(Command::PREA) / memSpec->tCK);
sqlite3_bind_int(insertCommandLengthsStatement, 4, memSpec->getCommandLength(Command::RD) / memSpec->tCK);
sqlite3_bind_int(insertCommandLengthsStatement, 5, memSpec->getCommandLength(Command::RDA) / memSpec->tCK);
sqlite3_bind_int(insertCommandLengthsStatement, 6, memSpec->getCommandLength(Command::WR) / memSpec->tCK);
sqlite3_bind_int(insertCommandLengthsStatement, 7, memSpec->getCommandLength(Command::WRA) / memSpec->tCK);
sqlite3_bind_int(insertCommandLengthsStatement, 8, memSpec->getCommandLength(Command::REFA) / memSpec->tCK);
sqlite3_bind_int(insertCommandLengthsStatement, 9, memSpec->getCommandLength(Command::REFB) / memSpec->tCK);
sqlite3_bind_int(insertCommandLengthsStatement, 10, memSpec->getCommandLength(Command::PDEA) / memSpec->tCK);
sqlite3_bind_int(insertCommandLengthsStatement, 11, memSpec->getCommandLength(Command::PDXA) / memSpec->tCK);
sqlite3_bind_int(insertCommandLengthsStatement, 12, memSpec->getCommandLength(Command::PDEP) / memSpec->tCK);
sqlite3_bind_int(insertCommandLengthsStatement, 13, memSpec->getCommandLength(Command::PDXP) / memSpec->tCK);
sqlite3_bind_int(insertCommandLengthsStatement, 14, memSpec->getCommandLength(Command::SREFEN) / memSpec->tCK);
sqlite3_bind_int(insertCommandLengthsStatement, 15, memSpec->getCommandLength(Command::SREFEX) / memSpec->tCK);
executeSqlStatement(insertCommandLengthsStatement);
}

36
DRAMSys/library/src/configuration/memspec/MemSpec.cpp
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@@ -43,25 +43,27 @@
using namespace tlm;
using json = nlohmann::json;
MemSpec::MemSpec(json &memspec)
MemSpec::MemSpec(json &memspec, unsigned numberOfRanks, unsigned banksPerRank,
unsigned groupsPerRank, unsigned banksPerGroup,
unsigned numberOfBanks, unsigned numberOfBankGroups)
: numberOfRanks(numberOfRanks),
banksPerRank(banksPerRank),
groupsPerRank(groupsPerRank),
banksPerGroup(banksPerGroup),
numberOfBanks(numberOfBanks),
numberOfBankGroups(numberOfBankGroups),
numberOfRows(parseUint(memspec["memarchitecturespec"]["nbrOfRows"],"nbrOfRows")),
numberOfColumns(parseUint(memspec["memarchitecturespec"]["nbrOfColumns"],"nbrOfColumns")),
burstLength(parseUint(memspec["memarchitecturespec"]["burstLength"],"burstLength")),
dataRate(parseUint(memspec["memarchitecturespec"]["dataRate"],"dataRate")),
bitWidth(parseUint(memspec["memarchitecturespec"]["width"],"width")),
fCKMHz(parseUdouble(memspec["memtimingspec"]["clkMhz"], "clkMhz")),
tCK(sc_time(1.0 / fCKMHz, SC_US)),
burstDuration(tCK * (burstLength / dataRate)),
memoryId(parseString(memspec["memoryId"], "memoryId")),
memoryType(parseString(memspec["memoryType"], "memoryType"))
{
commandLengthInCycles = std::vector<unsigned>(numberOfCommands(), 1);
memoryId = parseString(memspec["memoryId"], "memoryId");
memoryType = parseString(memspec["memoryType"], "memoryType");
// MemArchitecture
burstLength = parseUint(memspec["memarchitecturespec"]["burstLength"],"burstLength");
dataRate = parseUint(memspec["memarchitecturespec"]["dataRate"],"dataRate");
numberOfRows = parseUint(memspec["memarchitecturespec"]["nbrOfRows"],"nbrOfRows");
numberOfColumns = parseUint(memspec["memarchitecturespec"]["nbrOfColumns"],"nbrOfColumns");
bitWidth = parseUint(memspec["memarchitecturespec"]["width"],"width");
// Clock
fCKMHz = parseUdouble(memspec["memtimingspec"]["clkMhz"], "clkMhz");
tCK = sc_time(1.0 / fCKMHz, SC_US);
burstDuration = tCK * (burstLength / dataRate);
}
sc_time MemSpec::getCommandLength(Command command) const

50
DRAMSys/library/src/configuration/memspec/MemSpec.h
View File

@@ -47,10 +47,26 @@
class MemSpec
{
protected:
MemSpec(nlohmann::json &);
public:
unsigned numberOfRanks;
unsigned banksPerRank;
unsigned groupsPerRank;
unsigned banksPerGroup;
unsigned numberOfBanks;
unsigned numberOfBankGroups;
unsigned numberOfRows;
unsigned numberOfColumns;
unsigned burstLength;
unsigned dataRate;
unsigned bitWidth;
// Clock
double fCKMHz;
sc_time tCK;
std::string memoryId;
std::string memoryType;
virtual ~MemSpec() {}
virtual sc_time getRefreshIntervalAB() const = 0;
@@ -61,30 +77,14 @@ public:
sc_time getCommandLength(Command) const;
std::string memoryId = "not defined.";
std::string memoryType = "not defined.";
protected:
MemSpec(nlohmann::json &memspec, unsigned numberOfRanks, unsigned banksPerRank,
unsigned groupsPerRank, unsigned banksPerGroup,
unsigned numberOfBanks, unsigned numberOfBankGroups);
unsigned int numberOfRanks;
unsigned int numberOfBankGroups;
unsigned int numberOfBanks;
unsigned int numberOfRows;
unsigned int numberOfColumns;
unsigned int burstLength;
unsigned int dataRate;
unsigned int bitWidth;
unsigned int banksPerRank;
unsigned int banksPerGroup;
unsigned int groupsPerRank;
// Clock
double fCKMHz;
sc_time tCK;
sc_time burstDuration;
// Command lengths on bus, usually one clock cycle
// Command lengths in cycles on bus, usually one clock cycle
std::vector<unsigned> commandLengthInCycles;
sc_time burstDuration;
};
#endif // MEMSPEC_H

104
DRAMSys/library/src/configuration/memspec/MemSpecDDR3.cpp
View File

@@ -38,61 +38,55 @@
using namespace tlm;
using json = nlohmann::json;
MemSpecDDR3::MemSpecDDR3(json &memspec) : MemSpec(memspec)
{
std::string arch = "memarchitecturespec";
numberOfRanks = parseUint(memspec[arch]["nbrOfRanks"],"nbrOfRanks");
banksPerRank = parseUint(memspec[arch]["nbrOfBanks"],"nbrOfBanks");
groupsPerRank = 1;
banksPerGroup = banksPerRank / groupsPerRank;
numberOfBanks = banksPerRank * numberOfRanks;
numberOfBankGroups = groupsPerRank * numberOfRanks;
// MemTimings specific for DDR3
std::string timings = "memtimingspec";
tCKE = tCK * parseUint(memspec[timings]["CKE"], "CKE");
tPD = tCKE;
tCKESR = tCK * parseUint(memspec[timings]["CKESR"], "CKESR");
tCKE = tCK * parseUint(memspec[timings]["DQSCK"], "DQSCK");
tRAS = tCK * parseUint(memspec[timings]["RAS"], "RAS");
tRC = tCK * parseUint(memspec[timings]["RC"], "RC");
tRCD = tCK * parseUint(memspec[timings]["RCD"], "RCD");
tRL = tCK * parseUint(memspec[timings]["RL"], "RL");
tRTP = tCK * parseUint(memspec[timings]["RTP"], "RTP");
tWL = tCK * parseUint(memspec[timings]["WL"], "WL");
tWR = tCK * parseUint(memspec[timings]["WR"], "WR");
tXP = tCK * parseUint(memspec[timings]["XP"], "XP");
tXS = tCK * parseUint(memspec[timings]["XS"], "XS");
tCCD = tCK * parseUint(memspec[timings]["CCD"], "CCD");
tFAW = tCK * parseUint(memspec[timings]["FAW"], "FAW");
tREFI = tCK * parseUint(memspec[timings]["REFI"], "REFI");
tRFC = tCK * parseUint(memspec[timings]["RFC"], "RFC");
tRP = tCK * parseUint(memspec[timings]["RP"], "RP");
tRRD = tCK * parseUint(memspec[timings]["RRD"], "RRD");
tWTR = tCK * parseUint(memspec[timings]["WTR"], "WTR");
tAL = tCK * parseUint(memspec[timings]["AL"], "AL");
tXPDLL = tCK * parseUint(memspec[timings]["XPDLL"], "XPDLL");
tXSDLL = tCK * parseUint(memspec[timings]["XSDLL"], "XSDLL");
tACTPDEN = tCK * parseUint(memspec[timings]["ACTPDEN"], "ACTPDEN");
tPRPDEN = tCK * parseUint(memspec[timings]["PRPDEN"], "PRPDEN");
tREFPDEN = tCK * parseUint(memspec[timings]["REFPDEN"], "REFPDEN");
tRTRS = tCK * parseUint(memspec[timings]["RTRS"], "RTRS");
// Currents and voltages
std::string power = "mempowerspec";
iDD0 = parseUdouble(memspec[power]["idd0"], "idd0");
iDD2N = parseUdouble(memspec[power]["idd2n"], "idd2n");
iDD3N = parseUdouble(memspec[power]["idd3n"], "idd3n");
iDD4R = parseUdouble(memspec[power]["idd4r"], "idd4r");
iDD4W = parseUdouble(memspec[power]["idd4w"], "idd4w");
iDD5 = parseUdouble(memspec[power]["idd5"], "idd5");
iDD6 = parseUdouble(memspec[power]["idd6"], "idd6");
vDD = parseUdouble(memspec[power]["vdd"], "vdd");
iDD2P0 = parseUdouble(memspec[power]["idd2p0"], "idd2p0");
iDD2P1 = parseUdouble(memspec[power]["idd2p1"], "idd2p1");
iDD3P0 = parseUdouble(memspec[power]["idd3p0"], "idd3p0");
iDD3P1 = parseUdouble(memspec[power]["idd3p1"], "idd3p1");
}
MemSpecDDR3::MemSpecDDR3(json &memspec)
: MemSpec(memspec,
parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"),
parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks"),
1,
parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks"),
parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks")
* parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"),
parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks")),
tCKE (tCK * parseUint(memspec["memtimingspec"]["CKE"], "CKE")),
tPD (tCKE),
tCKESR (tCK * parseUint(memspec["memtimingspec"]["CKESR"], "CKESR")),
tDQSCK (tCK * parseUint(memspec["memtimingspec"]["DQSCK"], "DQSCK")),
tRAS (tCK * parseUint(memspec["memtimingspec"]["RAS"], "RAS")),
tRC (tCK * parseUint(memspec["memtimingspec"]["RC"], "RC")),
tRCD (tCK * parseUint(memspec["memtimingspec"]["RCD"], "RCD")),
tRL (tCK * parseUint(memspec["memtimingspec"]["RL"], "RL")),
tRTP (tCK * parseUint(memspec["memtimingspec"]["RTP"], "RTP")),
tWL (tCK * parseUint(memspec["memtimingspec"]["WL"], "WL")),
tWR (tCK * parseUint(memspec["memtimingspec"]["WR"], "WR")),
tXP (tCK * parseUint(memspec["memtimingspec"]["XP"], "XP")),
tXS (tCK * parseUint(memspec["memtimingspec"]["XS"], "XS")),
tCCD (tCK * parseUint(memspec["memtimingspec"]["CCD"], "CCD")),
tFAW (tCK * parseUint(memspec["memtimingspec"]["FAW"], "FAW")),
tREFI (tCK * parseUint(memspec["memtimingspec"]["REFI"], "REFI")),
tRFC (tCK * parseUint(memspec["memtimingspec"]["RFC"], "RFC")),
tRP (tCK * parseUint(memspec["memtimingspec"]["RP"], "RP")),
tRRD (tCK * parseUint(memspec["memtimingspec"]["RRD"], "RRD")),
tWTR (tCK * parseUint(memspec["memtimingspec"]["WTR"], "WTR")),
tAL (tCK * parseUint(memspec["memtimingspec"]["AL"], "AL")),
tXPDLL (tCK * parseUint(memspec["memtimingspec"]["XPDLL"], "XPDLL")),
tXSDLL (tCK * parseUint(memspec["memtimingspec"]["XSDLL"], "XSDLL")),
tACTPDEN (tCK * parseUint(memspec["memtimingspec"]["ACTPDEN"], "ACTPDEN")),
tPRPDEN (tCK * parseUint(memspec["memtimingspec"]["PRPDEN"], "PRPDEN")),
tREFPDEN (tCK * parseUint(memspec["memtimingspec"]["REFPDEN"], "REFPDEN")),
tRTRS (tCK * parseUint(memspec["memtimingspec"]["RTRS"], "RTRS")),
iDD0 (parseUdouble(memspec["mempowerspec"]["idd0"], "idd0")),
iDD2N (parseUdouble(memspec["mempowerspec"]["idd2n"], "idd2n")),
iDD3N (parseUdouble(memspec["mempowerspec"]["idd3n"], "idd3n")),
iDD4R (parseUdouble(memspec["mempowerspec"]["idd4r"], "idd4r")),
iDD4W (parseUdouble(memspec["mempowerspec"]["idd4w"], "idd4w")),
iDD5 (parseUdouble(memspec["mempowerspec"]["idd5"], "idd5")),
iDD6 (parseUdouble(memspec["mempowerspec"]["idd6"], "idd6")),
vDD (parseUdouble(memspec["mempowerspec"]["vdd"], "vdd")),
iDD2P0 (parseUdouble(memspec["mempowerspec"]["idd2p0"], "idd2p0")),
iDD2P1 (parseUdouble(memspec["mempowerspec"]["idd2p1"], "idd2p1")),
iDD3P0 (parseUdouble(memspec["mempowerspec"]["idd3p0"], "idd3p0")),
iDD3P1 (parseUdouble(memspec["mempowerspec"]["idd3p1"], "idd3p1"))
{}
sc_time MemSpecDDR3::getRefreshIntervalAB() const
{

80
DRAMSys/library/src/configuration/memspec/MemSpecDDR3.h
View File

@@ -42,50 +42,50 @@
class MemSpecDDR3 final : public MemSpec
{
public:
MemSpecDDR3(nlohmann::json &);
MemSpecDDR3(nlohmann::json &memspec);
// Memspec Variables:
sc_time tCKE;
sc_time tPD;
sc_time tCKESR;
sc_time tRAS;
sc_time tRC;
sc_time tRCD;
sc_time tRL;
sc_time tRTP;
sc_time tWL;
sc_time tWR;
sc_time tXP;
sc_time tXS;
sc_time tREFI;
sc_time tRFC;
sc_time tRP;
sc_time tDQSCK;
sc_time tCCD;
sc_time tFAW;
sc_time tRRD;
sc_time tWTR;
sc_time tXPDLL;
sc_time tXSDLL;
sc_time tAL;
sc_time tACTPDEN;
sc_time tPRPDEN;
sc_time tREFPDEN;
sc_time tRTRS;
const sc_time tCKE;
const sc_time tPD;
const sc_time tCKESR;
const sc_time tRAS;
const sc_time tRC;
const sc_time tRCD;
const sc_time tRL;
const sc_time tRTP;
const sc_time tWL;
const sc_time tWR;
const sc_time tXP;
const sc_time tXS;
const sc_time tREFI;
const sc_time tRFC;
const sc_time tRP;
const sc_time tDQSCK;
const sc_time tCCD;
const sc_time tFAW;
const sc_time tRRD;
const sc_time tWTR;
const sc_time tXPDLL;
const sc_time tXSDLL;
const sc_time tAL;
const sc_time tACTPDEN;
const sc_time tPRPDEN;
const sc_time tREFPDEN;
const sc_time tRTRS;
// Currents and Voltages:
double iDD0;
double iDD2N;
double iDD3N;
double iDD4R;
double iDD4W;
double iDD5;
double iDD6;
double vDD;
double iDD2P0;
double iDD2P1;
double iDD3P0;
double iDD3P1;
const double iDD0;
const double iDD2N;
const double iDD3N;
const double iDD4R;
const double iDD4W;
const double iDD5;
const double iDD6;
const double vDD;
const double iDD2P0;
const double iDD2P1;
const double iDD3P0;
const double iDD3P1;
virtual sc_time getRefreshIntervalAB() const override;
virtual sc_time getRefreshIntervalPB() const override;

144
DRAMSys/library/src/configuration/memspec/MemSpecDDR4.cpp
View File

@@ -39,85 +39,71 @@
using namespace tlm;
using json = nlohmann::json;
MemSpecDDR4::MemSpecDDR4(json &memspec) : MemSpec(memspec)
{
std::string arch = "memarchitecturespec";
numberOfRanks = parseUint(memspec[arch]["nbrOfRanks"],"nbrOfRanks");
banksPerRank = parseUint(memspec[arch]["nbrOfBanks"],"nbrOfBanks");
groupsPerRank = parseUint(memspec[arch]["nbrOfBankGroups"], "nbrOfBankGroups");
banksPerGroup = banksPerRank / groupsPerRank;
numberOfBanks = banksPerRank * numberOfRanks;
numberOfBankGroups = groupsPerRank * numberOfRanks;
// MemTimings specific for DDR4
std::string timings = "memtimingspec";
tCKE = tCK * parseUint(memspec[timings]["CKE"], "CKE");
tPD = tCKE;
tCKESR = tCK * parseUint(memspec[timings]["CKESR"], "CKESR");
tDQSCK = tCK * parseUint(memspec[timings]["DQSCK"], "DQSCK");
tRAS = tCK * parseUint(memspec[timings]["RAS"], "RAS");
tRC = tCK * parseUint(memspec[timings]["RC"], "RC");
tRCD = tCK * parseUint(memspec[timings]["RCD"], "RCD");
tRL = tCK * parseUint(memspec[timings]["RL"], "RL");
tRTP = tCK * parseUint(memspec[timings]["RTP"], "RTP");
tWL = tCK * parseUint(memspec[timings]["WL"], "WL");
tWR = tCK * parseUint(memspec[timings]["WR"], "WR");
tXP = tCK * parseUint(memspec[timings]["XP"], "XP");
tXS = tCK * parseUint(memspec[timings]["XS"], "XS");
tCCD_S = tCK * parseUint(memspec[timings]["CCD_S"], "CCD_S");
tCCD_L = tCK * parseUint(memspec[timings]["CCD_L"], "CCD_L");
tFAW = tCK * parseUint(memspec[timings]["FAW"], "FAW");
unsigned refreshMode = Configuration::getInstance().refreshMode;
if (refreshMode == 1)
{
tREFI = tCK * parseUint(memspec[timings]["REFI"], "REFI");
tRFC = tCK * parseUint(memspec[timings]["RFC"], "RFC");
}
else if (refreshMode == 2)
{
tREFI = tCK * (parseUint(memspec[timings]["REFI"], "REFI") / 2);
tRFC = tCK * parseUint(memspec[timings]["RFC2"], "RFC2");
}
else if (refreshMode == 4)
{
tREFI = tCK * (parseUint(memspec[timings]["REFI"], "REFI") / 2);
tRFC = tCK * parseUint(memspec[timings]["RFC4"], "RFC4");
}
else
SC_REPORT_FATAL("ConfigurationLoader", "Refresh Mode not supported");
tRP = tCK * parseUint(memspec[timings]["RP"], "RP");
tRRD_S = tCK * parseUint(memspec[timings]["RRD_S"], "RRD_S");
tRRD_L = tCK * parseUint(memspec[timings]["RRD_L"], "RRD_L");
tWTR_S = tCK * parseUint(memspec[timings]["WTR_S"], "WTR_S");
tWTR_L = tCK * parseUint(memspec[timings]["WTR_L"], "WTR_L");
tAL = tCK * parseUint(memspec[timings]["AL"], "AL");
tXPDLL = tCK * parseUint(memspec[timings]["XPDLL"], "XPDLL");
tXSDLL = tCK * parseUint(memspec[timings]["XSDLL"], "XSDLL");
tACTPDEN = tCK * parseUint(memspec[timings]["ACTPDEN"], "ACTPDEN");
tPRPDEN = tCK * parseUint(memspec[timings]["PRPDEN"], "PRPDEN");
tREFPDEN = tCK * parseUint(memspec[timings]["REFPDEN"], "REFPDEN");
tRTRS = tCK * parseUint(memspec[timings]["RTRS"], "RTRS");
// Currents and voltages
std::string power = "mempowerspec";
iDD0 = parseUdouble(memspec[power]["idd0"], "idd0");
iDD2N = parseUdouble(memspec[power]["idd2n"], "idd2n");
iDD3N = parseUdouble(memspec[power]["idd3n"], "idd3n");
iDD4R = parseUdouble(memspec[power]["idd4r"], "idd4r");
iDD4W = parseUdouble(memspec[power]["idd4w"], "idd4w");
iDD5 = parseUdouble(memspec[power]["idd5"], "idd5");
iDD6 = parseUdouble(memspec[power]["idd6"], "idd6");
vDD = parseUdouble(memspec[power]["vdd"], "vdd");
iDD02 = parseUdouble(memspec[power]["idd02"], "idd02");
iDD2P0 = parseUdouble(memspec[power]["idd2p0"], "idd2p0");
iDD2P1 = parseUdouble(memspec[power]["idd2p1"], "idd2p1");
iDD3P0 = parseUdouble(memspec[power]["idd3p0"], "idd3p0");
iDD3P1 = parseUdouble(memspec[power]["idd3p1"], "idd3p1");
iDD62 = parseUdouble(memspec[power]["idd62"], "idd62");
vDD2 = parseUdouble(memspec[power]["vdd2"], "vdd2");
}
MemSpecDDR4::MemSpecDDR4(json &memspec)
: MemSpec(memspec,
parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"),
parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks"),
parseUint(memspec["memarchitecturespec"]["nbrOfBankGroups"], "nbrOfBankGroups"),
parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks")
/ parseUint(memspec["memarchitecturespec"]["nbrOfBankGroups"], "nbrOfBankGroups"),
parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks")
* parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"),
parseUint(memspec["memarchitecturespec"]["nbrOfBankGroups"], "nbrOfBankGroups")
* parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks")),
tCKE (tCK * parseUint(memspec["memtimingspec"]["CKE"], "CKE")),
tPD (tCKE),
tCKESR (tCK * parseUint(memspec["memtimingspec"]["CKESR"], "CKESR")),
tDQSCK (tCK * parseUint(memspec["memtimingspec"]["DQSCK"], "DQSCK")),
tRAS (tCK * parseUint(memspec["memtimingspec"]["RAS"], "RAS")),
tRC (tCK * parseUint(memspec["memtimingspec"]["RC"], "RC")),
tRCD (tCK * parseUint(memspec["memtimingspec"]["RCD"], "RCD")),
tRL (tCK * parseUint(memspec["memtimingspec"]["RL"], "RL")),
tRTP (tCK * parseUint(memspec["memtimingspec"]["RTP"], "RTP")),
tWL (tCK * parseUint(memspec["memtimingspec"]["WL"], "WL")),
tWR (tCK * parseUint(memspec["memtimingspec"]["WR"], "WR")),
tXP (tCK * parseUint(memspec["memtimingspec"]["XP"], "XP")),
tXS (tCK * parseUint(memspec["memtimingspec"]["XS"], "XS")),
tCCD_S (tCK * parseUint(memspec["memtimingspec"]["CCD_S"], "CCD_S")),
tCCD_L (tCK * parseUint(memspec["memtimingspec"]["CCD_L"], "CCD_L")),
tFAW (tCK * parseUint(memspec["memtimingspec"]["FAW"], "FAW")),
tREFI ((Configuration::getInstance().refreshMode == 1) ?
(tCK * parseUint(memspec["memtimingspec"]["REFI"], "REFI")) :
((Configuration::getInstance().refreshMode == 2) ?
(tCK * (parseUint(memspec["memtimingspec"]["REFI"], "REFI") / 2)) :
(tCK * (parseUint(memspec["memtimingspec"]["REFI"], "REFI") / 4)))),
tRFC ((Configuration::getInstance().refreshMode == 1) ?
(tCK * parseUint(memspec["memtimingspec"]["RFC"], "RFC")) :
((Configuration::getInstance().refreshMode == 2) ?
(tCK * (parseUint(memspec["memtimingspec"]["RFC2"], "RFC2") / 2)) :
(tCK * (parseUint(memspec["memtimingspec"]["RFC4"], "RFC4") / 4)))),
tRP (tCK * parseUint(memspec["memtimingspec"]["RP"], "RP")),
tRRD_S (tCK * parseUint(memspec["memtimingspec"]["RRD_S"], "RRD_S")),
tRRD_L (tCK * parseUint(memspec["memtimingspec"]["RRD_L"], "RRD_L")),
tWTR_S (tCK * parseUint(memspec["memtimingspec"]["WTR_S"], "WTR_S")),
tWTR_L (tCK * parseUint(memspec["memtimingspec"]["WTR_L"], "WTR_L")),
tAL (tCK * parseUint(memspec["memtimingspec"]["AL"], "AL")),
tXPDLL (tCK * parseUint(memspec["memtimingspec"]["XPDLL"], "XPDLL")),
tXSDLL (tCK * parseUint(memspec["memtimingspec"]["XSDLL"], "XSDLL")),
tACTPDEN (tCK * parseUint(memspec["memtimingspec"]["ACTPDEN"], "ACTPDEN")),
tPRPDEN (tCK * parseUint(memspec["memtimingspec"]["PRPDEN"], "PRPDEN")),
tREFPDEN (tCK * parseUint(memspec["memtimingspec"]["REFPDEN"], "REFPDEN")),
tRTRS (tCK * parseUint(memspec["memtimingspec"]["RTRS"], "RTRS")),
iDD0 (parseUdouble(memspec["mempowerspec"]["idd0"], "idd0")),
iDD2N (parseUdouble(memspec["mempowerspec"]["idd2n"], "idd2n")),
iDD3N (parseUdouble(memspec["mempowerspec"]["idd3n"], "idd3n")),
iDD4R (parseUdouble(memspec["mempowerspec"]["idd4r"], "idd4r")),
iDD4W (parseUdouble(memspec["mempowerspec"]["idd4w"], "idd4w")),
iDD5 (parseUdouble(memspec["mempowerspec"]["idd5"], "idd5")),
iDD6 (parseUdouble(memspec["mempowerspec"]["idd6"], "idd6")),
vDD (parseUdouble(memspec["mempowerspec"]["vdd"], "vdd")),
iDD02 (parseUdouble(memspec["mempowerspec"]["idd02"], "idd02")),
iDD2P0 (parseUdouble(memspec["mempowerspec"]["idd2p0"], "idd2p0")),
iDD2P1 (parseUdouble(memspec["mempowerspec"]["idd2p1"], "idd2p1")),
iDD3P0 (parseUdouble(memspec["mempowerspec"]["idd3p0"], "idd3p0")),
iDD3P1 (parseUdouble(memspec["mempowerspec"]["idd3p1"], "idd3p1")),
iDD62 (parseUdouble(memspec["mempowerspec"]["idd62"], "idd62")),
vDD2 (parseUdouble(memspec["mempowerspec"]["vdd2"], "vdd2"))
{}
sc_time MemSpecDDR4::getRefreshIntervalAB() const
{

92
DRAMSys/library/src/configuration/memspec/MemSpecDDR4.h
View File

@@ -42,56 +42,56 @@
class MemSpecDDR4 final : public MemSpec
{
public:
MemSpecDDR4(nlohmann::json &);
MemSpecDDR4(nlohmann::json &memspec);
// Memspec Variables:
sc_time tCKE; // min time between pdx and pde
sc_time tPD; // min time in pdn
sc_time tCKESR; // min time in sref
sc_time tRAS; // active-time (act -> pre same bank)
sc_time tRC; // RAS-cycle-time (min time bw 2 succesive ACT to same bank)
sc_time tRCD; // act -> read/write
sc_time tRL; // read latency (read command start to data strobe)
sc_time tRTP; // read to precharge
sc_time tWL; // write latency
sc_time tWR; // write recovery (write to precharge)
sc_time tXP; // min delay to row access command after pdnpx pdnax
sc_time tXS; // min delay to row access command after srefx
sc_time tREFI;
sc_time tRFC;
sc_time tRP;
sc_time tDQSCK;
sc_time tCCD_S;
sc_time tCCD_L;
sc_time tFAW;
sc_time tRRD_S;
sc_time tRRD_L;
sc_time tWTR_S;
sc_time tWTR_L;
sc_time tAL;
sc_time tXPDLL;
sc_time tXSDLL;
sc_time tACTPDEN;
sc_time tPRPDEN;
sc_time tREFPDEN;
sc_time tRTRS;
const sc_time tCKE;
const sc_time tPD;
const sc_time tCKESR;
const sc_time tRAS;
const sc_time tRC;
const sc_time tRCD;
const sc_time tRL;
const sc_time tRTP;
const sc_time tWL;
const sc_time tWR;
const sc_time tXP;
const sc_time tXS;
const sc_time tREFI;
const sc_time tRFC;
const sc_time tRP;
const sc_time tDQSCK;
const sc_time tCCD_S;
const sc_time tCCD_L;
const sc_time tFAW;
const sc_time tRRD_S;
const sc_time tRRD_L;
const sc_time tWTR_S;
const sc_time tWTR_L;
const sc_time tAL;
const sc_time tXPDLL;
const sc_time tXSDLL;
const sc_time tACTPDEN;
const sc_time tPRPDEN;
const sc_time tREFPDEN;
const sc_time tRTRS;
// Currents and Voltages:
double iDD0;
double iDD2N;
double iDD3N;
double iDD4R;
double iDD4W;
double iDD5;
double iDD6;
double vDD;
double iDD02;
double iDD2P0;
double iDD2P1;
double iDD3P0;
double iDD3P1;
double iDD62;
double vDD2;
const double iDD0;
const double iDD2N;
const double iDD3N;
const double iDD4R;
const double iDD4W;
const double iDD5;
const double iDD6;
const double vDD;
const double iDD02;
const double iDD2P0;
const double iDD2P1;
const double iDD3P0;
const double iDD3P1;
const double iDD62;
const double vDD2;
virtual sc_time getRefreshIntervalPB() const override;
virtual sc_time getRefreshIntervalAB() const override;

101
DRAMSys/library/src/configuration/memspec/MemSpecGDDR5.cpp
View File

@@ -38,61 +38,52 @@
using namespace tlm;
using json = nlohmann::json;
MemSpecGDDR5::MemSpecGDDR5(json &memspec) : MemSpec(memspec)
{
// MemArchitecture
std::string arch = "memarchitecturespec";
numberOfRanks = parseUint(memspec[arch]["nbrOfRanks"], "nbrOfRanks");
banksPerRank = parseUint(memspec[arch]["nbrOfBanks"], "nbrOfBanks");
groupsPerRank = parseUint(memspec[arch]["nbrOfBankGroups"], "nbrOfBankGroups");
banksPerGroup = banksPerRank / groupsPerRank;
numberOfBanks = banksPerRank * numberOfRanks;
numberOfBankGroups = groupsPerRank * numberOfRanks;
// MemTimings specific for GDDR5
std::string timings = "memtimingspec";
tRP = tCK * parseUint(memspec[timings]["RP"], "RP");
tRAS = tCK * parseUint(memspec[timings]["RAS"], "RAS");
tRC = tCK * parseUint(memspec[timings]["RC"], "RC");
tRCDRD = tCK * parseUint(memspec[timings]["RCDRD"], "RCDRD");
tRCDWR = tCK * parseUint(memspec[timings]["RCDWR"], "RCDWR");
tRTP = tCK * parseUint(memspec[timings]["RTP"], "RTP");
tRRDS = tCK * parseUint(memspec[timings]["RRDS"], "RRDS");
tRRDL = tCK * parseUint(memspec[timings]["RRDL"], "RRDL");
tCCDS = tCK * parseUint(memspec[timings]["CCDS"], "CCDS");
tCCDL = tCK * parseUint(memspec[timings]["CCDL"], "CCDL");
tCL = tCK * parseUint(memspec[timings]["CL"], "CL");
tWCK2CKPIN = tCK * parseUint(memspec[timings]["WCK2CKPIN"], "WCK2CKPIN");
tWCK2CK = tCK * parseUint(memspec[timings]["WCK2CK"], "WCK2CK");
tWCK2DQO = tCK * parseUint(memspec[timings]["WCK2DQO"], "WCK2DQO");
tRTW = tCK * parseUint(memspec[timings]["RTW"], "RTW");
tWL = tCK * parseUint(memspec[timings]["WL"], "WL");
tWCK2DQI = tCK * parseUint(memspec[timings]["WCK2DQI"], "WCK2DQI");
tWR = tCK * parseUint(memspec[timings]["WR"], "WR");
tWTRS = tCK * parseUint(memspec[timings]["WTRS"], "WTRS");
tWTRL = tCK * parseUint(memspec[timings]["WTRL"], "WTRL");
tCKE = tCK * parseUint(memspec[timings]["CKE"], "CKE");
tPD = tCK * parseUint(memspec[timings]["PD"], "PD");
tXPN = tCK * parseUint(memspec[timings]["XPN"], "XPN");
tREFI = tCK * parseUint(memspec[timings]["REFI"], "REFI");
tREFIPB = tCK * parseUint(memspec[timings]["REFIPB"], "REFIPB");
tRFC = tCK * parseUint(memspec[timings]["RFC"], "RFC");
tRFCPB = tCK * parseUint(memspec[timings]["RFCPB"], "RFCPB");
tRREFD = tCK * parseUint(memspec[timings]["RREFD"], "RREFD");
tXS = tCK * parseUint(memspec[timings]["XS"], "XS");
tFAW = tCK * parseUint(memspec[timings]["FAW"], "FAW");
t32AW = tCK * parseUint(memspec[timings]["32AW"], "32AW");
// tRDSRE = tCL + tWCK2CKPIN + tWCK2CK
// + tWCK2DQO + burstLength / dataRate * tCK;
// tWRSRE = tWL + tWCK2CKPIN + tWCK2CK
// + tWCK2DQI + burstLength / dataRate * tCK;
tPPD = tCK * parseUint(memspec[timings]["PPD"], "PPD");
tLK = tCK * parseUint(memspec[timings]["LK"], "LK");
tRTRS = tCK * parseUint(memspec[timings]["RTRS"], "RTRS");
// Currents and voltages
// TODO: to be completed
}
MemSpecGDDR5::MemSpecGDDR5(json &memspec)
: MemSpec(memspec,
parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"),
parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks"),
parseUint(memspec["memarchitecturespec"]["nbrOfBankGroups"], "nbrOfBankGroups"),
parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks")
/ parseUint(memspec["memarchitecturespec"]["nbrOfBankGroups"], "nbrOfBankGroups"),
parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks")
* parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"),
parseUint(memspec["memarchitecturespec"]["nbrOfBankGroups"], "nbrOfBankGroups")
* parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks")),
tRP (tCK * parseUint(memspec["memtimingspec"]["RP"], "RP")),
tRAS (tCK * parseUint(memspec["memtimingspec"]["RAS"], "RAS")),
tRC (tCK * parseUint(memspec["memtimingspec"]["RC"], "RC")),
tRCDRD (tCK * parseUint(memspec["memtimingspec"]["RCDRD"], "RCDRD")),
tRCDWR (tCK * parseUint(memspec["memtimingspec"]["RCDWR"], "RCDWR")),
tRTP (tCK * parseUint(memspec["memtimingspec"]["RTP"], "RTP")),
tRRDS (tCK * parseUint(memspec["memtimingspec"]["RRDS"], "RRDS")),
tRRDL (tCK * parseUint(memspec["memtimingspec"]["RRDL"], "RRDL")),
tCCDS (tCK * parseUint(memspec["memtimingspec"]["CCDS"], "CCDS")),
tCCDL (tCK * parseUint(memspec["memtimingspec"]["CCDL"], "CCDL")),
tCL (tCK * parseUint(memspec["memtimingspec"]["CL"], "CL")),
tWCK2CKPIN (tCK * parseUint(memspec["memtimingspec"]["WCK2CKPIN"], "WCK2CKPIN")),
tWCK2CK (tCK * parseUint(memspec["memtimingspec"]["WCK2CK"], "WCK2CK")),
tWCK2DQO (tCK * parseUint(memspec["memtimingspec"]["WCK2DQO"], "WCK2DQO")),
tRTW (tCK * parseUint(memspec["memtimingspec"]["RTW"], "RTW")),
tWL (tCK * parseUint(memspec["memtimingspec"]["WL"], "WL")),
tWCK2DQI (tCK * parseUint(memspec["memtimingspec"]["WCK2DQI"], "WCK2DQI")),
tWR (tCK * parseUint(memspec["memtimingspec"]["WR"], "WR")),
tWTRS (tCK * parseUint(memspec["memtimingspec"]["WTRS"], "WTRS")),
tWTRL (tCK * parseUint(memspec["memtimingspec"]["WTRL"], "WTRL")),
tCKE (tCK * parseUint(memspec["memtimingspec"]["CKE"], "CKE")),
tPD (tCK * parseUint(memspec["memtimingspec"]["PD"], "PD")),
tXPN (tCK * parseUint(memspec["memtimingspec"]["XPN"], "XPN")),
tREFI (tCK * parseUint(memspec["memtimingspec"]["REFI"], "REFI")),
tREFIPB (tCK * parseUint(memspec["memtimingspec"]["REFIPB"], "REFIPB")),
tRFC (tCK * parseUint(memspec["memtimingspec"]["RFC"], "RFC")),
tRFCPB (tCK * parseUint(memspec["memtimingspec"]["RFCPB"], "RFCPB")),
tRREFD (tCK * parseUint(memspec["memtimingspec"]["RREFD"], "RREFD")),
tXS (tCK * parseUint(memspec["memtimingspec"]["XS"], "XS")),
tFAW (tCK * parseUint(memspec["memtimingspec"]["FAW"], "FAW")),
t32AW (tCK * parseUint(memspec["memtimingspec"]["32AW"], "32AW")),
tPPD (tCK * parseUint(memspec["memtimingspec"]["PPD"], "PPD")),
tLK (tCK * parseUint(memspec["memtimingspec"]["LK"], "LK")),
tRTRS (tCK * parseUint(memspec["memtimingspec"]["RTRS"], "RTRS"))
{}
sc_time MemSpecGDDR5::getRefreshIntervalAB() const
{

70
DRAMSys/library/src/configuration/memspec/MemSpecGDDR5.h
View File

@@ -42,45 +42,45 @@
class MemSpecGDDR5 final : public MemSpec
{
public:
MemSpecGDDR5(nlohmann::json &);
MemSpecGDDR5(nlohmann::json &memspec);
// Memspec Variables:
sc_time tRP;
sc_time tRAS;
sc_time tRC;
sc_time tRCDRD;
sc_time tRCDWR;
sc_time tRTP;
sc_time tRRDS;
sc_time tRRDL;
sc_time tCCDS;
sc_time tCCDL;
sc_time tCL;
sc_time tWCK2CKPIN;
sc_time tWCK2CK;
sc_time tWCK2DQO;
sc_time tRTW;
sc_time tWL;
sc_time tWCK2DQI;
sc_time tWR;
sc_time tWTRS;
sc_time tWTRL;
sc_time tCKE;
sc_time tPD;
sc_time tXPN;
sc_time tREFI;
sc_time tREFIPB;
sc_time tRFC;
sc_time tRFCPB;
sc_time tRREFD;
sc_time tXS;
sc_time tFAW;
sc_time t32AW;
const sc_time tRP;
const sc_time tRAS;
const sc_time tRC;
const sc_time tRCDRD;
const sc_time tRCDWR;
const sc_time tRTP;
const sc_time tRRDS;
const sc_time tRRDL;
const sc_time tCCDS;
const sc_time tCCDL;
const sc_time tCL;
const sc_time tWCK2CKPIN;
const sc_time tWCK2CK;
const sc_time tWCK2DQO;
const sc_time tRTW;
const sc_time tWL;
const sc_time tWCK2DQI;
const sc_time tWR;
const sc_time tWTRS;
const sc_time tWTRL;
const sc_time tCKE;
const sc_time tPD;
const sc_time tXPN;
const sc_time tREFI;
const sc_time tREFIPB;
const sc_time tRFC;
const sc_time tRFCPB;
const sc_time tRREFD;
const sc_time tXS;
const sc_time tFAW;
const sc_time t32AW;
// sc_time tRDSRE; // = tCL + tWCK2CKPIN + tWCK2CK + tWCK2DQO + BurstLength / DataRate * tCK;
// sc_time tWRSRE; // = tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI + BurstLength / DataRate * tCK;
sc_time tPPD;
sc_time tLK;
sc_time tRTRS;
const sc_time tPPD;
const sc_time tLK;
const sc_time tRTRS;
// Currents and Voltages:
// TODO: to be completed

101
DRAMSys/library/src/configuration/memspec/MemSpecGDDR5X.cpp
View File

@@ -38,61 +38,52 @@
using namespace tlm;
using json = nlohmann::json;
MemSpecGDDR5X::MemSpecGDDR5X(json &memspec) : MemSpec(memspec)
{
// MemArchitecture
std::string arch = "memarchitecturespec";
numberOfRanks = parseUint(memspec[arch]["nbrOfRanks"], "nbrOfRanks");
banksPerRank = parseUint(memspec[arch]["nbrOfBanks"], "nbrOfBanks");
groupsPerRank = parseUint(memspec[arch]["nbrOfBankGroups"], "nbrOfBankGroups");
banksPerGroup = banksPerRank / groupsPerRank;
numberOfBanks = banksPerRank * numberOfRanks;
numberOfBankGroups = groupsPerRank * numberOfRanks;
// MemTimings specific for GDDR5X
std::string timings = "memtimingspec";
tRP = tCK * parseUint(memspec[timings]["RP"], "RP");
tRAS = tCK * parseUint(memspec[timings]["RAS"], "RAS");
tRC = tCK * parseUint(memspec[timings]["RC"], "RC");
tRCDRD = tCK * parseUint(memspec[timings]["RCDRD"], "RCDRD");
tRCDWR = tCK * parseUint(memspec[timings]["RCDWR"], "RCDWR");
tRTP = tCK * parseUint(memspec[timings]["RTP"], "RTP");
tRRDS = tCK * parseUint(memspec[timings]["RRDS"], "RRDS");
tRRDL = tCK * parseUint(memspec[timings]["RRDL"], "RRDL");
tCCDS = tCK * parseUint(memspec[timings]["CCDS"], "CCDS");
tCCDL = tCK * parseUint(memspec[timings]["CCDL"], "CCDL");
tRL = tCK * parseUint(memspec[timings]["RL"], "RL");
tWCK2CKPIN = tCK * parseUint(memspec[timings]["WCK2CKPIN"], "WCK2CKPIN");
tWCK2CK = tCK * parseUint(memspec[timings]["WCK2CK"], "WCK2CK");
tWCK2DQO = tCK * parseUint(memspec[timings]["WCK2DQO"], "WCK2DQO");
tRTW = tCK * parseUint(memspec[timings]["RTW"], "RTW");
tWL = tCK * parseUint(memspec[timings]["WL"], "WL");
tWCK2DQI = tCK * parseUint(memspec[timings]["WCK2DQI"], "WCK2DQI");
tWR = tCK * parseUint(memspec[timings]["WR"], "WR");
tWTRS = tCK * parseUint(memspec[timings]["WTRS"], "WTRS");
tWTRL = tCK * parseUint(memspec[timings]["WTRL"], "WTRL");
tCKE = tCK * parseUint(memspec[timings]["CKE"], "CKE");
tPD = tCK * parseUint(memspec[timings]["PD"], "PD");
tXP = tCK * parseUint(memspec[timings]["XP"], "XP");
tREFI = tCK * parseUint(memspec[timings]["REFI"], "REFI");
tREFIPB = tCK * parseUint(memspec[timings]["REFIPB"], "REFIPB");
tRFC = tCK * parseUint(memspec[timings]["RFC"], "RFC");
tRFCPB = tCK * parseUint(memspec[timings]["RFCPB"], "RFCPB");
tRREFD = tCK * parseUint(memspec[timings]["RREFD"], "RREFD");
tXS = tCK * parseUint(memspec[timings]["XS"], "XS");
tFAW = tCK * parseUint(memspec[timings]["FAW"], "FAW");
t32AW = tCK * parseUint(memspec[timings]["32AW"], "32AW");
// tRDSRE = tRL + tWCK2CKPIN + tWCK2CK
// + tWCK2DQO + burstLength / dataRate * tCK;
// tWRSRE = tWL + tWCK2CKPIN + tWCK2CK
// + tWCK2DQI + burstLength / dataRate * tCK;
tPPD = tCK * parseUint(memspec[timings]["PPD"], "PPD");
tLK = tCK * parseUint(memspec[timings]["LK"], "LK");
tRTRS = tCK * parseUint(memspec[timings]["RTRS"], "RTRS");
// Currents and voltages
// TODO: to be completed
}
MemSpecGDDR5X::MemSpecGDDR5X(json &memspec)
: MemSpec(memspec,
parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"),
parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks"),
parseUint(memspec["memarchitecturespec"]["nbrOfBankGroups"], "nbrOfBankGroups"),
parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks")
/ parseUint(memspec["memarchitecturespec"]["nbrOfBankGroups"], "nbrOfBankGroups"),
parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks")
* parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"),
parseUint(memspec["memarchitecturespec"]["nbrOfBankGroups"], "nbrOfBankGroups")
* parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks")),
tRP (tCK * parseUint(memspec["memtimingspec"]["RP"], "RP")),
tRAS (tCK * parseUint(memspec["memtimingspec"]["RAS"], "RAS")),
tRC (tCK * parseUint(memspec["memtimingspec"]["RC"], "RC")),
tRCDRD (tCK * parseUint(memspec["memtimingspec"]["RCDRD"], "RCDRD")),
tRCDWR (tCK * parseUint(memspec["memtimingspec"]["RCDWR"], "RCDWR")),
tRTP (tCK * parseUint(memspec["memtimingspec"]["RTP"], "RTP")),
tRRDS (tCK * parseUint(memspec["memtimingspec"]["RRDS"], "RRDS")),
tRRDL (tCK * parseUint(memspec["memtimingspec"]["RRDL"], "RRDL")),
tCCDS (tCK * parseUint(memspec["memtimingspec"]["CCDS"], "CCDS")),
tCCDL (tCK * parseUint(memspec["memtimingspec"]["CCDL"], "CCDL")),
tRL (tCK * parseUint(memspec["memtimingspec"]["CL"], "CL")),
tWCK2CKPIN (tCK * parseUint(memspec["memtimingspec"]["WCK2CKPIN"], "WCK2CKPIN")),
tWCK2CK (tCK * parseUint(memspec["memtimingspec"]["WCK2CK"], "WCK2CK")),
tWCK2DQO (tCK * parseUint(memspec["memtimingspec"]["WCK2DQO"], "WCK2DQO")),
tRTW (tCK * parseUint(memspec["memtimingspec"]["RTW"], "RTW")),
tWL (tCK * parseUint(memspec["memtimingspec"]["WL"], "WL")),
tWCK2DQI (tCK * parseUint(memspec["memtimingspec"]["WCK2DQI"], "WCK2DQI")),
tWR (tCK * parseUint(memspec["memtimingspec"]["WR"], "WR")),
tWTRS (tCK * parseUint(memspec["memtimingspec"]["WTRS"], "WTRS")),
tWTRL (tCK * parseUint(memspec["memtimingspec"]["WTRL"], "WTRL")),
tCKE (tCK * parseUint(memspec["memtimingspec"]["CKE"], "CKE")),
tPD (tCK * parseUint(memspec["memtimingspec"]["PD"], "PD")),
tXP (tCK * parseUint(memspec["memtimingspec"]["XP"], "XP")),
tREFI (tCK * parseUint(memspec["memtimingspec"]["REFI"], "REFI")),
tREFIPB (tCK * parseUint(memspec["memtimingspec"]["REFIPB"], "REFIPB")),
tRFC (tCK * parseUint(memspec["memtimingspec"]["RFC"], "RFC")),
tRFCPB (tCK * parseUint(memspec["memtimingspec"]["RFCPB"], "RFCPB")),
tRREFD (tCK * parseUint(memspec["memtimingspec"]["RREFD"], "RREFD")),
tXS (tCK * parseUint(memspec["memtimingspec"]["XS"], "XS")),
tFAW (tCK * parseUint(memspec["memtimingspec"]["FAW"], "FAW")),
t32AW (tCK * parseUint(memspec["memtimingspec"]["32AW"], "32AW")),
tPPD (tCK * parseUint(memspec["memtimingspec"]["PPD"], "PPD")),
tLK (tCK * parseUint(memspec["memtimingspec"]["LK"], "LK")),
tRTRS (tCK * parseUint(memspec["memtimingspec"]["RTRS"], "RTRS"))
{}
sc_time MemSpecGDDR5X::getRefreshIntervalAB() const
{

70
DRAMSys/library/src/configuration/memspec/MemSpecGDDR5X.h
View File

@@ -42,45 +42,45 @@
class MemSpecGDDR5X final : public MemSpec
{
public:
MemSpecGDDR5X(nlohmann::json &);
MemSpecGDDR5X(nlohmann::json &memspec);
// Memspec Variables:
sc_time tRP;
sc_time tRAS;
sc_time tRC;
sc_time tRCDRD;
sc_time tRCDWR;
sc_time tRTP;
sc_time tRRDS;
sc_time tRRDL;
sc_time tCCDS;
sc_time tCCDL;
sc_time tRL;
sc_time tWCK2CKPIN;
sc_time tWCK2CK;
sc_time tWCK2DQO;
sc_time tRTW;
sc_time tWL;
sc_time tWCK2DQI;
sc_time tWR;
sc_time tWTRS;
sc_time tWTRL;
sc_time tCKE;
sc_time tPD;
sc_time tXP;
sc_time tREFI;
sc_time tREFIPB;
sc_time tRFC;
sc_time tRFCPB;
sc_time tRREFD;
sc_time tXS;
sc_time tFAW;
sc_time t32AW;
const sc_time tRP;
const sc_time tRAS;
const sc_time tRC;
const sc_time tRCDRD;
const sc_time tRCDWR;
const sc_time tRTP;
const sc_time tRRDS;
const sc_time tRRDL;
const sc_time tCCDS;
const sc_time tCCDL;
const sc_time tRL;
const sc_time tWCK2CKPIN;
const sc_time tWCK2CK;
const sc_time tWCK2DQO;
const sc_time tRTW;
const sc_time tWL;
const sc_time tWCK2DQI;
const sc_time tWR;
const sc_time tWTRS;
const sc_time tWTRL;
const sc_time tCKE;
const sc_time tPD;
const sc_time tXP;
const sc_time tREFI;
const sc_time tREFIPB;
const sc_time tRFC;
const sc_time tRFCPB;
const sc_time tRREFD;
const sc_time tXS;
const sc_time tFAW;
const sc_time t32AW;
// sc_time tRDSRE; // = tCL + tWCK2CKPIN + tWCK2CK + tWCK2DQO + BurstLength / DataRate * tCK;
// sc_time tWRSRE; // = tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI + BurstLength / DataRate * tCK;
sc_time tPPD;
sc_time tLK;
sc_time tRTRS;
const sc_time tPPD;
const sc_time tLK;
const sc_time tRTRS;
// Currents and Voltages:
// TODO: to be completed

105
DRAMSys/library/src/configuration/memspec/MemSpecGDDR6.cpp
View File

@@ -38,63 +38,54 @@
using namespace tlm;
using json = nlohmann::json;
MemSpecGDDR6::MemSpecGDDR6(json &memspec) : MemSpec(memspec)
{
// MemArchitecture
std::string arch = "memarchitecturespec";
numberOfRanks = parseUint(memspec[arch]["nbrOfRanks"], "nbrOfRanks");
banksPerRank = parseUint(memspec[arch]["nbrOfBanks"], "nbrOfBanks");
groupsPerRank = parseUint(memspec[arch]["nbrOfBankGroups"], "nbrOfBankGroups");
banksPerGroup = banksPerRank / groupsPerRank;
numberOfBanks = banksPerRank * numberOfRanks;
numberOfBankGroups = groupsPerRank * numberOfRanks;
// MemTimings specific for GDDR6
std::string timings = "memtimingspec";
tRP = tCK * parseUint(memspec[timings]["RP"], "RP");
tRAS = tCK * parseUint(memspec[timings]["RAS"], "RAS");
tRC = tCK * parseUint(memspec[timings]["RC"], "RC");
tRCDRD = tCK * parseUint(memspec[timings]["RCDRD"], "RCDRD");
tRCDWR = tCK * parseUint(memspec[timings]["RCDWR"], "RCDWR");
tRTP = tCK * parseUint(memspec[timings]["RTP"], "RTP");
tRRDS = tCK * parseUint(memspec[timings]["RRDS"], "RRDS");
tRRDL = tCK * parseUint(memspec[timings]["RRDL"], "RRDL");
tCCDS = tCK * parseUint(memspec[timings]["CCDS"], "CCDS");
tCCDL = tCK * parseUint(memspec[timings]["CCDL"], "CCDL");
tRL = tCK * parseUint(memspec[timings]["RL"], "RL");
tWCK2CKPIN = tCK * parseUint(memspec[timings]["WCK2CKPIN"], "WCK2CKPIN");
tWCK2CK = tCK * parseUint(memspec[timings]["WCK2CK"], "WCK2CK");
tWCK2DQO = tCK * parseUint(memspec[timings]["WCK2DQO"], "WCK2DQO");
tRTW = tCK * parseUint(memspec[timings]["RTW"], "RTW");
tWL = tCK * parseUint(memspec[timings]["WL"], "WL");
tWCK2DQI = tCK * parseUint(memspec[timings]["WCK2DQI"], "WCK2DQI");
tWR = tCK * parseUint(memspec[timings]["WR"], "WR");
tWTRS = tCK * parseUint(memspec[timings]["WTRS"], "WTRS");
tWTRL = tCK * parseUint(memspec[timings]["WTRL"], "WTRL");
tPD = tCK * parseUint(memspec[timings]["PD"], "PD");
tCKESR = tCK * parseUint(memspec[timings]["CKESR"], "CKESR");
tXP = tCK * parseUint(memspec[timings]["XP"], "XP");
tREFI = tCK * parseUint(memspec[timings]["REFI"], "REFI");
tREFIPB = tCK * parseUint(memspec[timings]["REFIPB"], "REFIPB");
tRFC = tCK * parseUint(memspec[timings]["RFC"], "RFC");
tRFCPB = tCK * parseUint(memspec[timings]["RFCPB"], "RFCPB");
tRREFD = tCK * parseUint(memspec[timings]["RREFD"], "RREFD");
tXS = tCK * parseUint(memspec[timings]["XS"], "XS");
tFAW = tCK * parseUint(memspec[timings]["FAW"], "FAW");
// tRDSRE = tRL + tWCK2CKPIN + tWCK2CK
// + tWCK2DQO + burstLength / dataRate * tCK;
// tWRSRE = tWL + tWCK2CKPIN + tWCK2CK
// + tWCK2DQI + burstLength / dataRate * tCK;
tPPD = tCK * parseUint(memspec[timings]["PPD"], "PPD");
tLK = tCK * parseUint(memspec[timings]["LK"], "LK");
tACTPDE = tCK * parseUint(memspec[timings]["ACTPDE"], "ACTPDE");
tPREPDE = tCK * parseUint(memspec[timings]["PREPDE"], "PREPDE");
tREFPDE = tCK * parseUint(memspec[timings]["REFPDE"], "REFPDE");
tRTRS = tCK * parseUint(memspec[timings]["RTRS"], "RTRS");
// Currents and voltages
// TODO: to be completed
}
MemSpecGDDR6::MemSpecGDDR6(json &memspec)
: MemSpec(memspec,
parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"),
parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks"),
parseUint(memspec["memarchitecturespec"]["nbrOfBankGroups"], "nbrOfBankGroups"),
parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks")
/ parseUint(memspec["memarchitecturespec"]["nbrOfBankGroups"], "nbrOfBankGroups"),
parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks")
* parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"),
parseUint(memspec["memarchitecturespec"]["nbrOfBankGroups"], "nbrOfBankGroups")
* parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks")),
tRP (tCK * parseUint(memspec["memtimingspec"]["RP"], "RP")),
tRAS (tCK * parseUint(memspec["memtimingspec"]["RAS"], "RAS")),
tRC (tCK * parseUint(memspec["memtimingspec"]["RC"], "RC")),
tRCDRD (tCK * parseUint(memspec["memtimingspec"]["RCDRD"], "RCDRD")),
tRCDWR (tCK * parseUint(memspec["memtimingspec"]["RCDWR"], "RCDWR")),
tRTP (tCK * parseUint(memspec["memtimingspec"]["RTP"], "RTP")),
tRRDS (tCK * parseUint(memspec["memtimingspec"]["RRDS"], "RRDS")),
tRRDL (tCK * parseUint(memspec["memtimingspec"]["RRDL"], "RRDL")),
tCCDS (tCK * parseUint(memspec["memtimingspec"]["CCDS"], "CCDS")),
tCCDL (tCK * parseUint(memspec["memtimingspec"]["CCDL"], "CCDL")),
tRL (tCK * parseUint(memspec["memtimingspec"]["RL"], "RL")),
tWCK2CKPIN (tCK * parseUint(memspec["memtimingspec"]["WCK2CKPIN"], "WCK2CKPIN")),
tWCK2CK (tCK * parseUint(memspec["memtimingspec"]["WCK2CK"], "WCK2CK")),
tWCK2DQO (tCK * parseUint(memspec["memtimingspec"]["WCK2DQO"], "WCK2DQO")),
tRTW (tCK * parseUint(memspec["memtimingspec"]["RTW"], "RTW")),
tWL (tCK * parseUint(memspec["memtimingspec"]["WL"], "WL")),
tWCK2DQI (tCK * parseUint(memspec["memtimingspec"]["WCK2DQI"], "WCK2DQI")),
tWR (tCK * parseUint(memspec["memtimingspec"]["WR"], "WR")),
tWTRS (tCK * parseUint(memspec["memtimingspec"]["WTRS"], "WTRS")),
tWTRL (tCK * parseUint(memspec["memtimingspec"]["WTRL"], "WTRL")),
tPD (tCK * parseUint(memspec["memtimingspec"]["PD"], "PD")),
tCKESR (tCK * parseUint(memspec["memtimingspec"]["CKESR"], "CKESR")),
tXP (tCK * parseUint(memspec["memtimingspec"]["XP"], "XP")),
tREFI (tCK * parseUint(memspec["memtimingspec"]["REFI"], "REFI")),
tREFIPB (tCK * parseUint(memspec["memtimingspec"]["REFIPB"], "REFIPB")),
tRFC (tCK * parseUint(memspec["memtimingspec"]["RFC"], "RFC")),
tRFCPB (tCK * parseUint(memspec["memtimingspec"]["RFCPB"], "RFCPB")),
tRREFD (tCK * parseUint(memspec["memtimingspec"]["RREFD"], "RREFD")),
tXS (tCK * parseUint(memspec["memtimingspec"]["XS"], "XS")),
tFAW (tCK * parseUint(memspec["memtimingspec"]["FAW"], "FAW")),
tPPD (tCK * parseUint(memspec["memtimingspec"]["PPD"], "PPD")),
tLK (tCK * parseUint(memspec["memtimingspec"]["LK"], "LK")),
tACTPDE (tCK * parseUint(memspec["memtimingspec"]["ACTPDE"], "ACTPDE")),
tPREPDE (tCK * parseUint(memspec["memtimingspec"]["PREPDE"], "PREPDE")),
tREFPDE (tCK * parseUint(memspec["memtimingspec"]["REFPDE"], "REFPDE")),
tRTRS (tCK * parseUint(memspec["memtimingspec"]["RTRS"], "RTRS"))
{}
sc_time MemSpecGDDR6::getRefreshIntervalAB() const
{

75
DRAMSys/library/src/configuration/memspec/MemSpecGDDR6.h
View File

@@ -41,47 +41,48 @@
struct MemSpecGDDR6 final : public MemSpec
{
MemSpecGDDR6(nlohmann::json &);
public:
MemSpecGDDR6(nlohmann::json &memspec);
// Memspec Variables:
sc_time tRP;
sc_time tRAS;
sc_time tRC;
sc_time tRCDRD;
sc_time tRCDWR;
sc_time tRTP;
sc_time tRRDS;
sc_time tRRDL;
sc_time tCCDS;
sc_time tCCDL;
sc_time tRL;
sc_time tWCK2CKPIN;
sc_time tWCK2CK;
sc_time tWCK2DQO;
sc_time tRTW;
sc_time tWL;
sc_time tWCK2DQI;
sc_time tWR;
sc_time tWTRS;
sc_time tWTRL;
sc_time tPD;
sc_time tCKESR;
sc_time tXP;
sc_time tREFI;
sc_time tREFIPB;
sc_time tRFC;
sc_time tRFCPB;
sc_time tRREFD;
sc_time tXS;
sc_time tFAW;
const sc_time tRP;
const sc_time tRAS;
const sc_time tRC;
const sc_time tRCDRD;
const sc_time tRCDWR;
const sc_time tRTP;
const sc_time tRRDS;
const sc_time tRRDL;
const sc_time tCCDS;
const sc_time tCCDL;
const sc_time tRL;
const sc_time tWCK2CKPIN;
const sc_time tWCK2CK;
const sc_time tWCK2DQO;
const sc_time tRTW;
const sc_time tWL;
const sc_time tWCK2DQI;
const sc_time tWR;
const sc_time tWTRS;
const sc_time tWTRL;
const sc_time tPD;
const sc_time tCKESR;
const sc_time tXP;
const sc_time tREFI;
const sc_time tREFIPB;
const sc_time tRFC;
const sc_time tRFCPB;
const sc_time tRREFD;
const sc_time tXS;
const sc_time tFAW;
// sc_time tRDSRE; // = tCL + tWCK2CKPIN + tWCK2CK + tWCK2DQO + BurstLength / DataRate * tCK;
// sc_time tWRSRE; // = tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI + BurstLength / DataRate * tCK;
sc_time tPPD;
sc_time tLK;
sc_time tACTPDE;
sc_time tPREPDE;
sc_time tREFPDE;
sc_time tRTRS;
const sc_time tPPD;
const sc_time tLK;
const sc_time tACTPDE;
const sc_time tPREPDE;
const sc_time tREFPDE;
const sc_time tRTRS;
// Currents and Voltages:
// TODO: to be completed

85
DRAMSys/library/src/configuration/memspec/MemSpecHBM2.cpp
View File

@@ -38,53 +38,48 @@
using namespace tlm;
using json = nlohmann::json;
MemSpecHBM2::MemSpecHBM2(json &memspec) : MemSpec(memspec)
MemSpecHBM2::MemSpecHBM2(json &memspec)
: MemSpec(memspec,
parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"),
parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks"),
parseUint(memspec["memarchitecturespec"]["nbrOfBankGroups"], "nbrOfBankGroups"),
parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks")
/ parseUint(memspec["memarchitecturespec"]["nbrOfBankGroups"], "nbrOfBankGroups"),
parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks")
* parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"),
parseUint(memspec["memarchitecturespec"]["nbrOfBankGroups"], "nbrOfBankGroups")
* parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks")),
tDQSCK (tCK * parseUint(memspec["memtimingspec"]["DQSCK"], "DQSCK")),
tRC (tCK * parseUint(memspec["memtimingspec"]["RC"], "RC")),
tRAS (tCK * parseUint(memspec["memtimingspec"]["RAS"], "RAS")),
tRCDRD (tCK * parseUint(memspec["memtimingspec"]["RCDRD"], "RCDRD")),
tRCDWR (tCK * parseUint(memspec["memtimingspec"]["RCDWR"], "RCDWR")),
tRRDL (tCK * parseUint(memspec["memtimingspec"]["RRDL"], "RRDL")),
tRRDS (tCK * parseUint(memspec["memtimingspec"]["RRDS"], "RRDS")),
tFAW (tCK * parseUint(memspec["memtimingspec"]["FAW"], "FAW")),
tRTP (tCK * parseUint(memspec["memtimingspec"]["RTP"], "RTP")),
tRP (tCK * parseUint(memspec["memtimingspec"]["RP"], "RP")),
tRL (tCK * parseUint(memspec["memtimingspec"]["RL"], "RL")),
tWL (tCK * parseUint(memspec["memtimingspec"]["WL"], "WL")),
tPL (tCK * parseUint(memspec["memtimingspec"]["PL"], "PL")),
tWR (tCK * parseUint(memspec["memtimingspec"]["WR"], "WR")),
tCCDL (tCK * parseUint(memspec["memtimingspec"]["CCDL"], "CCDL")),
tCCDS (tCK * parseUint(memspec["memtimingspec"]["CCDS"], "CCDS")),
tWTRL (tCK * parseUint(memspec["memtimingspec"]["WTRL"], "WTRL")),
tWTRS (tCK * parseUint(memspec["memtimingspec"]["WTRS"], "WTRS")),
tRTW (tCK * parseUint(memspec["memtimingspec"]["RTW"], "RTW")),
tXP (tCK * parseUint(memspec["memtimingspec"]["XP"], "XP")),
tCKE (tCK * parseUint(memspec["memtimingspec"]["CKE"], "CKE")),
tPD (tCKE),
tCKESR (tCKE + tCK),
tXS (tCK * parseUint(memspec["memtimingspec"]["XS"], "XS")),
tRFC (tCK * parseUint(memspec["memtimingspec"]["RFC"], "RFC")),
tRFCSB (tCK * parseUint(memspec["memtimingspec"]["RFCSB"], "RFCSB")),
tRREFD (tCK * parseUint(memspec["memtimingspec"]["RREFD"], "RREFD")),
tREFI (tCK * parseUint(memspec["memtimingspec"]["REFI"], "REFI")),
tREFISB (tCK * parseUint(memspec["memtimingspec"]["REFISB"], "REFISB"))
{
commandLengthInCycles[Command::ACT] = 2;
// MemArchitecture
std::string arch = "memarchitecturespec";
numberOfRanks = parseUint(memspec[arch]["nbrOfRanks"], "nbrOfRanks");
banksPerRank = parseUint(memspec[arch]["nbrOfBanks"], "nbrOfBanks");
groupsPerRank = parseUint(memspec[arch]["nbrOfBankGroups"], "nbrOfBankGroups");
banksPerGroup = banksPerRank / groupsPerRank;
numberOfBanks = banksPerRank * numberOfRanks;
numberOfBankGroups = groupsPerRank * numberOfRanks;
// MemTimings specific for HBM2
std::string timings = "memtimingspec";
tDQSCK = tCK * parseUint(memspec[timings]["DQSCK"], "DQSCK");
tRC = tCK * parseUint(memspec[timings]["RC"], "RC");
tRAS = tCK * parseUint(memspec[timings]["RAS"], "RAS");
tRCDRD = tCK * parseUint(memspec[timings]["RCDRD"], "RCDRD");
tRCDWR = tCK * parseUint(memspec[timings]["RCDWR"], "RCDWR");
tRRDL = tCK * parseUint(memspec[timings]["RRDL"], "RRDL");
tRRDS = tCK * parseUint(memspec[timings]["RRDS"], "RRDS");
tFAW = tCK * parseUint(memspec[timings]["FAW"], "FAW");
tRTP = tCK * parseUint(memspec[timings]["RTP"], "RTP");
tRP = tCK * parseUint(memspec[timings]["RP"], "RP");
tRL = tCK * parseUint(memspec[timings]["RL"], "RL");
tWL = tCK * parseUint(memspec[timings]["WL"], "WL");
tPL = tCK * parseUint(memspec[timings]["PL"], "PL");
tWR = tCK * parseUint(memspec[timings]["WR"], "WR");
tCCDL = tCK * parseUint(memspec[timings]["CCDL"], "CCDL");
tCCDS = tCK * parseUint(memspec[timings]["CCDS"], "CCDS");
tWTRL = tCK * parseUint(memspec[timings]["WTRL"], "WTRL");
tWTRS = tCK * parseUint(memspec[timings]["WTRS"], "WTRS");
tRTW = tCK * parseUint(memspec[timings]["RTW"], "RTW");
tXP = tCK * parseUint(memspec[timings]["XP"], "XP");
tCKE = tCK * parseUint(memspec[timings]["CKE"], "CKE");
tPD = tCKE;
tCKESR = tCKE + tCK;
tXS = tCK * parseUint(memspec[timings]["XS"], "XS");
tRFC = tCK * parseUint(memspec[timings]["RFC"], "RFC");
tRFCSB = tCK * parseUint(memspec[timings]["RFCSB"], "RFCSB");
tRREFD = tCK * parseUint(memspec[timings]["RREFD"], "RREFD");
tREFI = tCK * parseUint(memspec[timings]["REFI"], "REFI");
tREFISB = tCK * parseUint(memspec[timings]["REFISB"], "REFISB");
// Currents and voltages
// TODO: to be completed
}
sc_time MemSpecHBM2::getRefreshIntervalAB() const

58
DRAMSys/library/src/configuration/memspec/MemSpecHBM2.h
View File

@@ -45,37 +45,37 @@ public:
MemSpecHBM2(nlohmann::json &);
// Memspec Variables:
sc_time tDQSCK;
const sc_time tDQSCK;
// sc_time tDQSQ; // TODO: check actual value of this parameter
sc_time tRC;
sc_time tRAS;
sc_time tRCDRD;
sc_time tRCDWR;
sc_time tRRDL;
sc_time tRRDS;
sc_time tFAW;
sc_time tRTP;
sc_time tRP;
sc_time tRL;
sc_time tWL;
sc_time tPL;
sc_time tWR;
sc_time tCCDL;
sc_time tCCDS;
const sc_time tRC;
const sc_time tRAS;
const sc_time tRCDRD;
const sc_time tRCDWR;
const sc_time tRRDL;
const sc_time tRRDS;
const sc_time tFAW;
const sc_time tRTP;
const sc_time tRP;
const sc_time tRL;
const sc_time tWL;
const sc_time tPL;
const sc_time tWR;
const sc_time tCCDL;
const sc_time tCCDS;
// sc_time tCCDR; // TODO: consecutive reads to different stack IDs
sc_time tWTRL;
sc_time tWTRS;
sc_time tRTW;
sc_time tXP;
sc_time tCKE;
sc_time tPD; // = tCKE;
sc_time tCKESR; // = tCKE + tCK;
sc_time tXS;
sc_time tRFC;
sc_time tRFCSB;
sc_time tRREFD;
sc_time tREFI;
sc_time tREFISB;
const sc_time tWTRL;
const sc_time tWTRS;
const sc_time tRTW;
const sc_time tXP;
const sc_time tCKE;
const sc_time tPD; // = tCKE;
const sc_time tCKESR; // = tCKE + tCK;
const sc_time tXS;
const sc_time tRFC;
const sc_time tRFCSB;
const sc_time tRREFD;
const sc_time tREFI;
const sc_time tREFISB;
// Currents and Voltages:
// TODO: to be completed

87
DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.cpp
View File

@@ -38,7 +38,46 @@
using namespace tlm;
using json = nlohmann::json;
MemSpecLPDDR4::MemSpecLPDDR4(json &memspec) : MemSpec(memspec)
MemSpecLPDDR4::MemSpecLPDDR4(json &memspec)
: MemSpec(memspec,
parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"),
parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks"),
1,
parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks"),
parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks")
* parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"),
parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks")),
tREFI (tCK * parseUint(memspec["memtimingspec"]["REFI"], "REFI")),
tREFIpb (tCK * parseUint(memspec["memtimingspec"]["REFIPB"], "REFIPB")),
tRFCab (tCK * parseUint(memspec["memtimingspec"]["RFCAB"], "RFCAB")),
tRFCpb (tCK * parseUint(memspec["memtimingspec"]["RFCPB"], "RFCPB")),
tRPab (tCK * parseUint(memspec["memtimingspec"]["RPAB"], "RPAB")),
tRPpb (tCK * parseUint(memspec["memtimingspec"]["RPPB"], "RPPB")),
tRCab (tCK * parseUint(memspec["memtimingspec"]["RCAB"], "RCAB")),
tRCpb (tCK * parseUint(memspec["memtimingspec"]["RCPB"], "RCPB")),
tPPD (tCK * parseUint(memspec["memtimingspec"]["PPD"], "PPD")),
tRAS (tCK * parseUint(memspec["memtimingspec"]["RAS"], "RAS")),
tRCD (tCK * parseUint(memspec["memtimingspec"]["RCD"], "RCD")),
tFAW (tCK * parseUint(memspec["memtimingspec"]["FAW"], "FAW")),
tRRD (tCK * parseUint(memspec["memtimingspec"]["RRD"], "RRD")),
tCCD (tCK * parseUint(memspec["memtimingspec"]["CCD"], "CCD")),
tRL (tCK * parseUint(memspec["memtimingspec"]["RL"], "RL")),
tRPST (tCK * parseUint(memspec["memtimingspec"]["RPST"], "RPST")),
tDQSCK (tCK * parseUint(memspec["memtimingspec"]["DQSCK"], "DQSCK")),
tRTP (tCK * parseUint(memspec["memtimingspec"]["RTP"], "RTP")),
tWL (tCK * parseUint(memspec["memtimingspec"]["WL"], "WL")),
tDQSS (tCK * parseUint(memspec["memtimingspec"]["DQSS"], "DQSS")),
tDQS2DQ (tCK * parseUint(memspec["memtimingspec"]["DQS2DQ"], "DQS2DQ")),
tWR (tCK * parseUint(memspec["memtimingspec"]["WR"], "WR")),
tWPRE (tCK * parseUint(memspec["memtimingspec"]["WPRE"], "WPRE")),
tWTR (tCK * parseUint(memspec["memtimingspec"]["WTR"], "WTR")),
tXP (tCK * parseUint(memspec["memtimingspec"]["XP"], "XP")),
tSR (tCK * parseUint(memspec["memtimingspec"]["SR"], "SR")),
tXSR (tCK * parseUint(memspec["memtimingspec"]["XSR"], "XSR")),
tESCKE (tCK * parseUint(memspec["memtimingspec"]["ESCKE"], "ESCKE")),
tCKE (tCK * parseUint(memspec["memtimingspec"]["CKE"], "CKE")),
tCMDCKE (tCK * parseUint(memspec["memtimingspec"]["CMDCKE"], "CMDCKE")),
tRTRS (tCK * parseUint(memspec["memtimingspec"]["RTRS"], "RTRS"))
{
commandLengthInCycles[Command::ACT] = 4;
commandLengthInCycles[Command::PRE] = 2;
@@ -51,52 +90,6 @@ MemSpecLPDDR4::MemSpecLPDDR4(json &memspec) : MemSpec(memspec)
commandLengthInCycles[Command::REFB] = 2;
commandLengthInCycles[Command::SREFEN] = 2;
commandLengthInCycles[Command::SREFEX] = 2;
// MemArchitecture:
std::string arch = "memarchitecturespec";
numberOfRanks = parseUint(memspec[arch]["nbrOfRanks"],"nbrOfRanks");
banksPerRank = parseUint(memspec[arch]["nbrOfBanks"],"nbrOfBanks");
groupsPerRank = 1;
banksPerGroup = banksPerRank / groupsPerRank;
numberOfBanks = banksPerRank * numberOfRanks;
numberOfBankGroups = groupsPerRank * numberOfRanks;
// MemTimings specific for LPDDR4
std::string timings = "memtimingspec";
tREFI = tCK * parseUint(memspec[timings]["REFI"], "REFI");
tREFIpb = tCK * parseUint(memspec[timings]["REFIPB"], "REFIPB");
tRFCab = tCK * parseUint(memspec[timings]["RFCAB"], "RFCAB");
tRFCpb = tCK * parseUint(memspec[timings]["RFCPB"], "RFCPB");
tRPab = tCK * parseUint(memspec[timings]["RPAB"], "RPAB");
tRPpb = tCK * parseUint(memspec[timings]["RPPB"], "RPPB");
tRCab = tCK * parseUint(memspec[timings]["RCAB"], "RCAB");
tRCpb = tCK * parseUint(memspec[timings]["RCPB"], "RCPB");
tPPD = tCK * parseUint(memspec[timings]["PPD"], "PPD");
tRAS = tCK * parseUint(memspec[timings]["RAS"], "RAS");
tRCD = tCK * parseUint(memspec[timings]["RCD"], "RCD");
tFAW = tCK * parseUint(memspec[timings]["FAW"], "FAW");
tRRD = tCK * parseUint(memspec[timings]["RRD"], "RRD");
tCCD = tCK * parseUint(memspec[timings]["CCD"], "CCD");
tRL = tCK * parseUint(memspec[timings]["RL"], "RL");
tRPST = tCK * parseUint(memspec[timings]["RPST"], "RPST");
tDQSCK = tCK * parseUint(memspec[timings]["DQSCK"], "DQSCK");
tRTP = tCK * parseUint(memspec[timings]["RTP"], "RTP");
tWL = tCK * parseUint(memspec[timings]["WL"], "WL");
tDQSS = tCK * parseUint(memspec[timings]["DQSS"], "DQSS");
tDQS2DQ = tCK * parseUint(memspec[timings]["DQS2DQ"], "DQS2DQ");
tWR = tCK * parseUint(memspec[timings]["WR"], "WR");
tWPRE = tCK * parseUint(memspec[timings]["WPRE"], "WPRE");
tWTR = tCK * parseUint(memspec[timings]["WTR"], "WTR");
tXP = tCK * parseUint(memspec[timings]["XP"], "XP");
tSR = tCK * parseUint(memspec[timings]["SR"], "SR");
tXSR = tCK * parseUint(memspec[timings]["XSR"], "XSR");
tESCKE = tCK * parseUint(memspec[timings]["ESCKE"], "ESCKE");
tCKE = tCK * parseUint(memspec[timings]["CKE"], "CKE");
tCMDCKE = tCK * parseUint(memspec[timings]["CMDCKE"], "CMDCKE");
tRTRS = tCK * parseUint(memspec[timings]["RTRS"], "RTRS");
// Currents and voltages
// TODO: to be completed
}
sc_time MemSpecLPDDR4::getRefreshIntervalAB() const

62
DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.h
View File

@@ -45,37 +45,37 @@ public:
MemSpecLPDDR4(nlohmann::json &);
// Memspec Variables:
sc_time tREFI;
sc_time tREFIpb;
sc_time tRFCab;
sc_time tRFCpb;
sc_time tRAS;
sc_time tRPab;
sc_time tRPpb;
sc_time tRCpb;
sc_time tRCab;
sc_time tPPD;
sc_time tRCD;
sc_time tFAW;
sc_time tRRD;
sc_time tCCD;
sc_time tRL;
sc_time tRPST;
sc_time tDQSCK;
sc_time tRTP;
sc_time tWL;
sc_time tDQSS;
sc_time tDQS2DQ;
sc_time tWR;
sc_time tWPRE;
sc_time tWTR;
sc_time tXP;
sc_time tSR;
sc_time tXSR;
sc_time tESCKE;
sc_time tCKE;
sc_time tCMDCKE;
sc_time tRTRS;
const sc_time tREFI;
const sc_time tREFIpb;
const sc_time tRFCab;
const sc_time tRFCpb;
const sc_time tRAS;
const sc_time tRPab;
const sc_time tRPpb;
const sc_time tRCpb;
const sc_time tRCab;
const sc_time tPPD;
const sc_time tRCD;
const sc_time tFAW;
const sc_time tRRD;
const sc_time tCCD;
const sc_time tRL;
const sc_time tRPST;
const sc_time tDQSCK;
const sc_time tRTP;
const sc_time tWL;
const sc_time tDQSS;
const sc_time tDQS2DQ;
const sc_time tWR;
const sc_time tWPRE;
const sc_time tWTR;
const sc_time tXP;
const sc_time tSR;
const sc_time tXSR;
const sc_time tESCKE;
const sc_time tCKE;
const sc_time tCMDCKE;
const sc_time tRTRS;
// Currents and Voltages:
// TODO: to be completed

117
DRAMSys/library/src/configuration/memspec/MemSpecWideIO.cpp
View File

@@ -38,68 +38,61 @@
using namespace tlm;
using json = nlohmann::json;
MemSpecWideIO::MemSpecWideIO(json &memspec) : MemSpec(memspec)
{
// MemArchitecture
std::string arch = "memarchitecturespec";
numberOfRanks = parseUint(memspec[arch]["nbrOfRanks"], "nbrOfRanks");
banksPerRank = parseUint(memspec[arch]["nbrOfBanks"], "nbrOfBanks");
groupsPerRank = 1;
banksPerGroup = banksPerRank / groupsPerRank;
numberOfBanks = banksPerRank * numberOfRanks;
numberOfBankGroups = groupsPerRank * numberOfRanks;
// MemTimings specific for WideIO
std::string timings = "memtimingspec";
tCKE = tCK * parseUint(memspec[timings]["CKE"], "CKE");
tCKESR = tCK * parseUint(memspec[timings]["CKESR"], "CKESR");
tDQSCK = tCK * parseUint(memspec[timings]["DQSCK"], "DQSCK");
tAC = tCK * parseUint(memspec[timings]["AC"], "AC");
tRAS = tCK * parseUint(memspec[timings]["RAS"], "RAS");
tRC = tCK * parseUint(memspec[timings]["RC"], "RC");
tRCD = tCK * parseUint(memspec[timings]["RCD"], "RCD");
tRL = tCK * parseUint(memspec[timings]["RL"], "RL");
tWL = tCK * parseUint(memspec[timings]["WL"], "WL");
tWR = tCK * parseUint(memspec[timings]["WR"], "WR");
tXP = tCK * parseUint(memspec[timings]["XP"], "XP");
tXSR = tCK * parseUint(memspec[timings]["XSR"], "XSR");
tCCD_R = tCK * parseUint(memspec[timings]["CCD_R"], "CCD_R");
tCCD_W = tCK * parseUint(memspec[timings]["CCD_W"], "CCD_W");
tREFI = tCK * parseUint(memspec[timings]["REFI"], "REFI");
tRFC = tCK * parseUint(memspec[timings]["RFC"], "RFC");
tRP = tCK * parseUint(memspec[timings]["RP"], "RP");
tRRD = tCK * parseUint(memspec[timings]["RRD"], "RRD");
tTAW = tCK * parseUint(memspec[timings]["TAW"], "TAW");
tWTR = tCK * parseUint(memspec[timings]["WTR"], "WTR");
tRTRS = tCK * parseUint(memspec[timings]["RTRS"], "RTRS");
// Currents and voltages
std::string power = "mempowerspec";
iDD0 = parseUdouble(memspec[power]["idd0"], "idd0");
iDD2N = parseUdouble(memspec[power]["idd2n"], "idd2n");
iDD3N = parseUdouble(memspec[power]["idd3n"], "idd3n");
iDD4R = parseUdouble(memspec[power]["idd4r"], "idd4r");
iDD4W = parseUdouble(memspec[power]["idd4w"], "idd4w");
iDD5 = parseUdouble(memspec[power]["idd5"], "idd5");
iDD6 = parseUdouble(memspec[power]["idd6"], "idd6");
vDD = parseUdouble(memspec[power]["vdd"], "vdd");
iDD02 = parseUdouble(memspec[power]["idd02"], "idd02");
iDD2P0 = parseUdouble(memspec[power]["idd2p0"], "idd2p0");
iDD2P02 = parseUdouble(memspec[power]["idd2p02"], "idd2p02");
iDD2P1 = parseUdouble(memspec[power]["idd2p1"], "idd2p1");
iDD2P12 = parseUdouble(memspec[power]["idd2p12"], "idd2p12");
iDD2N2 = parseUdouble(memspec[power]["idd2n2"], "idd2n2");
iDD3P0 = parseUdouble(memspec[power]["idd3p0"], "idd3p0");
iDD3P02 = parseUdouble(memspec[power]["idd3p02"], "idd3p02");
iDD3P1 = parseUdouble(memspec[power]["idd3p1"], "idd3p1");
iDD3P12 = parseUdouble(memspec[power]["idd3p12"], "idd3p12");
iDD3N2 = parseUdouble(memspec[power]["idd3n2"], "idd3n2");
iDD4R2 = parseUdouble(memspec[power]["idd4r2"], "idd4r2");
iDD4W2 = parseUdouble(memspec[power]["idd4w2"], "idd4w2");
iDD52 = parseUdouble(memspec[power]["idd52"], "idd52");
iDD62 = parseUdouble(memspec[power]["idd62"], "idd62");
vDD2 = parseUdouble(memspec[power]["vdd2"], "vdd2");
}
MemSpecWideIO::MemSpecWideIO(json &memspec)
: MemSpec(memspec,
parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"),
parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks"),
1,
parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks"),
parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks")
* parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"),
parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks")),
tCKE (tCK * parseUint(memspec["memtimingspec"]["CKE"], "CKE")),
tCKESR (tCK * parseUint(memspec["memtimingspec"]["CKESR"], "CKESR")),
tDQSCK (tCK * parseUint(memspec["memtimingspec"]["DQSCK"], "DQSCK")),
tAC (tCK * parseUint(memspec["memtimingspec"]["AC"], "AC")),
tRAS (tCK * parseUint(memspec["memtimingspec"]["RAS"], "RAS")),
tRC (tCK * parseUint(memspec["memtimingspec"]["RC"], "RC")),
tRCD (tCK * parseUint(memspec["memtimingspec"]["RCD"], "RCD")),
tRL (tCK * parseUint(memspec["memtimingspec"]["RL"], "RL")),
tWL (tCK * parseUint(memspec["memtimingspec"]["WL"], "WL")),
tWR (tCK * parseUint(memspec["memtimingspec"]["WR"], "WR")),
tXP (tCK * parseUint(memspec["memtimingspec"]["XP"], "XP")),
tXSR (tCK * parseUint(memspec["memtimingspec"]["XSR"], "XSR")),
tCCD_R (tCK * parseUint(memspec["memtimingspec"]["CCD_R"], "CCD_R")),
tCCD_W (tCK * parseUint(memspec["memtimingspec"]["CCD_W"], "CCD_W")),
tREFI (tCK * parseUint(memspec["memtimingspec"]["REFI"], "REFI")),
tRFC (tCK * parseUint(memspec["memtimingspec"]["RFC"], "RFC")),
tRP (tCK * parseUint(memspec["memtimingspec"]["RP"], "RP")),
tRRD (tCK * parseUint(memspec["memtimingspec"]["RRD"], "RRD")),
tTAW (tCK * parseUint(memspec["memtimingspec"]["TAW"], "TAW")),
tWTR (tCK * parseUint(memspec["memtimingspec"]["WTR"], "WTR")),
tRTRS (tCK * parseUint(memspec["memtimingspec"]["RTRS"], "RTRS")),
iDD0 (parseUdouble(memspec["mempowerspec"]["idd0"], "idd0")),
iDD2N (parseUdouble(memspec["mempowerspec"]["idd2n"], "idd2n")),
iDD3N (parseUdouble(memspec["mempowerspec"]["idd3n"], "idd3n")),
iDD4R (parseUdouble(memspec["mempowerspec"]["idd4r"], "idd4r")),
iDD4W (parseUdouble(memspec["mempowerspec"]["idd4w"], "idd4w")),
iDD5 (parseUdouble(memspec["mempowerspec"]["idd5"], "idd5")),
iDD6 (parseUdouble(memspec["mempowerspec"]["idd6"], "idd6")),
vDD (parseUdouble(memspec["mempowerspec"]["vdd"], "vdd")),
iDD02 (parseUdouble(memspec["mempowerspec"]["idd02"], "idd02")),
iDD2P0 (parseUdouble(memspec["mempowerspec"]["idd2p0"], "idd2p0")),
iDD2P02 (parseUdouble(memspec["mempowerspec"]["idd2p02"], "idd2p02")),
iDD2P1 (parseUdouble(memspec["mempowerspec"]["idd2p1"], "idd2p1")),
iDD2P12 (parseUdouble(memspec["mempowerspec"]["idd2p12"], "idd2p12")),
iDD2N2 (parseUdouble(memspec["mempowerspec"]["idd2n2"], "idd2n2")),
iDD3P0 (parseUdouble(memspec["mempowerspec"]["idd3p0"], "idd3p0")),
iDD3P02 (parseUdouble(memspec["mempowerspec"]["idd3p02"], "idd3p02")),
iDD3P1 (parseUdouble(memspec["mempowerspec"]["idd3p1"], "idd3p1")),
iDD3P12 (parseUdouble(memspec["mempowerspec"]["idd3p12"], "idd3p12")),
iDD3N2 (parseUdouble(memspec["mempowerspec"]["idd3n2"], "idd3n2")),
iDD4R2 (parseUdouble(memspec["mempowerspec"]["idd4r2"], "idd4r2")),
iDD4W2 (parseUdouble(memspec["mempowerspec"]["idd4w2"], "idd4w2")),
iDD52 (parseUdouble(memspec["mempowerspec"]["idd52"], "idd52")),
iDD62 (parseUdouble(memspec["mempowerspec"]["idd62"], "idd62")),
vDD2 (parseUdouble(memspec["mempowerspec"]["vdd2"], "vdd2"))
{}
sc_time MemSpecWideIO::getRefreshIntervalAB() const
{

92
DRAMSys/library/src/configuration/memspec/MemSpecWideIO.h
View File

@@ -42,56 +42,56 @@
class MemSpecWideIO final : public MemSpec
{
public:
MemSpecWideIO(nlohmann::json &);
MemSpecWideIO(nlohmann::json &memspec);
// Memspec Variables:
sc_time tCKE; // min time in pdna or pdnp
sc_time tCKESR; // min time in sref
sc_time tRAS; // active-time (act -> pre same bank)
sc_time tRC; // RAS-cycle-time (min time bw 2 succesive ACT to same bank)
sc_time tRCD; // act -> read/write
sc_time tRL; // read latency (read command start to data strobe)
sc_time tWL; // write latency
sc_time tWR; // write recovery (write to precharge)
sc_time tXP; // min delay to row access command after pdnpx pdnax
sc_time tXSR; // min delay to row access command after srefx
sc_time tREFI;
sc_time tRFC;
sc_time tRP;
sc_time tDQSCK;
sc_time tAC;
sc_time tCCD_R;
sc_time tCCD_W;
sc_time tRRD;
sc_time tTAW;
sc_time tWTR;
sc_time tRTRS;
const sc_time tCKE;
const sc_time tCKESR;
const sc_time tRAS;
const sc_time tRC;
const sc_time tRCD;
const sc_time tRL;
const sc_time tWL;
const sc_time tWR;
const sc_time tXP;
const sc_time tXSR;
const sc_time tREFI;
const sc_time tRFC;
const sc_time tRP;
const sc_time tDQSCK;
const sc_time tAC;
const sc_time tCCD_R;
const sc_time tCCD_W;
const sc_time tRRD;
const sc_time tTAW;
const sc_time tWTR;
const sc_time tRTRS;
// Currents and Voltages:
double iDD0;
double iDD2N;
double iDD3N;
double iDD4R;
double iDD4W;
double iDD5;
double iDD6;
double vDD;
double iDD02;
double iDD2P0;
double iDD2P02;
double iDD2P1;
double iDD2P12;
double iDD2N2;
double iDD3P0;
double iDD3P02;
double iDD3P1;
double iDD3P12;
double iDD3N2;
double iDD4R2;
double iDD4W2;
double iDD52;
double iDD62;
double vDD2;
const double iDD0;
const double iDD2N;
const double iDD3N;
const double iDD4R;
const double iDD4W;
const double iDD5;
const double iDD6;
const double vDD;
const double iDD02;
const double iDD2P0;
const double iDD2P02;
const double iDD2P1;
const double iDD2P12;
const double iDD2N2;
const double iDD3P0;
const double iDD3P02;
const double iDD3P1;
const double iDD3P12;
const double iDD3N2;
const double iDD4R2;
const double iDD4W2;
const double iDD52;
const double iDD62;
const double vDD2;
virtual sc_time getRefreshIntervalPB() const override;
virtual sc_time getRefreshIntervalAB() const override;

81
DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.cpp
View File

@@ -38,50 +38,43 @@
using namespace tlm;
using json = nlohmann::json;
MemSpecWideIO2::MemSpecWideIO2(json &memspec) : MemSpec(memspec)
{
// MemArchitecture
std::string arch = "memarchitecturespec";
numberOfRanks = parseUint(memspec[arch]["nbrOfRanks"], "nbrOfRanks");
banksPerRank = parseUint(memspec[arch]["nbrOfBanks"], "nbrOfBanks");
groupsPerRank = 1;
banksPerGroup = banksPerRank / groupsPerRank;
numberOfBanks = banksPerRank * numberOfRanks;
numberOfBankGroups = groupsPerRank * numberOfRanks;
// MemTimings specific for WideIO2
std::string timings = "memtimingspec";
tDQSCK = tCK * parseUint(memspec[timings]["DQSCK"], "DQSCK");
tDQSS = tCK * parseUint(memspec[timings]["DQSS"], "DQSS");
tCKE = tCK * parseUint(memspec[timings]["CKE"], "CKE");
tRL = tCK * parseUint(memspec[timings]["RL"], "RL");
tWL = tCK * parseUint(memspec[timings]["WL"], "WL");
tRCpb = tCK * parseUint(memspec[timings]["RCPB"], "RCPB");
tRCab = tCK * parseUint(memspec[timings]["RCAB"], "RCAB");
tCKESR = tCK * parseUint(memspec[timings]["CKESR"], "CKESR");
tXSR = tCK * parseUint(memspec[timings]["XSR"], "XSR");
tXP = tCK * parseUint(memspec[timings]["XP"], "XP");
tCCD = tCK * parseUint(memspec[timings]["CCD"], "CCD");
tRTP = tCK * parseUint(memspec[timings]["RTP"], "RTP");
tRCD = tCK * parseUint(memspec[timings]["RCD"], "RCD");
tRPpb = tCK * parseUint(memspec[timings]["RPPB"], "RPPB");
tRPab = tCK * parseUint(memspec[timings]["RPAB"], "RPAB");
tRAS = tCK * parseUint(memspec[timings]["RAS"], "RAS");
tWR = tCK * parseUint(memspec[timings]["WR"], "WR");
tWTR = tCK * parseUint(memspec[timings]["WTR"], "WTR");
tRRD = tCK * parseUint(memspec[timings]["RRD"], "RRD");
tFAW = tCK * parseUint(memspec[timings]["FAW"], "FAW");
tREFI = tCK * (unsigned)(parseUint(memspec[timings]["REFI"], "REFI")
* parseUdouble(memspec[timings]["REFM"], "REFM"));
tREFIpb = tCK * (unsigned)(parseUint(memspec[timings]["REFIPB"], "REFIPB")
* parseUdouble(memspec[timings]["REFM"], "REFM"));
tRFCab = tCK * parseUint(memspec[timings]["RFCAB"], "RFCAB");
tRFCpb = tCK * parseUint(memspec[timings]["RFCPB"], "RFCPB");
tRTRS = tCK * parseUint(memspec[timings]["RTRS"], "RTRS");
// Currents and voltages
// TODO: to be completed
}
MemSpecWideIO2::MemSpecWideIO2(json &memspec)
: MemSpec(memspec,
parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"),
parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks"),
1,
parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks"),
parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks")
* parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"),
parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks")),
tDQSCK (tCK * parseUint(memspec["memtimingspec"]["DQSCK"], "DQSCK")),
tDQSS (tCK * parseUint(memspec["memtimingspec"]["DQSS"], "DQSS")),
tCKE (tCK * parseUint(memspec["memtimingspec"]["CKE"], "CKE")),
tRL (tCK * parseUint(memspec["memtimingspec"]["RL"], "RL")),
tWL (tCK * parseUint(memspec["memtimingspec"]["WL"], "WL")),
tRCpb (tCK * parseUint(memspec["memtimingspec"]["RCPB"], "RCPB")),
tRCab (tCK * parseUint(memspec["memtimingspec"]["RCAB"], "RCAB")),
tCKESR (tCK * parseUint(memspec["memtimingspec"]["CKESR"], "CKESR")),
tXSR (tCK * parseUint(memspec["memtimingspec"]["XSR"], "XSR")),
tXP (tCK * parseUint(memspec["memtimingspec"]["XP"], "XP")),
tCCD (tCK * parseUint(memspec["memtimingspec"]["CCD"], "CCD")),
tRTP (tCK * parseUint(memspec["memtimingspec"]["RTP"], "RTP")),
tRCD (tCK * parseUint(memspec["memtimingspec"]["RCD"], "RCD")),
tRPpb (tCK * parseUint(memspec["memtimingspec"]["RPPB"], "RPPB")),
tRPab (tCK * parseUint(memspec["memtimingspec"]["RPAB"], "RPAB")),
tRAS (tCK * parseUint(memspec["memtimingspec"]["RAS"], "RAS")),
tWR (tCK * parseUint(memspec["memtimingspec"]["WR"], "WR")),
tWTR (tCK * parseUint(memspec["memtimingspec"]["WTR"], "WTR")),
tRRD (tCK * parseUint(memspec["memtimingspec"]["RRD"], "RRD")),
tFAW (tCK * parseUint(memspec["memtimingspec"]["FAW"], "FAW")),
tREFI (tCK * (unsigned)(parseUint(memspec["memtimingspec"]["REFI"], "REFI")
* parseUdouble(memspec["memtimingspec"]["REFM"], "REFM"))),
tREFIpb (tCK * (unsigned)(parseUint(memspec["memtimingspec"]["REFIPB"], "REFIPB")
* parseUdouble(memspec["memtimingspec"]["REFM"], "REFM"))),
tRFCab (tCK * parseUint(memspec["memtimingspec"]["RFCAB"], "RFCAB")),
tRFCpb (tCK * parseUint(memspec["memtimingspec"]["RFCPB"], "RFCPB")),
tRTRS (tCK * parseUint(memspec["memtimingspec"]["RTRS"], "RTRS"))
{}
sc_time MemSpecWideIO2::getRefreshIntervalAB() const
{

52
DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.h
View File

@@ -42,34 +42,34 @@
class MemSpecWideIO2 final : public MemSpec
{
public:
MemSpecWideIO2(nlohmann::json &);
MemSpecWideIO2(nlohmann::json &memspec);
// Memspec Variables:
sc_time tDQSCK;
sc_time tDQSS;
sc_time tCKE;
sc_time tRL;
sc_time tWL;
sc_time tRCpb;
sc_time tRCab;
sc_time tCKESR;
sc_time tXSR;
sc_time tXP;
sc_time tCCD;
sc_time tRTP;
sc_time tRCD;
sc_time tRPpb;
sc_time tRPab;
sc_time tRAS;
sc_time tWR;
sc_time tWTR;
sc_time tRRD;
sc_time tFAW;
sc_time tREFI;
sc_time tREFIpb;
sc_time tRFCab;
sc_time tRFCpb;
sc_time tRTRS;
const sc_time tDQSCK;
const sc_time tDQSS;
const sc_time tCKE;
const sc_time tRL;
const sc_time tWL;
const sc_time tRCpb;
const sc_time tRCab;
const sc_time tCKESR;
const sc_time tXSR;
const sc_time tXP;
const sc_time tCCD;
const sc_time tRTP;
const sc_time tRCD;
const sc_time tRPpb;
const sc_time tRPab;
const sc_time tRAS;
const sc_time tWR;
const sc_time tWTR;
const sc_time tRRD;
const sc_time tFAW;
const sc_time tREFI;
const sc_time tREFIpb;
const sc_time tRFCab;
const sc_time tRFCpb;
const sc_time tRTRS;
// Currents and Voltages:
// TODO: to be completed