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traceAnalyzer tests run with json mcconfig/memspec

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This commit is contained in:
scorrea
2020-05-25 22:09:57 +02:00
parent efdfd7fc3d
commit 7792ef0aa0
5 changed files with 92 additions and 92 deletions
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2
DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G.json
View File

@@ -52,4 +52,4 @@
"clkMhz": 800
}
}
}
}

2
DRAMSys/library/resources/configs/simulator/ddr3.json
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@@ -18,4 +18,4 @@
"UseMalloc": false,
"WindowSize": 1000
}
}
}

18
DRAMSys/traceAnalyzer/scripts/memUtil.py
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@@ -1,5 +1,4 @@
import xml.etree.ElementTree as ET
import json
class MCConfig(object):
""" Memory Controller Configuration Class
@@ -9,7 +8,7 @@ class MCConfig(object):
uses the proper format when searching for elements.
"""
def getValue(self, id):
return self.xmlMCConfig.findall(id)[0].attrib['value']
return self.jsonMCConfig['mcconfig'][id]
def getIntValue(self, id):
return int(self.getValue(id))
@@ -18,7 +17,7 @@ class MCConfig(object):
cursor = dbconnection.cursor()
cursor.execute("SELECT MCconfig FROM GeneralInfo")
result = cursor.fetchone()
self.xmlMCConfig = ET.parse(result[0])
self.jsonMCConfig = json.load(open(result[0]))
class MemSpec(object):
@@ -29,18 +28,18 @@ class MemSpec(object):
proper format when searching for elements.
"""
def getValue(self, id):
match = ".//parameter[@id='{0}']".format(id)
val = self.xmlMemSpec.findall(match)[0].attrib['value']
val = self.jsonMemSpec['memspec'][id]
return val
def getIntValue(self, id):
return int(self.getValue(id))
def getIntValue(self, group, id):
val = self.jsonMemSpec['memspec'][group][id]
return int(val)
def __init__(self, dbconnection):
cursor = dbconnection.cursor()
cursor.execute("SELECT Memspec FROM GeneralInfo")
result = cursor.fetchone()
self.xmlMemSpec = ET.parse(result[0])
self.jsonMemSpec = json.load(open(result[0]))
def getClock(dbconnection):
@@ -119,3 +118,4 @@ def get_total_time_in_phase(connection, phase):
if (totalTime is None):
totalTime = 0.0
return totalTime

8
DRAMSys/traceAnalyzer/scripts/metrics.py
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@@ -462,7 +462,7 @@ def time_in_SREFB_percent(connection):
@metric
def time_in_power_down_states_in_ns(connection):
mcconfig = MCConfig(connection)
bankwiseLogic = mcconfig.getValue("BankwiseLogic")
bankwiseLogic = 0
if bankwiseLogic == "0":
totalTimeInPDNA = time_in_PDNA_in_ns(connection)
totalTimeInPDNP = time_in_PDNP_in_ns(connection)
@@ -480,7 +480,7 @@ def time_in_power_down_states_in_ns(connection):
@metric
def time_in_power_down_states_percent(connection):
mcconfig = MCConfig(connection)
bankwiseLogic = mcconfig.getValue("BankwiseLogic")
bankwiseLogic = 0
if bankwiseLogic == "0":
totalTimeAllBanks = trace_length_in_ns(connection)
else:
@@ -538,7 +538,7 @@ def getMetrics(pathToTrace):
connection = sqlite3.connect(pathToTrace)
mcconfig = MCConfig(connection)
bankwiseLogic = mcconfig.getValue("BankwiseLogic")
bankwiseLogic = 0
if bankwiseLogic == "0":
pdnMetrics = [time_in_PDNA_in_ns, time_in_PDNA_percent, time_in_PDNP_in_ns, time_in_PDNP_percent, time_in_SREF_in_ns, time_in_SREF_percent]
@@ -572,7 +572,7 @@ def calculateMetrics(pathToTrace, selectedMetrics=[]):
connection = sqlite3.connect(pathToTrace)
mcconfig = MCConfig(connection)
bankwiseLogic = mcconfig.getValue("BankwiseLogic")
bankwiseLogic = 0
if bankwiseLogic == "0":
pdnMetrics = [time_in_PDNA_in_ns, time_in_PDNA_percent,

154
DRAMSys/traceAnalyzer/scripts/tests.py
View File

@@ -2,7 +2,7 @@ import sys
import traceback
import sqlite3
import os
import xml.etree.ElementTree as ET
import json
from memUtil import *
@@ -52,102 +52,102 @@ class DramConfig(object):
self.clk = clkWithUnit[0]
self.unitOfTime = clkWithUnit[1].lower()
self.bankwiseLogic = mcconfig.getValue("BankwiseLogic")
self.refMode = mcconfig.getValue("ControllerCoreRefMode")
self.bankwiseLogic = 0
self.refMode = 0
self.scheduler = mcconfig.getValue("Scheduler")
self.numberOfBanks = memspec.getIntValue("nbrOfBanks")
self.burstLength = memspec.getIntValue("burstLength")
self.numberOfBanks = memspec.getIntValue("memarchitecturespec","nbrOfBanks")
self.burstLength = memspec.getIntValue("memarchitecturespec","burstLength")
self.memoryType = memspec.getValue("memoryType")
self.dataRate = memspec.getIntValue("dataRate")
self.dataRate = memspec.getIntValue("memarchitecturespec","dataRate")
if (self.memoryType == "WIDEIO_SDR"):
self.nActivateWindow = 2
self.tRP = self.clk * memspec.getIntValue("RP")
self.tRAS = self.clk * memspec.getIntValue("RAS")
self.tRC = self.clk * memspec.getIntValue("RC")
self.tRRD_S = self.clk * memspec.getIntValue("RRD")
self.tRP = self.clk * memspec.getIntValue("memtimingspec","RP")
self.tRAS = self.clk * memspec.getIntValue("memtimingspec","RAS")
self.tRC = self.clk * memspec.getIntValue("memtimingspec","RC")
self.tRRD_S = self.clk * memspec.getIntValue("memtimingspec","RRD")
self.tRRD_L = self.tRRD_S
self.tCCD_S = self.clk * memspec.getIntValue("CCD")
self.tCCD_S = self.clk * memspec.getIntValue("memtimingspec","CCD")
self.tCCD_L = self.tCCD_S
self.tRCD = self.clk * memspec.getIntValue("RCD")
self.tNAW = self.clk * memspec.getIntValue("TAW")
self.tRL = self.clk * memspec.getIntValue("RL")
self.tWL = self.clk * memspec.getIntValue("WL")
self.tWR = self.clk * memspec.getIntValue("WR")
self.tWTR_S = self.clk * memspec.getIntValue("WTR")
self.tRCD = self.clk * memspec.getIntValue("memtimingspec","RCD")
self.tNAW = self.clk * memspec.getIntValue("memtimingspec","TAW")
self.tRL = self.clk * memspec.getIntValue("memtimingspec","RL")
self.tWL = self.clk * memspec.getIntValue("memtimingspec","WL")
self.tWR = self.clk * memspec.getIntValue("memtimingspec","WR")
self.tWTR_S = self.clk * memspec.getIntValue("memtimingspec","WTR")
self.tWTR_L = self.tWTR_S
self.tRTP = self.clk * memspec.getIntValue("RTP")
self.tCKESR = self.clk * memspec.getIntValue("CKESR")
self.tCKE = self.clk * memspec.getIntValue("CKE")
self.tXP = self.clk * memspec.getIntValue("XP")
self.tRTP = self.clk * memspec.getIntValue("memtimingspec","RTP")
self.tCKESR = self.clk * memspec.getIntValue("memtimingspec","CKESR")
self.tCKE = self.clk * memspec.getIntValue("memtimingspec","CKE")
self.tXP = self.clk * memspec.getIntValue("memtimingspec","XP")
self.tXPDLL = self.tXP
self.tXS = self.clk * memspec.getIntValue("XS")
self.tXS = self.clk * memspec.getIntValue("memtimingspec","XS")
self.tXSDLL = self.tXS
self.tAL = self.clk * memspec.getIntValue("AL")
self.tRFC = self.clk * memspec.getIntValue("RFC")
self.tREFI = self.clk * memspec.getIntValue("REFI")
self.tAL = self.clk * memspec.getIntValue("memtimingspec","AL")
self.tRFC = self.clk * memspec.getIntValue("memtimingspec","RFC")
self.tREFI = self.clk * memspec.getIntValue("memtimingspec","REFI")
elif (self. memoryType == "DDR4"):
self.nActivateWindow = 4
self.tRP = self.clk * memspec.getIntValue("RP")
self.tRAS = self.clk * memspec.getIntValue("RAS")
self.tRC = self.clk * memspec.getIntValue("RC")
self.tRTP = self.clk * memspec.getIntValue("RTP")
self.tRRD_S = self.clk * memspec.getIntValue("RRD_S")
self.tRRD_L = self.clk * memspec.getIntValue("RRD_L")
self.tCCD_S = self.clk * memspec.getIntValue("CCD_S")
self.tCCD_L = self.clk * memspec.getIntValue("CCD_L")
self.tRCD = self.clk * memspec.getIntValue("RCD")
self.tNAW = self.clk * memspec.getIntValue("FAW")
self.tRL = self.clk * memspec.getIntValue("RL")
self.tWL = self.clk * memspec.getIntValue("WL")
self.tWR = self.clk * memspec.getIntValue("WR")
self.tWTR_S = self.clk * memspec.getIntValue("WTR_S")
self.tWTR_L = self.clk * memspec.getIntValue("WTR_L")
self.tCKESR = self.clk * memspec.getIntValue("CKESR")
self.tCKE = self.clk * memspec.getIntValue("CKE")
self.tXP = self.clk * memspec.getIntValue("XP")
self.tXPDLL = self.clk * memspec.getIntValue("XPDLL")
self.tXS = self.clk * memspec.getIntValue("XS")
self.tXSDLL = self.clk * memspec.getIntValue("XSDLL")
self.tAL = self.clk * memspec.getIntValue("AL")
self.tRP = self.clk * memspec.getIntValue("memtimingspec","RP")
self.tRAS = self.clk * memspec.getIntValue("memtimingspec","RAS")
self.tRC = self.clk * memspec.getIntValue("memtimingspec","RC")
self.tRTP = self.clk * memspec.getIntValue("memtimingspec","RTP")
self.tRRD_S = self.clk * memspec.getIntValue("memtimingspec","RRD_S")
self.tRRD_L = self.clk * memspec.getIntValue("memtimingspec","RRD_L")
self.tCCD_S = self.clk * memspec.getIntValue("memtimingspec","CCD_S")
self.tCCD_L = self.clk * memspec.getIntValue("memtimingspec","CCD_L")
self.tRCD = self.clk * memspec.getIntValue("memtimingspec","RCD")
self.tNAW = self.clk * memspec.getIntValue("memtimingspec","FAW")
self.tRL = self.clk * memspec.getIntValue("memtimingspec","RL")
self.tWL = self.clk * memspec.getIntValue("memtimingspec","WL")
self.tWR = self.clk * memspec.getIntValue("memtimingspec","WR")
self.tWTR_S = self.clk * memspec.getIntValue("memtimingspec","WTR_S")
self.tWTR_L = self.clk * memspec.getIntValue("memtimingspec","WTR_L")
self.tCKESR = self.clk * memspec.getIntValue("memtimingspec","CKESR")
self.tCKE = self.clk * memspec.getIntValue("memtimingspec","CKE")
self.tXP = self.clk * memspec.getIntValue("memtimingspec","XP")
self.tXPDLL = self.clk * memspec.getIntValue("memtimingspec","XPDLL")
self.tXS = self.clk * memspec.getIntValue("memtimingspec","XS")
self.tXSDLL = self.clk * memspec.getIntValue("memtimingspec","XSDLL")
self.tAL = self.clk * memspec.getIntValue("memtimingspec","AL")
if (self.refMode == "4"):
self.tRFC = self.clk * memspec.getIntValue("RFC4")
self.tREFI = self.clk * (memspec.getIntValue("REFI") / 4)
self.tRFC = self.clk * memspec.getIntValue("memtimingspec","RFC4")
self.tREFI = self.clk * (memspec.getIntValue("memtimingspec","REFI") / 4)
elif (self.refMode == "2"):
self.tRFC = self.clk * memspec.getIntValue("RFC2")
self.tREFI = self.clk * (memspec.getIntValue("REFI") / 2)
self.tRFC = self.clk * memspec.getIntValue("memtimingspec","RFC2")
self.tREFI = self.clk * (memspec.getIntValue("memtimingspec","REFI") / 2)
else:
self.tRFC = self.clk * memspec.getIntValue("RFC")
self.tREFI = self.clk * memspec.getIntValue("REFI")
self.tRFC = self.clk * memspec.getIntValue("memtimingspec","RFC")
self.tREFI = self.clk * memspec.getIntValue("memtimingspec","REFI")
elif (self. memoryType == "DDR3"):
self.nActivateWindow = 4
self.tRP = self.clk * memspec.getIntValue("RP")
self.tRAS = self.clk * memspec.getIntValue("RAS")
self.tRC = self.clk * memspec.getIntValue("RC")
self.tRTP = self.clk * memspec.getIntValue("RTP")
self.tRRD_S = self.clk * memspec.getIntValue("RRD")
self.tRRD_L = self.clk * memspec.getIntValue("RRD")
self.tCCD_S = self.clk * memspec.getIntValue("CCD")
self.tCCD_L = self.clk * memspec.getIntValue("CCD")
self.tRCD = self.clk * memspec.getIntValue("RCD")
self.tNAW = self.clk * memspec.getIntValue("FAW")
self.tRL = self.clk * memspec.getIntValue("RL")
self.tWL = self.clk * memspec.getIntValue("WL")
self.tWR = self.clk * memspec.getIntValue("WR")
self.tWTR_S = self.clk * memspec.getIntValue("WTR")
self.tWTR_L = self.clk * memspec.getIntValue("WTR")
self.tCKESR = self.clk * memspec.getIntValue("CKESR")
self.tCKE = self.clk * memspec.getIntValue("CKE")
self.tXP = self.clk * memspec.getIntValue("XP")
self.tXPDLL = self.clk * memspec.getIntValue("XPDLL")
self.tXS = self.clk * memspec.getIntValue("XS")
self.tXSDLL = self.clk * memspec.getIntValue("XSDLL")
self.tAL = self.clk * memspec.getIntValue("AL")
self.tRFC = self.clk * memspec.getIntValue("RFC")
self.tREFI = self.clk * memspec.getIntValue("REFI")
self.tRP = self.clk * memspec.getIntValue("memtimingspec","RP")
self.tRAS = self.clk * memspec.getIntValue("memtimingspec","RAS")
self.tRC = self.clk * memspec.getIntValue("memtimingspec","RC")
self.tRTP = self.clk * memspec.getIntValue("memtimingspec","RTP")
self.tRRD_S = self.clk * memspec.getIntValue("memtimingspec","RRD")
self.tRRD_L = self.clk * memspec.getIntValue("memtimingspec","RRD")
self.tCCD_S = self.clk * memspec.getIntValue("memtimingspec","CCD")
self.tCCD_L = self.clk * memspec.getIntValue("memtimingspec","CCD")
self.tRCD = self.clk * memspec.getIntValue("memtimingspec","RCD")
self.tNAW = self.clk * memspec.getIntValue("memtimingspec","FAW")
self.tRL = self.clk * memspec.getIntValue("memtimingspec","RL")
self.tWL = self.clk * memspec.getIntValue("memtimingspec","WL")
self.tWR = self.clk * memspec.getIntValue("memtimingspec","WR")
self.tWTR_S = self.clk * memspec.getIntValue("memtimingspec","WTR")
self.tWTR_L = self.clk * memspec.getIntValue("memtimingspec","WTR")
self.tCKESR = self.clk * memspec.getIntValue("memtimingspec","CKESR")
self.tCKE = self.clk * memspec.getIntValue("memtimingspec","CKE")
self.tXP = self.clk * memspec.getIntValue("memtimingspec","XP")
self.tXPDLL = self.clk * memspec.getIntValue("memtimingspec","XPDLL")
self.tXS = self.clk * memspec.getIntValue("memtimingspec","XS")
self.tXSDLL = self.clk * memspec.getIntValue("memtimingspec","XSDLL")
self.tAL = self.clk * memspec.getIntValue("memtimingspec","AL")
self.tRFC = self.clk * memspec.getIntValue("memtimingspec","RFC")
self.tREFI = self.clk * memspec.getIntValue("memtimingspec","REFI")
else:
raise Exception("MemoryType not supported yet. Insert a coin into the coin machine and try again")