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Prioritize command of PDM for staggered entry.

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This commit is contained in:
Lukas Steiner
2020-08-05 15:12:27 +02:00
parent 25a268fc8c
commit 772f6c8eed
10 changed files with 33 additions and 30 deletions
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6
DRAMSys/library/src/common/utils.cpp
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@@ -140,7 +140,7 @@ std::string parseString(json &obj, std::string name)
SC_REPORT_FATAL("Query json", ("Parameter '" + name + "' does not exist.").c_str());
}
void setUpDummy(tlm_generic_payload &payload, Rank rank, Bank bank)
void setUpDummy(tlm_generic_payload &payload, uint64_t payloadID, Rank rank, BankGroup bankgroup, Bank bank)
{
payload.set_address(bank.getStartAddress());
payload.set_command(TLM_READ_COMMAND);
@@ -149,6 +149,6 @@ void setUpDummy(tlm_generic_payload &payload, Rank rank, Bank bank)
payload.set_dmi_allowed(false);
payload.set_byte_enable_length(0);
payload.set_streaming_width(0);
payload.set_extension(new DramExtension(Thread(UINT_MAX), rank, BankGroup(0),
bank, Row(0), Column(0), 0, 0));
payload.set_extension(new DramExtension(Thread(UINT_MAX), rank, bankgroup,
bank, Row(0), Column(0), 0, payloadID));
}

2
DRAMSys/library/src/common/utils.h
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@@ -110,7 +110,7 @@ unsigned int parseUint(nlohmann::json &obj, std::string name);
double parseUdouble(nlohmann::json &obj, std::string name);
std::string parseString(nlohmann::json &obj, std::string name);
void setUpDummy(tlm::tlm_generic_payload &payload, Rank rank = Rank(0), Bank bank = Bank(0));
void setUpDummy(tlm::tlm_generic_payload &payload, uint64_t payloadID, Rank rank = Rank(0), BankGroup bankgroup = BankGroup(0), Bank bank = Bank(0));
#endif // UTILS_H

20
DRAMSys/library/src/controller/Controller.cpp
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@@ -247,18 +247,20 @@ void Controller::controllerMethod()
commandTuple = powerDownManagers[rankID]->getNextCommand();
if (std::get<0>(commandTuple) != Command::NOP)
readyCommands.push_back(commandTuple);
// (5.2) Check for refresh commands (PREA/PRE or REFA/REFB)
commandTuple = refreshManagers[rankID]->getNextCommand();
if (std::get<0>(commandTuple) != Command::NOP)
readyCommands.push_back(commandTuple);
// (5.3) Check for bank commands (PRE, ACT, RD/RDA or WR/WRA)
for (auto it : bankMachinesOnRank[rankID])
else
{
commandTuple = it->getNextCommand();
// (5.2) Check for refresh commands (PREA/PRE or REFA/REFB)
commandTuple = refreshManagers[rankID]->getNextCommand();
if (std::get<0>(commandTuple) != Command::NOP)
readyCommands.push_back(commandTuple);
// (5.3) Check for bank commands (PRE, ACT, RD/RDA or WR/WRA)
for (auto it : bankMachinesOnRank[rankID])
{
commandTuple = it->getNextCommand();
if (std::get<0>(commandTuple) != Command::NOP)
readyCommands.push_back(commandTuple);
}
}
}

6
DRAMSys/library/src/controller/Controller.h
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@@ -65,9 +65,9 @@ public:
virtual ~Controller();
protected:
virtual tlm::tlm_sync_enum nb_transport_fw(tlm::tlm_generic_payload &, tlm::tlm_phase &, sc_time &);
virtual tlm::tlm_sync_enum nb_transport_bw(tlm::tlm_generic_payload &, tlm::tlm_phase &, sc_time &);
virtual unsigned int transport_dbg(tlm::tlm_generic_payload &);
virtual tlm::tlm_sync_enum nb_transport_fw(tlm::tlm_generic_payload &, tlm::tlm_phase &, sc_time &) override;
virtual tlm::tlm_sync_enum nb_transport_bw(tlm::tlm_generic_payload &, tlm::tlm_phase &, sc_time &) override;
virtual unsigned int transport_dbg(tlm::tlm_generic_payload &) override;
virtual void sendToFrontend(tlm::tlm_generic_payload *, tlm::tlm_phase);
virtual void sendToDram(Command, tlm::tlm_generic_payload *);

18
DRAMSys/library/src/controller/ControllerRecordable.h
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@@ -44,17 +44,17 @@ public:
ControllerRecordable(sc_module_name name, TlmRecorder *tlmRecorder) :
Controller(name), tlmRecorder(tlmRecorder) {}
protected:
virtual tlm::tlm_sync_enum nb_transport_fw(tlm::tlm_generic_payload &trans,
tlm::tlm_phase &phase, sc_time &delay) override;
virtual tlm::tlm_sync_enum nb_transport_bw(tlm::tlm_generic_payload &trans,
tlm::tlm_phase &phase, sc_time &delay) override;
virtual void sendToFrontend(tlm::tlm_generic_payload *, tlm::tlm_phase) override;
virtual void sendToDram(Command, tlm::tlm_generic_payload *) override;
private:
tlm::tlm_sync_enum nb_transport_fw(tlm::tlm_generic_payload &trans,
tlm::tlm_phase &phase, sc_time &delay) override;
tlm::tlm_sync_enum nb_transport_bw(tlm::tlm_generic_payload &trans,
tlm::tlm_phase &phase, sc_time &delay) override;
void sendToFrontend(tlm::tlm_generic_payload *, tlm::tlm_phase) override;
void sendToDram(Command, tlm::tlm_generic_payload *) override;
void recordPhase(tlm::tlm_generic_payload &trans, tlm::tlm_phase phase, sc_time delay);
TlmRecorder *tlmRecorder;
};

2
DRAMSys/library/src/controller/powerdown/PowerDownManagerStaggered.cpp
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@@ -40,7 +40,7 @@ using namespace tlm;
PowerDownManagerStaggered::PowerDownManagerStaggered(Rank rank, CheckerIF *checker)
: rank(rank), checker(checker)
{
setUpDummy(powerDownPayload, rank);
setUpDummy(powerDownPayload, UINT64_MAX, rank);
}
void PowerDownManagerStaggered::triggerEntry()

2
DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.cpp
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@@ -50,7 +50,7 @@ RefreshManagerBankwise::RefreshManagerBankwise(std::vector<BankMachine *> &bankM
refreshPayloads = std::vector<tlm_generic_payload>(memSpec->banksPerRank);
for (unsigned bankID = 0; bankID < memSpec->banksPerRank; bankID++)
{
setUpDummy(refreshPayloads[bankID], rank, bankMachines[bankID]->getBank());
setUpDummy(refreshPayloads[bankID], 0, rank, bankMachines[bankID]->getBankGroup(), bankMachines[bankID]->getBank());
allBankMachines.push_back(bankMachines[bankID]);
}
remainingBankMachines = allBankMachines;

2
DRAMSys/library/src/controller/refresh/RefreshManagerRankwise.cpp
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@@ -46,7 +46,7 @@ RefreshManagerRankwise::RefreshManagerRankwise(std::vector<BankMachine *> &bankM
Configuration &config = Configuration::getInstance();
memSpec = config.memSpec;
timeForNextTrigger = memSpec->getRefreshIntervalAB();
setUpDummy(refreshPayload, rank);
setUpDummy(refreshPayload, 0, rank);
maxPostponed = config.refreshMaxPostponed;
maxPulledin = -config.refreshMaxPulledin;

2
DRAMSys/library/src/simulation/Arbiter.h
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@@ -82,7 +82,7 @@ private:
tlm::tlm_sync_enum nb_transport_bw(int channelId, tlm::tlm_generic_payload &payload,
tlm::tlm_phase &phase, sc_time &bwDelay);
virtual unsigned int transport_dbg(int /*id*/, tlm::tlm_generic_payload &trans);
unsigned int transport_dbg(int /*id*/, tlm::tlm_generic_payload &trans);
void peqCallback(tlm::tlm_generic_payload &payload, const tlm::tlm_phase &phase);

3
DRAMSys/library/src/simulation/dram/DramRecordable.h
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@@ -48,8 +48,9 @@ class DramRecordable final : public BaseDram
public:
DramRecordable(sc_module_name, TlmRecorder *);
SC_HAS_PROCESS(DramRecordable);
virtual ~DramRecordable() {}
virtual void reportPower();
virtual void reportPower() override;
private:
virtual tlm::tlm_sync_enum nb_transport_fw(tlm::tlm_generic_payload &payload,