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Merge branch 'bug/failing_test' into 'develop'

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Bugfix: Indeterministic test fails.

See merge request ems/astdm/modeling.dram/dram.sys!344
This commit is contained in:
Lukas Steiner
2022-02-18 13:14:44 +00:00
parent b1dfdc435f ad05a8afb0
commit 767ecf79db
10 changed files with 39 additions and 36 deletions
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4
DRAMSys/library/src/common/TlmRecorder.cpp
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@@ -221,7 +221,9 @@ void TlmRecorder::terminateRemainingTransactions()
{
while (!currentTransactionsInSystem.empty())
{
auto transaction = currentTransactionsInSystem.begin();
auto transaction = std::min_element(currentTransactionsInSystem.begin(),
currentTransactionsInSystem.end(), [](decltype(currentTransactionsInSystem)::value_type& l,
decltype(currentTransactionsInSystem)::value_type& r) -> bool {return l.second.id < r.second.id;});
if (transaction->second.cmd == 'X')
{
std::string beginPhase = transaction->second.recordedPhases.front().name;

9
DRAMSys/library/src/simulation/DRAMSys.cpp
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@@ -116,6 +116,15 @@ DRAMSys::DRAMSys(const sc_core::sc_module_name &name,
}
}
void DRAMSys::end_of_simulation()
{
if (Configuration::getInstance().powerAnalysis)
{
for (auto& dram : drams)
dram->reportPower();
}
}
void DRAMSys::logo()
{
#define GREENTXT(s) std::string(("\u001b[38;5;28m"+std::string((s))+"\033[0m"))

2
DRAMSys/library/src/simulation/DRAMSys.h
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@@ -70,6 +70,8 @@ protected:
const std::string &pathToResources,
bool initAndBind);
void end_of_simulation() override;
//TLM 2.0 Protocol Checkers
std::vector<tlm_utils::tlm2_base_protocol_checker<>*> controllersTlmCheckers;

2
DRAMSys/library/src/simulation/DRAMSysRecordable.cpp
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@@ -82,7 +82,7 @@ DRAMSysRecordable::DRAMSysRecordable(const sc_module_name &name,
void DRAMSysRecordable::end_of_simulation()
{
// Report power before TLM recorders are deleted
// Report power before TLM recorders are finalized
if (Configuration::getInstance().powerAnalysis)
{
for (auto& dram : drams)

5
DRAMSys/library/src/simulation/DRAMSysRecordable.h
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@@ -46,13 +46,14 @@ public:
const std::string &simulationToRun,
const std::string &pathToResources);
protected:
void end_of_simulation() override;
private:
// Transaction Recorders (one per channel).
// They generate the output databases.
std::vector<TlmRecorder> tlmRecorders;
void end_of_simulation() override;
void setupTlmRecorders(const std::string &traceName);
void instantiateModules(const std::string &traceName,

38
DRAMSys/library/src/simulation/dram/Dram.cpp
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@@ -95,38 +95,28 @@ Dram::Dram(const sc_module_name &name) : sc_module(name), tSocket("socket")
Dram::~Dram()
{
if (Configuration::getInstance().powerAnalysis)
{
Dram::reportPower();
delete DRAMPower;
}
if (Configuration::getInstance().useMalloc)
free(memory);
}
void Dram::reportPower()
{
if (!powerReported)
{
powerReported = true;
DRAMPower->calcEnergy();
DRAMPower->calcEnergy();
// Print the final total energy and the average power for
// the simulation:
std::cout << name() << std::string(" Total Energy: ")
<< std::fixed << std::setprecision( 2 )
<< DRAMPower->getEnergy().total_energy
* Configuration::getInstance().memSpec->numberOfDevices
<< std::string(" pJ")
<< std::endl;
// Print the final total energy and the average power for
// the simulation:
std::cout << name() << std::string(" Total Energy: ")
<< std::fixed << std::setprecision( 2 )
<< DRAMPower->getEnergy().total_energy
* Configuration::getInstance().memSpec->numberOfDevices
<< std::string(" pJ")
<< std::endl;
std::cout << name() << std::string(" Average Power: ")
<< std::fixed << std::setprecision( 2 )
<< DRAMPower->getPower().average_power
* Configuration::getInstance().memSpec->numberOfDevices
<< std::string(" mW") << std::endl;
}
std::cout << name() << std::string(" Average Power: ")
<< std::fixed << std::setprecision( 2 )
<< DRAMPower->getPower().average_power
* Configuration::getInstance().memSpec->numberOfDevices
<< std::string(" mW") << std::endl;
}
tlm_sync_enum Dram::nb_transport_fw(tlm_generic_payload &payload,

7
DRAMSys/library/src/simulation/dram/Dram.h
View File

@@ -40,6 +40,8 @@
#ifndef DRAM_H
#define DRAM_H
#include <memory>
#include <systemc>
#include <tlm>
#include <tlm_utils/simple_target_socket.h>
@@ -49,9 +51,6 @@
class Dram : public sc_core::sc_module
{
private:
bool powerReported = false;
protected:
explicit Dram(const sc_core::sc_module_name &name);
SC_HAS_PROCESS(Dram);
@@ -63,7 +62,7 @@ protected:
unsigned char *memory;
libDRAMPower *DRAMPower = nullptr;
std::unique_ptr<libDRAMPower> DRAMPower;
virtual tlm::tlm_sync_enum nb_transport_fw(tlm::tlm_generic_payload &payload,
tlm::tlm_phase &phase, sc_core::sc_time &delay);

2
DRAMSys/library/src/simulation/dram/DramDDR3.cpp
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@@ -138,6 +138,6 @@ DramDDR3::DramDDR3(const sc_module_name &name) : Dram(name)
powerSpec.memPowerSpec = memPowerSpec;
powerSpec.memArchSpec = memArchSpec;
DRAMPower = new libDRAMPower(powerSpec, false);
DRAMPower = std::unique_ptr<libDRAMPower>(new libDRAMPower(powerSpec, false));
}
}

2
DRAMSys/library/src/simulation/dram/DramDDR4.cpp
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@@ -138,6 +138,6 @@ DramDDR4::DramDDR4(const sc_module_name &name) : Dram(name)
powerSpec.memPowerSpec = memPowerSpec;
powerSpec.memArchSpec = memArchSpec;
DRAMPower = new libDRAMPower(powerSpec, false);
DRAMPower = std::unique_ptr<libDRAMPower>(new libDRAMPower(powerSpec, false));
}
}

4
DRAMSys/library/src/simulation/dram/DramWideIO.cpp
View File

@@ -139,7 +139,7 @@ DramWideIO::DramWideIO(const sc_module_name &name) : Dram(name)
powerSpec.memPowerSpec = memPowerSpec;
powerSpec.memArchSpec = memArchSpec;
DRAMPower = new libDRAMPower(powerSpec, false);
DRAMPower = std::unique_ptr<libDRAMPower>(new libDRAMPower(powerSpec, false));
// For each bank in a channel a error Model is created:
if (storeMode == Configuration::StoreMode::ErrorModel)
@@ -148,7 +148,7 @@ DramWideIO::DramWideIO(const sc_module_name &name) : Dram(name)
{
errorModel *em;
std::string errorModelStr = "errorModel_bank" + std::to_string(i);
em = new errorModel(errorModelStr.c_str(), DRAMPower);
em = new errorModel(errorModelStr.c_str(), DRAMPower.get());
ememory.push_back(em);
}
}