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Added FR-FCFS Grouping scheduler, updated config files.

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This commit is contained in:
Lukas Steiner
2020-03-25 22:46:18 +01:00
parent cdaa209909
commit 75e7047826
25 changed files with 283 additions and 541 deletions
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1
DRAMSys/library/CMakeLists.txt
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@@ -129,6 +129,7 @@ add_library(DRAMSysLibrary
src/controller/scheduler/SchedulerIF.h
src/controller/scheduler/SchedulerFifo.cpp
src/controller/scheduler/SchedulerFrFcfs.cpp
src/controller/scheduler/SchedulerFrFcfsGrp.cpp
src/error/eccbaseclass.cpp
src/error/ecchamming.cpp

1
DRAMSys/library/resources/configs/mcconfigs/.gitignore vendored
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@@ -1 +0,0 @@
memconfig.xml

8
DRAMSys/library/resources/configs/mcconfigs/fifo.xml
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@@ -1,7 +1,13 @@
<mcconfig>
<OpenPagePolicy value="1" />
<MaxNrOfTransactions value="8" />
<!-- Open, OpenAdaptive, Closed, ClosedAdaptive -->
<PagePolicy value="Open" />
<!-- Fifo, FrFcfs, FrFcfsGrp -->
<Scheduler value="Fifo" />
<!-- Oldest, Strict -->
<CmdMux value="Strict" />
<!-- Fifo, Reorder -->
<RespQueue value="Fifo" />
<Capsize value="5" />
<!-- 4 Modes: NoPowerDown, Staggered, TimeoutPDN, TimeoutSREF -->
<PowerDownMode value="NoPowerDown" />

44
DRAMSys/library/resources/configs/mcconfigs/fifoStrict.xml
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@@ -1,44 +0,0 @@
<mcconfig>
<OpenPagePolicy value="1" />
<AdaptivePagePolicy value="0" />
<MaxNrOfTransactions value="8" />
<Scheduler value="FifoStrict" />
<Capsize value="5" />
<!-- 4 Modes: NoPowerDown, Staggered, TimeoutPDN, TimeoutSREF -->
<PowerDownMode value="NoPowerDown" />
<PowerDownTimeout value="100" />
<!-- Bankwise -->
<BankwiseLogic value="0"/>
<!-- Refresh yes, no -->
<ControllerCoreRefDisable value="0"/>
<!-- Refresh Mode. 1: 1X, 2: 2X, 4: 4X (e.g., DDR4) -->
<ControllerCoreRefMode value="1"/>
<!-- Number of AR commands in a tREFI in 1X mode -->
<ControllerCoreRefNumARCmdsIntREFI value="8192"/>
<!-- RGR -->
<ControllerCoreRGR value="0"/>
<ControllerCoreRGRRowInc value="1"/>
<!-- Banks to be refreshed in RGR mode. 1: yes, 0: no (max. 16 banks) -->
<ControllerCoreRGRB0 value="1"/>
<ControllerCoreRGRB1 value="1"/>
<ControllerCoreRGRB2 value="1"/>
<ControllerCoreRGRB3 value="1"/>
<ControllerCoreRGRB4 value="1"/>
<ControllerCoreRGRB5 value="1"/>
<ControllerCoreRGRB6 value="1"/>
<ControllerCoreRGRB7 value="1"/>
<ControllerCoreRGRB8 value="0"/>
<ControllerCoreRGRB9 value="0"/>
<ControllerCoreRGRB10 value="0"/>
<ControllerCoreRGRB11 value="0"/>
<ControllerCoreRGRB12 value="0"/>
<ControllerCoreRGRB13 value="0"/>
<ControllerCoreRGRB14 value="0"/>
<ControllerCoreRGRB15 value="0"/>
<!-- Postpone, pull-in -->
<ControllerCoreRefEnablePostpone value="0"/>
<ControllerCoreRefEnablePullIn value="0"/>
<ControllerCoreRefMaxPostponed value="8"/>
<ControllerCoreRefMaxPulledIn value="8"/>
<ControllerCoreRefForceMaxPostponeBurst value="0"/>
</mcconfig>

43
DRAMSys/library/resources/configs/mcconfigs/fifo_ecc.xml
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@@ -1,43 +0,0 @@
<mcconfig>
<OpenPagePolicy value="1" />
<MaxNrOfTransactions value="8" />
<Scheduler value="Fifo" />
<Capsize value="5" />
<!-- 4 Modes: NoPowerDown, Staggered, TimeoutPDN, TimeoutSREF -->
<PowerDownMode value="NoPowerDown" />
<PowerDownTimeout value="100" />
<!-- Bankwise -->
<BankwiseLogic value="0"/>
<!-- Refresh yes, no -->
<ControllerCoreRefDisable value="0"/>
<!-- Refresh Mode. 1: 1X, 2: 2X, 4: 4X (e.g., DDR4) -->
<ControllerCoreRefMode value="1"/>
<!-- Number of AR commands in a tREFI in 1X mode -->
<ControllerCoreRefNumARCmdsIntREFI value="8192"/>
<!-- RGR -->
<ControllerCoreRGR value="0"/>
<ControllerCoreRGRRowInc value="1"/>
<!-- Banks to be refreshed in RGR mode. 1: yes, 0: no (max. 16 banks) -->
<ControllerCoreRGRB0 value="1"/>
<ControllerCoreRGRB1 value="1"/>
<ControllerCoreRGRB2 value="1"/>
<ControllerCoreRGRB3 value="1"/>
<ControllerCoreRGRB4 value="1"/>
<ControllerCoreRGRB5 value="1"/>
<ControllerCoreRGRB6 value="1"/>
<ControllerCoreRGRB7 value="1"/>
<ControllerCoreRGRB8 value="0"/>
<ControllerCoreRGRB9 value="0"/>
<ControllerCoreRGRB10 value="0"/>
<ControllerCoreRGRB11 value="0"/>
<ControllerCoreRGRB12 value="0"/>
<ControllerCoreRGRB13 value="0"/>
<ControllerCoreRGRB14 value="0"/>
<ControllerCoreRGRB15 value="0"/>
<!-- Postpone, pull-in -->
<ControllerCoreRefEnablePostpone value="0"/>
<ControllerCoreRefEnablePullIn value="0"/>
<ControllerCoreRefMaxPostponed value="8"/>
<ControllerCoreRefMaxPulledIn value="8"/>
<ControllerCoreRefForceMaxPostponeBurst value="0"/>
</mcconfig>

9
DRAMSys/library/resources/configs/mcconfigs/fr_fcfs.xml
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@@ -1,8 +1,13 @@
<mcconfig>
<OpenPagePolicy value="1" />
<AdaptivePagePolicy value="1" />
<MaxNrOfTransactions value="8" />
<!-- Open, OpenAdaptive, Closed, ClosedAdaptive -->
<PagePolicy value="Open" />
<!-- Fifo, FrFcfs, FrFcfsGrp -->
<Scheduler value="FrFcfs" />
<!-- Oldest, Strict -->
<CmdMux value="Oldest" />
<!-- Fifo, Reorder -->
<RespQueue value="Fifo" />
<Capsize value="5" />
<!-- 4 Modes: NoPowerDown, Staggered, TimeoutPDN, TimeoutSREF -->
<PowerDownMode value="NoPowerDown" />

42
DRAMSys/library/resources/configs/mcconfigs/fr_fcfs_bw_buffer16.xml
View File

@@ -1,42 +0,0 @@
<mcconfig>
<OpenPagePolicy value="1" />
<MaxNrOfTransactions value="16" />
<Scheduler value="FR_FCFS" />
<Capsize value="5" />
<PowerDownMode value="NoPowerDown" />
<PowerDownTimeout value="100" />
<!-- Bankwise -->
<BankwiseLogic value="1"/>
<!-- Refresh yes, no -->
<ControllerCoreRefDisable value="0"/>
<!-- Refresh Mode. 1: 1X, 2: 2X, 4: 4X (e.g., DDR4) -->
<ControllerCoreRefMode value="1"/>
<!-- Number of AR commands in a tREFI in 1X mode -->
<ControllerCoreRefNumARCmdsIntREFI value="8192"/>
<!-- RGR -->
<ControllerCoreRGR value="0"/>
<ControllerCoreRGRRowInc value="1"/>
<!-- Banks to be refreshed in RGR mode. 1: yes, 0: no (max. 16 banks) -->
<ControllerCoreRGRB0 value="1"/>
<ControllerCoreRGRB1 value="1"/>
<ControllerCoreRGRB2 value="1"/>
<ControllerCoreRGRB3 value="1"/>
<ControllerCoreRGRB4 value="1"/>
<ControllerCoreRGRB5 value="1"/>
<ControllerCoreRGRB6 value="1"/>
<ControllerCoreRGRB7 value="1"/>
<ControllerCoreRGRB8 value="0"/>
<ControllerCoreRGRB9 value="0"/>
<ControllerCoreRGRB10 value="0"/>
<ControllerCoreRGRB11 value="0"/>
<ControllerCoreRGRB12 value="0"/>
<ControllerCoreRGRB13 value="0"/>
<ControllerCoreRGRB14 value="0"/>
<ControllerCoreRGRB15 value="0"/>
<!-- Postpone, pull-in -->
<ControllerCoreRefEnablePostpone value="0"/>
<ControllerCoreRefEnablePullIn value="0"/>
<ControllerCoreRefMaxPostponed value="8"/>
<ControllerCoreRefMaxPulledIn value="8"/>
<ControllerCoreRefForceMaxPostponeBurst value="0"/>
</mcconfig>

42
DRAMSys/library/resources/configs/mcconfigs/fr_fcfs_bw_buffer16_close_page.xml
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@@ -1,42 +0,0 @@
<mcconfig>
<OpenPagePolicy value="0" />
<MaxNrOfTransactions value="16" />
<Scheduler value="FR_FCFS" />
<Capsize value="5" />
<PowerDownMode value="NoPowerDown" />
<PowerDownTimeout value="100" />
<!-- Bankwise -->
<BankwiseLogic value="1"/>
<!-- Refresh yes, no -->
<ControllerCoreRefDisable value="0"/>
<!-- Refresh Mode. 1: 1X, 2: 2X, 4: 4X (e.g., DDR4) -->
<ControllerCoreRefMode value="1"/>
<!-- Number of AR commands in a tREFI in 1X mode -->
<ControllerCoreRefNumARCmdsIntREFI value="8192"/>
<!-- RGR -->
<ControllerCoreRGR value="0"/>
<ControllerCoreRGRRowInc value="1"/>
<!-- Banks to be refreshed in RGR mode. 1: yes, 0: no (max. 16 banks) -->
<ControllerCoreRGRB0 value="1"/>
<ControllerCoreRGRB1 value="1"/>
<ControllerCoreRGRB2 value="1"/>
<ControllerCoreRGRB3 value="1"/>
<ControllerCoreRGRB4 value="1"/>
<ControllerCoreRGRB5 value="1"/>
<ControllerCoreRGRB6 value="1"/>
<ControllerCoreRGRB7 value="1"/>
<ControllerCoreRGRB8 value="0"/>
<ControllerCoreRGRB9 value="0"/>
<ControllerCoreRGRB10 value="0"/>
<ControllerCoreRGRB11 value="0"/>
<ControllerCoreRGRB12 value="0"/>
<ControllerCoreRGRB13 value="0"/>
<ControllerCoreRGRB14 value="0"/>
<ControllerCoreRGRB15 value="0"/>
<!-- Postpone, pull-in -->
<ControllerCoreRefEnablePostpone value="0"/>
<ControllerCoreRefEnablePullIn value="0"/>
<ControllerCoreRefMaxPostponed value="8"/>
<ControllerCoreRefMaxPulledIn value="8"/>
<ControllerCoreRefForceMaxPostponeBurst value="0"/>
</mcconfig>

10
DRAMSys/library/resources/configs/mcconfigs/fr_fcfs_grp.xml
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@@ -1,7 +1,13 @@
<mcconfig>
<OpenPagePolicy value="1" />
<MaxNrOfTransactions value="16" />
<MaxNrOfTransactions value="8" />
<!-- Open, OpenAdaptive, Closed, ClosedAdaptive -->
<PagePolicy value="Open" />
<!-- Fifo, FrFcfs, FrFcfsGrp -->
<Scheduler value="FrFcfsGrp" />
<!-- Oldest, Strict -->
<CmdMux value="Oldest" />
<!-- Fifo, Reorder -->
<RespQueue value="Fifo" />
<Capsize value="5" />
<!-- 4 Modes: NoPowerDown, Staggered, TimeoutPDN, TimeoutSREF -->
<PowerDownMode value="NoPowerDown" />

38
DRAMSys/library/resources/configs/mcconfigs/fr_fcfs_nbw_buffer16.xml
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@@ -1,38 +0,0 @@
<mcconfig>
<BankwiseLogic value="1"/>
<OpenPagePolicy value="1" />
<MaxNrOfTransactions value="16" />
<Scheduler value="FR_FCFS" />
<Capsize value="5" />
<PowerDownMode value="NoPowerDown" />
<PowerDownTimeout value="100" />
<ControllerCoreRefDisable value="0"/>
<ControllerCoreRefForceMaxPostponeBurst value="0"/>
<ControllerCoreRefEnablePostpone value="0"/>
<ControllerCoreRefEnablePullIn value="0"/>
<ControllerCoreRefMaxPostponed value="8"/>
<ControllerCoreRefMaxPulledIn value="8"/>
<ControllerCoreRefDisable value="0"/>
<ControllerCoreRGR value="1"/>
<ControllerCoreRefNumARCmdsIntREFI value="8192"/>
<ControllerCoreRGRRowInc value="1"/>
<!-- Select the banks you want to refresh. 1: yes, 0: no (max. 16 banks) -->
<ControllerCoreRGRB0 value="1"/>
<ControllerCoreRGRB1 value="1"/>
<ControllerCoreRGRB2 value="1"/>
<ControllerCoreRGRB3 value="1"/>
<ControllerCoreRGRB4 value="1"/>
<ControllerCoreRGRB5 value="1"/>
<ControllerCoreRGRB6 value="1"/>
<ControllerCoreRGRB7 value="1"/>
<ControllerCoreRGRB8 value="0"/>
<ControllerCoreRGRB9 value="0"/>
<ControllerCoreRGRB10 value="0"/>
<ControllerCoreRGRB11 value="0"/>
<ControllerCoreRGRB12 value="0"/>
<ControllerCoreRGRB13 value="0"/>
<ControllerCoreRGRB14 value="0"/>
<ControllerCoreRGRB15 value="0"/>
</mcconfig>

42
DRAMSys/library/resources/configs/mcconfigs/fr_fcfs_nbw_buffer16_close_page.xml
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@@ -1,42 +0,0 @@
<mcconfig>
<OpenPagePolicy value="0" />
<MaxNrOfTransactions value="16" />
<Scheduler value="FR_FCFS" />
<Capsize value="5" />
<PowerDownMode value="NoPowerDown" />
<PowerDownTimeout value="100" />
<!-- Bankwise -->
<BankwiseLogic value="0"/>
<!-- Refresh yes, no -->
<ControllerCoreRefDisable value="0"/>
<!-- Refresh Mode. 1: 1X, 2: 2X, 4: 4X (e.g., DDR4) -->
<ControllerCoreRefMode value="1"/>
<!-- Number of AR commands in a tREFI in 1X mode -->
<ControllerCoreRefNumARCmdsIntREFI value="8192"/>
<!-- RGR -->
<ControllerCoreRGR value="0"/>
<ControllerCoreRGRRowInc value="1"/>
<!-- Banks to be refreshed in RGR mode. 1: yes, 0: no (max. 16 banks) -->
<ControllerCoreRGRB0 value="1"/>
<ControllerCoreRGRB1 value="1"/>
<ControllerCoreRGRB2 value="1"/>
<ControllerCoreRGRB3 value="1"/>
<ControllerCoreRGRB4 value="1"/>
<ControllerCoreRGRB5 value="1"/>
<ControllerCoreRGRB6 value="1"/>
<ControllerCoreRGRB7 value="1"/>
<ControllerCoreRGRB8 value="0"/>
<ControllerCoreRGRB9 value="0"/>
<ControllerCoreRGRB10 value="0"/>
<ControllerCoreRGRB11 value="0"/>
<ControllerCoreRGRB12 value="0"/>
<ControllerCoreRGRB13 value="0"/>
<ControllerCoreRGRB14 value="0"/>
<ControllerCoreRGRB15 value="0"/>
<!-- Postpone, pull-in -->
<ControllerCoreRefEnablePostpone value="0"/>
<ControllerCoreRefEnablePullIn value="0"/>
<ControllerCoreRefMaxPostponed value="8"/>
<ControllerCoreRefMaxPulledIn value="8"/>
<ControllerCoreRefForceMaxPostponeBurst value="0"/>
</mcconfig>

43
DRAMSys/library/resources/configs/mcconfigs/fr_fcfs_rp.xml
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@@ -1,43 +0,0 @@
<mcconfig>
<OpenPagePolicy value="1" />
<MaxNrOfTransactions value="16" />
<Scheduler value="FrFcfsRp" />
<Capsize value="5" />
<!-- 4 Modes: NoPowerDown, Staggered, TimeoutPDN, TimeoutSREF -->
<PowerDownMode value="NoPowerDown" />
<PowerDownTimeout value="100" />
<!-- Bankwise -->
<BankwiseLogic value="0"/>
<!-- Refresh yes, no -->
<ControllerCoreRefDisable value="0"/>
<!-- Refresh Mode. 1: 1X, 2: 2X, 4: 4X (e.g., DDR4) -->
<ControllerCoreRefMode value="1"/>
<!-- Number of AR commands in a tREFI in 1X mode -->
<ControllerCoreRefNumARCmdsIntREFI value="8192"/>
<!-- RGR -->
<ControllerCoreRGR value="0"/>
<ControllerCoreRGRRowInc value="1"/>
<!-- Banks to be refreshed in RGR mode. 1: yes, 0: no (max. 16 banks) -->
<ControllerCoreRGRB0 value="1"/>
<ControllerCoreRGRB1 value="1"/>
<ControllerCoreRGRB2 value="1"/>
<ControllerCoreRGRB3 value="1"/>
<ControllerCoreRGRB4 value="1"/>
<ControllerCoreRGRB5 value="1"/>
<ControllerCoreRGRB6 value="1"/>
<ControllerCoreRGRB7 value="1"/>
<ControllerCoreRGRB8 value="0"/>
<ControllerCoreRGRB9 value="0"/>
<ControllerCoreRGRB10 value="0"/>
<ControllerCoreRGRB11 value="0"/>
<ControllerCoreRGRB12 value="0"/>
<ControllerCoreRGRB13 value="0"/>
<ControllerCoreRGRB14 value="0"/>
<ControllerCoreRGRB15 value="0"/>
<!-- Postpone, pull-in -->
<ControllerCoreRefEnablePostpone value="0"/>
<ControllerCoreRefEnablePullIn value="0"/>
<ControllerCoreRefMaxPostponed value="8"/>
<ControllerCoreRefMaxPulledIn value="8"/>
<ControllerCoreRefForceMaxPostponeBurst value="0"/>
</mcconfig>

43
DRAMSys/library/resources/configs/mcconfigs/grp.xml
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@@ -1,43 +0,0 @@
<mcconfig>
<OpenPagePolicy value="1" />
<MaxNrOfTransactions value="32" />
<Scheduler value="Grp" />
<Capsize value="5" />
<!-- 4 Modes: NoPowerDown, Staggered, TimeoutPDN, TimeoutSREF -->
<PowerDownMode value="NoPowerDown" />
<PowerDownTimeout value="100" />
<!-- Bankwise -->
<BankwiseLogic value="0"/>
<!-- Refresh yes, no -->
<ControllerCoreRefDisable value="0"/>
<!-- Refresh Mode. 1: 1X, 2: 2X, 4: 4X (e.g., DDR4) -->
<ControllerCoreRefMode value="1"/>
<!-- Number of AR commands in a tREFI in 1X mode -->
<ControllerCoreRefNumARCmdsIntREFI value="8192"/>
<!-- RGR -->
<ControllerCoreRGR value="0"/>
<ControllerCoreRGRRowInc value="1"/>
<!-- Banks to be refreshed in RGR mode. 1: yes, 0: no (max. 16 banks) -->
<ControllerCoreRGRB0 value="1"/>
<ControllerCoreRGRB1 value="1"/>
<ControllerCoreRGRB2 value="1"/>
<ControllerCoreRGRB3 value="1"/>
<ControllerCoreRGRB4 value="1"/>
<ControllerCoreRGRB5 value="1"/>
<ControllerCoreRGRB6 value="1"/>
<ControllerCoreRGRB7 value="1"/>
<ControllerCoreRGRB8 value="0"/>
<ControllerCoreRGRB9 value="0"/>
<ControllerCoreRGRB10 value="0"/>
<ControllerCoreRGRB11 value="0"/>
<ControllerCoreRGRB12 value="0"/>
<ControllerCoreRGRB13 value="0"/>
<ControllerCoreRGRB14 value="0"/>
<ControllerCoreRGRB15 value="0"/>
<!-- Postpone, pull-in -->
<ControllerCoreRefEnablePostpone value="0"/>
<ControllerCoreRefEnablePullIn value="0"/>
<ControllerCoreRefMaxPostponed value="8"/>
<ControllerCoreRefMaxPulledIn value="8"/>
<ControllerCoreRefForceMaxPostponeBurst value="0"/>
</mcconfig>

43
DRAMSys/library/resources/configs/mcconfigs/par_bs.xml
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@@ -1,43 +0,0 @@
<mcconfig>
<OpenPagePolicy value="1" />
<MaxNrOfTransactions value="8" />
<Scheduler value="PAR_BS" />
<Capsize value="5" />
<!-- 4 Modes: NoPowerDown, Staggered, TimeoutPDN, TimeoutSREF -->
<PowerDownMode value="NoPowerDown" />
<PowerDownTimeout value="100" />
<!-- Bankwise -->
<BankwiseLogic value="0"/>
<!-- Refresh yes, no -->
<ControllerCoreRefDisable value="0"/>
<!-- Refresh Mode. 1: 1X, 2: 2X, 4: 4X (e.g., DDR4) -->
<ControllerCoreRefMode value="1"/>
<!-- Number of AR commands in a tREFI in 1X mode -->
<ControllerCoreRefNumARCmdsIntREFI value="8192"/>
<!-- RGR -->
<ControllerCoreRGR value="0"/>
<ControllerCoreRGRRowInc value="1"/>
<!-- Banks to be refreshed in RGR mode. 1: yes, 0: no (max. 16 banks) -->
<ControllerCoreRGRB0 value="1"/>
<ControllerCoreRGRB1 value="1"/>
<ControllerCoreRGRB2 value="1"/>
<ControllerCoreRGRB3 value="1"/>
<ControllerCoreRGRB4 value="1"/>
<ControllerCoreRGRB5 value="1"/>
<ControllerCoreRGRB6 value="1"/>
<ControllerCoreRGRB7 value="1"/>
<ControllerCoreRGRB8 value="0"/>
<ControllerCoreRGRB9 value="0"/>
<ControllerCoreRGRB10 value="0"/>
<ControllerCoreRGRB11 value="0"/>
<ControllerCoreRGRB12 value="0"/>
<ControllerCoreRGRB13 value="0"/>
<ControllerCoreRGRB14 value="0"/>
<ControllerCoreRGRB15 value="0"/>
<!-- Postpone, pull-in -->
<ControllerCoreRefEnablePostpone value="0"/>
<ControllerCoreRefEnablePullIn value="0"/>
<ControllerCoreRefMaxPostponed value="8"/>
<ControllerCoreRefMaxPulledIn value="8"/>
<ControllerCoreRefForceMaxPostponeBurst value="0"/>
</mcconfig>

42
DRAMSys/library/resources/configs/mcconfigs/rgrmccfg.xml
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@@ -1,42 +0,0 @@
<mcconfig>
<OpenPagePolicy value="1" />
<MaxNrOfTransactions value="16" />
<Scheduler value="FrFcfs" />
<Capsize value="5" />
<PowerDownMode value="NoPowerDown" />
<PowerDownTimeout value="100" />
<!-- Bankwise -->
<BankwiseLogic value="0"/>
<!-- Refresh yes, no -->
<ControllerCoreRefDisable value="0"/>
<!-- Refresh Mode. 1: 1X, 2: 2X, 4: 4X (e.g., DDR4) -->
<ControllerCoreRefMode value="1"/>
<!-- Number of AR commands in a tREFI in 1X mode -->
<ControllerCoreRefNumARCmdsIntREFI value="8192"/>
<!-- RGR -->
<ControllerCoreRGR value="1"/>
<ControllerCoreRGRRowInc value="1"/>
<!-- Banks to be refreshed in RGR mode. 1: yes, 0: no (max. 16 banks) -->
<ControllerCoreRGRB0 value="1"/>
<ControllerCoreRGRB1 value="1"/>
<ControllerCoreRGRB2 value="1"/>
<ControllerCoreRGRB3 value="1"/>
<ControllerCoreRGRB4 value="1"/>
<ControllerCoreRGRB5 value="1"/>
<ControllerCoreRGRB6 value="1"/>
<ControllerCoreRGRB7 value="1"/>
<ControllerCoreRGRB8 value="0"/>
<ControllerCoreRGRB9 value="0"/>
<ControllerCoreRGRB10 value="0"/>
<ControllerCoreRGRB11 value="0"/>
<ControllerCoreRGRB12 value="0"/>
<ControllerCoreRGRB13 value="0"/>
<ControllerCoreRGRB14 value="0"/>
<ControllerCoreRGRB15 value="0"/>
<!-- Postpone, pull-in -->
<ControllerCoreRefEnablePostpone value="0"/>
<ControllerCoreRefEnablePullIn value="0"/>
<ControllerCoreRefMaxPostponed value="8"/>
<ControllerCoreRefMaxPulledIn value="8"/>
<ControllerCoreRefForceMaxPostponeBurst value="0"/>
</mcconfig>

43
DRAMSys/library/resources/configs/mcconfigs/sms.xml
View File

@@ -1,43 +0,0 @@
<mcconfig>
<OpenPagePolicy value="1" />
<MaxNrOfTransactions value="30" />
<Scheduler value="SMS" />
<SJFProbability value="50" />
<RequestBufferSize value = "10" />
<PowerDownMode value="NoPowerDown" /> <!-- 4 Modes: NoPowerDown, Staggered, TimeoutPDN, TimeoutSREF -->
<PowerDownTimeout value="100" />
<!-- Bankwise -->
<BankwiseLogic value="0"/>
<!-- Refresh yes, no -->
<ControllerCoreRefDisable value="0"/>
<!-- Refresh Mode. 1: 1X, 2: 2X, 4: 4X (e.g., DDR4) -->
<ControllerCoreRefMode value="1"/>
<!-- Number of AR commands in a tREFI in 1X mode -->
<ControllerCoreRefNumARCmdsIntREFI value="8192"/>
<!-- RGR -->
<ControllerCoreRGR value="0"/>
<ControllerCoreRGRRowInc value="1"/>
<!-- Banks to be refreshed in RGR mode. 1: yes, 0: no (max. 16 banks) -->
<ControllerCoreRGRB0 value="1"/>
<ControllerCoreRGRB1 value="1"/>
<ControllerCoreRGRB2 value="1"/>
<ControllerCoreRGRB3 value="1"/>
<ControllerCoreRGRB4 value="1"/>
<ControllerCoreRGRB5 value="1"/>
<ControllerCoreRGRB6 value="1"/>
<ControllerCoreRGRB7 value="1"/>
<ControllerCoreRGRB8 value="0"/>
<ControllerCoreRGRB9 value="0"/>
<ControllerCoreRGRB10 value="0"/>
<ControllerCoreRGRB11 value="0"/>
<ControllerCoreRGRB12 value="0"/>
<ControllerCoreRGRB13 value="0"/>
<ControllerCoreRGRB14 value="0"/>
<ControllerCoreRGRB15 value="0"/>
<!-- Postpone, pull-in -->
<ControllerCoreRefEnablePostpone value="0"/>
<ControllerCoreRefEnablePullIn value="0"/>
<ControllerCoreRefMaxPostponed value="8"/>
<ControllerCoreRefMaxPulledIn value="8"/>
<ControllerCoreRefForceMaxPostponeBurst value="0"/>
</mcconfig>

6
DRAMSys/library/resources/simulations/ddr3-example.xml
View File

@@ -8,9 +8,9 @@
<!-- Memory Device Specification: Which Device is on the DDR3 DIMM -->
<memspec src="MICRON_1Gb_DDR3-1600_8bit_G.xml"></memspec>
<!-- Addressmapping Configuration of the Memory Controller -->
<addressmapping src="am_ddr3_8x1Gbx8_dimm_p1KB_brc.xml"></addressmapping>
<addressmapping src="am_ddr3_8x1Gbx8_dimm_p1KB_rbc.xml"></addressmapping>
<!-- Memory Controller Configuration: -->
<mcconfig src="fifoStrict.xml"/>
<mcconfig src="fifo.xml"/>
<!--
The following trace setup is only used in standalone mode.
In library mode e.g. in Platform Architect the trace setup is ignored.
@@ -20,6 +20,6 @@
This device mimics an image processing application
running on an FPGA with 200 Mhz.
-->
<device clkMhz="200">ddr3_example.stl</device>
<device clkMhz="800">ddr3_example.stl</device>
</tracesetup>
</simulation>

12
DRAMSys/library/src/configuration/Configuration.cpp
View File

@@ -136,14 +136,16 @@ void Configuration::setParameter(std::string name, std::string value)
{
if (name == "BankwiseLogic")
BankwiseLogic = string2bool(value);
else if (name == "OpenPagePolicy")
OpenPagePolicy = string2bool(value);
else if (name == "AdaptivePagePolicy")
AdaptivePagePolicy = string2bool(value);
else if (name == "PagePolicy")
pagePolicy = value;
else if (name == "MaxNrOfTransactions")
MaxNrOfTransactions = string2int(value);
else if (name == "Scheduler")
Scheduler = value;
scheduler = value;
else if (name == "CmdMux")
cmdMux = value;
else if (name == "RespQueue")
respQueue = value;
else if (name == "SJFProbability")
{
if (string2int(value) > 100 || string2int(value) < 0)

5
DRAMSys/library/src/configuration/Configuration.h
View File

@@ -64,10 +64,9 @@ struct Configuration
// MCConfig:
bool BankwiseLogic = false;
bool OpenPagePolicy = true;
bool AdaptivePagePolicy = false;
unsigned int MaxNrOfTransactions = 8;
std::string Scheduler;
std::string pagePolicy;
std::string scheduler, cmdMux, respQueue;
unsigned int SJFProbability;
unsigned int RequestBufferSize;
unsigned int Capsize = 5;

14
DRAMSys/library/src/configuration/memspec/MemSpec.cpp
View File

@@ -71,17 +71,3 @@ unsigned MemSpec::getCommandLength(Command command) const
{
return commandLength[command];
}
//sc_time MemSpec::getMinExecutionTimeForPowerDownCmd(Command command) const
//{
// if (command == Command::PDEA || command == Command::PDEP)
// return tCKE;
// else if (command == Command::SREFEN)
// return tCKESR;
// else
// {
// SC_REPORT_FATAL("getMinimalExecutionTime",
// "command is not know or command has a fixed execution time");
// return SC_ZERO_TIME;
// }
//}

5
DRAMSys/library/src/configuration/memspec/MemSpec.h
View File

@@ -64,9 +64,6 @@ struct MemSpec
unsigned getCommandLength(Command) const;
// Returns the minimum execution time for commands that have a variable execution time
//virtual sc_time getMinExecutionTimeForPowerDownCmd(Command command) const = 0;
std::string MemoryId = "not defined.";
std::string MemoryType = "not defined.";
@@ -87,7 +84,7 @@ struct MemSpec
double clkMHz;
sc_time clk;
// Command lengths on bus, standardly one clock cycle
// Command lengths on bus, usually one clock cycle
std::vector<unsigned> commandLength;
};

83
DRAMSys/library/src/controller/Controller.cpp
View File

@@ -35,10 +35,6 @@
#include "Controller.h"
#include "../configuration/Configuration.h"
#include "scheduler/SchedulerFifo.h"
#include "scheduler/SchedulerFrFcfs.h"
#include "cmdmux/CmdMuxStrict.h"
#include "cmdmux/CmdMuxOldest.h"
#include "../common/dramExtensions.h"
#include "../common/protocol.h"
#include "checker/CheckerDDR3.h"
@@ -50,13 +46,18 @@
#include "checker/CheckerGDDR5.h"
#include "checker/CheckerGDDR5X.h"
#include "checker/CheckerGDDR6.h"
#include "scheduler/SchedulerFifo.h"
#include "scheduler/SchedulerFrFcfs.h"
#include "scheduler/SchedulerFrFcfsGrp.h"
#include "cmdmux/CmdMuxStrict.h"
#include "cmdmux/CmdMuxOldest.h"
#include "respqueue/RespQueueFifo.h"
#include "respqueue/RespQueueReorder.h"
#include "refresh/RefreshManager.h"
#include "refresh/RefreshManagerDummy.h"
#include "refresh/RefreshManagerBankwise.h"
#include "powerdown/PowerDownManagerStaggered.h"
#include "powerdown/PowerDownManagerDummy.h"
#include "respqueue/RespQueueFifo.h"
#include "respqueue/RespQueueReorder.h"
Controller::Controller(sc_module_name name) :
GenericController(name)
@@ -92,46 +93,52 @@ Controller::Controller(sc_module_name name) :
SC_REPORT_FATAL("Controller", "Unsupported DRAM type!");
// instantiate scheduler and command mux
if (config.Scheduler == "FifoStrict")
{
if (config.scheduler == "Fifo")
scheduler = new SchedulerFifo();
commandMux = new CmdMuxStrict();
}
else if (config.Scheduler == "FrFcfs")
{
else if (config.scheduler == "FrFcfs")
scheduler = new SchedulerFrFcfs();
commandMux = new CmdMuxOldest();
}
else if (config.scheduler == "FrFcfsGrp")
scheduler = new SchedulerFrFcfsGrp();
else
SC_REPORT_FATAL("Controller", "Selected scheduler not supported!");
if (config.cmdMux == "Oldest")
commandMux = new CmdMuxOldest();
else if (config.cmdMux == "Strict")
commandMux = new CmdMuxStrict();
else
SC_REPORT_FATAL("Controller", "Selected cmdmux not supported!");
if (config.respQueue == "Fifo")
respQueue = new RespQueueFifo();
else if (config.respQueue == "Reorder")
respQueue = new RespQueueReorder();
else
SC_REPORT_FATAL("Controller", "Selected respqueue not supported!");
// instantiate bank machines (one per bank)
if (config.OpenPagePolicy)
if (config.pagePolicy == "Open")
{
if (config.AdaptivePagePolicy)
{
for (unsigned bankID = 0; bankID < memSpec->NumberOfBanks; bankID++)
bankMachines.push_back(new BankMachineOpenAdaptive(scheduler, checker, Bank(bankID)));
}
else
{
for (unsigned bankID = 0; bankID < memSpec->NumberOfBanks; bankID++)
bankMachines.push_back(new BankMachineOpen(scheduler, checker, Bank(bankID)));
}
for (unsigned bankID = 0; bankID < memSpec->NumberOfBanks; bankID++)
bankMachines.push_back(new BankMachineOpen(scheduler, checker, Bank(bankID)));
}
else if (config.pagePolicy == "OpenAdaptive")
{
for (unsigned bankID = 0; bankID < memSpec->NumberOfBanks; bankID++)
bankMachines.push_back(new BankMachineOpenAdaptive(scheduler, checker, Bank(bankID)));
}
else if (config.pagePolicy == "Closed")
{
for (unsigned bankID = 0; bankID < memSpec->NumberOfBanks; bankID++)
bankMachines.push_back(new BankMachineClosed(scheduler, checker, Bank(bankID)));
}
else if (config.pagePolicy == "ClosedAdaptive")
{
for (unsigned bankID = 0; bankID < memSpec->NumberOfBanks; bankID++)
bankMachines.push_back(new BankMachineClosedAdaptive(scheduler, checker, Bank(bankID)));
}
else
{
if (config.AdaptivePagePolicy)
{
for (unsigned bankID = 0; bankID < memSpec->NumberOfBanks; bankID++)
bankMachines.push_back(new BankMachineClosedAdaptive(scheduler, checker, Bank(bankID)));
}
else
{
for (unsigned bankID = 0; bankID < memSpec->NumberOfBanks; bankID++)
bankMachines.push_back(new BankMachineClosed(scheduler, checker, Bank(bankID)));
}
}
SC_REPORT_FATAL("Controller", "Selected page policy not supported!");
for (unsigned rankID = 0; rankID < memSpec->NumberOfRanks; rankID++)
{
@@ -189,8 +196,6 @@ Controller::Controller(sc_module_name name) :
}
}
respQueue = new RespQueueFifo();
startBandwidthIdleCollector();
}

3
DRAMSys/library/src/controller/scheduler/SchedulerFrFcfs.cpp
View File

@@ -75,8 +75,7 @@ tlm_generic_payload *SchedulerFrFcfs::getNextRequest(BankMachine *bankMachine)
unsigned bankID = bankMachine->getBank().ID();
if (!buffer[bankID].empty())
{
BmState currentState = bankMachine->getState();
if (currentState == BmState::Activated)
if (bankMachine->getState() == BmState::Activated)
{
// Search for row hit
Row openRow = bankMachine->getOpenRow();

138
DRAMSys/library/src/controller/scheduler/SchedulerFrFcfsGrp.cpp Normal file
View File

@@ -0,0 +1,138 @@
/*
* Copyright (c) 2020, University of Kaiserslautern
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
* OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Author: Lukas Steiner
*/
#include "SchedulerFrFcfsGrp.h"
SchedulerFrFcfsGrp::SchedulerFrFcfsGrp()
{
buffer = std::vector<std::list<tlm_generic_payload *>>
(Configuration::getInstance().memSpec->NumberOfBanks);
maxNumberOfRequests = Configuration::getInstance().MaxNrOfTransactions;
}
bool SchedulerFrFcfsGrp::hasBufferSpace(tlm_generic_payload *payload)
{
if (buffer[DramExtension::getBank(payload).ID()].size() < maxNumberOfRequests)
return true;
else
return false;
}
void SchedulerFrFcfsGrp::storeRequest(tlm_generic_payload *payload)
{
buffer[DramExtension::getBank(payload).ID()].push_back(payload);
}
void SchedulerFrFcfsGrp::removeRequest(tlm_generic_payload *payload)
{
lastCommand = payload->get_command();
unsigned bankID = DramExtension::getBank(payload).ID();
for (auto it = buffer[bankID].begin(); it != buffer[bankID].end(); it++)
{
if (*it == payload)
{
buffer[bankID].erase(it);
return;
}
}
SC_REPORT_FATAL("SchedulerFrFcfs", "removeRequest failed!");
}
tlm_generic_payload *SchedulerFrFcfsGrp::getNextRequest(BankMachine *bankMachine)
{
unsigned bankID = bankMachine->getBank().ID();
if (!buffer[bankID].empty())
{
if (bankMachine->getState() == BmState::Activated)
{
// Filter all row hits
Row openRow = bankMachine->getOpenRow();
std::list<tlm_generic_payload *> rowHits;
for (auto it = buffer[bankID].begin(); it != buffer[bankID].end(); it++)
{
if (DramExtension::getRow(*it) == openRow)
rowHits.push_back(*it);
}
if (!rowHits.empty())
{
for (auto outerIt = rowHits.begin(); outerIt != rowHits.end(); outerIt++)
{
if ((*outerIt)->get_command() == lastCommand)
{
bool hazardDetected = false;
for (auto innerIt = rowHits.begin(); *innerIt != *outerIt; innerIt++)
{
if ((*outerIt)->get_address() == (*innerIt)->get_address())
{
hazardDetected = true;
break;
}
}
if (!hazardDetected)
return *outerIt;
}
}
// no rd/wr hit found -> take first row hit
return *rowHits.begin();
}
}
// No row hit found or bank precharged
return buffer[bankID].front();
}
return nullptr;
}
bool SchedulerFrFcfsGrp::hasFurtherRowHit(Bank bank, Row row)
{
unsigned rowHitCounter = 0;
for (auto it = buffer[bank.ID()].begin(); it != buffer[bank.ID()].end(); it++)
{
if (DramExtension::getRow(*it) == row)
{
rowHitCounter++;
if (rowHitCounter == 2)
return true;
}
}
return false;
}
bool SchedulerFrFcfsGrp::hasFurtherRequest(Bank bank)
{
if (buffer[bank.ID()].size() >= 2)
return true;
else
return false;
}

64
DRAMSys/library/src/controller/scheduler/SchedulerFrFcfsGrp.h Normal file
View File

@@ -0,0 +1,64 @@
/*
* Copyright (c) 2020, University of Kaiserslautern
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
* OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Author: Lukas Steiner
*/
#ifndef SCHEDULERFRFCFSGRP_H
#define SCHEDULERFRFCFSGRP_H
#include <tlm.h>
#include <vector>
#include <list>
#include "SchedulerIF.h"
#include "../../common/dramExtensions.h"
#include "../BankMachine.h"
using namespace tlm;
class SchedulerFrFcfsGrp : public SchedulerIF
{
public:
SchedulerFrFcfsGrp();
virtual bool hasBufferSpace(tlm_generic_payload *) override;
virtual void storeRequest(tlm_generic_payload *) override;
virtual void removeRequest(tlm_generic_payload *) override;
virtual tlm_generic_payload *getNextRequest(BankMachine *) override;
virtual bool hasFurtherRowHit(Bank, Row) override;
virtual bool hasFurtherRequest(Bank) override;
private:
std::vector<std::list<tlm_generic_payload *>> buffer;
unsigned maxNumberOfRequests;
tlm_command lastCommand = TLM_READ_COMMAND;
};
#endif // SCHEDULERFRFCFSGRP_H