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resolved most warnings

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This commit is contained in:
robert
2014-07-01 14:39:58 +02:00
parent e128263833
commit 61bacdfb9f
12 changed files with 78 additions and 79 deletions
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1
dram/src/common/DebugManager.h
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@@ -35,6 +35,7 @@ public:
void addToWhiteList(std::string sender);
void addToWhiteList(std::vector<std::string> senders);
private:
DebugManager();
DebugManager(const DebugManager&){}

2
dram/src/controller/Controller.h
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@@ -49,7 +49,7 @@ public:
tlm_utils::simple_initiator_socket<Controller, BUSWIDTH, tlm::tlm_base_protocol_types> iSocket;
tlm_utils::simple_target_socket<Controller, BUSWIDTH, tlm::tlm_base_protocol_types> tSocket;
Controller(sc_module_name name) :
Controller(sc_module_name /*name*/) :
frontendPEQ(this, &Controller::frontendPEQCallback), dramPEQ(this, &Controller::dramPEQCallback), controllerCorePEQ(
this, &Controller::controllerCorePEQCallback), debugManager(DebugManager::getInstance())
{

4
dram/src/controller/core/ControllerCore.cpp
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@@ -30,8 +30,8 @@ namespace core {
std::string ControllerCore::senderName = "Controller Core";
ControllerCore::ControllerCore(IWrapperConnector& wrapperConnector, std::map<Bank, int>& numberOfPayloads) :
config(Configuration::getInstance()), state(&config), wrapper(wrapperConnector), commandChecker(), numberOfPayloads(
numberOfPayloads), savedState(&config), commandSequenceGenerator(state), commandSequenceScheduler(*this)
config(Configuration::getInstance()), state(&config), wrapper(wrapperConnector), numberOfPayloads(
numberOfPayloads), commandChecker(), savedState(&config), commandSequenceGenerator(state), commandSequenceScheduler(*this)
{
commandChecker[Command::Activate] = new ActivateChecker(config, state);

4
dram/src/controller/core/powerdown/PowerDownManagerTimeout.cpp
View File

@@ -102,7 +102,7 @@ void PowerDownManagerTimeout::wakeUpForRefresh(Bank bank, sc_time time)
}
}
void PowerDownManagerTimeout::triggerSleep(Bank bank, sc_time time)
void PowerDownManagerTimeout::triggerSleep(Bank /*bank*/, sc_time time)
{
if(canSleep() && !isInPowerDown())
{
@@ -110,7 +110,7 @@ void PowerDownManagerTimeout::triggerSleep(Bank bank, sc_time time)
}
}
bool PowerDownManagerTimeout::isInSelfRefresh(Bank bank)
bool PowerDownManagerTimeout::isInSelfRefresh(Bank /*bank*/)
{
return powerDownState == PowerDownState::PDNSelfRefresh;
}

64
dram/src/controller/core/refresh/RefreshManagerBankwise.cpp
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@@ -15,13 +15,13 @@ using namespace std;
namespace core {
RefreshManagerBankwise::RefreshManagerBankwise(ControllerCore& controller) :
controller(controller)
controller(controller)
{
for (Bank bank : controller.getBanks())
{
setUpDummy(refreshPayloads[bank], bank);
planNextRefresh(bank);
}
for (Bank bank : controller.getBanks())
{
setUpDummy(refreshPayloads[bank], bank);
planNextRefresh(bank);
}
}
RefreshManagerBankwise::~RefreshManagerBankwise()
@@ -30,58 +30,56 @@ RefreshManagerBankwise::~RefreshManagerBankwise()
bool RefreshManagerBankwise::hasCollision(const CommandSchedule& schedule)
{
return schedule.getStart() < controller.state.getLastCommand(Command::AutoRefresh, schedule.getBank()).getEnd()
|| schedule.getEnd() > nextPlannedRefreshs[schedule.getBank()];
return schedule.getStart() < controller.state.getLastCommand(Command::AutoRefresh, schedule.getBank()).getEnd()
|| schedule.getEnd() > nextPlannedRefreshs[schedule.getBank()];
}
bool RefreshManagerBankwise::hasCollision(const ScheduledCommand& command)
{
const ScheduledCommand& ref= controller.state.getLastCommand(Command::AutoRefresh, command.getBank());
return command.getStart() < controller.state.getLastCommand(Command::AutoRefresh, command.getBank()).getEnd()
|| command.getEnd() > nextPlannedRefreshs[command.getBank()];}
return command.getStart() < controller.state.getLastCommand(Command::AutoRefresh, command.getBank()).getEnd()
|| command.getEnd() > nextPlannedRefreshs[command.getBank()];}
void RefreshManagerBankwise::scheduleRefresh(tlm::tlm_generic_payload& payload, sc_time time)
{
sc_assert(!isInvalidated(payload, time));
sc_assert(!isInvalidated(payload, time));
tlm::tlm_generic_payload& refreshPayload = refreshPayloads[DramExtension::getExtension(payload).getBank()];
tlm::tlm_generic_payload& refreshPayload = refreshPayloads[DramExtension::getExtension(payload).getBank()];
DramExtension& extension = DramExtension::getExtension(refreshPayload);
DramExtension& extension = DramExtension::getExtension(refreshPayload);
if (controller.state.rowBufferStates.rowBufferIsOpen(extension.getBank()))
{
ScheduledCommand precharge(Command::Precharge, time, getExecutionTime(Command::Precharge, refreshPayload), extension);
if (controller.state.rowBufferStates.rowBufferIsOpen(extension.getBank()))
{
ScheduledCommand precharge(Command::Precharge, time, getExecutionTime(Command::Precharge, refreshPayload), extension);
controller.getCommandChecker(Command::Precharge).delayToSatisfyConstraints(precharge);
controller.state.change(precharge);
controller.wrapper.send(precharge, refreshPayload);
}
controller.getCommandChecker(Command::Precharge).delayToSatisfyConstraints(precharge);
controller.state.change(precharge);
controller.wrapper.send(precharge, refreshPayload);
}
ScheduledCommand nextRefresh(Command::AutoRefresh, time, getExecutionTime(Command::AutoRefresh, refreshPayload), extension);
controller.getCommandChecker(Command::AutoRefresh).delayToSatisfyConstraints(nextRefresh);
controller.state.change(nextRefresh);
controller.wrapper.send(nextRefresh, refreshPayload);
ScheduledCommand nextRefresh(Command::AutoRefresh, time, getExecutionTime(Command::AutoRefresh, refreshPayload), extension);
controller.getCommandChecker(Command::AutoRefresh).delayToSatisfyConstraints(nextRefresh);
controller.state.change(nextRefresh);
controller.wrapper.send(nextRefresh, refreshPayload);
extension.increaseRow();
planNextRefresh(extension.getBank());
extension.increaseRow();
planNextRefresh(extension.getBank());
}
void RefreshManagerBankwise::planNextRefresh(Bank bank)
{
nextPlannedRefreshs[bank] += Configuration::getInstance().Timings.refreshTimings[bank].tREFI;
controller.wrapper.send(REFTrigger, nextPlannedRefreshs[bank], refreshPayloads[bank]);
nextPlannedRefreshs[bank] += Configuration::getInstance().Timings.refreshTimings[bank].tREFI;
controller.wrapper.send(REFTrigger, nextPlannedRefreshs[bank], refreshPayloads[bank]);
}
void RefreshManagerBankwise::reInitialize(Bank bank, sc_time time)
{
nextPlannedRefreshs[bank] = clkAlign(time, Alignment::DOWN);
planNextRefresh(bank);
nextPlannedRefreshs[bank] = clkAlign(time, Alignment::DOWN);
planNextRefresh(bank);
}
bool RefreshManagerBankwise::isInvalidated(tlm::tlm_generic_payload& payload, sc_time time)
{
return nextPlannedRefreshs[DramExtension::getExtension(payload).getBank()] > time;
return nextPlannedRefreshs[DramExtension::getExtension(payload).getBank()] > time;
}
} /* namespace core */

64
dram/src/controller/core/scheduling/ScheduledCommand.cpp
View File

@@ -13,98 +13,98 @@ namespace core {
bool ScheduledCommand::isNoCommand() const
{
return (command == Command::NOP && start == SC_ZERO_TIME && executionTime == SC_ZERO_TIME && end == SC_ZERO_TIME);
return (command == Command::NOP && start == SC_ZERO_TIME && executionTime == SC_ZERO_TIME && end == SC_ZERO_TIME);
}
bool ScheduledCommand::isValidCommand() const
{
return !isNoCommand();
return !isNoCommand();
}
const sc_time ScheduledCommand::getStart() const
{
return start;
return start;
}
void ScheduledCommand::setStart(sc_time newStart)
{
start = newStart;
end = newStart + executionTime;
start = newStart;
end = newStart + executionTime;
}
void ScheduledCommand::delayStart(sc_time delay)
{
setStart(start+delay);
setStart(start+delay);
}
void ScheduledCommand::delayToMeetConstraint(sc_time previous, sc_time constraint)
{
delayStart(getDelayToMeetConstraint(previous, start, constraint));
delayStart(getDelayToMeetConstraint(previous, start, constraint));
}
const sc_time ScheduledCommand::getEnd() const
sc_time ScheduledCommand::getEnd() const
{
return end;
return end;
}
const Command ScheduledCommand::getCommand() const
Command ScheduledCommand::getCommand() const
{
return command;
return command;
}
const sc_time ScheduledCommand::getExecutionTime() const
sc_time ScheduledCommand::getExecutionTime() const
{
return executionTime;
return executionTime;
}
Bank ScheduledCommand::getBank() const
{
return extension.getBank();
return extension.getBank();
}
BankGroup ScheduledCommand::getBankGroup() const
{
return extension.getBankGroup();
return extension.getBankGroup();
}
Row ScheduledCommand::getRow() const
{
return extension.getRow();
return extension.getRow();
}
unsigned int ScheduledCommand::getBurstLength() const
{
return extension.getBurstlength();
return extension.getBurstlength();
}
bool ScheduledCommand::operator ==(const ScheduledCommand& b) const
{
return b.command == command && b.start == start && b.executionTime == executionTime && b.end == end;
return b.command == command && b.start == start && b.executionTime == executionTime && b.end == end;
}
bool ScheduledCommand::commandIsIn(const std::vector<Command>& commandSet) const
{
return isIn(command, commandSet);
return isIn(command, commandSet);
}
TimeInterval ScheduledCommand::getIntervalOnDataStrobe() const
{
sc_assert(
getCommand() == Command::Read || getCommand() == Command::ReadA
|| getCommand() == Command::Write
|| getCommand() == Command::WriteA);
sc_assert(
getCommand() == Command::Read || getCommand() == Command::ReadA
|| getCommand() == Command::Write
|| getCommand() == Command::WriteA);
TimingConfiguration& timings = Configuration::getInstance().Timings;
TimingConfiguration& timings = Configuration::getInstance().Timings;
if (getCommand() == Command::Read || getCommand() == Command::ReadA)
{
return TimeInterval(getStart() + timings.tRL,getStart() + timings.tRL + getReadAccessTime());
}
else
{
return TimeInterval(getStart() + timings.tWL - timings.clk / 2, getStart() + timings.tWL + getWriteAccessTime() - timings.clk / 2);
}
if (getCommand() == Command::Read || getCommand() == Command::ReadA)
{
return TimeInterval(getStart() + timings.tRL,getStart() + timings.tRL + getReadAccessTime());
}
else
{
return TimeInterval(getStart() + timings.tWL - timings.clk / 2, getStart() + timings.tWL + getWriteAccessTime() - timings.clk / 2);
}
}

8
dram/src/controller/core/scheduling/ScheduledCommand.h
View File

@@ -41,9 +41,9 @@ public:
void delayStart(sc_time delay);
void delayToMeetConstraint(sc_time previous, sc_time constraint);
const sc_time getEnd() const;
const Command getCommand() const;
const sc_time getExecutionTime() const;
sc_time getEnd() const;
Command getCommand() const;
sc_time getExecutionTime() const;
Bank getBank() const;
BankGroup getBankGroup() const;
@@ -57,11 +57,11 @@ public:
private:
DramExtension extension;
Command command;
sc_time start;
sc_time executionTime;
sc_time end;
DramExtension extension;
};
} /* namespace controller */

2
dram/src/controller/scheduler/PARBS.h
View File

@@ -25,8 +25,8 @@ public:
private:
void formBatch();
bool useExternalBankstates;
core::ControllerCore& controllerCore;
bool useExternalBankstates;
core::RowBufferState internalBankstates;
FR_FCFS *batch;
FR_FCFS *buffer;

2
dram/src/simulation/Simulation.cpp
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@@ -20,7 +20,7 @@ using namespace std;
namespace simulation {
Simulation::Simulation(sc_module_name name, string pathToResources, string traceName, DramSetup setup,
Simulation::Simulation(sc_module_name /*name*/, string pathToResources, string traceName, DramSetup setup,
std::vector<Device> devices) :
traceName(traceName), dramSetup(setup)

2
dram/src/simulation/SimulationManager.cpp
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@@ -16,7 +16,7 @@ using namespace simulation;
namespace simulation {
SimulationManager::SimulationManager(string resources) :
resources(resources), silent(false)
silent(false), resources(resources)
{
}

2
dram/src/simulation/TracePlayer.h
View File

@@ -31,7 +31,7 @@ struct TracePlayer: public sc_module
{
public:
tlm_utils::simple_initiator_socket<TracePlayer, BUSWIDTH, tlm::tlm_base_protocol_types> iSocket;
TracePlayer(sc_module_name name, string pathToTrace, unsigned int burstLength,
TracePlayer(sc_module_name /*name*/, string pathToTrace, unsigned int burstLength,
simulation::ISimulation* simulationManager) :
payloadEventQueue(this, &TracePlayer::peqCallback), file(pathToTrace), burstlenght(burstLength), numberOfPendingTransactions(
0), transactionsSent(0), transactionsReceived(0), simulationManager(

2
dram/src/simulation/main.cpp
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@@ -39,7 +39,7 @@ int sc_main(int argc, char **argv)
if(argc > 1)
simulationToRun = argv[1];
else
simulationToRun = "sim-batch.xml";
simulationToRun = "tests.xml";
SimulationManager manager(resources);
manager.loadSimulationsFromXML(resources + "/simulations/" + simulationToRun);