Fix configuration tests

This commit is contained in:
2024-01-15 13:05:07 +01:00
parent 454cb00ddb
commit 5391b4351d
7 changed files with 14 additions and 18 deletions

View File

@@ -145,8 +145,6 @@
"DatabaseRecording": true,
"Debug": false,
"EnableWindowing": false,
"ErrorCSVFile": "error.csv",
"ErrorChipSeed": 42,
"PowerAnalysis": false,
"SimulationName": "ddr5",
"SimulationProgressBar": true,
@@ -207,4 +205,4 @@
}
]
}
}
}

View File

@@ -6,8 +6,6 @@
"Debug": false,
"ECCControllerMode": "Disabled",
"EnableWindowing": false,
"ErrorCSVFile": "",
"ErrorChipSeed": 42,
"PowerAnalysis": false,
"SimulationName": "ddr5",
"SimulationProgressBar": true,

View File

@@ -166,7 +166,11 @@ DRAMSys::Config::MemSpec ConfigurationTest::createMemSpec()
{"clkMhz", 1600},
}}};
return {memArchitectureSpec, "JEDEC_2x8x2Gbx4_DDR5-3200A", "DDR5", memTimingSpec, {}};
return {memArchitectureSpec,
"JEDEC_2x8x2Gbx4_DDR5-3200A",
DRAMSys::Config::MemoryType::DDR5,
memTimingSpec,
{}};
}
DRAMSys::Config::TracePlayer ConfigurationTest::createTracePlayer()
@@ -317,8 +321,6 @@ TEST_F(ConfigurationTest, SimConfig)
"DatabaseRecording": true,
"Debug": false,
"EnableWindowing": false,
"ErrorCSVFile": "error.csv",
"ErrorChipSeed": 42,
"PowerAnalysis": false,
"SimulationName": "ddr5",
"SimulationProgressBar": true,