derek/DRAMSys
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

changed build structure

Browse Source
This commit is contained in:
gernhard
2014-03-15 18:31:16 +01:00
parent 8ecd91c040
commit 4dffbf9383
49 changed files with 214 additions and 447 deletions
Download Patch File Download Diff File Expand all files Collapse all files

21
DRAM/testing/CommandGenerator_test.cpp
View File

@@ -1,16 +1,17 @@
#include <gtest/gtest.h>
#include <vector>
#include <tlm.h>
#include "core/scheduling/CommandSequenceGenerator.h"
#include "testUtils.h"
#include <vector>
using namespace controller;
using namespace common;
using namespace std;
constexpr unsigned int numberOfBanks = 8;
constexpr tlm::tlm_command READ = tlm::tlm_command::TLM_READ_COMMAND;
constexpr tlm::tlm_command WRITE = tlm::tlm_command::TLM_WRITE_COMMAND;
constexpr tlm::tlm_command READ = tlm::TLM_READ_COMMAND;
constexpr tlm::tlm_command WRITE = tlm::TLM_WRITE_COMMAND;
TEST(CommandSequenceGenerator, ReadAndWriteWithRowHit)
{
@@ -23,8 +24,8 @@ TEST(CommandSequenceGenerator, ReadAndWriteWithRowHit)
auto hit_write = createDummyPayload(Thread(0), Bank(0), Row(3), Column(1), WRITE);
vector<Command> expected_read ({Command::Read});
vector<Command> expected_write ({Command::Write});
vector<Command> expected_read ({Read});
vector<Command> expected_write ({Write});
EXPECT_EQ(expected_read, generator.generateCommandSequence(hit_read.get()));
EXPECT_EQ(expected_write, generator.generateCommandSequence(hit_write.get()));
@@ -41,8 +42,8 @@ TEST(CommandSequenceGenerator, ReadAndWriteWithRowMiss)
auto miss_write = createDummyPayload(Thread(0), Bank(0), Row(4), Column(1), WRITE);
vector<Command> expected_read ({Command::Precharge, Command::Activate, Command::Read});
vector<Command> expected_write ({Command::Precharge, Command::Activate, Command::Write});
vector<Command> expected_read ({Precharge, Activate, Read});
vector<Command> expected_write ({Precharge, Activate, Write});
EXPECT_EQ(expected_read, generator.generateCommandSequence(miss_read.get()));
EXPECT_EQ(expected_write, generator.generateCommandSequence(miss_write.get()));
@@ -59,8 +60,8 @@ TEST(CommandSequenceGenerator, ReadAndWriteWithBankMiss)
auto miss_write = createDummyPayload(Thread(0), Bank(1), Row(4), Column(1), WRITE);
vector<Command> expected_read ({Command::Activate, Command::Read});
vector<Command> expected_write ({Command::Activate, Command::Write});
vector<Command> expected_read ({Activate, Read});
vector<Command> expected_write ({Activate, Write});
EXPECT_EQ(expected_read, generator.generateCommandSequence(miss_read.get()));
EXPECT_EQ(expected_write, generator.generateCommandSequence(miss_write.get()));