Merge branch 'bug/first_trans_start' into 'develop'
Remove check to issue first transaction at zero time. See merge request ems/astdm/modeling.dram/dram.sys.5!29
This commit is contained in:
@@ -6,7 +6,7 @@ Initiators in the simulator are split up into two disctinct components: **Reques
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**RequestProducers** are simple C++ classes that implement the `RequestProducer` interface. Upon calling the `nextRequest()` method of a producer, a new `Request` is either generated on-the-fly or constructed from a trace file.
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**RequestIssuers** are the SystemC modules that connect with DRAMSys. Issuers have no knowledge of where the requests are coming from. They simply call their `nextRequest()` callback that it has been passed in the constructor to obtain the next request to be sent to DRAMSys. Using this concept, the generation and the issuing of request is completely decoupled to make very flexible initiator designs possible.
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**RequestIssuers** are the SystemC modules that connect to DRAMSys. Issuers have no knowledge of where the requests are coming from. They simply call their `nextRequest()` callback that it has been passed in the constructor to obtain the next request to be sent to DRAMSys. Using this concept, the generation and the issuing of request is completely decoupled to make very flexible initiator designs possible.
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**Initiators** implement the `Initiator` interface, which describes how the initiator is bound to DRAMSys. This abstracts over the actual socket type used by the initiator.
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Complex initiators may implement the interface directly, but for simple cases, there exists the templated `SimpleInitiator<Producer>` class. This specialized initiator consists of only one producer and one issuer that operate together. The `StlPlayer` and `RowHammer` issuers make use of the `SimpleInitiator`.
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@@ -150,6 +150,7 @@ int sc_main(int argc, char **argv)
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return std::make_unique<SimpleInitiator<StlPlayer>>(config.name.c_str(),
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memoryManager,
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config.clkMhz,
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std::nullopt,
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std::nullopt,
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transactionFinished,
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@@ -159,10 +160,11 @@ int sc_main(int argc, char **argv)
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else if constexpr (std::is_same_v<T, DRAMSys::Config::RowHammer>)
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{
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RowHammer hammer(
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config.numRequests, config.clkMhz, config.rowIncrement, defaultDataLength);
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config.numRequests, config.rowIncrement, defaultDataLength);
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return std::make_unique<SimpleInitiator<RowHammer>>(config.name.c_str(),
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memoryManager,
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config.clkMhz,
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1,
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1,
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transactionFinished,
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@@ -44,6 +44,7 @@ class SimpleInitiator : public Initiator
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public:
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SimpleInitiator(sc_core::sc_module_name const &name,
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MemoryManager &memoryManager,
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unsigned int clkMhz,
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std::optional<unsigned int> maxPendingReadRequests,
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std::optional<unsigned int> maxPendingWriteRequests,
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std::function<void()> transactionFinished,
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@@ -53,6 +54,7 @@ public:
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issuer(
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name,
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memoryManager,
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clkMhz,
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maxPendingReadRequests,
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maxPendingWriteRequests,
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[this] { return this->producer.nextRequest(); },
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@@ -39,7 +39,6 @@
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RandomProducer::RandomProducer(uint64_t numRequests,
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std::optional<uint64_t> seed,
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double rwRatio,
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unsigned int clkMhz,
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std::optional<uint64_t> minAddress,
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std::optional<uint64_t> maxAddress,
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uint64_t memorySize,
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@@ -49,7 +48,6 @@ RandomProducer::RandomProducer(uint64_t numRequests,
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seed(seed.value_or(DEFAULT_SEED)),
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rwRatio(rwRatio),
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randomGenerator(this->seed),
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generatorPeriod(sc_core::sc_time(1.0 / static_cast<double>(clkMhz), sc_core::SC_US)),
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dataLength(dataLength),
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dataAlignment(dataAlignment),
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randomAddressDistribution(minAddress.value_or(DEFAULT_MIN_ADDRESS),
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@@ -79,7 +77,7 @@ Request RandomProducer::nextRequest()
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request.command = readWriteDistribution(randomGenerator) < rwRatio ? Request::Command::Read
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: Request::Command::Write;
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request.length = dataLength;
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request.delay = generatorPeriod;
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request.delay = sc_core::SC_ZERO_TIME;
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return request;
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}
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@@ -46,7 +46,6 @@ public:
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RandomProducer(uint64_t numRequests,
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std::optional<uint64_t> seed,
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double rwRatio,
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unsigned int clkMhz,
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std::optional<uint64_t> minAddress,
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std::optional<uint64_t> maxAddress,
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uint64_t memorySize,
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@@ -56,12 +55,10 @@ public:
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Request nextRequest() override;
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uint64_t totalRequests() override { return numberOfRequests; }
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sc_core::sc_time clkPeriod() override { return generatorPeriod; }
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const uint64_t numberOfRequests;
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const uint64_t seed;
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const double rwRatio;
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const sc_core::sc_time generatorPeriod;
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const unsigned int dataLength;
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const unsigned int dataAlignment;
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@@ -39,7 +39,6 @@
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SequentialProducer::SequentialProducer(uint64_t numRequests,
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std::optional<uint64_t> seed,
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double rwRatio,
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unsigned int clkMhz,
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std::optional<uint64_t> addressIncrement,
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std::optional<uint64_t> minAddress,
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std::optional<uint64_t> maxAddress,
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@@ -52,7 +51,6 @@ SequentialProducer::SequentialProducer(uint64_t numRequests,
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seed(seed.value_or(DEFAULT_SEED)),
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rwRatio(rwRatio),
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randomGenerator(this->seed),
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generatorPeriod(sc_core::sc_time(1.0 / static_cast<double>(clkMhz), sc_core::SC_US)),
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dataLength(dataLength)
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{
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if (minAddress > memorySize - 1)
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@@ -75,7 +73,7 @@ Request SequentialProducer::nextRequest()
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request.command = readWriteDistribution(randomGenerator) < rwRatio ? Request::Command::Read
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: Request::Command::Write;
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request.length = dataLength;
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request.delay = generatorPeriod;
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request.delay = sc_core::SC_ZERO_TIME;
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generatedRequests++;
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return request;
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@@ -46,7 +46,6 @@ public:
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SequentialProducer(uint64_t numRequests,
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std::optional<uint64_t> seed,
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double rwRatio,
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unsigned int clkMhz,
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std::optional<uint64_t> addressIncrement,
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std::optional<uint64_t> minAddress,
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std::optional<uint64_t> maxAddress,
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@@ -56,7 +55,6 @@ public:
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Request nextRequest() override;
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uint64_t totalRequests() override { return numberOfRequests; }
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sc_core::sc_time clkPeriod() override { return generatorPeriod; }
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void reset() override { generatedRequests = 0; }
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const uint64_t numberOfRequests;
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@@ -65,7 +63,6 @@ public:
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const uint64_t maxAddress;
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const uint64_t seed;
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const double rwRatio;
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const sc_core::sc_time generatorPeriod;
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const unsigned int dataLength;
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std::default_random_engine randomGenerator;
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@@ -35,43 +35,44 @@
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#include "TrafficGenerator.h"
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TrafficGenerator::TrafficGenerator(DRAMSys::Config::TrafficGeneratorStateMachine const &config,
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MemoryManager &memoryManager,
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TrafficGenerator::TrafficGenerator(DRAMSys::Config::TrafficGeneratorStateMachine const& config,
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MemoryManager& memoryManager,
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uint64_t memorySize,
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unsigned int defaultDataLength,
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std::function<void()> transactionFinished,
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std::function<void()> terminateInitiator)
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: consumer(
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config.name.c_str(),
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memoryManager,
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config.maxPendingReadRequests,
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config.maxPendingWriteRequests,
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[this] { return nextRequest(); },
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std::move(transactionFinished),
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std::move(terminateInitiator)),
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stateTransistions(config.transitions)
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std::function<void()> terminateInitiator) :
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issuer(
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config.name.c_str(),
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memoryManager,
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config.clkMhz,
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config.maxPendingReadRequests,
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config.maxPendingWriteRequests,
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[this] { return nextRequest(); },
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std::move(transactionFinished),
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std::move(terminateInitiator)),
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stateTransistions(config.transitions),
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generatorPeriod(sc_core::sc_time(1.0 / static_cast<double>(config.clkMhz), sc_core::SC_US))
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{
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unsigned int dataLength = config.dataLength.value_or(defaultDataLength);
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unsigned int dataAlignment = config.dataAlignment.value_or(dataLength);
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for (auto const &state : config.states)
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for (auto const& state : config.states)
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{
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std::visit(
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[=, &config](auto &&arg)
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[=, &config](auto&& arg)
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{
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using DRAMSys::Config::TrafficGeneratorActiveState;
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using DRAMSys::Config::TrafficGeneratorIdleState;
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using T = std::decay_t<decltype(arg)>;
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if constexpr (std::is_same_v<T, TrafficGeneratorActiveState>)
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{
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auto const &activeState = arg;
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auto const& activeState = arg;
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if (activeState.addressDistribution ==
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DRAMSys::Config::AddressDistribution::Random)
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{
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auto producer = std::make_unique<RandomProducer>(activeState.numRequests,
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config.seed,
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activeState.rwRatio,
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config.clkMhz,
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activeState.minAddress,
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activeState.maxAddress,
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memorySize,
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@@ -86,7 +87,6 @@ TrafficGenerator::TrafficGenerator(DRAMSys::Config::TrafficGeneratorStateMachine
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std::make_unique<SequentialProducer>(activeState.numRequests,
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config.seed,
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activeState.rwRatio,
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config.clkMhz,
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activeState.addressIncrement,
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activeState.minAddress,
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activeState.maxAddress,
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@@ -98,7 +98,7 @@ TrafficGenerator::TrafficGenerator(DRAMSys::Config::TrafficGeneratorStateMachine
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}
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else if constexpr (std::is_same_v<T, TrafficGeneratorIdleState>)
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{
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auto const &idleState = arg;
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auto const& idleState = arg;
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idleStateClks.emplace(idleState.id, idleState.idleClks);
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}
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},
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@@ -106,20 +106,22 @@ TrafficGenerator::TrafficGenerator(DRAMSys::Config::TrafficGeneratorStateMachine
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}
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}
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TrafficGenerator::TrafficGenerator(DRAMSys::Config::TrafficGenerator const &config,
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MemoryManager &memoryManager,
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TrafficGenerator::TrafficGenerator(DRAMSys::Config::TrafficGenerator const& config,
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MemoryManager& memoryManager,
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uint64_t memorySize,
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unsigned int defaultDataLength,
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std::function<void()> transactionFinished,
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std::function<void()> terminateInitiator)
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: consumer(
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config.name.c_str(),
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memoryManager,
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config.maxPendingReadRequests,
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config.maxPendingWriteRequests,
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[this] { return nextRequest(); },
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std::move(transactionFinished),
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std::move(terminateInitiator))
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std::function<void()> terminateInitiator) :
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issuer(
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config.name.c_str(),
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memoryManager,
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config.clkMhz,
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config.maxPendingReadRequests,
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config.maxPendingWriteRequests,
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[this] { return nextRequest(); },
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std::move(transactionFinished),
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std::move(terminateInitiator)),
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generatorPeriod(sc_core::sc_time(1.0 / static_cast<double>(config.clkMhz), sc_core::SC_US))
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{
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unsigned int dataLength = config.dataLength.value_or(defaultDataLength);
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unsigned int dataAlignment = config.dataAlignment.value_or(dataLength);
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@@ -129,7 +131,6 @@ TrafficGenerator::TrafficGenerator(DRAMSys::Config::TrafficGenerator const &conf
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auto producer = std::make_unique<RandomProducer>(config.numRequests,
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config.seed,
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config.rwRatio,
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config.clkMhz,
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config.minAddress,
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config.maxAddress,
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memorySize,
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@@ -142,7 +143,6 @@ TrafficGenerator::TrafficGenerator(DRAMSys::Config::TrafficGenerator const &conf
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auto producer = std::make_unique<SequentialProducer>(config.numRequests,
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config.seed,
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config.rwRatio,
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config.clkMhz,
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config.addressIncrement,
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config.minAddress,
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config.maxAddress,
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@@ -183,9 +183,9 @@ Request TrafficGenerator::nextRequest()
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}
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requestsInState++;
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Request request = producers[currentState]->nextRequest();
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request.delay += producers[currentState]->clkPeriod() * clksToIdle;
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request.delay += generatorPeriod * static_cast<double>(clksToIdle);
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return request;
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}
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@@ -60,7 +60,7 @@ public:
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std::function<void()> transactionFinished,
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std::function<void()> terminateInitiator);
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void bind(tlm_utils::multi_target_base<> &target) override { consumer.iSocket.bind(target); }
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void bind(tlm_utils::multi_target_base<> &target) override { issuer.iSocket.bind(target); }
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uint64_t totalRequests() override;
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Request nextRequest();
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@@ -74,9 +74,10 @@ private:
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using IdleClks = uint64_t;
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std::unordered_map<unsigned int, IdleClks> idleStateClks;
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const sc_core::sc_time generatorPeriod;
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std::default_random_engine randomGenerator;
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std::unordered_map<unsigned int, std::unique_ptr<RequestProducer>> producers;
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RequestIssuer consumer;
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RequestIssuer issuer;
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};
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@@ -36,11 +36,9 @@
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#include "RowHammer.h"
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RowHammer::RowHammer(uint64_t numRequests,
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unsigned int clkMhz,
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uint64_t rowIncrement,
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unsigned int dataLength)
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: numberOfRequests(numRequests),
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generatorPeriod(sc_core::sc_time(1.0 / static_cast<double>(clkMhz), sc_core::SC_US)),
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dataLength(dataLength),
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rowIncrement(rowIncrement)
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{
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@@ -62,6 +60,6 @@ Request RowHammer::nextRequest()
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request.address = currentAddress;
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request.command = Request::Command::Read;
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request.length = dataLength;
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request.delay = generatorPeriod;
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request.delay = sc_core::SC_ZERO_TIME;
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return request;
|
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}
|
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|
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@@ -43,16 +43,13 @@ class RowHammer : public RequestProducer
|
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{
|
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public:
|
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RowHammer(uint64_t numRequests,
|
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unsigned int clkMhz,
|
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uint64_t rowIncrement,
|
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unsigned int dataLength);
|
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|
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Request nextRequest() override;
|
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sc_core::sc_time clkPeriod() override { return generatorPeriod; }
|
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uint64_t totalRequests() override { return numberOfRequests; }
|
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|
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const uint64_t numberOfRequests;
|
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const sc_core::sc_time generatorPeriod;
|
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const unsigned int dataLength;
|
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const uint64_t rowIncrement;
|
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|
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|
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@@ -94,17 +94,15 @@ Request StlPlayer::nextRequest()
|
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}
|
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}
|
||||
|
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sc_core::sc_time delay = readoutIt->delay;
|
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sc_core::sc_time offset = playerPeriod - (sc_core::sc_time_stamp() % playerPeriod);
|
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|
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sc_core::sc_time delay;
|
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if (traceType == TraceType::Absolute)
|
||||
{
|
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delay = std::max(sc_core::sc_time_stamp() + offset, delay);
|
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delay -= sc_core::sc_time_stamp();
|
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bool behindSchedule = sc_core::sc_time_stamp() > readoutIt->delay;
|
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delay = behindSchedule ? sc_core::SC_ZERO_TIME : readoutIt->delay - sc_core::sc_time_stamp();
|
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}
|
||||
else // if (traceType == TraceType::Relative)
|
||||
{
|
||||
delay = offset + delay;
|
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delay = readoutIt->delay;
|
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}
|
||||
|
||||
Request request(*readoutIt);
|
||||
|
||||
@@ -68,7 +68,6 @@ public:
|
||||
|
||||
Request nextRequest() override;
|
||||
|
||||
sc_core::sc_time clkPeriod() override { return playerPeriod; }
|
||||
uint64_t totalRequests() override { return numberOfLines; }
|
||||
|
||||
private:
|
||||
|
||||
@@ -37,6 +37,7 @@
|
||||
|
||||
RequestIssuer::RequestIssuer(sc_core::sc_module_name const &name,
|
||||
MemoryManager &memoryManager,
|
||||
unsigned int clkMhz,
|
||||
std::optional<unsigned int> maxPendingReadRequests,
|
||||
std::optional<unsigned int> maxPendingWriteRequests,
|
||||
std::function<Request()> nextRequest,
|
||||
@@ -44,6 +45,7 @@ RequestIssuer::RequestIssuer(sc_core::sc_module_name const &name,
|
||||
std::function<void()> terminate)
|
||||
: sc_module(name),
|
||||
memoryManager(memoryManager),
|
||||
clkPeriod(sc_core::sc_time(1.0 / static_cast<double>(clkMhz), sc_core::SC_US)),
|
||||
maxPendingReadRequests(maxPendingReadRequests),
|
||||
maxPendingWriteRequests(maxPendingWriteRequests),
|
||||
nextRequest(std::move(nextRequest)),
|
||||
@@ -79,14 +81,14 @@ void RequestIssuer::sendNextRequest()
|
||||
tlm::tlm_phase phase = tlm::BEGIN_REQ;
|
||||
sc_core::sc_time delay = request.delay;
|
||||
|
||||
if (request.address == 0x4000f000)
|
||||
int x = 0;
|
||||
|
||||
if (transactionsSent == 0)
|
||||
delay = sc_core::SC_ZERO_TIME;
|
||||
// Align to next clock
|
||||
if (delay < clkPeriod && transactionsSent != 0)
|
||||
{
|
||||
delay = delay + clkPeriod;
|
||||
delay -= delay % clkPeriod;
|
||||
}
|
||||
|
||||
iSocket->nb_transport_fw(payload, phase, delay);
|
||||
transactionInProgress = true;
|
||||
|
||||
if (request.command == Request::Command::Read)
|
||||
pendingReadRequests++;
|
||||
@@ -121,12 +123,11 @@ void RequestIssuer::peqCallback(tlm::tlm_generic_payload &payload, const tlm::tl
|
||||
}
|
||||
else if (phase == tlm::BEGIN_RESP)
|
||||
{
|
||||
tlm::tlm_phase phase = tlm::END_RESP;
|
||||
tlm::tlm_phase nextPhase = tlm::END_RESP;
|
||||
sc_core::sc_time delay = sc_core::SC_ZERO_TIME;
|
||||
iSocket->nb_transport_fw(payload, phase, delay);
|
||||
iSocket->nb_transport_fw(payload, nextPhase, delay);
|
||||
|
||||
payload.release();
|
||||
transactionInProgress = false;
|
||||
|
||||
transactionFinished();
|
||||
|
||||
|
||||
@@ -52,6 +52,7 @@ public:
|
||||
|
||||
RequestIssuer(sc_core::sc_module_name const &name,
|
||||
MemoryManager &memoryManager,
|
||||
unsigned int clkMhz,
|
||||
std::optional<unsigned int> maxPendingReadRequests,
|
||||
std::optional<unsigned int> maxPendingWriteRequests,
|
||||
std::function<Request()> nextRequest,
|
||||
@@ -63,7 +64,8 @@ private:
|
||||
tlm_utils::peq_with_cb_and_phase<RequestIssuer> payloadEventQueue;
|
||||
MemoryManager &memoryManager;
|
||||
|
||||
bool transactionInProgress = false;
|
||||
const sc_core::sc_time clkPeriod;
|
||||
|
||||
bool transactionPostponed = false;
|
||||
bool finished = false;
|
||||
|
||||
@@ -75,8 +77,6 @@ private:
|
||||
const std::optional<unsigned int> maxPendingReadRequests;
|
||||
const std::optional<unsigned int> maxPendingWriteRequests;
|
||||
|
||||
unsigned int activeProducers = 0;
|
||||
|
||||
std::function<void()> transactionFinished;
|
||||
std::function<void()> terminate;
|
||||
std::function<Request()> nextRequest;
|
||||
|
||||
@@ -44,6 +44,5 @@ public:
|
||||
|
||||
virtual Request nextRequest() = 0;
|
||||
virtual uint64_t totalRequests() = 0;
|
||||
virtual sc_core::sc_time clkPeriod() = 0;
|
||||
virtual void reset(){};
|
||||
};
|
||||
|
||||
Reference in New Issue
Block a user