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Update readme, change examples to FR-FCFS scheduler.

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This commit is contained in:
Lukas Steiner
2020-07-22 09:54:06 +02:00
parent de47f25f4f
commit 4379390473
8 changed files with 39 additions and 24 deletions
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2
DRAMSys/library/resources/simulations/ddr3-example.json
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@@ -1,7 +1,7 @@
{
"simulation": {
"addressmapping": "am_ddr3_8x1Gbx8_dimm_p1KB_rbc.json",
"mcconfig": "fifoStrict.json",
"mcconfig": "fr_fcfs.json",
"memspec": "MICRON_1Gb_DDR3-1600_8bit_G.json",
"simconfig": "ddr3.json",
"simulationid": "ddr3-example",

2
DRAMSys/library/resources/simulations/ddr3-example2.json
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@@ -1,7 +1,7 @@
{
"simulation": {
"addressmapping": "am_ddr3_8x1Gbx8_dimm_p1KB_brc.json",
"mcconfig": "fifoStrict.json",
"mcconfig": "fr_fcfs.json",
"memspec": "MICRON_1Gb_DDR3-1600_8bit_G.json",
"simconfig": "ddr3.json",
"simulationid": "ddr3-example2",

2
DRAMSys/library/resources/simulations/ddr4-example.json
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@@ -1,7 +1,7 @@
{
"simulation": {
"addressmapping": "am_ddr4_8x4Gbx8_dimm_p1KB_brc.json",
"mcconfig": "fifoStrict.json",
"mcconfig": "fr_fcfs.json",
"memspec": "JEDEC_4Gb_DDR4-1866_8bit_A.json",
"simconfig": "ddr4.json",
"simulationid": "ddr4-example",

2
DRAMSys/library/resources/simulations/hbm2-example.json
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@@ -1,7 +1,7 @@
{
"simulation": {
"addressmapping": "am_hbm2_8Gb_pc_brc.json",
"mcconfig": "fifoStrict.json",
"mcconfig": "fr_fcfs.json",
"memspec": "HBM2.json",
"simconfig": "hbm2.json",
"simulationid": "hbm2-example",

2
DRAMSys/library/resources/simulations/lpddr4-example.json
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@@ -1,7 +1,7 @@
{
"simulation": {
"addressmapping": "am_lpddr4_8Gbx16_brc.json",
"mcconfig": "fifoStrict.json",
"mcconfig": "fr_fcfs.json",
"memspec": "JEDEC_8Gb_LPDDR4-3200_16bit.json",
"simconfig": "lpddr4.json",
"simulationid": "lpddr4-example",

2
DRAMSys/library/resources/simulations/ranktest.json
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@@ -1,7 +1,7 @@
{
"simulation": {
"addressmapping": "am_ranktest.json",
"mcconfig": "fifoStrict.json",
"mcconfig": "fr_fcfs.json",
"memspec": "memspec_ranktest.json",
"simconfig": "ddr3.json",
"simulationid": "ranktest",

2
DRAMSys/library/resources/simulations/wideio-example.json
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@@ -1,7 +1,7 @@
{
"simulation": {
"addressmapping": "am_wideio_4x256Mb_rbc.json",
"mcconfig": "fifoStrict.json",
"mcconfig": "fr_fcfs.json",
"memspec": "JEDEC_256Mb_WIDEIO-200_128bit.json",
"simconfig": "wideio.json",
"simulationid": "wideio-example",

27
README.md
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@@ -1,13 +1,13 @@
<img src="DRAMSys/docs/images/dramsys4_0.png" width="350" style="float: left;"/>
**DRAMSys4.0** is a flexible DRAM subsystem design space exploration framework based on SystemC TLM-2.0.
**DRAMSys4.0** is a flexible DRAM subsystem design space exploration framework based on SystemC TLM-2.0. It was developed at the [Microelectronic Systems Design Research Group](https://ems.eit.uni-kl.de/en/start/) and [Fraunhofer IESE](https://www.iese.fraunhofer.de/en.html).
Pipeline Status: [![pipeline status](https://git.eit.uni-kl.de/ems/astdm/dram.sys/badges/master/pipeline.svg)](https://git.eit.uni-kl.de/ems/astdm/dram.sys/commits/master)
[![Coverage report](https://git.eit.uni-kl.de/ems/astdm/dram.sys/badges/master/coverage.svg?job=coverage)](https://git.eit.uni-kl.de/ems/astdm/dram.sys/commits/master)
## Disclaimer
This is the public read-only mirror of an internal DRAMSys repository. Pull requests will not be merged but the changes might be added internally and published with a future commit. The repositories are synchronized from time to time.
This is the public read-only mirror of an internal DRAMSys repository. Pull requests will not be merged but the changes might be added internally and published with a future commit. Both repositories are synchronized from time to time.
The user DOES NOT get ANY WARRANTIES when using this tool. This software is released under the BSD 3-Clause License. By using this software, the user implicitly agrees to the licensing terms.
@@ -393,13 +393,24 @@ $ unzip 3d-ice-latest.zip
$ cd 3d-ice-latest/3d-ice-2.2.6
```
Open the file makefile.def and set some variables.
Open the makefile.def and set the following variables properly, e.g.:
```bash
SLU_MAIN = $(HOME)/SuperLU_$(SLU_VERSION)
YACC = bison-2.4.1
SYSTEMC_VERSION = 2.3.4
SYSTEMC_ARCH = linux64
SYSTEMC_MAIN = $(HOME)/systemc-2.3.x
SYSTEMC_MAIN = $(HOME)/systemc-$(SYSTEMC_VERSION)
SYSTEMC_INCLUDE = $(SYSTEMC_MAIN)/include
SYSTEMC_LIB = $(SYSTEMC_MAIN)/lib-$(SYSTEMC_ARCH)
```
In case you are using the SystemC submodule and DRAMSys is located in your home directory the variables should be set as follows:
```bash
SYSTEMC_INCLUDE = $(HOME)/DRAMSys/DRAMSys/library/src/common/third_party/systemc/src
SYSTEMC_LIB = $(HOME)/DRAMSys/build/library/src/common/third_party/systemc/src
```
Compile 3D-ICE with SystemC TLM-2.0 support:
@@ -507,7 +518,9 @@ If you are interested in the database recording feature and the Trace Analyzer,
![Trace Analyzer Main Window](DRAMSys/docs/images/traceanalyzer.png)
## List of Contributors
## Acknowledgements
The development of DRAMSys was supported by the German Research Foundation (DFG) as part of the priority program [Dependable Embedded Systems SPP1500](http://spp1500.itec.kit.edu) and the DFG grant no. [WE2442/10-1](https://www.uni-kl.de/en/3d-dram/). Furthermore, it was supported within the Fraunhofer and DFG cooperation program (grant no. [WE2442/14-1](https://www.iese.fraunhofer.de/en/innovation_trends/autonomous-systems/memtonomy.html)) and by the [Fraunhofer High Performance Center for Simulation- and Software-Based Innovation](https://www.leistungszentrum-simulation-software.de/en.html). Special thanks go to all listed contributors for their work and commitment during seven years of development.
Shama Bhosale
Luiza Correa
@@ -519,10 +532,12 @@ Matthias Jung
Frederik Lauer
Ana Mativi
Felipe S. Prado
Tran Anh Quoc
Janik Schlemminger
Lukas Steiner
Thanh C. Tran
Tran Anh Quoc
Norbert Wehn
Christian Weis
Éder F. Zulian
## References