From 4379390473bb42621b256c42b6feff7e7b83716b Mon Sep 17 00:00:00 2001 From: Lukas Steiner Date: Wed, 22 Jul 2020 09:54:06 +0200 Subject: [PATCH] Update readme, change examples to FR-FCFS scheduler. --- .../resources/simulations/ddr3-example.json | 2 +- .../resources/simulations/ddr3-example2.json | 2 +- .../resources/simulations/ddr4-example.json | 2 +- .../resources/simulations/hbm2-example.json | 2 +- .../resources/simulations/lpddr4-example.json | 2 +- .../resources/simulations/ranktest.json | 2 +- .../resources/simulations/wideio-example.json | 2 +- README.md | 49 ++++++++++++------- 8 files changed, 39 insertions(+), 24 deletions(-) diff --git a/DRAMSys/library/resources/simulations/ddr3-example.json b/DRAMSys/library/resources/simulations/ddr3-example.json index 7a5d7c16..6b820354 100644 --- a/DRAMSys/library/resources/simulations/ddr3-example.json +++ b/DRAMSys/library/resources/simulations/ddr3-example.json @@ -1,7 +1,7 @@ { "simulation": { "addressmapping": "am_ddr3_8x1Gbx8_dimm_p1KB_rbc.json", - "mcconfig": "fifoStrict.json", + "mcconfig": "fr_fcfs.json", "memspec": "MICRON_1Gb_DDR3-1600_8bit_G.json", "simconfig": "ddr3.json", "simulationid": "ddr3-example", diff --git a/DRAMSys/library/resources/simulations/ddr3-example2.json b/DRAMSys/library/resources/simulations/ddr3-example2.json index a3886b55..99e1821a 100644 --- a/DRAMSys/library/resources/simulations/ddr3-example2.json +++ b/DRAMSys/library/resources/simulations/ddr3-example2.json @@ -1,7 +1,7 @@ { "simulation": { "addressmapping": "am_ddr3_8x1Gbx8_dimm_p1KB_brc.json", - "mcconfig": "fifoStrict.json", + "mcconfig": "fr_fcfs.json", "memspec": "MICRON_1Gb_DDR3-1600_8bit_G.json", "simconfig": "ddr3.json", "simulationid": "ddr3-example2", diff --git a/DRAMSys/library/resources/simulations/ddr4-example.json b/DRAMSys/library/resources/simulations/ddr4-example.json index 6b55b665..09fdac1b 100644 --- a/DRAMSys/library/resources/simulations/ddr4-example.json +++ b/DRAMSys/library/resources/simulations/ddr4-example.json @@ -1,7 +1,7 @@ { "simulation": { "addressmapping": "am_ddr4_8x4Gbx8_dimm_p1KB_brc.json", - "mcconfig": "fifoStrict.json", + "mcconfig": "fr_fcfs.json", "memspec": "JEDEC_4Gb_DDR4-1866_8bit_A.json", "simconfig": "ddr4.json", "simulationid": "ddr4-example", diff --git a/DRAMSys/library/resources/simulations/hbm2-example.json b/DRAMSys/library/resources/simulations/hbm2-example.json index f81e2f13..22eed0df 100644 --- a/DRAMSys/library/resources/simulations/hbm2-example.json +++ b/DRAMSys/library/resources/simulations/hbm2-example.json @@ -1,7 +1,7 @@ { "simulation": { "addressmapping": "am_hbm2_8Gb_pc_brc.json", - "mcconfig": "fifoStrict.json", + "mcconfig": "fr_fcfs.json", "memspec": "HBM2.json", "simconfig": "hbm2.json", "simulationid": "hbm2-example", diff --git a/DRAMSys/library/resources/simulations/lpddr4-example.json b/DRAMSys/library/resources/simulations/lpddr4-example.json index d9a6726b..0054b777 100644 --- a/DRAMSys/library/resources/simulations/lpddr4-example.json +++ b/DRAMSys/library/resources/simulations/lpddr4-example.json @@ -1,7 +1,7 @@ { "simulation": { "addressmapping": "am_lpddr4_8Gbx16_brc.json", - "mcconfig": "fifoStrict.json", + "mcconfig": "fr_fcfs.json", "memspec": "JEDEC_8Gb_LPDDR4-3200_16bit.json", "simconfig": "lpddr4.json", "simulationid": "lpddr4-example", diff --git a/DRAMSys/library/resources/simulations/ranktest.json b/DRAMSys/library/resources/simulations/ranktest.json index 2c115a4b..47f6b1c4 100644 --- a/DRAMSys/library/resources/simulations/ranktest.json +++ b/DRAMSys/library/resources/simulations/ranktest.json @@ -1,7 +1,7 @@ { "simulation": { "addressmapping": "am_ranktest.json", - "mcconfig": "fifoStrict.json", + "mcconfig": "fr_fcfs.json", "memspec": "memspec_ranktest.json", "simconfig": "ddr3.json", "simulationid": "ranktest", diff --git a/DRAMSys/library/resources/simulations/wideio-example.json b/DRAMSys/library/resources/simulations/wideio-example.json index 464a2591..4bfd6979 100644 --- a/DRAMSys/library/resources/simulations/wideio-example.json +++ b/DRAMSys/library/resources/simulations/wideio-example.json @@ -1,7 +1,7 @@ { "simulation": { "addressmapping": "am_wideio_4x256Mb_rbc.json", - "mcconfig": "fifoStrict.json", + "mcconfig": "fr_fcfs.json", "memspec": "JEDEC_256Mb_WIDEIO-200_128bit.json", "simconfig": "wideio.json", "simulationid": "wideio-example", diff --git a/README.md b/README.md index ca7dca1c..b6351eb5 100644 --- a/README.md +++ b/README.md @@ -1,13 +1,13 @@ -**DRAMSys4.0** is a flexible DRAM subsystem design space exploration framework based on SystemC TLM-2.0. +**DRAMSys4.0** is a flexible DRAM subsystem design space exploration framework based on SystemC TLM-2.0. It was developed at the [Microelectronic Systems Design Research Group](https://ems.eit.uni-kl.de/en/start/) and [Fraunhofer IESE](https://www.iese.fraunhofer.de/en.html). Pipeline Status: [![pipeline status](https://git.eit.uni-kl.de/ems/astdm/dram.sys/badges/master/pipeline.svg)](https://git.eit.uni-kl.de/ems/astdm/dram.sys/commits/master) [![Coverage report](https://git.eit.uni-kl.de/ems/astdm/dram.sys/badges/master/coverage.svg?job=coverage)](https://git.eit.uni-kl.de/ems/astdm/dram.sys/commits/master) ## Disclaimer -This is the public read-only mirror of an internal DRAMSys repository. Pull requests will not be merged but the changes might be added internally and published with a future commit. The repositories are synchronized from time to time. +This is the public read-only mirror of an internal DRAMSys repository. Pull requests will not be merged but the changes might be added internally and published with a future commit. Both repositories are synchronized from time to time. The user DOES NOT get ANY WARRANTIES when using this tool. This software is released under the BSD 3-Clause License. By using this software, the user implicitly agrees to the licensing terms. @@ -235,16 +235,16 @@ The content of [ddr3.json](DRAMSys/library/resources/configs/simulator/ddr3.json - *UseMalloc* (boolean) - false: model storage using mmap() (DEFAULT) - true: allocate memory for modeling storage using malloc() -- *AddressOffset* (unsigned int) - - Address offset of the DRAM subsystem (required for the gem5 coupling). -- *ErrorChipSeed* (unsigned int) - - Seed to initialize the random error generator. -- *ErrorCSVFile* (string) - - CSV file with error injection information. -- *StoreMode* (string) - - "NoStorage": no storage - - "Store": store data without error model - - "ErrorModel": store data with error model [6] + - *AddressOffset* (unsigned int) + - Address offset of the DRAM subsystem (required for the gem5 coupling). + - *ErrorChipSeed* (unsigned int) + - Seed to initialize the random error generator. + - *ErrorCSVFile* (string) + - CSV file with error injection information. + - *StoreMode* (string) + - "NoStorage": no storage + - "Store": store data without error model + - "ErrorModel": store data with error model [6] ##### Thermal Simulation @@ -393,13 +393,24 @@ $ unzip 3d-ice-latest.zip $ cd 3d-ice-latest/3d-ice-2.2.6 ``` -Open the file makefile.def and set some variables. +Open the makefile.def and set the following variables properly, e.g.: ```bash SLU_MAIN = $(HOME)/SuperLU_$(SLU_VERSION) YACC = bison-2.4.1 -SYSTEMC_ARCH = linux64 -SYSTEMC_MAIN = $(HOME)/systemc-2.3.x + +SYSTEMC_VERSION = 2.3.4 +SYSTEMC_ARCH = linux64 +SYSTEMC_MAIN = $(HOME)/systemc-$(SYSTEMC_VERSION) +SYSTEMC_INCLUDE = $(SYSTEMC_MAIN)/include +SYSTEMC_LIB = $(SYSTEMC_MAIN)/lib-$(SYSTEMC_ARCH) +``` + +In case you are using the SystemC submodule and DRAMSys is located in your home directory the variables should be set as follows: + +```bash +SYSTEMC_INCLUDE = $(HOME)/DRAMSys/DRAMSys/library/src/common/third_party/systemc/src +SYSTEMC_LIB = $(HOME)/DRAMSys/build/library/src/common/third_party/systemc/src ``` Compile 3D-ICE with SystemC TLM-2.0 support: @@ -507,7 +518,9 @@ If you are interested in the database recording feature and the Trace Analyzer, ![Trace Analyzer Main Window](DRAMSys/docs/images/traceanalyzer.png) -## List of Contributors +## Acknowledgements + +The development of DRAMSys was supported by the German Research Foundation (DFG) as part of the priority program [Dependable Embedded Systems SPP1500](http://spp1500.itec.kit.edu) and the DFG grant no. [WE2442/10-1](https://www.uni-kl.de/en/3d-dram/). Furthermore, it was supported within the Fraunhofer and DFG cooperation program (grant no. [WE2442/14-1](https://www.iese.fraunhofer.de/en/innovation_trends/autonomous-systems/memtonomy.html)) and by the [Fraunhofer High Performance Center for Simulation- and Software-Based Innovation](https://www.leistungszentrum-simulation-software.de/en.html). Special thanks go to all listed contributors for their work and commitment during seven years of development. Shama Bhosale Luiza Correa @@ -519,10 +532,12 @@ Matthias Jung Frederik Lauer Ana Mativi Felipe S. Prado +Tran Anh Quoc Janik Schlemminger Lukas Steiner Thanh C. Tran -Tran Anh Quoc +Norbert Wehn +Christian Weis Éder F. Zulian ## References