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Integrate DRAMUtils and new DRAMPower

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This commit is contained in:
marcomoerz
2024-07-04 10:54:04 +02:00
committed by Derek Christ
parent 0bd943e588
commit 4120e9c35b
240 changed files with 10895 additions and 3138 deletions
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77
tests/tests_regression/LPDDR4/lpddr4-example.json
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@@ -54,6 +54,7 @@
},
"memspec": {
"memarchitecturespec": {
"nbrOfBankGroups": 1,
"burstLength": 16,
"dataRate": 2,
"nbrOfBanks": 8,
@@ -62,7 +63,8 @@
"nbrOfChannels": 1,
"nbrOfDevices": 1,
"nbrOfRows": 65536,
"width": 16
"width": 16,
"maxBurstLength": 16
},
"memoryId": "JEDEC_8Gb_LPDDR4-3200_16bit",
"memoryType": "LPDDR4",
@@ -80,14 +82,14 @@
"RAS": 68,
"RCD": 29,
"REFI": 6246,
"REFIPB": 780,
"RFCAB": 448,
"RFCPB": 224,
"REFIpb": 780,
"RFCab": 448,
"RFCpb": 224,
"RL": 28,
"RPAB": 34,
"RPPB": 29,
"RCAB": 102,
"RCPB": 97,
"RPab": 34,
"RPpb": 29,
"RCab": 102,
"RCpb": 97,
"RPST": 0,
"RRD": 16,
"RTP": 12,
@@ -99,7 +101,64 @@
"XP": 12,
"XSR": 460,
"RTRS": 1,
"tCK": 625
"REFM": 0,
"tCK": 625e-12
},
"mempowerspec": {
"vdd1": 0.0,
"idd01": 0.0,
"idd2n1": 0.0,
"idd3n1": 0.0,
"idd4r1": 0.0,
"idd4w1": 0.0,
"idd51": 0.0,
"idd5pb1": 0.0,
"idd61": 0.0,
"idd2p1": 0.0,
"idd3p1": 0.0,
"vdd2": 0.0,
"idd02": 0.0,
"idd2n2": 0.0,
"idd3n2": 0.0,
"idd4r2": 0.0,
"idd4w2": 0.0,
"idd52": 0.0,
"idd5pb2": 0.0,
"idd62": 0.0,
"idd2p2": 0.0,
"idd3p2": 0.0,
"vddq": 0.0,
"iBeta_vdd1": 0.0,
"iBeta_vdd2": 0.0
},
"memimpedancespec": {
"ck_termination": true,
"ck_R_eq": 1e6,
"ck_dyn_E": 1e-12,
"ca_termination": true,
"ca_R_eq": 1e6,
"ca_dyn_E": 1e-12,
"rdq_termination": true,
"rdq_R_eq": 1e6,
"rdq_dyn_E": 1e-12,
"wdq_termination": true,
"wdq_R_eq": 1e6,
"wdq_dyn_E": 1e-12,
"wdqs_termination": true,
"wdqs_R_eq": 1e6,
"wdqs_dyn_E": 1e-12,
"rdqs_termination": true,
"rdqs_R_eq": 1e6,
"rdqs_dyn_E": 1e-12
},
"bankwisespec": {
"factRho": 1.0,
"factSigma": 1.0,
"pasrMode": 0,
"hasPASR": false
}
},
"simconfig": {