From 4120e9c35b0690d33aa04c79af98cfbc9111fdd7 Mon Sep 17 00:00:00 2001 From: marcomoerz Date: Thu, 4 Jul 2024 10:54:04 +0200 Subject: [PATCH] Integrate DRAMUtils and new DRAMPower --- CMakeLists.txt | 12 +- configs/ddr4-full-example.json | 122 ++++-- configs/memspec/HBM2.json | 5 +- configs/memspec/HBM3.json | 5 +- .../memspec/JEDEC_1Gbx16_16B_LPDDR5-0533.json | 74 +++- .../memspec/JEDEC_1Gbx16_16B_LPDDR5-1067.json | 74 +++- .../memspec/JEDEC_1Gbx16_16B_LPDDR5-1600.json | 74 +++- .../memspec/JEDEC_1Gbx16_16B_LPDDR5-2133.json | 74 +++- .../memspec/JEDEC_1Gbx16_16B_LPDDR5-2750.json | 74 +++- .../memspec/JEDEC_1Gbx16_16B_LPDDR5-3200.json | 74 +++- .../JEDEC_1Gbx16_16B_LPDDR5X-0533.json | 74 +++- .../JEDEC_1Gbx16_16B_LPDDR5X-1067.json | 74 +++- .../JEDEC_1Gbx16_16B_LPDDR5X-1600.json | 74 +++- .../JEDEC_1Gbx16_16B_LPDDR5X-2133.json | 74 +++- .../JEDEC_1Gbx16_16B_LPDDR5X-2750.json | 74 +++- .../JEDEC_1Gbx16_16B_LPDDR5X-3200.json | 74 +++- .../memspec/JEDEC_1Gbx16_8B_LPDDR5-0533.json | 74 +++- .../memspec/JEDEC_1Gbx16_8B_LPDDR5-1067.json | 74 +++- .../memspec/JEDEC_1Gbx16_8B_LPDDR5-1600.json | 74 +++- .../memspec/JEDEC_1Gbx16_8B_LPDDR5-2133.json | 74 +++- .../memspec/JEDEC_1Gbx16_8B_LPDDR5-2750.json | 74 +++- .../memspec/JEDEC_1Gbx16_8B_LPDDR5-3200.json | 74 +++- .../memspec/JEDEC_1Gbx16_8B_LPDDR5-3733.json | 74 +++- .../memspec/JEDEC_1Gbx16_8B_LPDDR5-4267.json | 74 +++- .../memspec/JEDEC_1Gbx16_8B_LPDDR5-4800.json | 74 +++- .../memspec/JEDEC_1Gbx16_8B_LPDDR5-5500.json | 74 +++- .../memspec/JEDEC_1Gbx16_8B_LPDDR5-6000.json | 74 +++- .../memspec/JEDEC_1Gbx16_8B_LPDDR5-6400.json | 74 +++- .../memspec/JEDEC_1Gbx16_BG_LPDDR5-3733.json | 74 +++- .../memspec/JEDEC_1Gbx16_BG_LPDDR5-4267.json | 74 +++- .../memspec/JEDEC_1Gbx16_BG_LPDDR5-4800.json | 74 +++- .../memspec/JEDEC_1Gbx16_BG_LPDDR5-5500.json | 74 +++- .../memspec/JEDEC_1Gbx16_BG_LPDDR5-6000.json | 74 +++- .../memspec/JEDEC_1Gbx16_BG_LPDDR5-6400.json | 76 +++- .../memspec/JEDEC_1Gbx16_BG_LPDDR5X-3733.json | 74 +++- .../memspec/JEDEC_1Gbx16_BG_LPDDR5X-4267.json | 74 +++- .../memspec/JEDEC_1Gbx16_BG_LPDDR5X-4800.json | 74 +++- .../memspec/JEDEC_1Gbx16_BG_LPDDR5X-5500.json | 74 +++- .../memspec/JEDEC_1Gbx16_BG_LPDDR5X-6000.json | 74 +++- .../memspec/JEDEC_1Gbx16_BG_LPDDR5X-6400.json | 74 +++- .../memspec/JEDEC_1Gbx16_BG_LPDDR5X-7500.json | 74 +++- .../memspec/JEDEC_1Gbx16_BG_LPDDR5X-8533.json | 74 +++- configs/memspec/JEDEC_1Gbx16_LPDDR4-0533.json | 76 +++- configs/memspec/JEDEC_1Gbx16_LPDDR4-1066.json | 76 +++- configs/memspec/JEDEC_1Gbx16_LPDDR4-1600.json | 76 +++- configs/memspec/JEDEC_1Gbx16_LPDDR4-2133.json | 76 +++- configs/memspec/JEDEC_1Gbx16_LPDDR4-2666.json | 76 +++- configs/memspec/JEDEC_1Gbx16_LPDDR4-3200.json | 76 +++- configs/memspec/JEDEC_1Gbx16_LPDDR4-3733.json | 76 +++- configs/memspec/JEDEC_1Gbx16_LPDDR4-4266.json | 76 +++- .../JEDEC_256Mb_WIDEIO-200_128bit.json | 49 +-- .../JEDEC_256Mb_WIDEIO-266_128bit.json | 49 +-- .../memspec/JEDEC_2x2x8x4Gbx4_DDR5-3200A.json | 67 +++- .../memspec/JEDEC_2x4x1Gbx8_DDR5-3200A.json | 67 +++- .../memspec/JEDEC_2x4x1Gbx8_DDR5-3600A.json | 67 +++- .../memspec/JEDEC_2x4x1Gbx8_DDR5-4000A.json | 67 +++- .../memspec/JEDEC_2x4x1Gbx8_DDR5-4400A.json | 67 +++- .../memspec/JEDEC_2x4x1Gbx8_DDR5-4800A.json | 67 +++- .../memspec/JEDEC_2x4x1Gbx8_DDR5-5200A.json | 67 +++- .../memspec/JEDEC_2x4x1Gbx8_DDR5-5600A.json | 67 +++- .../memspec/JEDEC_2x4x1Gbx8_DDR5-6000A.json | 67 +++- .../memspec/JEDEC_2x4x1Gbx8_DDR5-6400A.json | 67 +++- .../memspec/JEDEC_2x8x2Gbx4_DDR5-3200A.json | 67 +++- .../memspec/JEDEC_2x8x2Gbx4_DDR5-3600A.json | 67 +++- .../memspec/JEDEC_2x8x2Gbx4_DDR5-4000A.json | 67 +++- .../memspec/JEDEC_2x8x2Gbx4_DDR5-4400A.json | 67 +++- .../memspec/JEDEC_2x8x2Gbx4_DDR5-4800A.json | 67 +++- .../memspec/JEDEC_2x8x2Gbx4_DDR5-5200A.json | 67 +++- .../memspec/JEDEC_2x8x2Gbx4_DDR5-5600A.json | 67 +++- .../memspec/JEDEC_2x8x2Gbx4_DDR5-6000A.json | 67 +++- .../memspec/JEDEC_2x8x2Gbx4_DDR5-6400A.json | 67 +++- .../memspec/JEDEC_2x8x8x2Gbx4_DDR5-3200A.json | 67 +++- .../memspec/JEDEC_4Gb_DDR4-1866_8bit_A.json | 89 ++++- .../memspec/JEDEC_4Gb_DDR4-2400_8bit_A.json | 89 ++++- .../JEDEC_4x64_2Gb_WIDEIO2-400_64bit.json | 8 +- .../JEDEC_4x64_2Gb_WIDEIO2-533_64bit.json | 8 +- .../JEDEC_512Mbx16_16B_LPDDR5-0533.json | 74 +++- .../JEDEC_512Mbx16_16B_LPDDR5-1067.json | 74 +++- .../JEDEC_512Mbx16_16B_LPDDR5-1600.json | 74 +++- .../JEDEC_512Mbx16_16B_LPDDR5-2133.json | 74 +++- .../JEDEC_512Mbx16_16B_LPDDR5-2750.json | 74 +++- .../JEDEC_512Mbx16_16B_LPDDR5-3200.json | 74 +++- .../JEDEC_512Mbx16_16B_LPDDR5X-0533.json | 74 +++- .../JEDEC_512Mbx16_16B_LPDDR5X-1067.json | 74 +++- .../JEDEC_512Mbx16_16B_LPDDR5X-1600.json | 74 +++- .../JEDEC_512Mbx16_16B_LPDDR5X-2133.json | 74 +++- .../JEDEC_512Mbx16_16B_LPDDR5X-2750.json | 74 +++- .../JEDEC_512Mbx16_16B_LPDDR5X-3200.json | 74 +++- .../JEDEC_512Mbx16_8B_LPDDR5-0533.json | 74 +++- .../JEDEC_512Mbx16_8B_LPDDR5-1067.json | 74 +++- .../JEDEC_512Mbx16_8B_LPDDR5-1600.json | 74 +++- .../JEDEC_512Mbx16_8B_LPDDR5-2133.json | 74 +++- .../JEDEC_512Mbx16_8B_LPDDR5-2750.json | 74 +++- .../JEDEC_512Mbx16_8B_LPDDR5-3200.json | 74 +++- .../JEDEC_512Mbx16_8B_LPDDR5-3733.json | 74 +++- .../JEDEC_512Mbx16_8B_LPDDR5-4267.json | 74 +++- .../JEDEC_512Mbx16_8B_LPDDR5-4800.json | 74 +++- .../JEDEC_512Mbx16_8B_LPDDR5-5500.json | 74 +++- .../JEDEC_512Mbx16_8B_LPDDR5-6000.json | 74 +++- .../JEDEC_512Mbx16_8B_LPDDR5-6400.json | 74 +++- .../JEDEC_512Mbx16_BG_LPDDR5-3733.json | 74 +++- .../JEDEC_512Mbx16_BG_LPDDR5-4267.json | 74 +++- .../JEDEC_512Mbx16_BG_LPDDR5-4800.json | 74 +++- .../JEDEC_512Mbx16_BG_LPDDR5-5500.json | 74 +++- .../JEDEC_512Mbx16_BG_LPDDR5-6000.json | 74 +++- .../JEDEC_512Mbx16_BG_LPDDR5-6400.json | 74 +++- .../JEDEC_512Mbx16_BG_LPDDR5X-3733.json | 74 +++- .../JEDEC_512Mbx16_BG_LPDDR5X-4267.json | 74 +++- .../JEDEC_512Mbx16_BG_LPDDR5X-4800.json | 74 +++- .../JEDEC_512Mbx16_BG_LPDDR5X-5500.json | 74 +++- .../JEDEC_512Mbx16_BG_LPDDR5X-6000.json | 74 +++- .../JEDEC_512Mbx16_BG_LPDDR5X-6400.json | 74 +++- .../JEDEC_512Mbx16_BG_LPDDR5X-7500.json | 74 +++- .../JEDEC_512Mbx16_BG_LPDDR5X-8533.json | 74 +++- .../memspec/JEDEC_512Mbx16_LPDDR4-0533.json | 76 +++- .../memspec/JEDEC_512Mbx16_LPDDR4-1066.json | 76 +++- .../memspec/JEDEC_512Mbx16_LPDDR4-1600.json | 76 +++- .../memspec/JEDEC_512Mbx16_LPDDR4-2133.json | 76 +++- .../memspec/JEDEC_512Mbx16_LPDDR4-2666.json | 76 +++- .../memspec/JEDEC_512Mbx16_LPDDR4-3200.json | 76 +++- .../memspec/JEDEC_512Mbx16_LPDDR4-3733.json | 76 +++- .../memspec/JEDEC_512Mbx16_LPDDR4-4266.json | 76 +++- .../memspec/JEDEC_8Gb_LPDDR4-3200_16bit.json | 145 +++++--- .../memspec/MICRON_1Gb_DDR2-1066_16bit_H.json | 24 +- .../memspec/MICRON_1Gb_DDR2-800_16bit_H.json | 24 +- .../memspec/MICRON_1Gb_DDR3-1066_16bit_G.json | 27 +- .../MICRON_1Gb_DDR3-1066_16bit_G_2s.json | 27 +- .../MICRON_1Gb_DDR3-1066_16bit_G_3s.json | 27 +- .../MICRON_1Gb_DDR3-1066_16bit_G_mu.json | 27 +- .../memspec/MICRON_1Gb_DDR3-1066_8bit_G.json | 27 +- .../MICRON_1Gb_DDR3-1066_8bit_G_2s.json | 27 +- .../MICRON_1Gb_DDR3-1066_8bit_G_3s.json | 27 +- .../MICRON_1Gb_DDR3-1066_8bit_G_mu.json | 27 +- .../memspec/MICRON_1Gb_DDR3-1600_8bit_G.json | 27 +- .../MICRON_1Gb_DDR3-1600_8bit_G_2s.json | 27 +- .../MICRON_1Gb_DDR3-1600_8bit_G_3s.json | 27 +- ...RON_1Gb_DDR3-1600_8bit_G_less_refresh.json | 27 +- .../MICRON_1Gb_DDR3-1600_8bit_G_mu.json | 27 +- .../memspec/MICRON_1Gb_DDR3-800_8bit_G.json | 27 +- .../MICRON_2GB_DDR3-1066_64bit_D_SODIMM.json | 27 +- .../MICRON_2GB_DDR3-1066_64bit_G_UDIMM.json | 27 +- .../MICRON_2GB_DDR3-1333_64bit_D_SODIMM.json | 27 +- .../MICRON_2GB_DDR3-1600_64bit_G_UDIMM.json | 27 +- .../memspec/MICRON_2Gb_DDR3-1066_8bit_D.json | 27 +- .../MICRON_2Gb_DDR3-1066_8bit_D_2s.json | 27 +- .../MICRON_2Gb_DDR3-1066_8bit_D_3s.json | 27 +- .../MICRON_2Gb_DDR3-1066_8bit_D_mu.json | 27 +- .../memspec/MICRON_2Gb_DDR3-1600_16bit_D.json | 27 +- .../MICRON_2Gb_DDR3-1600_16bit_D_2s.json | 27 +- .../MICRON_2Gb_DDR3-1600_16bit_D_3s.json | 27 +- .../MICRON_2Gb_DDR3-1600_16bit_D_mu.json | 27 +- .../memspec/MICRON_2Gb_LPDDR-266_16bit_A.json | 24 +- .../memspec/MICRON_2Gb_LPDDR-333_16bit_A.json | 24 +- .../MICRON_2Gb_LPDDR2-1066-S4_16bit_A.json | 46 +-- .../MICRON_2Gb_LPDDR2-800-S4_16bit_A.json | 46 +-- .../memspec/MICRON_4Gb_DDR4-1866_8bit_A.json | 92 ++++- .../memspec/MICRON_4Gb_DDR4-2400_8bit_A.json | 91 ++++- .../MICRON_4Gb_LPDDR3-1333_32bit_A.json | 46 +-- .../MICRON_4Gb_LPDDR3-1600_32bit_A.json | 46 +-- .../MICRON_6Gb_LPDDR4-3200_32bit_A.json | 155 +++++--- ...AMSUNG_K4B1G1646E_1Gb_DDR3-1600_16bit.json | 3 +- ...AMSUNG_K4B4G1646Q_4Gb_DDR3-1066_16bit.json | 5 +- configs/memspec/STT-MRAM-1.2x.json | 5 +- configs/memspec/STT-MRAM-1.5x.json | 5 +- configs/memspec/STT-MRAM-2.0x.json | 5 +- configs/simconfig/example.json | 12 +- configs/stt-mram-example.json | 1 + .../specialized/TimeDependenciesInfoDDR5.cpp | 4 +- .../specialized/TimeDependenciesInfoDDR5.h | 2 +- .../apps/traceAnalyzer/scripts/tests.py | 8 +- .../configuration/memspec/MemSpecDDR5.cpp | 161 ++++---- .../configuration/memspec/MemSpecDDR5.h | 19 +- .../configuration/memspec/MemSpecHBM3.cpp | 90 ++--- .../configuration/memspec/MemSpecHBM3.h | 6 +- .../configuration/memspec/MemSpecLPDDR5.cpp | 99 ++--- .../configuration/memspec/MemSpecLPDDR5.h | 19 +- src/configuration/CMakeLists.txt | 6 +- .../DRAMSys/config/AddressMapping.h | 2 +- .../DRAMSys/config/DRAMSysConfiguration.cpp | 6 +- .../DRAMSys/config/DRAMSysConfiguration.h | 6 +- src/configuration/DRAMSys/config/McConfig.h | 2 +- .../{memspec/MemPowerSpec.cpp => MemSpec.h} | 27 +- src/configuration/DRAMSys/config/SimConfig.h | 7 +- src/configuration/DRAMSys/config/TraceSetup.h | 2 +- .../config/memspec/MemArchitectureSpec.cpp | 59 --- .../config/memspec/MemArchitectureSpec.h | 56 --- .../DRAMSys/config/memspec/MemPowerSpec.h | 56 --- .../DRAMSys/config/memspec/MemSpec.h | 99 ----- .../DRAMSys/config/memspec/MemTimingSpec.cpp | 59 --- .../DRAMSys/config/memspec/MemTimingSpec.h | 57 --- src/configuration/DRAMSys/util/json.h | 166 --------- src/libdramsys/CMakeLists.txt | 1 + .../DRAMSys/configuration/memspec/MemSpec.cpp | 62 +--- .../DRAMSys/configuration/memspec/MemSpec.h | 121 ++++-- .../configuration/memspec/MemSpecDDR3.cpp | 182 ++------- .../configuration/memspec/MemSpecDDR3.h | 23 +- .../configuration/memspec/MemSpecDDR4.cpp | 225 ++++------- .../configuration/memspec/MemSpecDDR4.h | 30 +- .../configuration/memspec/MemSpecGDDR5.cpp | 93 ++--- .../configuration/memspec/MemSpecGDDR5.h | 5 +- .../configuration/memspec/MemSpecGDDR5X.cpp | 93 ++--- .../configuration/memspec/MemSpecGDDR5X.h | 5 +- .../configuration/memspec/MemSpecGDDR6.cpp | 99 ++--- .../configuration/memspec/MemSpecGDDR6.h | 6 +- .../configuration/memspec/MemSpecHBM2.cpp | 83 +++-- .../configuration/memspec/MemSpecHBM2.h | 5 +- .../configuration/memspec/MemSpecLPDDR4.cpp | 91 +++-- .../configuration/memspec/MemSpecLPDDR4.h | 16 +- .../configuration/memspec/MemSpecSTTMRAM.cpp | 65 ++-- .../configuration/memspec/MemSpecSTTMRAM.h | 4 +- .../configuration/memspec/MemSpecWideIO.cpp | 193 ++-------- .../configuration/memspec/MemSpecWideIO.h | 35 +- .../configuration/memspec/MemSpecWideIO2.cpp | 73 ++-- .../configuration/memspec/MemSpecWideIO2.h | 5 +- src/libdramsys/DRAMSys/controller/Command.cpp | 63 ++-- src/libdramsys/DRAMSys/controller/Command.h | 5 +- .../DRAMSys/controller/Controller.cpp | 28 +- src/libdramsys/DRAMSys/simulation/DRAMSys.cpp | 88 +++-- src/libdramsys/DRAMSys/simulation/DRAMSys.h | 6 +- src/libdramsys/DRAMSys/simulation/Dram.cpp | 86 +++-- src/libdramsys/DRAMSys/simulation/Dram.h | 11 +- .../DRAMSys/simulation/SimConfig.cpp | 4 +- src/libdramsys/DRAMSys/simulation/SimConfig.h | 4 + tests/tests_configuration/CMakeLists.txt | 1 + tests/tests_configuration/reference.json | 132 +++++-- .../memspec/JEDEC_2x8x2Gbx4_DDR5-3200A.json | 88 ++++- .../test_configuration.cpp | 350 +++++++++++++----- tests/tests_configuration/test_json.cpp | 2 +- .../b_transport/configs/no_storage.json | 70 +++- .../b_transport/configs/storage.json | 70 +++- tests/tests_regression/DDR3/ddr3-example.json | 29 +- .../DRAMSys_ddr3-dual-rank_ddr3_ch0.tdb | 2 +- tests/tests_regression/DDR4/ddr4-example.json | 102 ++++- .../DRAMSys_ddr4-bankgrp_ddr4_ch0.tdb | 4 +- tests/tests_regression/DDR5/ddr5-example.json | 67 +++- tests/tests_regression/HBM2/hbm2-example.json | 5 +- tests/tests_regression/HBM3/hbm3-example.json | 5 +- .../LPDDR4/lpddr4-example.json | 77 +++- .../LPDDR5/lpddr5-example.json | 74 +++- tools/CMakeLists.txt | 8 +- 240 files changed, 10895 insertions(+), 3138 deletions(-) rename src/configuration/DRAMSys/config/{memspec/MemPowerSpec.cpp => MemSpec.h} (83%) delete mode 100644 src/configuration/DRAMSys/config/memspec/MemArchitectureSpec.cpp delete mode 100644 src/configuration/DRAMSys/config/memspec/MemArchitectureSpec.h delete mode 100644 src/configuration/DRAMSys/config/memspec/MemPowerSpec.h delete mode 100644 src/configuration/DRAMSys/config/memspec/MemSpec.h delete mode 100644 src/configuration/DRAMSys/config/memspec/MemTimingSpec.cpp delete mode 100644 src/configuration/DRAMSys/config/memspec/MemTimingSpec.h delete mode 100644 src/configuration/DRAMSys/util/json.h diff --git a/CMakeLists.txt b/CMakeLists.txt index af0230e5..a5f0e2dd 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -130,10 +130,16 @@ if (DRAMSYS_USE_FETCH_CONTENT) endif() if (DRAMSYS_USE_FETCH_CONTENT_INTERNAL) + FetchContent_Declare( + DRAMUtils + URL "https://github.com/tukl-msd/DRAMUtils/archive/refs/tags/v1.7.0.tar.gz" + OVERRIDE_FIND_PACKAGE + ) + FetchContent_MakeAvailable(DRAMUtils) + FetchContent_Declare( DRAMPower - GIT_REPOSITORY https://github.com/tukl-msd/DRAMPower - GIT_TAG ebd9ff7 + URL "https://github.com/tukl-msd/DRAMPower/archive/refs/tags/v5.4.1.tar.gz" OVERRIDE_FIND_PACKAGE ) @@ -143,7 +149,7 @@ endif() find_package(SystemCLanguage REQUIRED) find_package(SQLite3 REQUIRED) -find_package(nlohmann_json REQUIRED) +find_package(DRAMUtils REQUIRED) find_package(DRAMPower) diff --git a/configs/ddr4-full-example.json b/configs/ddr4-full-example.json index 8b7bbb46..82ce03f4 100644 --- a/configs/ddr4-full-example.json +++ b/configs/ddr4-full-example.json @@ -65,34 +65,51 @@ "dataRate": 2, "nbrOfBankGroups": 4, "nbrOfBanks": 16, - "nbrOfChannels": 1, "nbrOfColumns": 1024, - "nbrOfDevices": 8, "nbrOfRanks": 1, "nbrOfRows": 32768, - "width": 8 + "width": 8, + "nbrOfDevices": 8, + "nbrOfChannels": 1, + "RefMode": 1, + "maxBurstLength": 8 }, "memoryId": "MICRON_4Gb_DDR4-1866_8bit_A", "memoryType": "DDR4", "mempowerspec": { - "idd0": 56.25, - "idd02": 4.05, - "idd2n": 33.75, - "idd2p0": 17.0, - "idd2p1": 17.0, - "idd3n": 39.5, - "idd3p0": 22.5, - "idd3p1": 22.5, - "idd4r": 157.5, - "idd4w": 135.0, - "idd5": 118.0, - "idd6": 20.25, - "idd62": 2.6, "vdd": 1.2, - "vdd2": 2.5 + "idd0": 56.25e-3, + "idd2n": 33.75e-3, + "idd3n": 39.5e-3, + "idd4r": 157.5e-3, + "idd4w": 135.0e-3, + "idd6n": 20.25e-3, + "idd2p": 17.0e-3, + "idd3p": 22.5e-3, + + "vpp": 2.5, + "ipp0": 4.05e-3, + "ipp2n": 0, + "ipp3n": 0, + "ipp4r": 0, + "ipp4w": 0, + "ipp6n": 2.6e-3, + "ipp2p": 17.0e-3, + "ipp3p": 22.5e-3, + + "idd5B": 118.0e-3, + "ipp5B": 0.0, + "idd5F2": 0.0, + "ipp5F2": 0.0, + "idd5F4": 0.0, + "ipp5F4": 0.0, + "vddq": 0.0, + + "iBeta_vdd": 56.25e-3, + "iBeta_vpp": 4.05e-3 + }, "memtimingspec": { - "ACTPDEN": 1, "AL": 0, "CCD_L": 5, "CCD_S": 4, @@ -101,23 +118,20 @@ "CL": 13, "DQSCK": 2, "FAW": 22, - "PRPDEN": 1, "RAS": 32, "RC": 45, "RCD": 13, - "REFI": 7280, "REFM": 1, - "REFPDEN": 1, - "RFC": 243, - "RFC2": 150, - "RFC4": 103, + "REFI": 3644, + "RFC1": 243, + "RFC2": 0, + "RFC4": 0, "RL": 13, - "RP": 13, "RPRE": 1, + "RP": 13, "RRD_L": 5, "RRD_S": 4, "RTP": 8, - "RTRS": 1, "WL": 12, "WPRE": 1, "WR": 14, @@ -127,7 +141,49 @@ "XPDLL": 255, "XS": 252, "XSDLL": 512, - "tCK": 1072 + "ACTPDEN": 1, + "PRPDEN": 1, + "REFPDEN": 1, + "RTRS": 1, + "tCK": 1072e-12 + }, + "bankwisespec": { + "factRho": 1.0 + }, + "memimpedancespec": { + "ck_termination": true, + "ck_R_eq": 1e6, + "ck_dyn_E": 1e-12, + + "ca_termination": true, + "ca_R_eq": 1e6, + "ca_dyn_E": 1e-12, + + "rdq_termination": true, + "rdq_R_eq": 1e6, + "rdq_dyn_E": 1e-12, + "wdq_termination": true, + "wdq_R_eq": 1e6, + "wdq_dyn_E": 1e-12, + + "wdqs_termination": true, + "wdqs_R_eq": 1e6, + "wdqs_dyn_E": 1e-12, + "rdqs_termination": true, + "rdqs_R_eq": 1e6, + "rdqs_dyn_E": 1e-12 + }, + "prepostamble": { + "read_zeroes": 0.0, + "write_zeroes": 0.0, + "read_ones": 0.0, + "write_ones": 0.0, + "read_zeroes_to_ones": 0, + "write_zeroes_to_ones": 0, + "write_ones_to_zeroes": 0, + "read_ones_to_zeroes": 0, + "readMinTccd": 0, + "writeMinTccd": 0 } }, "simconfig": { @@ -136,12 +192,20 @@ "DatabaseRecording": true, "Debug": false, "EnableWindowing": false, - "PowerAnalysis": false, + "PowerAnalysis": true, "SimulationName": "example", "SimulationProgressBar": true, "StoreMode": "NoStorage", "UseMalloc": false, - "WindowSize": 1000 + "WindowSize": 1000, + "TogglingRate": { + "togglingRateRead": 0.5, + "togglingRateWrite": 0.5, + "dutyCycleRead": 0.5, + "dutyCycleWrite": 0.5, + "idlePatternRead": "L", + "idlePatternWrite": "L" + } }, "simulationid": "ddr4-example", "tracesetup": [ diff --git a/configs/memspec/HBM2.json b/configs/memspec/HBM2.json index b4b696f6..56062eac 100644 --- a/configs/memspec/HBM2.json +++ b/configs/memspec/HBM2.json @@ -11,7 +11,8 @@ "nbrOfRows": 32768, "width": 64, "nbrOfDevices": 1, - "nbrOfChannels": 1 + "nbrOfChannels": 1, + "maxBurstLength": 4 }, "memoryId": "https://www.computerbase.de/2019-05/amd-memory-tweak-vram-oc/#bilder", "memoryType": "HBM2", @@ -44,7 +45,7 @@ "WTRS": 4, "XP": 8, "XS": 216, - "tCK": 1000 + "tCK": 1000e-12 } } } diff --git a/configs/memspec/HBM3.json b/configs/memspec/HBM3.json index 10519dc9..70ff19ec 100644 --- a/configs/memspec/HBM3.json +++ b/configs/memspec/HBM3.json @@ -14,7 +14,8 @@ "nbrOfChannels": 1, "RAAIMT" : 16, "RAAMMT" : 96, - "RAADEC" : 16 + "RAADEC" : 16, + "maxBurstLength": 8 }, "memoryId": "", "memoryType": "HBM3", @@ -48,7 +49,7 @@ "WTRS": 4, "XP": 8, "XS": 260, - "tCK": 625 + "tCK": 625e-12 } } } diff --git a/configs/memspec/JEDEC_1Gbx16_16B_LPDDR5-0533.json b/configs/memspec/JEDEC_1Gbx16_16B_LPDDR5-0533.json index 97d4b2ed..0d17cdf4 100644 --- a/configs/memspec/JEDEC_1Gbx16_16B_LPDDR5-0533.json +++ b/configs/memspec/JEDEC_1Gbx16_16B_LPDDR5-0533.json @@ -11,7 +11,77 @@ "nbrOfDevices": 1, "nbrOfChannels": 1, "width": 16, - "per2BankOffset": 8 + "per2BankOffset": 8, + "WCKalwaysOn": false, + "maxBurstLength": 16 + }, + "mempowerspec": { + "vdd1": 0.0, + "idd01": 0.0, + "idd2n1": 0.0, + "idd3n1": 0.0, + "idd4r1": 0.0, + "idd4w1": 0.0, + "idd51": 0.0, + "idd5pb1": 0.0, + "idd61": 0.0, + "idd6ds1": 0.0, + "idd2p1": 0.0, + "idd3p1": 0.0, + "vdd2h": 0.0, + "idd02h": 0.0, + "idd2n2h": 0.0, + "idd3n2h": 0.0, + "idd4r2h": 0.0, + "idd4w2h": 0.0, + "idd52h": 0.0, + "idd5pb2h": 0.0, + "idd62h": 0.0, + "idd6ds2h": 0.0, + "idd2p2h": 0.0, + "idd3p2h": 0.0, + "vdd2l": 0.0, + "idd02l": 0.0, + "idd2n2l": 0.0, + "idd3n2l": 0.0, + "idd4r2l": 0.0, + "idd4w2l": 0.0, + "idd52l": 0.0, + "idd5pb2l": 0.0, + "idd62l": 0.0, + "idd6ds2l": 0.0, + "idd2p2l": 0.0, + "idd3p2l": 0.0, + "vddq": 0.0, + "iBeta_vdd1": 0.0, + "iBeta_vdd2h": 0.0, + "iBeta_vdd2l": 0.0 + }, + "bankwisespec": { + "factRho": 1 + }, + "memimpedancespec": { + "ck_termination": true, + "ck_R_eq": 1e6, + "ck_dyn_E": 1e-12, + + "ca_termination": true, + "ca_R_eq": 1e6, + "ca_dyn_E": 1e-12, + + "rdq_termination": true, + "rdq_R_eq": 1e6, + "rdq_dyn_E": 1e-12, + "wdq_termination": true, + "wdq_R_eq": 1e6, + "wdq_dyn_E": 1e-12, + + "wck_termination": true, + "wck_R_eq": 1e6, + "wck_dyn_E": 1e-12, + "rdqs_termination": true, + "rdqs_R_eq": 1e6, + "rdqs_dyn_E": 1e-12 }, "memoryId": "JEDEC_1Gbx16_16B_LPDDR5-0533", "memoryType": "LPDDR5", @@ -55,7 +125,7 @@ "BL_n_S_32": 8, "pbR2act": 1, "pbR2pbR": 12, - "tCK": 7519 + "tCK": 7519e-12 } } } diff --git a/configs/memspec/JEDEC_1Gbx16_16B_LPDDR5-1067.json b/configs/memspec/JEDEC_1Gbx16_16B_LPDDR5-1067.json index b2abb7e0..8ac02a09 100644 --- a/configs/memspec/JEDEC_1Gbx16_16B_LPDDR5-1067.json +++ b/configs/memspec/JEDEC_1Gbx16_16B_LPDDR5-1067.json @@ -11,7 +11,77 @@ "nbrOfDevices": 1, "nbrOfChannels": 1, "width": 16, - "per2BankOffset": 8 + "per2BankOffset": 8, + "WCKalwaysOn": false, + "maxBurstLength": 16 + }, + "mempowerspec": { + "vdd1": 0.0, + "idd01": 0.0, + "idd2n1": 0.0, + "idd3n1": 0.0, + "idd4r1": 0.0, + "idd4w1": 0.0, + "idd51": 0.0, + "idd5pb1": 0.0, + "idd61": 0.0, + "idd6ds1": 0.0, + "idd2p1": 0.0, + "idd3p1": 0.0, + "vdd2h": 0.0, + "idd02h": 0.0, + "idd2n2h": 0.0, + "idd3n2h": 0.0, + "idd4r2h": 0.0, + "idd4w2h": 0.0, + "idd52h": 0.0, + "idd5pb2h": 0.0, + "idd62h": 0.0, + "idd6ds2h": 0.0, + "idd2p2h": 0.0, + "idd3p2h": 0.0, + "vdd2l": 0.0, + "idd02l": 0.0, + "idd2n2l": 0.0, + "idd3n2l": 0.0, + "idd4r2l": 0.0, + "idd4w2l": 0.0, + "idd52l": 0.0, + "idd5pb2l": 0.0, + "idd62l": 0.0, + "idd6ds2l": 0.0, + "idd2p2l": 0.0, + "idd3p2l": 0.0, + "vddq": 0.0, + "iBeta_vdd1": 0.0, + "iBeta_vdd2h": 0.0, + "iBeta_vdd2l": 0.0 + }, + "bankwisespec": { + "factRho": 1 + }, + "memimpedancespec": { + "ck_termination": true, + "ck_R_eq": 1e6, + "ck_dyn_E": 1e-12, + + "ca_termination": true, + "ca_R_eq": 1e6, + "ca_dyn_E": 1e-12, + + "rdq_termination": true, + "rdq_R_eq": 1e6, + "rdq_dyn_E": 1e-12, + "wdq_termination": true, + "wdq_R_eq": 1e6, + "wdq_dyn_E": 1e-12, + + "wck_termination": true, + "wck_R_eq": 1e6, + "wck_dyn_E": 1e-12, + "rdqs_termination": true, + "rdqs_R_eq": 1e6, + "rdqs_dyn_E": 1e-12 }, "memoryId": "JEDEC_1Gbx16_16B_LPDDR5-1067", "memoryType": "LPDDR5", @@ -55,7 +125,7 @@ "BL_n_S_32": 8, "pbR2act": 2, "pbR2pbR": 24, - "tCK": 3745 + "tCK": 3745e-12 } } } diff --git a/configs/memspec/JEDEC_1Gbx16_16B_LPDDR5-1600.json b/configs/memspec/JEDEC_1Gbx16_16B_LPDDR5-1600.json index 292c4371..3065adb5 100644 --- a/configs/memspec/JEDEC_1Gbx16_16B_LPDDR5-1600.json +++ b/configs/memspec/JEDEC_1Gbx16_16B_LPDDR5-1600.json @@ -11,7 +11,77 @@ "nbrOfDevices": 1, "nbrOfChannels": 1, "width": 16, - "per2BankOffset": 8 + "per2BankOffset": 8, + "WCKalwaysOn": false, + "maxBurstLength": 16 + }, + "mempowerspec": { + "vdd1": 0.0, + "idd01": 0.0, + "idd2n1": 0.0, + "idd3n1": 0.0, + "idd4r1": 0.0, + "idd4w1": 0.0, + "idd51": 0.0, + "idd5pb1": 0.0, + "idd61": 0.0, + "idd6ds1": 0.0, + "idd2p1": 0.0, + "idd3p1": 0.0, + "vdd2h": 0.0, + "idd02h": 0.0, + "idd2n2h": 0.0, + "idd3n2h": 0.0, + "idd4r2h": 0.0, + "idd4w2h": 0.0, + "idd52h": 0.0, + "idd5pb2h": 0.0, + "idd62h": 0.0, + "idd6ds2h": 0.0, + "idd2p2h": 0.0, + "idd3p2h": 0.0, + "vdd2l": 0.0, + "idd02l": 0.0, + "idd2n2l": 0.0, + "idd3n2l": 0.0, + "idd4r2l": 0.0, + "idd4w2l": 0.0, + "idd52l": 0.0, + "idd5pb2l": 0.0, + "idd62l": 0.0, + "idd6ds2l": 0.0, + "idd2p2l": 0.0, + "idd3p2l": 0.0, + "vddq": 0.0, + "iBeta_vdd1": 0.0, + "iBeta_vdd2h": 0.0, + "iBeta_vdd2l": 0.0 + }, + "bankwisespec": { + "factRho": 1 + }, + "memimpedancespec": { + "ck_termination": true, + "ck_R_eq": 1e6, + "ck_dyn_E": 1e-12, + + "ca_termination": true, + "ca_R_eq": 1e6, + "ca_dyn_E": 1e-12, + + "rdq_termination": true, + "rdq_R_eq": 1e6, + "rdq_dyn_E": 1e-12, + "wdq_termination": true, + "wdq_R_eq": 1e6, + "wdq_dyn_E": 1e-12, + + "wck_termination": true, + "wck_R_eq": 1e6, + "wck_dyn_E": 1e-12, + "rdqs_termination": true, + "rdqs_R_eq": 1e6, + "rdqs_dyn_E": 1e-12 }, "memoryId": "JEDEC_1Gbx16_16B_LPDDR5-1600", "memoryType": "LPDDR5", @@ -55,7 +125,7 @@ "BL_n_S_32": 8, "pbR2act": 3, "pbR2pbR": 36, - "tCK": 2500 + "tCK": 2500e-12 } } } diff --git a/configs/memspec/JEDEC_1Gbx16_16B_LPDDR5-2133.json b/configs/memspec/JEDEC_1Gbx16_16B_LPDDR5-2133.json index 5ea6797a..baf3ee30 100644 --- a/configs/memspec/JEDEC_1Gbx16_16B_LPDDR5-2133.json +++ b/configs/memspec/JEDEC_1Gbx16_16B_LPDDR5-2133.json @@ -11,7 +11,77 @@ "nbrOfDevices": 1, "nbrOfChannels": 1, "width": 16, - "per2BankOffset": 8 + "per2BankOffset": 8, + "WCKalwaysOn": false, + "maxBurstLength": 16 + }, + "mempowerspec": { + "vdd1": 0.0, + "idd01": 0.0, + "idd2n1": 0.0, + "idd3n1": 0.0, + "idd4r1": 0.0, + "idd4w1": 0.0, + "idd51": 0.0, + "idd5pb1": 0.0, + "idd61": 0.0, + "idd6ds1": 0.0, + "idd2p1": 0.0, + "idd3p1": 0.0, + "vdd2h": 0.0, + "idd02h": 0.0, + "idd2n2h": 0.0, + "idd3n2h": 0.0, + "idd4r2h": 0.0, + "idd4w2h": 0.0, + "idd52h": 0.0, + "idd5pb2h": 0.0, + "idd62h": 0.0, + "idd6ds2h": 0.0, + "idd2p2h": 0.0, + "idd3p2h": 0.0, + "vdd2l": 0.0, + "idd02l": 0.0, + "idd2n2l": 0.0, + "idd3n2l": 0.0, + "idd4r2l": 0.0, + "idd4w2l": 0.0, + "idd52l": 0.0, + "idd5pb2l": 0.0, + "idd62l": 0.0, + "idd6ds2l": 0.0, + "idd2p2l": 0.0, + "idd3p2l": 0.0, + "vddq": 0.0, + "iBeta_vdd1": 0.0, + "iBeta_vdd2h": 0.0, + "iBeta_vdd2l": 0.0 + }, + "bankwisespec": { + "factRho": 1 + }, + "memimpedancespec": { + "ck_termination": true, + "ck_R_eq": 1e6, + "ck_dyn_E": 1e-12, + + "ca_termination": true, + "ca_R_eq": 1e6, + "ca_dyn_E": 1e-12, + + "rdq_termination": true, + "rdq_R_eq": 1e6, + "rdq_dyn_E": 1e-12, + "wdq_termination": true, + "wdq_R_eq": 1e6, + "wdq_dyn_E": 1e-12, + + "wck_termination": true, + "wck_R_eq": 1e6, + "wck_dyn_E": 1e-12, + "rdqs_termination": true, + "rdqs_R_eq": 1e6, + "rdqs_dyn_E": 1e-12 }, "memoryId": "JEDEC_1Gbx16_16B_LPDDR5-2133", "memoryType": "LPDDR5", @@ -55,7 +125,7 @@ "BL_n_S_32": 8, "pbR2act": 4, "pbR2pbR": 48, - "tCK": 1876 + "tCK": 1876e-12 } } } diff --git a/configs/memspec/JEDEC_1Gbx16_16B_LPDDR5-2750.json b/configs/memspec/JEDEC_1Gbx16_16B_LPDDR5-2750.json index 4dd25888..0cc10ddb 100644 --- a/configs/memspec/JEDEC_1Gbx16_16B_LPDDR5-2750.json +++ b/configs/memspec/JEDEC_1Gbx16_16B_LPDDR5-2750.json @@ -11,7 +11,77 @@ "nbrOfDevices": 1, "nbrOfChannels": 1, "width": 16, - "per2BankOffset": 8 + "per2BankOffset": 8, + "WCKalwaysOn": false, + "maxBurstLength": 16 + }, + "mempowerspec": { + "vdd1": 0.0, + "idd01": 0.0, + "idd2n1": 0.0, + "idd3n1": 0.0, + "idd4r1": 0.0, + "idd4w1": 0.0, + "idd51": 0.0, + "idd5pb1": 0.0, + "idd61": 0.0, + "idd6ds1": 0.0, + "idd2p1": 0.0, + "idd3p1": 0.0, + "vdd2h": 0.0, + "idd02h": 0.0, + "idd2n2h": 0.0, + "idd3n2h": 0.0, + "idd4r2h": 0.0, + "idd4w2h": 0.0, + "idd52h": 0.0, + "idd5pb2h": 0.0, + "idd62h": 0.0, + "idd6ds2h": 0.0, + "idd2p2h": 0.0, + "idd3p2h": 0.0, + "vdd2l": 0.0, + "idd02l": 0.0, + "idd2n2l": 0.0, + "idd3n2l": 0.0, + "idd4r2l": 0.0, + "idd4w2l": 0.0, + "idd52l": 0.0, + "idd5pb2l": 0.0, + "idd62l": 0.0, + "idd6ds2l": 0.0, + "idd2p2l": 0.0, + "idd3p2l": 0.0, + "vddq": 0.0, + "iBeta_vdd1": 0.0, + "iBeta_vdd2h": 0.0, + "iBeta_vdd2l": 0.0 + }, + "bankwisespec": { + "factRho": 1 + }, + "memimpedancespec": { + "ck_termination": true, + "ck_R_eq": 1e6, + "ck_dyn_E": 1e-12, + + "ca_termination": true, + "ca_R_eq": 1e6, + "ca_dyn_E": 1e-12, + + "rdq_termination": true, + "rdq_R_eq": 1e6, + "rdq_dyn_E": 1e-12, + "wdq_termination": true, + "wdq_R_eq": 1e6, + "wdq_dyn_E": 1e-12, + + "wck_termination": true, + "wck_R_eq": 1e6, + "wck_dyn_E": 1e-12, + "rdqs_termination": true, + "rdqs_R_eq": 1e6, + "rdqs_dyn_E": 1e-12 }, "memoryId": "JEDEC_1Gbx16_16B_LPDDR5-2750", "memoryType": "LPDDR5", @@ -55,7 +125,7 @@ "BL_n_S_32": 8, "pbR2act": 6, "pbR2pbR": 62, - "tCK": 1453 + "tCK": 1453e-12 } } } diff --git a/configs/memspec/JEDEC_1Gbx16_16B_LPDDR5-3200.json b/configs/memspec/JEDEC_1Gbx16_16B_LPDDR5-3200.json index 393a2212..ad65baa7 100644 --- a/configs/memspec/JEDEC_1Gbx16_16B_LPDDR5-3200.json +++ b/configs/memspec/JEDEC_1Gbx16_16B_LPDDR5-3200.json @@ -11,7 +11,77 @@ "nbrOfDevices": 1, "nbrOfChannels": 1, "width": 16, - "per2BankOffset": 8 + "per2BankOffset": 8, + "WCKalwaysOn": false, + "maxBurstLength": 16 + }, + "mempowerspec": { + "vdd1": 0.0, + "idd01": 0.0, + "idd2n1": 0.0, + "idd3n1": 0.0, + "idd4r1": 0.0, + "idd4w1": 0.0, + "idd51": 0.0, + "idd5pb1": 0.0, + "idd61": 0.0, + "idd6ds1": 0.0, + "idd2p1": 0.0, + "idd3p1": 0.0, + "vdd2h": 0.0, + "idd02h": 0.0, + "idd2n2h": 0.0, + "idd3n2h": 0.0, + "idd4r2h": 0.0, + "idd4w2h": 0.0, + "idd52h": 0.0, + "idd5pb2h": 0.0, + "idd62h": 0.0, + "idd6ds2h": 0.0, + "idd2p2h": 0.0, + "idd3p2h": 0.0, + "vdd2l": 0.0, + "idd02l": 0.0, + "idd2n2l": 0.0, + "idd3n2l": 0.0, + "idd4r2l": 0.0, + "idd4w2l": 0.0, + "idd52l": 0.0, + "idd5pb2l": 0.0, + "idd62l": 0.0, + "idd6ds2l": 0.0, + "idd2p2l": 0.0, + "idd3p2l": 0.0, + "vddq": 0.0, + "iBeta_vdd1": 0.0, + "iBeta_vdd2h": 0.0, + "iBeta_vdd2l": 0.0 + }, + "bankwisespec": { + "factRho": 1 + }, + "memimpedancespec": { + "ck_termination": true, + "ck_R_eq": 1e6, + "ck_dyn_E": 1e-12, + + "ca_termination": true, + "ca_R_eq": 1e6, + "ca_dyn_E": 1e-12, + + "rdq_termination": true, + "rdq_R_eq": 1e6, + "rdq_dyn_E": 1e-12, + "wdq_termination": true, + "wdq_R_eq": 1e6, + "wdq_dyn_E": 1e-12, + + "wck_termination": true, + "wck_R_eq": 1e6, + "wck_dyn_E": 1e-12, + "rdqs_termination": true, + "rdqs_R_eq": 1e6, + "rdqs_dyn_E": 1e-12 }, "memoryId": "JEDEC_1Gbx16_16B_LPDDR5-3200", "memoryType": "LPDDR5", @@ -55,7 +125,7 @@ "BL_n_S_32": 8, "pbR2act": 6, "pbR2pbR": 72, - "tCK": 1250 + "tCK": 1250e-12 } } } diff --git a/configs/memspec/JEDEC_1Gbx16_16B_LPDDR5X-0533.json b/configs/memspec/JEDEC_1Gbx16_16B_LPDDR5X-0533.json index 6e2917cb..fdf9a10a 100644 --- a/configs/memspec/JEDEC_1Gbx16_16B_LPDDR5X-0533.json +++ b/configs/memspec/JEDEC_1Gbx16_16B_LPDDR5X-0533.json @@ -11,7 +11,77 @@ "nbrOfDevices": 1, "nbrOfChannels": 1, "width": 16, - "per2BankOffset": 8 + "per2BankOffset": 8, + "WCKalwaysOn": false, + "maxBurstLength": 16 + }, + "mempowerspec": { + "vdd1": 0.0, + "idd01": 0.0, + "idd2n1": 0.0, + "idd3n1": 0.0, + "idd4r1": 0.0, + "idd4w1": 0.0, + "idd51": 0.0, + "idd5pb1": 0.0, + "idd61": 0.0, + "idd6ds1": 0.0, + "idd2p1": 0.0, + "idd3p1": 0.0, + "vdd2h": 0.0, + "idd02h": 0.0, + "idd2n2h": 0.0, + "idd3n2h": 0.0, + "idd4r2h": 0.0, + "idd4w2h": 0.0, + "idd52h": 0.0, + "idd5pb2h": 0.0, + "idd62h": 0.0, + "idd6ds2h": 0.0, + "idd2p2h": 0.0, + "idd3p2h": 0.0, + "vdd2l": 0.0, + "idd02l": 0.0, + "idd2n2l": 0.0, + "idd3n2l": 0.0, + "idd4r2l": 0.0, + "idd4w2l": 0.0, + "idd52l": 0.0, + "idd5pb2l": 0.0, + "idd62l": 0.0, + "idd6ds2l": 0.0, + "idd2p2l": 0.0, + "idd3p2l": 0.0, + "vddq": 0.0, + "iBeta_vdd1": 0.0, + "iBeta_vdd2h": 0.0, + "iBeta_vdd2l": 0.0 + }, + "bankwisespec": { + "factRho": 1 + }, + "memimpedancespec": { + "ck_termination": true, + "ck_R_eq": 1e6, + "ck_dyn_E": 1e-12, + + "ca_termination": true, + "ca_R_eq": 1e6, + "ca_dyn_E": 1e-12, + + "rdq_termination": true, + "rdq_R_eq": 1e6, + "rdq_dyn_E": 1e-12, + "wdq_termination": true, + "wdq_R_eq": 1e6, + "wdq_dyn_E": 1e-12, + + "wck_termination": true, + "wck_R_eq": 1e6, + "wck_dyn_E": 1e-12, + "rdqs_termination": true, + "rdqs_R_eq": 1e6, + "rdqs_dyn_E": 1e-12 }, "memoryId": "JEDEC_1Gbx16_16B_LPDDR5X-0533", "memoryType": "LPDDR5", @@ -57,7 +127,7 @@ "BL_n_S_32": 4, "pbR2act": 1, "pbR2pbR": 7, - "tCK": 14925 + "tCK": 14925e-12 } } } diff --git a/configs/memspec/JEDEC_1Gbx16_16B_LPDDR5X-1067.json b/configs/memspec/JEDEC_1Gbx16_16B_LPDDR5X-1067.json index 4a534ad4..a525d868 100644 --- a/configs/memspec/JEDEC_1Gbx16_16B_LPDDR5X-1067.json +++ b/configs/memspec/JEDEC_1Gbx16_16B_LPDDR5X-1067.json @@ -11,7 +11,77 @@ "nbrOfDevices": 1, "nbrOfChannels": 1, "width": 16, - "per2BankOffset": 8 + "per2BankOffset": 8, + "WCKalwaysOn": false, + "maxBurstLength": 16 + }, + "mempowerspec": { + "vdd1": 0.0, + "idd01": 0.0, + "idd2n1": 0.0, + "idd3n1": 0.0, + "idd4r1": 0.0, + "idd4w1": 0.0, + "idd51": 0.0, + "idd5pb1": 0.0, + "idd61": 0.0, + "idd6ds1": 0.0, + "idd2p1": 0.0, + "idd3p1": 0.0, + "vdd2h": 0.0, + "idd02h": 0.0, + "idd2n2h": 0.0, + "idd3n2h": 0.0, + "idd4r2h": 0.0, + "idd4w2h": 0.0, + "idd52h": 0.0, + "idd5pb2h": 0.0, + "idd62h": 0.0, + "idd6ds2h": 0.0, + "idd2p2h": 0.0, + "idd3p2h": 0.0, + "vdd2l": 0.0, + "idd02l": 0.0, + "idd2n2l": 0.0, + "idd3n2l": 0.0, + "idd4r2l": 0.0, + "idd4w2l": 0.0, + "idd52l": 0.0, + "idd5pb2l": 0.0, + "idd62l": 0.0, + "idd6ds2l": 0.0, + "idd2p2l": 0.0, + "idd3p2l": 0.0, + "vddq": 0.0, + "iBeta_vdd1": 0.0, + "iBeta_vdd2h": 0.0, + "iBeta_vdd2l": 0.0 + }, + "bankwisespec": { + "factRho": 1 + }, + "memimpedancespec": { + "ck_termination": true, + "ck_R_eq": 1e6, + "ck_dyn_E": 1e-12, + + "ca_termination": true, + "ca_R_eq": 1e6, + "ca_dyn_E": 1e-12, + + "rdq_termination": true, + "rdq_R_eq": 1e6, + "rdq_dyn_E": 1e-12, + "wdq_termination": true, + "wdq_R_eq": 1e6, + "wdq_dyn_E": 1e-12, + + "wck_termination": true, + "wck_R_eq": 1e6, + "wck_dyn_E": 1e-12, + "rdqs_termination": true, + "rdqs_R_eq": 1e6, + "rdqs_dyn_E": 1e-12 }, "memoryId": "JEDEC_1Gbx16_16B_LPDDR5X-1067", "memoryType": "LPDDR5", @@ -57,7 +127,7 @@ "BL_n_S_32": 4, "pbR2act": 1, "pbR2pbR": 12, - "tCK": 7519 + "tCK": 7519e-12 } } } diff --git a/configs/memspec/JEDEC_1Gbx16_16B_LPDDR5X-1600.json b/configs/memspec/JEDEC_1Gbx16_16B_LPDDR5X-1600.json index f2477e2e..22992db1 100644 --- a/configs/memspec/JEDEC_1Gbx16_16B_LPDDR5X-1600.json +++ b/configs/memspec/JEDEC_1Gbx16_16B_LPDDR5X-1600.json @@ -11,7 +11,77 @@ "nbrOfDevices": 1, "nbrOfChannels": 1, "width": 16, - "per2BankOffset": 8 + "per2BankOffset": 8, + "WCKalwaysOn": false, + "maxBurstLength": 16 + }, + "mempowerspec": { + "vdd1": 0.0, + "idd01": 0.0, + "idd2n1": 0.0, + "idd3n1": 0.0, + "idd4r1": 0.0, + "idd4w1": 0.0, + "idd51": 0.0, + "idd5pb1": 0.0, + "idd61": 0.0, + "idd6ds1": 0.0, + "idd2p1": 0.0, + "idd3p1": 0.0, + "vdd2h": 0.0, + "idd02h": 0.0, + "idd2n2h": 0.0, + "idd3n2h": 0.0, + "idd4r2h": 0.0, + "idd4w2h": 0.0, + "idd52h": 0.0, + "idd5pb2h": 0.0, + "idd62h": 0.0, + "idd6ds2h": 0.0, + "idd2p2h": 0.0, + "idd3p2h": 0.0, + "vdd2l": 0.0, + "idd02l": 0.0, + "idd2n2l": 0.0, + "idd3n2l": 0.0, + "idd4r2l": 0.0, + "idd4w2l": 0.0, + "idd52l": 0.0, + "idd5pb2l": 0.0, + "idd62l": 0.0, + "idd6ds2l": 0.0, + "idd2p2l": 0.0, + "idd3p2l": 0.0, + "vddq": 0.0, + "iBeta_vdd1": 0.0, + "iBeta_vdd2h": 0.0, + "iBeta_vdd2l": 0.0 + }, + "bankwisespec": { + "factRho": 1 + }, + "memimpedancespec": { + "ck_termination": true, + "ck_R_eq": 1e6, + "ck_dyn_E": 1e-12, + + "ca_termination": true, + "ca_R_eq": 1e6, + "ca_dyn_E": 1e-12, + + "rdq_termination": true, + "rdq_R_eq": 1e6, + "rdq_dyn_E": 1e-12, + "wdq_termination": true, + "wdq_R_eq": 1e6, + "wdq_dyn_E": 1e-12, + + "wck_termination": true, + "wck_R_eq": 1e6, + "wck_dyn_E": 1e-12, + "rdqs_termination": true, + "rdqs_R_eq": 1e6, + "rdqs_dyn_E": 1e-12 }, "memoryId": "JEDEC_1Gbx16_16B_LPDDR5X-1600", "memoryType": "LPDDR5", @@ -57,7 +127,7 @@ "BL_n_S_32": 4, "pbR2act": 2, "pbR2pbR": 18, - "tCK": 5000 + "tCK": 5000e-12 } } } diff --git a/configs/memspec/JEDEC_1Gbx16_16B_LPDDR5X-2133.json b/configs/memspec/JEDEC_1Gbx16_16B_LPDDR5X-2133.json index 77b5e431..2a81a425 100644 --- a/configs/memspec/JEDEC_1Gbx16_16B_LPDDR5X-2133.json +++ b/configs/memspec/JEDEC_1Gbx16_16B_LPDDR5X-2133.json @@ -11,7 +11,77 @@ "nbrOfDevices": 1, "nbrOfChannels": 1, "width": 16, - "per2BankOffset": 8 + "per2BankOffset": 8, + "WCKalwaysOn": false, + "maxBurstLength": 16 + }, + "mempowerspec": { + "vdd1": 0.0, + "idd01": 0.0, + "idd2n1": 0.0, + "idd3n1": 0.0, + "idd4r1": 0.0, + "idd4w1": 0.0, + "idd51": 0.0, + "idd5pb1": 0.0, + "idd61": 0.0, + "idd6ds1": 0.0, + "idd2p1": 0.0, + "idd3p1": 0.0, + "vdd2h": 0.0, + "idd02h": 0.0, + "idd2n2h": 0.0, + "idd3n2h": 0.0, + "idd4r2h": 0.0, + "idd4w2h": 0.0, + "idd52h": 0.0, + "idd5pb2h": 0.0, + "idd62h": 0.0, + "idd6ds2h": 0.0, + "idd2p2h": 0.0, + "idd3p2h": 0.0, + "vdd2l": 0.0, + "idd02l": 0.0, + "idd2n2l": 0.0, + "idd3n2l": 0.0, + "idd4r2l": 0.0, + "idd4w2l": 0.0, + "idd52l": 0.0, + "idd5pb2l": 0.0, + "idd62l": 0.0, + "idd6ds2l": 0.0, + "idd2p2l": 0.0, + "idd3p2l": 0.0, + "vddq": 0.0, + "iBeta_vdd1": 0.0, + "iBeta_vdd2h": 0.0, + "iBeta_vdd2l": 0.0 + }, + "bankwisespec": { + "factRho": 1 + }, + "memimpedancespec": { + "ck_termination": true, + "ck_R_eq": 1e6, + "ck_dyn_E": 1e-12, + + "ca_termination": true, + "ca_R_eq": 1e6, + "ca_dyn_E": 1e-12, + + "rdq_termination": true, + "rdq_R_eq": 1e6, + "rdq_dyn_E": 1e-12, + "wdq_termination": true, + "wdq_R_eq": 1e6, + "wdq_dyn_E": 1e-12, + + "wck_termination": true, + "wck_R_eq": 1e6, + "wck_dyn_E": 1e-12, + "rdqs_termination": true, + "rdqs_R_eq": 1e6, + "rdqs_dyn_E": 1e-12 }, "memoryId": "JEDEC_1Gbx16_16B_LPDDR5X-2133", "memoryType": "LPDDR5", @@ -57,7 +127,7 @@ "BL_n_S_32": 4, "pbR2act": 2, "pbR2pbR": 24, - "tCK": 3745 + "tCK": 3745e-12 } } } diff --git a/configs/memspec/JEDEC_1Gbx16_16B_LPDDR5X-2750.json b/configs/memspec/JEDEC_1Gbx16_16B_LPDDR5X-2750.json index 5f028f5c..0edc5c21 100644 --- a/configs/memspec/JEDEC_1Gbx16_16B_LPDDR5X-2750.json +++ b/configs/memspec/JEDEC_1Gbx16_16B_LPDDR5X-2750.json @@ -11,7 +11,77 @@ "nbrOfDevices": 1, "nbrOfChannels": 1, "width": 16, - "per2BankOffset": 8 + "per2BankOffset": 8, + "WCKalwaysOn": false, + "maxBurstLength": 16 + }, + "mempowerspec": { + "vdd1": 0.0, + "idd01": 0.0, + "idd2n1": 0.0, + "idd3n1": 0.0, + "idd4r1": 0.0, + "idd4w1": 0.0, + "idd51": 0.0, + "idd5pb1": 0.0, + "idd61": 0.0, + "idd6ds1": 0.0, + "idd2p1": 0.0, + "idd3p1": 0.0, + "vdd2h": 0.0, + "idd02h": 0.0, + "idd2n2h": 0.0, + "idd3n2h": 0.0, + "idd4r2h": 0.0, + "idd4w2h": 0.0, + "idd52h": 0.0, + "idd5pb2h": 0.0, + "idd62h": 0.0, + "idd6ds2h": 0.0, + "idd2p2h": 0.0, + "idd3p2h": 0.0, + "vdd2l": 0.0, + "idd02l": 0.0, + "idd2n2l": 0.0, + "idd3n2l": 0.0, + "idd4r2l": 0.0, + "idd4w2l": 0.0, + "idd52l": 0.0, + "idd5pb2l": 0.0, + "idd62l": 0.0, + "idd6ds2l": 0.0, + "idd2p2l": 0.0, + "idd3p2l": 0.0, + "vddq": 0.0, + "iBeta_vdd1": 0.0, + "iBeta_vdd2h": 0.0, + "iBeta_vdd2l": 0.0 + }, + "bankwisespec": { + "factRho": 1 + }, + "memimpedancespec": { + "ck_termination": true, + "ck_R_eq": 1e6, + "ck_dyn_E": 1e-12, + + "ca_termination": true, + "ca_R_eq": 1e6, + "ca_dyn_E": 1e-12, + + "rdq_termination": true, + "rdq_R_eq": 1e6, + "rdq_dyn_E": 1e-12, + "wdq_termination": true, + "wdq_R_eq": 1e6, + "wdq_dyn_E": 1e-12, + + "wck_termination": true, + "wck_R_eq": 1e6, + "wck_dyn_E": 1e-12, + "rdqs_termination": true, + "rdqs_R_eq": 1e6, + "rdqs_dyn_E": 1e-12 }, "memoryId": "JEDEC_1Gbx16_16B_LPDDR5X-2750", "memoryType": "LPDDR5", @@ -57,7 +127,7 @@ "BL_n_S_32": 4, "pbR2act": 3, "pbR2pbR": 32, - "tCK": 2907 + "tCK": 2907e-12 } } } diff --git a/configs/memspec/JEDEC_1Gbx16_16B_LPDDR5X-3200.json b/configs/memspec/JEDEC_1Gbx16_16B_LPDDR5X-3200.json index 04dd0f44..f38b5bde 100644 --- a/configs/memspec/JEDEC_1Gbx16_16B_LPDDR5X-3200.json +++ b/configs/memspec/JEDEC_1Gbx16_16B_LPDDR5X-3200.json @@ -11,7 +11,77 @@ "nbrOfDevices": 1, "nbrOfChannels": 1, "width": 16, - "per2BankOffset": 8 + "per2BankOffset": 8, + "WCKalwaysOn": false, + "maxBurstLength": 16 + }, + "mempowerspec": { + "vdd1": 0.0, + "idd01": 0.0, + "idd2n1": 0.0, + "idd3n1": 0.0, + "idd4r1": 0.0, + "idd4w1": 0.0, + "idd51": 0.0, + "idd5pb1": 0.0, + "idd61": 0.0, + "idd6ds1": 0.0, + "idd2p1": 0.0, + "idd3p1": 0.0, + "vdd2h": 0.0, + "idd02h": 0.0, + "idd2n2h": 0.0, + "idd3n2h": 0.0, + "idd4r2h": 0.0, + "idd4w2h": 0.0, + "idd52h": 0.0, + "idd5pb2h": 0.0, + "idd62h": 0.0, + "idd6ds2h": 0.0, + "idd2p2h": 0.0, + "idd3p2h": 0.0, + "vdd2l": 0.0, + "idd02l": 0.0, + "idd2n2l": 0.0, + "idd3n2l": 0.0, + "idd4r2l": 0.0, + "idd4w2l": 0.0, + "idd52l": 0.0, + "idd5pb2l": 0.0, + "idd62l": 0.0, + "idd6ds2l": 0.0, + "idd2p2l": 0.0, + "idd3p2l": 0.0, + "vddq": 0.0, + "iBeta_vdd1": 0.0, + "iBeta_vdd2h": 0.0, + "iBeta_vdd2l": 0.0 + }, + "bankwisespec": { + "factRho": 1 + }, + "memimpedancespec": { + "ck_termination": true, + "ck_R_eq": 1e6, + "ck_dyn_E": 1e-12, + + "ca_termination": true, + "ca_R_eq": 1e6, + "ca_dyn_E": 1e-12, + + "rdq_termination": true, + "rdq_R_eq": 1e6, + "rdq_dyn_E": 1e-12, + "wdq_termination": true, + "wdq_R_eq": 1e6, + "wdq_dyn_E": 1e-12, + + "wck_termination": true, + "wck_R_eq": 1e6, + "wck_dyn_E": 1e-12, + "rdqs_termination": true, + "rdqs_R_eq": 1e6, + "rdqs_dyn_E": 1e-12 }, "memoryId": "JEDEC_1Gbx16_16B_LPDDR5X-3200", "memoryType": "LPDDR5", @@ -57,7 +127,7 @@ "BL_n_S_32": 4, "pbR2act": 3, "pbR2pbR": 36, - "tCK": 2500 + "tCK": 2500e-12 } } } diff --git a/configs/memspec/JEDEC_1Gbx16_8B_LPDDR5-0533.json b/configs/memspec/JEDEC_1Gbx16_8B_LPDDR5-0533.json index 6f3a81ff..1ff9cb7a 100644 --- a/configs/memspec/JEDEC_1Gbx16_8B_LPDDR5-0533.json +++ b/configs/memspec/JEDEC_1Gbx16_8B_LPDDR5-0533.json @@ -11,7 +11,77 @@ "nbrOfDevices": 1, "nbrOfChannels": 1, "width": 16, - "per2BankOffset": 8 + "per2BankOffset": 8, + "WCKalwaysOn": false, + "maxBurstLength": 32 + }, + "mempowerspec": { + "vdd1": 0.0, + "idd01": 0.0, + "idd2n1": 0.0, + "idd3n1": 0.0, + "idd4r1": 0.0, + "idd4w1": 0.0, + "idd51": 0.0, + "idd5pb1": 0.0, + "idd61": 0.0, + "idd6ds1": 0.0, + "idd2p1": 0.0, + "idd3p1": 0.0, + "vdd2h": 0.0, + "idd02h": 0.0, + "idd2n2h": 0.0, + "idd3n2h": 0.0, + "idd4r2h": 0.0, + "idd4w2h": 0.0, + "idd52h": 0.0, + "idd5pb2h": 0.0, + "idd62h": 0.0, + "idd6ds2h": 0.0, + "idd2p2h": 0.0, + "idd3p2h": 0.0, + "vdd2l": 0.0, + "idd02l": 0.0, + "idd2n2l": 0.0, + "idd3n2l": 0.0, + "idd4r2l": 0.0, + "idd4w2l": 0.0, + "idd52l": 0.0, + "idd5pb2l": 0.0, + "idd62l": 0.0, + "idd6ds2l": 0.0, + "idd2p2l": 0.0, + "idd3p2l": 0.0, + "vddq": 0.0, + "iBeta_vdd1": 0.0, + "iBeta_vdd2h": 0.0, + "iBeta_vdd2l": 0.0 + }, + "bankwisespec": { + "factRho": 1 + }, + "memimpedancespec": { + "ck_termination": true, + "ck_R_eq": 1e6, + "ck_dyn_E": 1e-12, + + "ca_termination": true, + "ca_R_eq": 1e6, + "ca_dyn_E": 1e-12, + + "rdq_termination": true, + "rdq_R_eq": 1e6, + "rdq_dyn_E": 1e-12, + "wdq_termination": true, + "wdq_R_eq": 1e6, + "wdq_dyn_E": 1e-12, + + "wck_termination": true, + "wck_R_eq": 1e6, + "wck_dyn_E": 1e-12, + "rdqs_termination": true, + "rdqs_R_eq": 1e6, + "rdqs_dyn_E": 1e-12 }, "memoryId": "JEDEC_1Gbx16_8B_LPDDR5-0533", "memoryType": "LPDDR5", @@ -55,7 +125,7 @@ "BL_n_S_32": 8, "pbR2act": 2, "pbR2pbR": 12, - "tCK": 7519 + "tCK": 7519e-12 } } } diff --git a/configs/memspec/JEDEC_1Gbx16_8B_LPDDR5-1067.json b/configs/memspec/JEDEC_1Gbx16_8B_LPDDR5-1067.json index 849ac665..4e3c6e21 100644 --- a/configs/memspec/JEDEC_1Gbx16_8B_LPDDR5-1067.json +++ b/configs/memspec/JEDEC_1Gbx16_8B_LPDDR5-1067.json @@ -11,7 +11,77 @@ "nbrOfDevices": 1, "nbrOfChannels": 1, "width": 16, - "per2BankOffset": 8 + "per2BankOffset": 8, + "WCKalwaysOn": false, + "maxBurstLength": 32 + }, + "mempowerspec": { + "vdd1": 0.0, + "idd01": 0.0, + "idd2n1": 0.0, + "idd3n1": 0.0, + "idd4r1": 0.0, + "idd4w1": 0.0, + "idd51": 0.0, + "idd5pb1": 0.0, + "idd61": 0.0, + "idd6ds1": 0.0, + "idd2p1": 0.0, + "idd3p1": 0.0, + "vdd2h": 0.0, + "idd02h": 0.0, + "idd2n2h": 0.0, + "idd3n2h": 0.0, + "idd4r2h": 0.0, + "idd4w2h": 0.0, + "idd52h": 0.0, + "idd5pb2h": 0.0, + "idd62h": 0.0, + "idd6ds2h": 0.0, + "idd2p2h": 0.0, + "idd3p2h": 0.0, + "vdd2l": 0.0, + "idd02l": 0.0, + "idd2n2l": 0.0, + "idd3n2l": 0.0, + "idd4r2l": 0.0, + "idd4w2l": 0.0, + "idd52l": 0.0, + "idd5pb2l": 0.0, + "idd62l": 0.0, + "idd6ds2l": 0.0, + "idd2p2l": 0.0, + "idd3p2l": 0.0, + "vddq": 0.0, + "iBeta_vdd1": 0.0, + "iBeta_vdd2h": 0.0, + "iBeta_vdd2l": 0.0 + }, + "bankwisespec": { + "factRho": 1 + }, + "memimpedancespec": { + "ck_termination": true, + "ck_R_eq": 1e6, + "ck_dyn_E": 1e-12, + + "ca_termination": true, + "ca_R_eq": 1e6, + "ca_dyn_E": 1e-12, + + "rdq_termination": true, + "rdq_R_eq": 1e6, + "rdq_dyn_E": 1e-12, + "wdq_termination": true, + "wdq_R_eq": 1e6, + "wdq_dyn_E": 1e-12, + + "wck_termination": true, + "wck_R_eq": 1e6, + "wck_dyn_E": 1e-12, + "rdqs_termination": true, + "rdqs_R_eq": 1e6, + "rdqs_dyn_E": 1e-12 }, "memoryId": "JEDEC_1Gbx16_8B_LPDDR5-1067", "memoryType": "LPDDR5", @@ -55,7 +125,7 @@ "BL_n_S_32": 8, "pbR2act": 3, "pbR2pbR": 24, - "tCK": 3745 + "tCK": 3745e-12 } } } diff --git a/configs/memspec/JEDEC_1Gbx16_8B_LPDDR5-1600.json b/configs/memspec/JEDEC_1Gbx16_8B_LPDDR5-1600.json index 1ce8741a..24a6f801 100644 --- a/configs/memspec/JEDEC_1Gbx16_8B_LPDDR5-1600.json +++ b/configs/memspec/JEDEC_1Gbx16_8B_LPDDR5-1600.json @@ -11,7 +11,77 @@ "nbrOfDevices": 1, "nbrOfChannels": 1, "width": 16, - "per2BankOffset": 8 + "per2BankOffset": 8, + "WCKalwaysOn": false, + "maxBurstLength": 32 + }, + "mempowerspec": { + "vdd1": 0.0, + "idd01": 0.0, + "idd2n1": 0.0, + "idd3n1": 0.0, + "idd4r1": 0.0, + "idd4w1": 0.0, + "idd51": 0.0, + "idd5pb1": 0.0, + "idd61": 0.0, + "idd6ds1": 0.0, + "idd2p1": 0.0, + "idd3p1": 0.0, + "vdd2h": 0.0, + "idd02h": 0.0, + "idd2n2h": 0.0, + "idd3n2h": 0.0, + "idd4r2h": 0.0, + "idd4w2h": 0.0, + "idd52h": 0.0, + "idd5pb2h": 0.0, + "idd62h": 0.0, + "idd6ds2h": 0.0, + "idd2p2h": 0.0, + "idd3p2h": 0.0, + "vdd2l": 0.0, + "idd02l": 0.0, + "idd2n2l": 0.0, + "idd3n2l": 0.0, + "idd4r2l": 0.0, + "idd4w2l": 0.0, + "idd52l": 0.0, + "idd5pb2l": 0.0, + "idd62l": 0.0, + "idd6ds2l": 0.0, + "idd2p2l": 0.0, + "idd3p2l": 0.0, + "vddq": 0.0, + "iBeta_vdd1": 0.0, + "iBeta_vdd2h": 0.0, + "iBeta_vdd2l": 0.0 + }, + "bankwisespec": { + "factRho": 1 + }, + "memimpedancespec": { + "ck_termination": true, + "ck_R_eq": 1e6, + "ck_dyn_E": 1e-12, + + "ca_termination": true, + "ca_R_eq": 1e6, + "ca_dyn_E": 1e-12, + + "rdq_termination": true, + "rdq_R_eq": 1e6, + "rdq_dyn_E": 1e-12, + "wdq_termination": true, + "wdq_R_eq": 1e6, + "wdq_dyn_E": 1e-12, + + "wck_termination": true, + "wck_R_eq": 1e6, + "wck_dyn_E": 1e-12, + "rdqs_termination": true, + "rdqs_R_eq": 1e6, + "rdqs_dyn_E": 1e-12 }, "memoryId": "JEDEC_1Gbx16_8B_LPDDR5-1600", "memoryType": "LPDDR5", @@ -55,7 +125,7 @@ "BL_n_S_32": 8, "pbR2act": 4, "pbR2pbR": 36, - "tCK": 2500 + "tCK": 2500e-12 } } } diff --git a/configs/memspec/JEDEC_1Gbx16_8B_LPDDR5-2133.json b/configs/memspec/JEDEC_1Gbx16_8B_LPDDR5-2133.json index 6573ed46..efaf9758 100644 --- a/configs/memspec/JEDEC_1Gbx16_8B_LPDDR5-2133.json +++ b/configs/memspec/JEDEC_1Gbx16_8B_LPDDR5-2133.json @@ -11,7 +11,77 @@ "nbrOfDevices": 1, "nbrOfChannels": 1, "width": 16, - "per2BankOffset": 8 + "per2BankOffset": 8, + "WCKalwaysOn": false, + "maxBurstLength": 32 + }, + "mempowerspec": { + "vdd1": 0.0, + "idd01": 0.0, + "idd2n1": 0.0, + "idd3n1": 0.0, + "idd4r1": 0.0, + "idd4w1": 0.0, + "idd51": 0.0, + "idd5pb1": 0.0, + "idd61": 0.0, + "idd6ds1": 0.0, + "idd2p1": 0.0, + "idd3p1": 0.0, + "vdd2h": 0.0, + "idd02h": 0.0, + "idd2n2h": 0.0, + "idd3n2h": 0.0, + "idd4r2h": 0.0, + "idd4w2h": 0.0, + "idd52h": 0.0, + "idd5pb2h": 0.0, + "idd62h": 0.0, + "idd6ds2h": 0.0, + "idd2p2h": 0.0, + "idd3p2h": 0.0, + "vdd2l": 0.0, + "idd02l": 0.0, + "idd2n2l": 0.0, + "idd3n2l": 0.0, + "idd4r2l": 0.0, + "idd4w2l": 0.0, + "idd52l": 0.0, + "idd5pb2l": 0.0, + "idd62l": 0.0, + "idd6ds2l": 0.0, + "idd2p2l": 0.0, + "idd3p2l": 0.0, + "vddq": 0.0, + "iBeta_vdd1": 0.0, + "iBeta_vdd2h": 0.0, + "iBeta_vdd2l": 0.0 + }, + "bankwisespec": { + "factRho": 1 + }, + "memimpedancespec": { + "ck_termination": true, + "ck_R_eq": 1e6, + "ck_dyn_E": 1e-12, + + "ca_termination": true, + "ca_R_eq": 1e6, + "ca_dyn_E": 1e-12, + + "rdq_termination": true, + "rdq_R_eq": 1e6, + "rdq_dyn_E": 1e-12, + "wdq_termination": true, + "wdq_R_eq": 1e6, + "wdq_dyn_E": 1e-12, + + "wck_termination": true, + "wck_R_eq": 1e6, + "wck_dyn_E": 1e-12, + "rdqs_termination": true, + "rdqs_R_eq": 1e6, + "rdqs_dyn_E": 1e-12 }, "memoryId": "JEDEC_1Gbx16_8B_LPDDR5-2133", "memoryType": "LPDDR5", @@ -55,7 +125,7 @@ "BL_n_S_32": 8, "pbR2act": 6, "pbR2pbR": 48, - "tCK": 1876 + "tCK": 1876e-12 } } } diff --git a/configs/memspec/JEDEC_1Gbx16_8B_LPDDR5-2750.json b/configs/memspec/JEDEC_1Gbx16_8B_LPDDR5-2750.json index 75c4a09e..31aab20a 100644 --- a/configs/memspec/JEDEC_1Gbx16_8B_LPDDR5-2750.json +++ b/configs/memspec/JEDEC_1Gbx16_8B_LPDDR5-2750.json @@ -11,7 +11,77 @@ "nbrOfDevices": 1, "nbrOfChannels": 1, "width": 16, - "per2BankOffset": 8 + "per2BankOffset": 8, + "WCKalwaysOn": false, + "maxBurstLength": 32 + }, + "mempowerspec": { + "vdd1": 0.0, + "idd01": 0.0, + "idd2n1": 0.0, + "idd3n1": 0.0, + "idd4r1": 0.0, + "idd4w1": 0.0, + "idd51": 0.0, + "idd5pb1": 0.0, + "idd61": 0.0, + "idd6ds1": 0.0, + "idd2p1": 0.0, + "idd3p1": 0.0, + "vdd2h": 0.0, + "idd02h": 0.0, + "idd2n2h": 0.0, + "idd3n2h": 0.0, + "idd4r2h": 0.0, + "idd4w2h": 0.0, + "idd52h": 0.0, + "idd5pb2h": 0.0, + "idd62h": 0.0, + "idd6ds2h": 0.0, + "idd2p2h": 0.0, + "idd3p2h": 0.0, + "vdd2l": 0.0, + "idd02l": 0.0, + "idd2n2l": 0.0, + "idd3n2l": 0.0, + "idd4r2l": 0.0, + "idd4w2l": 0.0, + "idd52l": 0.0, + "idd5pb2l": 0.0, + "idd62l": 0.0, + "idd6ds2l": 0.0, + "idd2p2l": 0.0, + "idd3p2l": 0.0, + "vddq": 0.0, + "iBeta_vdd1": 0.0, + "iBeta_vdd2h": 0.0, + "iBeta_vdd2l": 0.0 + }, + "bankwisespec": { + "factRho": 1 + }, + "memimpedancespec": { + "ck_termination": true, + "ck_R_eq": 1e6, + "ck_dyn_E": 1e-12, + + "ca_termination": true, + "ca_R_eq": 1e6, + "ca_dyn_E": 1e-12, + + "rdq_termination": true, + "rdq_R_eq": 1e6, + "rdq_dyn_E": 1e-12, + "wdq_termination": true, + "wdq_R_eq": 1e6, + "wdq_dyn_E": 1e-12, + + "wck_termination": true, + "wck_R_eq": 1e6, + "wck_dyn_E": 1e-12, + "rdqs_termination": true, + "rdqs_R_eq": 1e6, + "rdqs_dyn_E": 1e-12 }, "memoryId": "JEDEC_1Gbx16_8B_LPDDR5-2750", "memoryType": "LPDDR5", @@ -55,7 +125,7 @@ "BL_n_S_32": 8, "pbR2act": 7, "pbR2pbR": 62, - "tCK": 1453 + "tCK": 1453e-12 } } } diff --git a/configs/memspec/JEDEC_1Gbx16_8B_LPDDR5-3200.json b/configs/memspec/JEDEC_1Gbx16_8B_LPDDR5-3200.json index de78c20f..5365257a 100644 --- a/configs/memspec/JEDEC_1Gbx16_8B_LPDDR5-3200.json +++ b/configs/memspec/JEDEC_1Gbx16_8B_LPDDR5-3200.json @@ -11,7 +11,77 @@ "nbrOfDevices": 1, "nbrOfChannels": 1, "width": 16, - "per2BankOffset": 8 + "per2BankOffset": 8, + "WCKalwaysOn": false, + "maxBurstLength": 32 + }, + "mempowerspec": { + "vdd1": 0.0, + "idd01": 0.0, + "idd2n1": 0.0, + "idd3n1": 0.0, + "idd4r1": 0.0, + "idd4w1": 0.0, + "idd51": 0.0, + "idd5pb1": 0.0, + "idd61": 0.0, + "idd6ds1": 0.0, + "idd2p1": 0.0, + "idd3p1": 0.0, + "vdd2h": 0.0, + "idd02h": 0.0, + "idd2n2h": 0.0, + "idd3n2h": 0.0, + "idd4r2h": 0.0, + "idd4w2h": 0.0, + "idd52h": 0.0, + "idd5pb2h": 0.0, + "idd62h": 0.0, + "idd6ds2h": 0.0, + "idd2p2h": 0.0, + "idd3p2h": 0.0, + "vdd2l": 0.0, + "idd02l": 0.0, + "idd2n2l": 0.0, + "idd3n2l": 0.0, + "idd4r2l": 0.0, + "idd4w2l": 0.0, + "idd52l": 0.0, + "idd5pb2l": 0.0, + "idd62l": 0.0, + "idd6ds2l": 0.0, + "idd2p2l": 0.0, + "idd3p2l": 0.0, + "vddq": 0.0, + "iBeta_vdd1": 0.0, + "iBeta_vdd2h": 0.0, + "iBeta_vdd2l": 0.0 + }, + "bankwisespec": { + "factRho": 1 + }, + "memimpedancespec": { + "ck_termination": true, + "ck_R_eq": 1e6, + "ck_dyn_E": 1e-12, + + "ca_termination": true, + "ca_R_eq": 1e6, + "ca_dyn_E": 1e-12, + + "rdq_termination": true, + "rdq_R_eq": 1e6, + "rdq_dyn_E": 1e-12, + "wdq_termination": true, + "wdq_R_eq": 1e6, + "wdq_dyn_E": 1e-12, + + "wck_termination": true, + "wck_R_eq": 1e6, + "wck_dyn_E": 1e-12, + "rdqs_termination": true, + "rdqs_R_eq": 1e6, + "rdqs_dyn_E": 1e-12 }, "memoryId": "JEDEC_1Gbx16_8B_LPDDR5-3200", "memoryType": "LPDDR5", @@ -55,7 +125,7 @@ "BL_n_S_32": 8, "pbR2act": 8, "pbR2pbR": 72, - "tCK": 1250 + "tCK": 1250e-12 } } } diff --git a/configs/memspec/JEDEC_1Gbx16_8B_LPDDR5-3733.json b/configs/memspec/JEDEC_1Gbx16_8B_LPDDR5-3733.json index 133abfa9..2d8fe4b2 100644 --- a/configs/memspec/JEDEC_1Gbx16_8B_LPDDR5-3733.json +++ b/configs/memspec/JEDEC_1Gbx16_8B_LPDDR5-3733.json @@ -11,7 +11,77 @@ "nbrOfDevices": 1, "nbrOfChannels": 1, "width": 16, - "per2BankOffset": 8 + "per2BankOffset": 8, + "WCKalwaysOn": false, + "maxBurstLength": 32 + }, + "mempowerspec": { + "vdd1": 0.0, + "idd01": 0.0, + "idd2n1": 0.0, + "idd3n1": 0.0, + "idd4r1": 0.0, + "idd4w1": 0.0, + "idd51": 0.0, + "idd5pb1": 0.0, + "idd61": 0.0, + "idd6ds1": 0.0, + "idd2p1": 0.0, + "idd3p1": 0.0, + "vdd2h": 0.0, + "idd02h": 0.0, + "idd2n2h": 0.0, + "idd3n2h": 0.0, + "idd4r2h": 0.0, + "idd4w2h": 0.0, + "idd52h": 0.0, + "idd5pb2h": 0.0, + "idd62h": 0.0, + "idd6ds2h": 0.0, + "idd2p2h": 0.0, + "idd3p2h": 0.0, + "vdd2l": 0.0, + "idd02l": 0.0, + "idd2n2l": 0.0, + "idd3n2l": 0.0, + "idd4r2l": 0.0, + "idd4w2l": 0.0, + "idd52l": 0.0, + "idd5pb2l": 0.0, + "idd62l": 0.0, + "idd6ds2l": 0.0, + "idd2p2l": 0.0, + "idd3p2l": 0.0, + "vddq": 0.0, + "iBeta_vdd1": 0.0, + "iBeta_vdd2h": 0.0, + "iBeta_vdd2l": 0.0 + }, + "bankwisespec": { + "factRho": 1 + }, + "memimpedancespec": { + "ck_termination": true, + "ck_R_eq": 1e6, + "ck_dyn_E": 1e-12, + + "ca_termination": true, + "ca_R_eq": 1e6, + "ca_dyn_E": 1e-12, + + "rdq_termination": true, + "rdq_R_eq": 1e6, + "rdq_dyn_E": 1e-12, + "wdq_termination": true, + "wdq_R_eq": 1e6, + "wdq_dyn_E": 1e-12, + + "wck_termination": true, + "wck_R_eq": 1e6, + "wck_dyn_E": 1e-12, + "rdqs_termination": true, + "rdqs_R_eq": 1e6, + "rdqs_dyn_E": 1e-12 }, "memoryId": "JEDEC_1Gbx16_8B_LPDDR5-3733", "memoryType": "LPDDR5", @@ -55,7 +125,7 @@ "BL_n_S_32": 4, "pbR2act": 5, "pbR2pbR": 42, - "tCK": 2141 + "tCK": 2141e-12 } } } diff --git a/configs/memspec/JEDEC_1Gbx16_8B_LPDDR5-4267.json b/configs/memspec/JEDEC_1Gbx16_8B_LPDDR5-4267.json index cb7c3dc8..262f9db5 100644 --- a/configs/memspec/JEDEC_1Gbx16_8B_LPDDR5-4267.json +++ b/configs/memspec/JEDEC_1Gbx16_8B_LPDDR5-4267.json @@ -11,7 +11,77 @@ "nbrOfDevices": 1, "nbrOfChannels": 1, "width": 16, - "per2BankOffset": 8 + "per2BankOffset": 8, + "WCKalwaysOn": false, + "maxBurstLength": 32 + }, + "mempowerspec": { + "vdd1": 0.0, + "idd01": 0.0, + "idd2n1": 0.0, + "idd3n1": 0.0, + "idd4r1": 0.0, + "idd4w1": 0.0, + "idd51": 0.0, + "idd5pb1": 0.0, + "idd61": 0.0, + "idd6ds1": 0.0, + "idd2p1": 0.0, + "idd3p1": 0.0, + "vdd2h": 0.0, + "idd02h": 0.0, + "idd2n2h": 0.0, + "idd3n2h": 0.0, + "idd4r2h": 0.0, + "idd4w2h": 0.0, + "idd52h": 0.0, + "idd5pb2h": 0.0, + "idd62h": 0.0, + "idd6ds2h": 0.0, + "idd2p2h": 0.0, + "idd3p2h": 0.0, + "vdd2l": 0.0, + "idd02l": 0.0, + "idd2n2l": 0.0, + "idd3n2l": 0.0, + "idd4r2l": 0.0, + "idd4w2l": 0.0, + "idd52l": 0.0, + "idd5pb2l": 0.0, + "idd62l": 0.0, + "idd6ds2l": 0.0, + "idd2p2l": 0.0, + "idd3p2l": 0.0, + "vddq": 0.0, + "iBeta_vdd1": 0.0, + "iBeta_vdd2h": 0.0, + "iBeta_vdd2l": 0.0 + }, + "bankwisespec": { + "factRho": 1 + }, + "memimpedancespec": { + "ck_termination": true, + "ck_R_eq": 1e6, + "ck_dyn_E": 1e-12, + + "ca_termination": true, + "ca_R_eq": 1e6, + "ca_dyn_E": 1e-12, + + "rdq_termination": true, + "rdq_R_eq": 1e6, + "rdq_dyn_E": 1e-12, + "wdq_termination": true, + "wdq_R_eq": 1e6, + "wdq_dyn_E": 1e-12, + + "wck_termination": true, + "wck_R_eq": 1e6, + "wck_dyn_E": 1e-12, + "rdqs_termination": true, + "rdqs_R_eq": 1e6, + "rdqs_dyn_E": 1e-12 }, "memoryId": "JEDEC_1Gbx16_8B_LPDDR5-4267", "memoryType": "LPDDR5", @@ -55,7 +125,7 @@ "BL_n_S_32": 4, "pbR2act": 6, "pbR2pbR": 48, - "tCK": 1876 + "tCK": 1876e-12 } } } diff --git a/configs/memspec/JEDEC_1Gbx16_8B_LPDDR5-4800.json b/configs/memspec/JEDEC_1Gbx16_8B_LPDDR5-4800.json index 90c2fd69..a34f94bc 100644 --- a/configs/memspec/JEDEC_1Gbx16_8B_LPDDR5-4800.json +++ b/configs/memspec/JEDEC_1Gbx16_8B_LPDDR5-4800.json @@ -11,7 +11,77 @@ "nbrOfDevices": 1, "nbrOfChannels": 1, "width": 16, - "per2BankOffset": 8 + "per2BankOffset": 8, + "WCKalwaysOn": false, + "maxBurstLength": 32 + }, + "mempowerspec": { + "vdd1": 0.0, + "idd01": 0.0, + "idd2n1": 0.0, + "idd3n1": 0.0, + "idd4r1": 0.0, + "idd4w1": 0.0, + "idd51": 0.0, + "idd5pb1": 0.0, + "idd61": 0.0, + "idd6ds1": 0.0, + "idd2p1": 0.0, + "idd3p1": 0.0, + "vdd2h": 0.0, + "idd02h": 0.0, + "idd2n2h": 0.0, + "idd3n2h": 0.0, + "idd4r2h": 0.0, + "idd4w2h": 0.0, + "idd52h": 0.0, + "idd5pb2h": 0.0, + "idd62h": 0.0, + "idd6ds2h": 0.0, + "idd2p2h": 0.0, + "idd3p2h": 0.0, + "vdd2l": 0.0, + "idd02l": 0.0, + "idd2n2l": 0.0, + "idd3n2l": 0.0, + "idd4r2l": 0.0, + "idd4w2l": 0.0, + "idd52l": 0.0, + "idd5pb2l": 0.0, + "idd62l": 0.0, + "idd6ds2l": 0.0, + "idd2p2l": 0.0, + "idd3p2l": 0.0, + "vddq": 0.0, + "iBeta_vdd1": 0.0, + "iBeta_vdd2h": 0.0, + "iBeta_vdd2l": 0.0 + }, + "bankwisespec": { + "factRho": 1 + }, + "memimpedancespec": { + "ck_termination": true, + "ck_R_eq": 1e6, + "ck_dyn_E": 1e-12, + + "ca_termination": true, + "ca_R_eq": 1e6, + "ca_dyn_E": 1e-12, + + "rdq_termination": true, + "rdq_R_eq": 1e6, + "rdq_dyn_E": 1e-12, + "wdq_termination": true, + "wdq_R_eq": 1e6, + "wdq_dyn_E": 1e-12, + + "wck_termination": true, + "wck_R_eq": 1e6, + "wck_dyn_E": 1e-12, + "rdqs_termination": true, + "rdqs_R_eq": 1e6, + "rdqs_dyn_E": 1e-12 }, "memoryId": "JEDEC_1Gbx16_8B_LPDDR5-4800", "memoryType": "LPDDR5", @@ -55,7 +125,7 @@ "BL_n_S_32": 4, "pbR2act": 6, "pbR2pbR": 54, - "tCK": 1667 + "tCK": 1667e-12 } } } diff --git a/configs/memspec/JEDEC_1Gbx16_8B_LPDDR5-5500.json b/configs/memspec/JEDEC_1Gbx16_8B_LPDDR5-5500.json index 62b35548..330495f0 100644 --- a/configs/memspec/JEDEC_1Gbx16_8B_LPDDR5-5500.json +++ b/configs/memspec/JEDEC_1Gbx16_8B_LPDDR5-5500.json @@ -11,7 +11,77 @@ "nbrOfDevices": 1, "nbrOfChannels": 1, "width": 16, - "per2BankOffset": 8 + "per2BankOffset": 8, + "WCKalwaysOn": false, + "maxBurstLength": 32 + }, + "mempowerspec": { + "vdd1": 0.0, + "idd01": 0.0, + "idd2n1": 0.0, + "idd3n1": 0.0, + "idd4r1": 0.0, + "idd4w1": 0.0, + "idd51": 0.0, + "idd5pb1": 0.0, + "idd61": 0.0, + "idd6ds1": 0.0, + "idd2p1": 0.0, + "idd3p1": 0.0, + "vdd2h": 0.0, + "idd02h": 0.0, + "idd2n2h": 0.0, + "idd3n2h": 0.0, + "idd4r2h": 0.0, + "idd4w2h": 0.0, + "idd52h": 0.0, + "idd5pb2h": 0.0, + "idd62h": 0.0, + "idd6ds2h": 0.0, + "idd2p2h": 0.0, + "idd3p2h": 0.0, + "vdd2l": 0.0, + "idd02l": 0.0, + "idd2n2l": 0.0, + "idd3n2l": 0.0, + "idd4r2l": 0.0, + "idd4w2l": 0.0, + "idd52l": 0.0, + "idd5pb2l": 0.0, + "idd62l": 0.0, + "idd6ds2l": 0.0, + "idd2p2l": 0.0, + "idd3p2l": 0.0, + "vddq": 0.0, + "iBeta_vdd1": 0.0, + "iBeta_vdd2h": 0.0, + "iBeta_vdd2l": 0.0 + }, + "bankwisespec": { + "factRho": 1 + }, + "memimpedancespec": { + "ck_termination": true, + "ck_R_eq": 1e6, + "ck_dyn_E": 1e-12, + + "ca_termination": true, + "ca_R_eq": 1e6, + "ca_dyn_E": 1e-12, + + "rdq_termination": true, + "rdq_R_eq": 1e6, + "rdq_dyn_E": 1e-12, + "wdq_termination": true, + "wdq_R_eq": 1e6, + "wdq_dyn_E": 1e-12, + + "wck_termination": true, + "wck_R_eq": 1e6, + "wck_dyn_E": 1e-12, + "rdqs_termination": true, + "rdqs_R_eq": 1e6, + "rdqs_dyn_E": 1e-12 }, "memoryId": "JEDEC_1Gbx16_8B_LPDDR5-5500", "memoryType": "LPDDR5", @@ -55,7 +125,7 @@ "BL_n_S_32": 4, "pbR2act": 7, "pbR2pbR": 62, - "tCK": 1453 + "tCK": 1453e-12 } } } diff --git a/configs/memspec/JEDEC_1Gbx16_8B_LPDDR5-6000.json b/configs/memspec/JEDEC_1Gbx16_8B_LPDDR5-6000.json index 5d627eb1..ef5181ae 100644 --- a/configs/memspec/JEDEC_1Gbx16_8B_LPDDR5-6000.json +++ b/configs/memspec/JEDEC_1Gbx16_8B_LPDDR5-6000.json @@ -11,7 +11,77 @@ "nbrOfDevices": 1, "nbrOfChannels": 1, "width": 16, - "per2BankOffset": 8 + "per2BankOffset": 8, + "WCKalwaysOn": false, + "maxBurstLength": 32 + }, + "mempowerspec": { + "vdd1": 0.0, + "idd01": 0.0, + "idd2n1": 0.0, + "idd3n1": 0.0, + "idd4r1": 0.0, + "idd4w1": 0.0, + "idd51": 0.0, + "idd5pb1": 0.0, + "idd61": 0.0, + "idd6ds1": 0.0, + "idd2p1": 0.0, + "idd3p1": 0.0, + "vdd2h": 0.0, + "idd02h": 0.0, + "idd2n2h": 0.0, + "idd3n2h": 0.0, + "idd4r2h": 0.0, + "idd4w2h": 0.0, + "idd52h": 0.0, + "idd5pb2h": 0.0, + "idd62h": 0.0, + "idd6ds2h": 0.0, + "idd2p2h": 0.0, + "idd3p2h": 0.0, + "vdd2l": 0.0, + "idd02l": 0.0, + "idd2n2l": 0.0, + "idd3n2l": 0.0, + "idd4r2l": 0.0, + "idd4w2l": 0.0, + "idd52l": 0.0, + "idd5pb2l": 0.0, + "idd62l": 0.0, + "idd6ds2l": 0.0, + "idd2p2l": 0.0, + "idd3p2l": 0.0, + "vddq": 0.0, + "iBeta_vdd1": 0.0, + "iBeta_vdd2h": 0.0, + "iBeta_vdd2l": 0.0 + }, + "bankwisespec": { + "factRho": 1 + }, + "memimpedancespec": { + "ck_termination": true, + "ck_R_eq": 1e6, + "ck_dyn_E": 1e-12, + + "ca_termination": true, + "ca_R_eq": 1e6, + "ca_dyn_E": 1e-12, + + "rdq_termination": true, + "rdq_R_eq": 1e6, + "rdq_dyn_E": 1e-12, + "wdq_termination": true, + "wdq_R_eq": 1e6, + "wdq_dyn_E": 1e-12, + + "wck_termination": true, + "wck_R_eq": 1e6, + "wck_dyn_E": 1e-12, + "rdqs_termination": true, + "rdqs_R_eq": 1e6, + "rdqs_dyn_E": 1e-12 }, "memoryId": "JEDEC_1Gbx16_8B_LPDDR5-6000", "memoryType": "LPDDR5", @@ -55,7 +125,7 @@ "BL_n_S_32": 4, "pbR2act": 8, "pbR2pbR": 68, - "tCK": 1333 + "tCK": 1333e-12 } } } diff --git a/configs/memspec/JEDEC_1Gbx16_8B_LPDDR5-6400.json b/configs/memspec/JEDEC_1Gbx16_8B_LPDDR5-6400.json index c9e24363..57ed3745 100644 --- a/configs/memspec/JEDEC_1Gbx16_8B_LPDDR5-6400.json +++ b/configs/memspec/JEDEC_1Gbx16_8B_LPDDR5-6400.json @@ -11,7 +11,77 @@ "nbrOfDevices": 1, "nbrOfChannels": 1, "width": 16, - "per2BankOffset": 8 + "per2BankOffset": 8, + "WCKalwaysOn": false, + "maxBurstLength": 32 + }, + "mempowerspec": { + "vdd1": 0.0, + "idd01": 0.0, + "idd2n1": 0.0, + "idd3n1": 0.0, + "idd4r1": 0.0, + "idd4w1": 0.0, + "idd51": 0.0, + "idd5pb1": 0.0, + "idd61": 0.0, + "idd6ds1": 0.0, + "idd2p1": 0.0, + "idd3p1": 0.0, + "vdd2h": 0.0, + "idd02h": 0.0, + "idd2n2h": 0.0, + "idd3n2h": 0.0, + "idd4r2h": 0.0, + "idd4w2h": 0.0, + "idd52h": 0.0, + "idd5pb2h": 0.0, + "idd62h": 0.0, + "idd6ds2h": 0.0, + "idd2p2h": 0.0, + "idd3p2h": 0.0, + "vdd2l": 0.0, + "idd02l": 0.0, + "idd2n2l": 0.0, + "idd3n2l": 0.0, + "idd4r2l": 0.0, + "idd4w2l": 0.0, + "idd52l": 0.0, + "idd5pb2l": 0.0, + "idd62l": 0.0, + "idd6ds2l": 0.0, + "idd2p2l": 0.0, + "idd3p2l": 0.0, + "vddq": 0.0, + "iBeta_vdd1": 0.0, + "iBeta_vdd2h": 0.0, + "iBeta_vdd2l": 0.0 + }, + "bankwisespec": { + "factRho": 1 + }, + "memimpedancespec": { + "ck_termination": true, + "ck_R_eq": 1e6, + "ck_dyn_E": 1e-12, + + "ca_termination": true, + "ca_R_eq": 1e6, + "ca_dyn_E": 1e-12, + + "rdq_termination": true, + "rdq_R_eq": 1e6, + "rdq_dyn_E": 1e-12, + "wdq_termination": true, + "wdq_R_eq": 1e6, + "wdq_dyn_E": 1e-12, + + "wck_termination": true, + "wck_R_eq": 1e6, + "wck_dyn_E": 1e-12, + "rdqs_termination": true, + "rdqs_R_eq": 1e6, + "rdqs_dyn_E": 1e-12 }, "memoryId": "JEDEC_1Gbx16_8B_LPDDR5-6400", "memoryType": "LPDDR5", @@ -55,7 +125,7 @@ "BL_n_S_32": 4, "pbR2act": 8, "pbR2pbR": 72, - "tCK": 1250 + "tCK": 1250e-12 } } } diff --git a/configs/memspec/JEDEC_1Gbx16_BG_LPDDR5-3733.json b/configs/memspec/JEDEC_1Gbx16_BG_LPDDR5-3733.json index 97ee62c0..87e5d736 100644 --- a/configs/memspec/JEDEC_1Gbx16_BG_LPDDR5-3733.json +++ b/configs/memspec/JEDEC_1Gbx16_BG_LPDDR5-3733.json @@ -11,7 +11,77 @@ "nbrOfDevices": 1, "nbrOfChannels": 1, "width": 16, - "per2BankOffset": 8 + "per2BankOffset": 8, + "WCKalwaysOn": false, + "maxBurstLength": 16 + }, + "mempowerspec": { + "vdd1": 0.0, + "idd01": 0.0, + "idd2n1": 0.0, + "idd3n1": 0.0, + "idd4r1": 0.0, + "idd4w1": 0.0, + "idd51": 0.0, + "idd5pb1": 0.0, + "idd61": 0.0, + "idd6ds1": 0.0, + "idd2p1": 0.0, + "idd3p1": 0.0, + "vdd2h": 0.0, + "idd02h": 0.0, + "idd2n2h": 0.0, + "idd3n2h": 0.0, + "idd4r2h": 0.0, + "idd4w2h": 0.0, + "idd52h": 0.0, + "idd5pb2h": 0.0, + "idd62h": 0.0, + "idd6ds2h": 0.0, + "idd2p2h": 0.0, + "idd3p2h": 0.0, + "vdd2l": 0.0, + "idd02l": 0.0, + "idd2n2l": 0.0, + "idd3n2l": 0.0, + "idd4r2l": 0.0, + "idd4w2l": 0.0, + "idd52l": 0.0, + "idd5pb2l": 0.0, + "idd62l": 0.0, + "idd6ds2l": 0.0, + "idd2p2l": 0.0, + "idd3p2l": 0.0, + "vddq": 0.0, + "iBeta_vdd1": 0.0, + "iBeta_vdd2h": 0.0, + "iBeta_vdd2l": 0.0 + }, + "bankwisespec": { + "factRho": 1 + }, + "memimpedancespec": { + "ck_termination": true, + "ck_R_eq": 1e6, + "ck_dyn_E": 1e-12, + + "ca_termination": true, + "ca_R_eq": 1e6, + "ca_dyn_E": 1e-12, + + "rdq_termination": true, + "rdq_R_eq": 1e6, + "rdq_dyn_E": 1e-12, + "wdq_termination": true, + "wdq_R_eq": 1e6, + "wdq_dyn_E": 1e-12, + + "wck_termination": true, + "wck_R_eq": 1e6, + "wck_dyn_E": 1e-12, + "rdqs_termination": true, + "rdqs_R_eq": 1e6, + "rdqs_dyn_E": 1e-12 }, "memoryId": "JEDEC_1Gbx16_BG_LPDDR5-3733", "memoryType": "LPDDR5", @@ -55,7 +125,7 @@ "BL_n_S_32": 2, "pbR2act": 4, "pbR2pbR": 42, - "tCK": 2141 + "tCK": 2141e-12 } } } diff --git a/configs/memspec/JEDEC_1Gbx16_BG_LPDDR5-4267.json b/configs/memspec/JEDEC_1Gbx16_BG_LPDDR5-4267.json index 29ae0154..6424709c 100644 --- a/configs/memspec/JEDEC_1Gbx16_BG_LPDDR5-4267.json +++ b/configs/memspec/JEDEC_1Gbx16_BG_LPDDR5-4267.json @@ -11,7 +11,77 @@ "nbrOfDevices": 1, "nbrOfChannels": 1, "width": 16, - "per2BankOffset": 8 + "per2BankOffset": 8, + "WCKalwaysOn": false, + "maxBurstLength": 16 + }, + "mempowerspec": { + "vdd1": 0.0, + "idd01": 0.0, + "idd2n1": 0.0, + "idd3n1": 0.0, + "idd4r1": 0.0, + "idd4w1": 0.0, + "idd51": 0.0, + "idd5pb1": 0.0, + "idd61": 0.0, + "idd6ds1": 0.0, + "idd2p1": 0.0, + "idd3p1": 0.0, + "vdd2h": 0.0, + "idd02h": 0.0, + "idd2n2h": 0.0, + "idd3n2h": 0.0, + "idd4r2h": 0.0, + "idd4w2h": 0.0, + "idd52h": 0.0, + "idd5pb2h": 0.0, + "idd62h": 0.0, + "idd6ds2h": 0.0, + "idd2p2h": 0.0, + "idd3p2h": 0.0, + "vdd2l": 0.0, + "idd02l": 0.0, + "idd2n2l": 0.0, + "idd3n2l": 0.0, + "idd4r2l": 0.0, + "idd4w2l": 0.0, + "idd52l": 0.0, + "idd5pb2l": 0.0, + "idd62l": 0.0, + "idd6ds2l": 0.0, + "idd2p2l": 0.0, + "idd3p2l": 0.0, + "vddq": 0.0, + "iBeta_vdd1": 0.0, + "iBeta_vdd2h": 0.0, + "iBeta_vdd2l": 0.0 + }, + "bankwisespec": { + "factRho": 1 + }, + "memimpedancespec": { + "ck_termination": true, + "ck_R_eq": 1e6, + "ck_dyn_E": 1e-12, + + "ca_termination": true, + "ca_R_eq": 1e6, + "ca_dyn_E": 1e-12, + + "rdq_termination": true, + "rdq_R_eq": 1e6, + "rdq_dyn_E": 1e-12, + "wdq_termination": true, + "wdq_R_eq": 1e6, + "wdq_dyn_E": 1e-12, + + "wck_termination": true, + "wck_R_eq": 1e6, + "wck_dyn_E": 1e-12, + "rdqs_termination": true, + "rdqs_R_eq": 1e6, + "rdqs_dyn_E": 1e-12 }, "memoryId": "JEDEC_1Gbx16_BG_LPDDR5-4267", "memoryType": "LPDDR5", @@ -55,7 +125,7 @@ "BL_n_S_32": 2, "pbR2act": 4, "pbR2pbR": 48, - "tCK": 1876 + "tCK": 1876e-12 } } } diff --git a/configs/memspec/JEDEC_1Gbx16_BG_LPDDR5-4800.json b/configs/memspec/JEDEC_1Gbx16_BG_LPDDR5-4800.json index dc346ea9..b7186879 100644 --- a/configs/memspec/JEDEC_1Gbx16_BG_LPDDR5-4800.json +++ b/configs/memspec/JEDEC_1Gbx16_BG_LPDDR5-4800.json @@ -11,7 +11,77 @@ "nbrOfDevices": 1, "nbrOfChannels": 1, "width": 16, - "per2BankOffset": 8 + "per2BankOffset": 8, + "WCKalwaysOn": false, + "maxBurstLength": 16 + }, + "mempowerspec": { + "vdd1": 0.0, + "idd01": 0.0, + "idd2n1": 0.0, + "idd3n1": 0.0, + "idd4r1": 0.0, + "idd4w1": 0.0, + "idd51": 0.0, + "idd5pb1": 0.0, + "idd61": 0.0, + "idd6ds1": 0.0, + "idd2p1": 0.0, + "idd3p1": 0.0, + "vdd2h": 0.0, + "idd02h": 0.0, + "idd2n2h": 0.0, + "idd3n2h": 0.0, + "idd4r2h": 0.0, + "idd4w2h": 0.0, + "idd52h": 0.0, + "idd5pb2h": 0.0, + "idd62h": 0.0, + "idd6ds2h": 0.0, + "idd2p2h": 0.0, + "idd3p2h": 0.0, + "vdd2l": 0.0, + "idd02l": 0.0, + "idd2n2l": 0.0, + "idd3n2l": 0.0, + "idd4r2l": 0.0, + "idd4w2l": 0.0, + "idd52l": 0.0, + "idd5pb2l": 0.0, + "idd62l": 0.0, + "idd6ds2l": 0.0, + "idd2p2l": 0.0, + "idd3p2l": 0.0, + "vddq": 0.0, + "iBeta_vdd1": 0.0, + "iBeta_vdd2h": 0.0, + "iBeta_vdd2l": 0.0 + }, + "bankwisespec": { + "factRho": 1 + }, + "memimpedancespec": { + "ck_termination": true, + "ck_R_eq": 1e6, + "ck_dyn_E": 1e-12, + + "ca_termination": true, + "ca_R_eq": 1e6, + "ca_dyn_E": 1e-12, + + "rdq_termination": true, + "rdq_R_eq": 1e6, + "rdq_dyn_E": 1e-12, + "wdq_termination": true, + "wdq_R_eq": 1e6, + "wdq_dyn_E": 1e-12, + + "wck_termination": true, + "wck_R_eq": 1e6, + "wck_dyn_E": 1e-12, + "rdqs_termination": true, + "rdqs_R_eq": 1e6, + "rdqs_dyn_E": 1e-12 }, "memoryId": "JEDEC_1Gbx16_BG_LPDDR5-4800", "memoryType": "LPDDR5", @@ -55,7 +125,7 @@ "BL_n_S_32": 2, "pbR2act": 5, "pbR2pbR": 54, - "tCK": 1667 + "tCK": 1667e-12 } } } diff --git a/configs/memspec/JEDEC_1Gbx16_BG_LPDDR5-5500.json b/configs/memspec/JEDEC_1Gbx16_BG_LPDDR5-5500.json index 0d92cb13..62492a55 100644 --- a/configs/memspec/JEDEC_1Gbx16_BG_LPDDR5-5500.json +++ b/configs/memspec/JEDEC_1Gbx16_BG_LPDDR5-5500.json @@ -11,7 +11,77 @@ "nbrOfDevices": 1, "nbrOfChannels": 1, "width": 16, - "per2BankOffset": 8 + "per2BankOffset": 8, + "WCKalwaysOn": false, + "maxBurstLength": 16 + }, + "mempowerspec": { + "vdd1": 0.0, + "idd01": 0.0, + "idd2n1": 0.0, + "idd3n1": 0.0, + "idd4r1": 0.0, + "idd4w1": 0.0, + "idd51": 0.0, + "idd5pb1": 0.0, + "idd61": 0.0, + "idd6ds1": 0.0, + "idd2p1": 0.0, + "idd3p1": 0.0, + "vdd2h": 0.0, + "idd02h": 0.0, + "idd2n2h": 0.0, + "idd3n2h": 0.0, + "idd4r2h": 0.0, + "idd4w2h": 0.0, + "idd52h": 0.0, + "idd5pb2h": 0.0, + "idd62h": 0.0, + "idd6ds2h": 0.0, + "idd2p2h": 0.0, + "idd3p2h": 0.0, + "vdd2l": 0.0, + "idd02l": 0.0, + "idd2n2l": 0.0, + "idd3n2l": 0.0, + "idd4r2l": 0.0, + "idd4w2l": 0.0, + "idd52l": 0.0, + "idd5pb2l": 0.0, + "idd62l": 0.0, + "idd6ds2l": 0.0, + "idd2p2l": 0.0, + "idd3p2l": 0.0, + "vddq": 0.0, + "iBeta_vdd1": 0.0, + "iBeta_vdd2h": 0.0, + "iBeta_vdd2l": 0.0 + }, + "bankwisespec": { + "factRho": 1 + }, + "memimpedancespec": { + "ck_termination": true, + "ck_R_eq": 1e6, + "ck_dyn_E": 1e-12, + + "ca_termination": true, + "ca_R_eq": 1e6, + "ca_dyn_E": 1e-12, + + "rdq_termination": true, + "rdq_R_eq": 1e6, + "rdq_dyn_E": 1e-12, + "wdq_termination": true, + "wdq_R_eq": 1e6, + "wdq_dyn_E": 1e-12, + + "wck_termination": true, + "wck_R_eq": 1e6, + "wck_dyn_E": 1e-12, + "rdqs_termination": true, + "rdqs_R_eq": 1e6, + "rdqs_dyn_E": 1e-12 }, "memoryId": "JEDEC_1Gbx16_BG_LPDDR5-5500", "memoryType": "LPDDR5", @@ -55,7 +125,7 @@ "BL_n_S_32": 2, "pbR2act": 6, "pbR2pbR": 62, - "tCK": 1453 + "tCK": 1453e-12 } } } diff --git a/configs/memspec/JEDEC_1Gbx16_BG_LPDDR5-6000.json b/configs/memspec/JEDEC_1Gbx16_BG_LPDDR5-6000.json index 0b5d03c6..fd9f3fd0 100644 --- a/configs/memspec/JEDEC_1Gbx16_BG_LPDDR5-6000.json +++ b/configs/memspec/JEDEC_1Gbx16_BG_LPDDR5-6000.json @@ -11,7 +11,77 @@ "nbrOfDevices": 1, "nbrOfChannels": 1, "width": 16, - "per2BankOffset": 8 + "per2BankOffset": 8, + "WCKalwaysOn": false, + "maxBurstLength": 16 + }, + "mempowerspec": { + "vdd1": 0.0, + "idd01": 0.0, + "idd2n1": 0.0, + "idd3n1": 0.0, + "idd4r1": 0.0, + "idd4w1": 0.0, + "idd51": 0.0, + "idd5pb1": 0.0, + "idd61": 0.0, + "idd6ds1": 0.0, + "idd2p1": 0.0, + "idd3p1": 0.0, + "vdd2h": 0.0, + "idd02h": 0.0, + "idd2n2h": 0.0, + "idd3n2h": 0.0, + "idd4r2h": 0.0, + "idd4w2h": 0.0, + "idd52h": 0.0, + "idd5pb2h": 0.0, + "idd62h": 0.0, + "idd6ds2h": 0.0, + "idd2p2h": 0.0, + "idd3p2h": 0.0, + "vdd2l": 0.0, + "idd02l": 0.0, + "idd2n2l": 0.0, + "idd3n2l": 0.0, + "idd4r2l": 0.0, + "idd4w2l": 0.0, + "idd52l": 0.0, + "idd5pb2l": 0.0, + "idd62l": 0.0, + "idd6ds2l": 0.0, + "idd2p2l": 0.0, + "idd3p2l": 0.0, + "vddq": 0.0, + "iBeta_vdd1": 0.0, + "iBeta_vdd2h": 0.0, + "iBeta_vdd2l": 0.0 + }, + "bankwisespec": { + "factRho": 1 + }, + "memimpedancespec": { + "ck_termination": true, + "ck_R_eq": 1e6, + "ck_dyn_E": 1e-12, + + "ca_termination": true, + "ca_R_eq": 1e6, + "ca_dyn_E": 1e-12, + + "rdq_termination": true, + "rdq_R_eq": 1e6, + "rdq_dyn_E": 1e-12, + "wdq_termination": true, + "wdq_R_eq": 1e6, + "wdq_dyn_E": 1e-12, + + "wck_termination": true, + "wck_R_eq": 1e6, + "wck_dyn_E": 1e-12, + "rdqs_termination": true, + "rdqs_R_eq": 1e6, + "rdqs_dyn_E": 1e-12 }, "memoryId": "JEDEC_1Gbx16_BG_LPDDR5-6000", "memoryType": "LPDDR5", @@ -55,7 +125,7 @@ "BL_n_S_32": 2, "pbR2act": 6, "pbR2pbR": 68, - "tCK": 1333 + "tCK": 1333e-12 } } } diff --git a/configs/memspec/JEDEC_1Gbx16_BG_LPDDR5-6400.json b/configs/memspec/JEDEC_1Gbx16_BG_LPDDR5-6400.json index 6f6e7254..439c6f5a 100644 --- a/configs/memspec/JEDEC_1Gbx16_BG_LPDDR5-6400.json +++ b/configs/memspec/JEDEC_1Gbx16_BG_LPDDR5-6400.json @@ -11,7 +11,77 @@ "nbrOfDevices": 1, "nbrOfChannels": 1, "width": 16, - "per2BankOffset": 8 + "per2BankOffset": 8, + "WCKalwaysOn": false, + "maxBurstLength": 16 + }, + "mempowerspec": { + "vdd1": 1.2, + "idd01": 1e-3, + "idd2n1": 1e-3, + "idd3n1": 1e-3, + "idd4r1": 1e-3, + "idd4w1": 1e-3, + "idd51": 1e-3, + "idd5pb1": 1e-3, + "idd61": 1e-3, + "idd6ds1": 1e-3, + "idd2p1": 1e-3, + "idd3p1": 1e-3, + "vdd2h": 1.2, + "idd02h": 1e-3, + "idd2n2h": 1e-3, + "idd3n2h": 1e-3, + "idd4r2h": 1e-3, + "idd4w2h": 1e-3, + "idd52h": 1e-3, + "idd5pb2h": 1e-3, + "idd62h": 1e-3, + "idd6ds2h": 1e-3, + "idd2p2h": 1e-3, + "idd3p2h": 1e-3, + "vdd2l": 1.2, + "idd02l": 1e-3, + "idd2n2l": 1e-3, + "idd3n2l": 1e-3, + "idd4r2l": 1e-3, + "idd4w2l": 1e-3, + "idd52l": 1e-3, + "idd5pb2l": 1e-3, + "idd62l": 1e-3, + "idd6ds2l": 1e-3, + "idd2p2l": 1e-3, + "idd3p2l": 1e-3, + "vddq": 1.2, + "iBeta_vdd1": 0.0, + "iBeta_vdd2h": 0.0, + "iBeta_vdd2l": 0.0 + }, + "bankwisespec": { + "factRho": 1 + }, + "memimpedancespec": { + "ck_termination": true, + "ck_R_eq": 1e6, + "ck_dyn_E": 1e-12, + + "ca_termination": true, + "ca_R_eq": 1e6, + "ca_dyn_E": 1e-12, + + "rdq_termination": true, + "rdq_R_eq": 1e6, + "rdq_dyn_E": 1e-12, + "wdq_termination": true, + "wdq_R_eq": 1e6, + "wdq_dyn_E": 1e-12, + + "wck_termination": true, + "wck_R_eq": 1e6, + "wck_dyn_E": 1e-12, + "rdqs_termination": true, + "rdqs_R_eq": 1e6, + "rdqs_dyn_E": 1e-12 }, "memoryId": "JEDEC_1Gbx16_BG_LPDDR5-6400", "memoryType": "LPDDR5", @@ -27,7 +97,7 @@ "FAW": 16, "RRD": 4, "RL": 17, - "WCK2CK": 0, + "WCK2CK": 2, "WCK2DQO": 1, "RBTP": 4, "RPRE": 0, @@ -55,7 +125,7 @@ "BL_n_S_32": 2, "pbR2act": 6, "pbR2pbR": 72, - "tCK": 1250 + "tCK": 1250e-12 } } } diff --git a/configs/memspec/JEDEC_1Gbx16_BG_LPDDR5X-3733.json b/configs/memspec/JEDEC_1Gbx16_BG_LPDDR5X-3733.json index 00b58e54..384e598d 100644 --- a/configs/memspec/JEDEC_1Gbx16_BG_LPDDR5X-3733.json +++ b/configs/memspec/JEDEC_1Gbx16_BG_LPDDR5X-3733.json @@ -11,7 +11,77 @@ "nbrOfDevices": 1, "nbrOfChannels": 1, "width": 16, - "per2BankOffset": 8 + "per2BankOffset": 8, + "WCKalwaysOn": false, + "maxBurstLength": 16 + }, + "mempowerspec": { + "vdd1": 0.0, + "idd01": 0.0, + "idd2n1": 0.0, + "idd3n1": 0.0, + "idd4r1": 0.0, + "idd4w1": 0.0, + "idd51": 0.0, + "idd5pb1": 0.0, + "idd61": 0.0, + "idd6ds1": 0.0, + "idd2p1": 0.0, + "idd3p1": 0.0, + "vdd2h": 0.0, + "idd02h": 0.0, + "idd2n2h": 0.0, + "idd3n2h": 0.0, + "idd4r2h": 0.0, + "idd4w2h": 0.0, + "idd52h": 0.0, + "idd5pb2h": 0.0, + "idd62h": 0.0, + "idd6ds2h": 0.0, + "idd2p2h": 0.0, + "idd3p2h": 0.0, + "vdd2l": 0.0, + "idd02l": 0.0, + "idd2n2l": 0.0, + "idd3n2l": 0.0, + "idd4r2l": 0.0, + "idd4w2l": 0.0, + "idd52l": 0.0, + "idd5pb2l": 0.0, + "idd62l": 0.0, + "idd6ds2l": 0.0, + "idd2p2l": 0.0, + "idd3p2l": 0.0, + "vddq": 0.0, + "iBeta_vdd1": 0.0, + "iBeta_vdd2h": 0.0, + "iBeta_vdd2l": 0.0 + }, + "bankwisespec": { + "factRho": 1 + }, + "memimpedancespec": { + "ck_termination": true, + "ck_R_eq": 1e6, + "ck_dyn_E": 1e-12, + + "ca_termination": true, + "ca_R_eq": 1e6, + "ca_dyn_E": 1e-12, + + "rdq_termination": true, + "rdq_R_eq": 1e6, + "rdq_dyn_E": 1e-12, + "wdq_termination": true, + "wdq_R_eq": 1e6, + "wdq_dyn_E": 1e-12, + + "wck_termination": true, + "wck_R_eq": 1e6, + "wck_dyn_E": 1e-12, + "rdqs_termination": true, + "rdqs_R_eq": 1e6, + "rdqs_dyn_E": 1e-12 }, "memoryId": "JEDEC_1Gbx16_BG_LPDDR5X-3733", "memoryType": "LPDDR5", @@ -57,7 +127,7 @@ "BL_n_S_32": 2, "pbR2act": 4, "pbR2pbR": 42, - "tCK": 2141 + "tCK": 2141e-12 } } } diff --git a/configs/memspec/JEDEC_1Gbx16_BG_LPDDR5X-4267.json b/configs/memspec/JEDEC_1Gbx16_BG_LPDDR5X-4267.json index 608d2a52..0cb238e6 100644 --- a/configs/memspec/JEDEC_1Gbx16_BG_LPDDR5X-4267.json +++ b/configs/memspec/JEDEC_1Gbx16_BG_LPDDR5X-4267.json @@ -11,7 +11,77 @@ "nbrOfDevices": 1, "nbrOfChannels": 1, "width": 16, - "per2BankOffset": 8 + "per2BankOffset": 8, + "WCKalwaysOn": false, + "maxBurstLength": 16 + }, + "mempowerspec": { + "vdd1": 0.0, + "idd01": 0.0, + "idd2n1": 0.0, + "idd3n1": 0.0, + "idd4r1": 0.0, + "idd4w1": 0.0, + "idd51": 0.0, + "idd5pb1": 0.0, + "idd61": 0.0, + "idd6ds1": 0.0, + "idd2p1": 0.0, + "idd3p1": 0.0, + "vdd2h": 0.0, + "idd02h": 0.0, + "idd2n2h": 0.0, + "idd3n2h": 0.0, + "idd4r2h": 0.0, + "idd4w2h": 0.0, + "idd52h": 0.0, + "idd5pb2h": 0.0, + "idd62h": 0.0, + "idd6ds2h": 0.0, + "idd2p2h": 0.0, + "idd3p2h": 0.0, + "vdd2l": 0.0, + "idd02l": 0.0, + "idd2n2l": 0.0, + "idd3n2l": 0.0, + "idd4r2l": 0.0, + "idd4w2l": 0.0, + "idd52l": 0.0, + "idd5pb2l": 0.0, + "idd62l": 0.0, + "idd6ds2l": 0.0, + "idd2p2l": 0.0, + "idd3p2l": 0.0, + "vddq": 0.0, + "iBeta_vdd1": 0.0, + "iBeta_vdd2h": 0.0, + "iBeta_vdd2l": 0.0 + }, + "bankwisespec": { + "factRho": 1 + }, + "memimpedancespec": { + "ck_termination": true, + "ck_R_eq": 1e6, + "ck_dyn_E": 1e-12, + + "ca_termination": true, + "ca_R_eq": 1e6, + "ca_dyn_E": 1e-12, + + "rdq_termination": true, + "rdq_R_eq": 1e6, + "rdq_dyn_E": 1e-12, + "wdq_termination": true, + "wdq_R_eq": 1e6, + "wdq_dyn_E": 1e-12, + + "wck_termination": true, + "wck_R_eq": 1e6, + "wck_dyn_E": 1e-12, + "rdqs_termination": true, + "rdqs_R_eq": 1e6, + "rdqs_dyn_E": 1e-12 }, "memoryId": "JEDEC_1Gbx16_BG_LPDDR5X-4267", "memoryType": "LPDDR5", @@ -57,7 +127,7 @@ "BL_n_S_32": 2, "pbR2act": 4, "pbR2pbR": 48, - "tCK": 1876 + "tCK": 1876e-12 } } } diff --git a/configs/memspec/JEDEC_1Gbx16_BG_LPDDR5X-4800.json b/configs/memspec/JEDEC_1Gbx16_BG_LPDDR5X-4800.json index 3c6924ae..d3b7aa25 100644 --- a/configs/memspec/JEDEC_1Gbx16_BG_LPDDR5X-4800.json +++ b/configs/memspec/JEDEC_1Gbx16_BG_LPDDR5X-4800.json @@ -11,7 +11,77 @@ "nbrOfDevices": 1, "nbrOfChannels": 1, "width": 16, - "per2BankOffset": 8 + "per2BankOffset": 8, + "WCKalwaysOn": false, + "maxBurstLength": 16 + }, + "mempowerspec": { + "vdd1": 0.0, + "idd01": 0.0, + "idd2n1": 0.0, + "idd3n1": 0.0, + "idd4r1": 0.0, + "idd4w1": 0.0, + "idd51": 0.0, + "idd5pb1": 0.0, + "idd61": 0.0, + "idd6ds1": 0.0, + "idd2p1": 0.0, + "idd3p1": 0.0, + "vdd2h": 0.0, + "idd02h": 0.0, + "idd2n2h": 0.0, + "idd3n2h": 0.0, + "idd4r2h": 0.0, + "idd4w2h": 0.0, + "idd52h": 0.0, + "idd5pb2h": 0.0, + "idd62h": 0.0, + "idd6ds2h": 0.0, + "idd2p2h": 0.0, + "idd3p2h": 0.0, + "vdd2l": 0.0, + "idd02l": 0.0, + "idd2n2l": 0.0, + "idd3n2l": 0.0, + "idd4r2l": 0.0, + "idd4w2l": 0.0, + "idd52l": 0.0, + "idd5pb2l": 0.0, + "idd62l": 0.0, + "idd6ds2l": 0.0, + "idd2p2l": 0.0, + "idd3p2l": 0.0, + "vddq": 0.0, + "iBeta_vdd1": 0.0, + "iBeta_vdd2h": 0.0, + "iBeta_vdd2l": 0.0 + }, + "bankwisespec": { + "factRho": 1 + }, + "memimpedancespec": { + "ck_termination": true, + "ck_R_eq": 1e6, + "ck_dyn_E": 1e-12, + + "ca_termination": true, + "ca_R_eq": 1e6, + "ca_dyn_E": 1e-12, + + "rdq_termination": true, + "rdq_R_eq": 1e6, + "rdq_dyn_E": 1e-12, + "wdq_termination": true, + "wdq_R_eq": 1e6, + "wdq_dyn_E": 1e-12, + + "wck_termination": true, + "wck_R_eq": 1e6, + "wck_dyn_E": 1e-12, + "rdqs_termination": true, + "rdqs_R_eq": 1e6, + "rdqs_dyn_E": 1e-12 }, "memoryId": "JEDEC_1Gbx16_BG_LPDDR5X-4800", "memoryType": "LPDDR5", @@ -57,7 +127,7 @@ "BL_n_S_32": 2, "pbR2act": 5, "pbR2pbR": 54, - "tCK": 1667 + "tCK": 1667e-12 } } } diff --git a/configs/memspec/JEDEC_1Gbx16_BG_LPDDR5X-5500.json b/configs/memspec/JEDEC_1Gbx16_BG_LPDDR5X-5500.json index bf1829d2..0dc3d9f9 100644 --- a/configs/memspec/JEDEC_1Gbx16_BG_LPDDR5X-5500.json +++ b/configs/memspec/JEDEC_1Gbx16_BG_LPDDR5X-5500.json @@ -11,7 +11,77 @@ "nbrOfDevices": 1, "nbrOfChannels": 1, "width": 16, - "per2BankOffset": 8 + "per2BankOffset": 8, + "WCKalwaysOn": false, + "maxBurstLength": 16 + }, + "mempowerspec": { + "vdd1": 0.0, + "idd01": 0.0, + "idd2n1": 0.0, + "idd3n1": 0.0, + "idd4r1": 0.0, + "idd4w1": 0.0, + "idd51": 0.0, + "idd5pb1": 0.0, + "idd61": 0.0, + "idd6ds1": 0.0, + "idd2p1": 0.0, + "idd3p1": 0.0, + "vdd2h": 0.0, + "idd02h": 0.0, + "idd2n2h": 0.0, + "idd3n2h": 0.0, + "idd4r2h": 0.0, + "idd4w2h": 0.0, + "idd52h": 0.0, + "idd5pb2h": 0.0, + "idd62h": 0.0, + "idd6ds2h": 0.0, + "idd2p2h": 0.0, + "idd3p2h": 0.0, + "vdd2l": 0.0, + "idd02l": 0.0, + "idd2n2l": 0.0, + "idd3n2l": 0.0, + "idd4r2l": 0.0, + "idd4w2l": 0.0, + "idd52l": 0.0, + "idd5pb2l": 0.0, + "idd62l": 0.0, + "idd6ds2l": 0.0, + "idd2p2l": 0.0, + "idd3p2l": 0.0, + "vddq": 0.0, + "iBeta_vdd1": 0.0, + "iBeta_vdd2h": 0.0, + "iBeta_vdd2l": 0.0 + }, + "bankwisespec": { + "factRho": 1 + }, + "memimpedancespec": { + "ck_termination": true, + "ck_R_eq": 1e6, + "ck_dyn_E": 1e-12, + + "ca_termination": true, + "ca_R_eq": 1e6, + "ca_dyn_E": 1e-12, + + "rdq_termination": true, + "rdq_R_eq": 1e6, + "rdq_dyn_E": 1e-12, + "wdq_termination": true, + "wdq_R_eq": 1e6, + "wdq_dyn_E": 1e-12, + + "wck_termination": true, + "wck_R_eq": 1e6, + "wck_dyn_E": 1e-12, + "rdqs_termination": true, + "rdqs_R_eq": 1e6, + "rdqs_dyn_E": 1e-12 }, "memoryId": "JEDEC_1Gbx16_BG_LPDDR5X-5500", "memoryType": "LPDDR5", @@ -57,7 +127,7 @@ "BL_n_S_32": 2, "pbR2act": 6, "pbR2pbR": 62, - "tCK": 1453 + "tCK": 1453e-12 } } } diff --git a/configs/memspec/JEDEC_1Gbx16_BG_LPDDR5X-6000.json b/configs/memspec/JEDEC_1Gbx16_BG_LPDDR5X-6000.json index 269a7682..73a86828 100644 --- a/configs/memspec/JEDEC_1Gbx16_BG_LPDDR5X-6000.json +++ b/configs/memspec/JEDEC_1Gbx16_BG_LPDDR5X-6000.json @@ -11,7 +11,77 @@ "nbrOfDevices": 1, "nbrOfChannels": 1, "width": 16, - "per2BankOffset": 8 + "per2BankOffset": 8, + "WCKalwaysOn": false, + "maxBurstLength": 16 + }, + "mempowerspec": { + "vdd1": 0.0, + "idd01": 0.0, + "idd2n1": 0.0, + "idd3n1": 0.0, + "idd4r1": 0.0, + "idd4w1": 0.0, + "idd51": 0.0, + "idd5pb1": 0.0, + "idd61": 0.0, + "idd6ds1": 0.0, + "idd2p1": 0.0, + "idd3p1": 0.0, + "vdd2h": 0.0, + "idd02h": 0.0, + "idd2n2h": 0.0, + "idd3n2h": 0.0, + "idd4r2h": 0.0, + "idd4w2h": 0.0, + "idd52h": 0.0, + "idd5pb2h": 0.0, + "idd62h": 0.0, + "idd6ds2h": 0.0, + "idd2p2h": 0.0, + "idd3p2h": 0.0, + "vdd2l": 0.0, + "idd02l": 0.0, + "idd2n2l": 0.0, + "idd3n2l": 0.0, + "idd4r2l": 0.0, + "idd4w2l": 0.0, + "idd52l": 0.0, + "idd5pb2l": 0.0, + "idd62l": 0.0, + "idd6ds2l": 0.0, + "idd2p2l": 0.0, + "idd3p2l": 0.0, + "vddq": 0.0, + "iBeta_vdd1": 0.0, + "iBeta_vdd2h": 0.0, + "iBeta_vdd2l": 0.0 + }, + "bankwisespec": { + "factRho": 1 + }, + "memimpedancespec": { + "ck_termination": true, + "ck_R_eq": 1e6, + "ck_dyn_E": 1e-12, + + "ca_termination": true, + "ca_R_eq": 1e6, + "ca_dyn_E": 1e-12, + + "rdq_termination": true, + "rdq_R_eq": 1e6, + "rdq_dyn_E": 1e-12, + "wdq_termination": true, + "wdq_R_eq": 1e6, + "wdq_dyn_E": 1e-12, + + "wck_termination": true, + "wck_R_eq": 1e6, + "wck_dyn_E": 1e-12, + "rdqs_termination": true, + "rdqs_R_eq": 1e6, + "rdqs_dyn_E": 1e-12 }, "memoryId": "JEDEC_1Gbx16_BG_LPDDR5X-6000", "memoryType": "LPDDR5", @@ -57,7 +127,7 @@ "BL_n_S_32": 2, "pbR2act": 6, "pbR2pbR": 68, - "tCK": 1333 + "tCK": 1333e-12 } } } diff --git a/configs/memspec/JEDEC_1Gbx16_BG_LPDDR5X-6400.json b/configs/memspec/JEDEC_1Gbx16_BG_LPDDR5X-6400.json index f94a4f60..4093042c 100644 --- a/configs/memspec/JEDEC_1Gbx16_BG_LPDDR5X-6400.json +++ b/configs/memspec/JEDEC_1Gbx16_BG_LPDDR5X-6400.json @@ -11,7 +11,77 @@ "nbrOfDevices": 1, "nbrOfChannels": 1, "width": 16, - "per2BankOffset": 8 + "per2BankOffset": 8, + "WCKalwaysOn": false, + "maxBurstLength": 16 + }, + "mempowerspec": { + "vdd1": 0.0, + "idd01": 0.0, + "idd2n1": 0.0, + "idd3n1": 0.0, + "idd4r1": 0.0, + "idd4w1": 0.0, + "idd51": 0.0, + "idd5pb1": 0.0, + "idd61": 0.0, + "idd6ds1": 0.0, + "idd2p1": 0.0, + "idd3p1": 0.0, + "vdd2h": 0.0, + "idd02h": 0.0, + "idd2n2h": 0.0, + "idd3n2h": 0.0, + "idd4r2h": 0.0, + "idd4w2h": 0.0, + "idd52h": 0.0, + "idd5pb2h": 0.0, + "idd62h": 0.0, + "idd6ds2h": 0.0, + "idd2p2h": 0.0, + "idd3p2h": 0.0, + "vdd2l": 0.0, + "idd02l": 0.0, + "idd2n2l": 0.0, + "idd3n2l": 0.0, + "idd4r2l": 0.0, + "idd4w2l": 0.0, + "idd52l": 0.0, + "idd5pb2l": 0.0, + "idd62l": 0.0, + "idd6ds2l": 0.0, + "idd2p2l": 0.0, + "idd3p2l": 0.0, + "vddq": 0.0, + "iBeta_vdd1": 0.0, + "iBeta_vdd2h": 0.0, + "iBeta_vdd2l": 0.0 + }, + "bankwisespec": { + "factRho": 1 + }, + "memimpedancespec": { + "ck_termination": true, + "ck_R_eq": 1e6, + "ck_dyn_E": 1e-12, + + "ca_termination": true, + "ca_R_eq": 1e6, + "ca_dyn_E": 1e-12, + + "rdq_termination": true, + "rdq_R_eq": 1e6, + "rdq_dyn_E": 1e-12, + "wdq_termination": true, + "wdq_R_eq": 1e6, + "wdq_dyn_E": 1e-12, + + "wck_termination": true, + "wck_R_eq": 1e6, + "wck_dyn_E": 1e-12, + "rdqs_termination": true, + "rdqs_R_eq": 1e6, + "rdqs_dyn_E": 1e-12 }, "memoryId": "JEDEC_1Gbx16_BG_LPDDR5X-6400", "memoryType": "LPDDR5", @@ -57,7 +127,7 @@ "BL_n_S_32": 2, "pbR2act": 6, "pbR2pbR": 72, - "tCK": 1250 + "tCK": 1250e-12 } } } diff --git a/configs/memspec/JEDEC_1Gbx16_BG_LPDDR5X-7500.json b/configs/memspec/JEDEC_1Gbx16_BG_LPDDR5X-7500.json index 575ea6e4..5a80685a 100644 --- a/configs/memspec/JEDEC_1Gbx16_BG_LPDDR5X-7500.json +++ b/configs/memspec/JEDEC_1Gbx16_BG_LPDDR5X-7500.json @@ -11,7 +11,77 @@ "nbrOfDevices": 1, "nbrOfChannels": 1, "width": 16, - "per2BankOffset": 8 + "per2BankOffset": 8, + "WCKalwaysOn": false, + "maxBurstLength": 16 + }, + "mempowerspec": { + "vdd1": 0.0, + "idd01": 0.0, + "idd2n1": 0.0, + "idd3n1": 0.0, + "idd4r1": 0.0, + "idd4w1": 0.0, + "idd51": 0.0, + "idd5pb1": 0.0, + "idd61": 0.0, + "idd6ds1": 0.0, + "idd2p1": 0.0, + "idd3p1": 0.0, + "vdd2h": 0.0, + "idd02h": 0.0, + "idd2n2h": 0.0, + "idd3n2h": 0.0, + "idd4r2h": 0.0, + "idd4w2h": 0.0, + "idd52h": 0.0, + "idd5pb2h": 0.0, + "idd62h": 0.0, + "idd6ds2h": 0.0, + "idd2p2h": 0.0, + "idd3p2h": 0.0, + "vdd2l": 0.0, + "idd02l": 0.0, + "idd2n2l": 0.0, + "idd3n2l": 0.0, + "idd4r2l": 0.0, + "idd4w2l": 0.0, + "idd52l": 0.0, + "idd5pb2l": 0.0, + "idd62l": 0.0, + "idd6ds2l": 0.0, + "idd2p2l": 0.0, + "idd3p2l": 0.0, + "vddq": 0.0, + "iBeta_vdd1": 0.0, + "iBeta_vdd2h": 0.0, + "iBeta_vdd2l": 0.0 + }, + "bankwisespec": { + "factRho": 1 + }, + "memimpedancespec": { + "ck_termination": true, + "ck_R_eq": 1e6, + "ck_dyn_E": 1e-12, + + "ca_termination": true, + "ca_R_eq": 1e6, + "ca_dyn_E": 1e-12, + + "rdq_termination": true, + "rdq_R_eq": 1e6, + "rdq_dyn_E": 1e-12, + "wdq_termination": true, + "wdq_R_eq": 1e6, + "wdq_dyn_E": 1e-12, + + "wck_termination": true, + "wck_R_eq": 1e6, + "wck_dyn_E": 1e-12, + "rdqs_termination": true, + "rdqs_R_eq": 1e6, + "rdqs_dyn_E": 1e-12 }, "memoryId": "JEDEC_1Gbx16_BG_LPDDR5X-7500", "memoryType": "LPDDR5", @@ -57,7 +127,7 @@ "BL_n_S_32": 2, "pbR2act": 8, "pbR2pbR": 85, - "tCK": 1066 + "tCK": 1066e-12 } } } diff --git a/configs/memspec/JEDEC_1Gbx16_BG_LPDDR5X-8533.json b/configs/memspec/JEDEC_1Gbx16_BG_LPDDR5X-8533.json index db047c99..a4ada374 100644 --- a/configs/memspec/JEDEC_1Gbx16_BG_LPDDR5X-8533.json +++ b/configs/memspec/JEDEC_1Gbx16_BG_LPDDR5X-8533.json @@ -11,7 +11,77 @@ "nbrOfDevices": 1, "nbrOfChannels": 1, "width": 16, - "per2BankOffset": 8 + "per2BankOffset": 8, + "WCKalwaysOn": false, + "maxBurstLength": 16 + }, + "mempowerspec": { + "vdd1": 0.0, + "idd01": 0.0, + "idd2n1": 0.0, + "idd3n1": 0.0, + "idd4r1": 0.0, + "idd4w1": 0.0, + "idd51": 0.0, + "idd5pb1": 0.0, + "idd61": 0.0, + "idd6ds1": 0.0, + "idd2p1": 0.0, + "idd3p1": 0.0, + "vdd2h": 0.0, + "idd02h": 0.0, + "idd2n2h": 0.0, + "idd3n2h": 0.0, + "idd4r2h": 0.0, + "idd4w2h": 0.0, + "idd52h": 0.0, + "idd5pb2h": 0.0, + "idd62h": 0.0, + "idd6ds2h": 0.0, + "idd2p2h": 0.0, + "idd3p2h": 0.0, + "vdd2l": 0.0, + "idd02l": 0.0, + "idd2n2l": 0.0, + "idd3n2l": 0.0, + "idd4r2l": 0.0, + "idd4w2l": 0.0, + "idd52l": 0.0, + "idd5pb2l": 0.0, + "idd62l": 0.0, + "idd6ds2l": 0.0, + "idd2p2l": 0.0, + "idd3p2l": 0.0, + "vddq": 0.0, + "iBeta_vdd1": 0.0, + "iBeta_vdd2h": 0.0, + "iBeta_vdd2l": 0.0 + }, + "bankwisespec": { + "factRho": 1 + }, + "memimpedancespec": { + "ck_termination": true, + "ck_R_eq": 1e6, + "ck_dyn_E": 1e-12, + + "ca_termination": true, + "ca_R_eq": 1e6, + "ca_dyn_E": 1e-12, + + "rdq_termination": true, + "rdq_R_eq": 1e6, + "rdq_dyn_E": 1e-12, + "wdq_termination": true, + "wdq_R_eq": 1e6, + "wdq_dyn_E": 1e-12, + + "wck_termination": true, + "wck_R_eq": 1e6, + "wck_dyn_E": 1e-12, + "rdqs_termination": true, + "rdqs_R_eq": 1e6, + "rdqs_dyn_E": 1e-12 }, "memoryId": "JEDEC_1Gbx16_BG_LPDDR5X-8533", "memoryType": "LPDDR5", @@ -57,7 +127,7 @@ "BL_n_S_32": 2, "pbR2act": 8, "pbR2pbR": 96, - "tCK": 937 + "tCK": 937e-12 } } } diff --git a/configs/memspec/JEDEC_1Gbx16_LPDDR4-0533.json b/configs/memspec/JEDEC_1Gbx16_LPDDR4-0533.json index d7de396b..25a1e6a5 100644 --- a/configs/memspec/JEDEC_1Gbx16_LPDDR4-0533.json +++ b/configs/memspec/JEDEC_1Gbx16_LPDDR4-0533.json @@ -9,7 +9,9 @@ "nbrOfRows": 131072, "width": 16, "nbrOfDevices": 1, - "nbrOfChannels": 1 + "nbrOfChannels": 1, + "nbrOfBankGroups": 1, + "maxBurstLength": 16 }, "memoryId": "JEDEC_1Gbx16_LPDDR4-0533", "memoryType": "LPDDR4", @@ -26,15 +28,15 @@ "PPD": 4, "RCD": 5, "REFI": 1041, - "REFIPB": 130, - "RFCAB": 102, - "RFCPB": 51, + "REFIpb": 130, + "RFCab": 102, + "RFCpb": 51, "RL": 6, "RAS": 12, - "RPAB": 6, - "RPPB": 5, - "RCAB": 18, - "RCPB": 17, + "RPab": 6, + "RPpb": 5, + "RCab": 18, + "RCpb": 17, "RPST": 0, "RRD": 4, "RTP": 8, @@ -46,7 +48,63 @@ "XP": 5, "XSR": 104, "RTRS": 1, - "tCK": 3759 + "tCK": 3759e-12 + }, + "mempowerspec": { + "vdd1": 0.0, + "idd01": 0.0, + "idd2n1": 0.0, + "idd3n1": 0.0, + "idd4r1": 0.0, + "idd4w1": 0.0, + "idd51": 0.0, + "idd5pb1": 0.0, + "idd61": 0.0, + "idd2p1": 0.0, + "idd3p1": 0.0, + "vdd2": 0.0, + "idd02": 0.0, + "idd2n2": 0.0, + "idd3n2": 0.0, + "idd4r2": 0.0, + "idd4w2": 0.0, + "idd52": 0.0, + "idd5pb2": 0.0, + "idd62": 0.0, + "idd2p2": 0.0, + "idd3p2": 0.0, + "vddq": 0.0, + "iBeta_vdd1": 0.0, + "iBeta_vdd2": 0.0 + }, + "memimpedancespec": { + "ck_termination": true, + "ck_R_eq": 1e6, + "ck_dyn_E": 1e-12, + + "ca_termination": true, + "ca_R_eq": 1e6, + "ca_dyn_E": 1e-12, + + "rdq_termination": true, + "rdq_R_eq": 1e6, + "rdq_dyn_E": 1e-12, + "wdq_termination": true, + "wdq_R_eq": 1e6, + "wdq_dyn_E": 1e-12, + + "wdqs_termination": true, + "wdqs_R_eq": 1e6, + "wdqs_dyn_E": 1e-12, + "rdqs_termination": true, + "rdqs_R_eq": 1e6, + "rdqs_dyn_E": 1e-12 + }, + "bankwisespec": { + "factRho": 1, + "factSigma": 1, + "pasrMode": 0, + "hasPASR": false } } } diff --git a/configs/memspec/JEDEC_1Gbx16_LPDDR4-1066.json b/configs/memspec/JEDEC_1Gbx16_LPDDR4-1066.json index 704a2f20..af2cc18c 100644 --- a/configs/memspec/JEDEC_1Gbx16_LPDDR4-1066.json +++ b/configs/memspec/JEDEC_1Gbx16_LPDDR4-1066.json @@ -9,7 +9,9 @@ "nbrOfRows": 131072, "width": 16, "nbrOfDevices": 1, - "nbrOfChannels": 1 + "nbrOfChannels": 1, + "nbrOfBankGroups": 1, + "maxBurstLength": 16 }, "memoryId": "JEDEC_1Gbx16_LPDDR4-1066", "memoryType": "LPDDR4", @@ -26,15 +28,15 @@ "PPD": 4, "RCD": 10, "REFI": 2082, - "REFIPB": 260, - "RFCAB": 203, - "RFCPB": 102, + "REFIpb": 260, + "RFCab": 203, + "RFCpb": 102, "RL": 10, "RAS": 23, - "RPAB": 12, - "RPPB": 10, - "RCAB": 35, - "RCPB": 33, + "RPab": 12, + "RPpb": 10, + "RCab": 35, + "RCpb": 33, "RPST": 0, "RRD": 6, "RTP": 8, @@ -46,7 +48,63 @@ "XP": 5, "XSR": 207, "RTRS": 1, - "tCK": 1876 + "tCK": 1876e-12 + }, + "mempowerspec": { + "vdd1": 0.0, + "idd01": 0.0, + "idd2n1": 0.0, + "idd3n1": 0.0, + "idd4r1": 0.0, + "idd4w1": 0.0, + "idd51": 0.0, + "idd5pb1": 0.0, + "idd61": 0.0, + "idd2p1": 0.0, + "idd3p1": 0.0, + "vdd2": 0.0, + "idd02": 0.0, + "idd2n2": 0.0, + "idd3n2": 0.0, + "idd4r2": 0.0, + "idd4w2": 0.0, + "idd52": 0.0, + "idd5pb2": 0.0, + "idd62": 0.0, + "idd2p2": 0.0, + "idd3p2": 0.0, + "vddq": 0.0, + "iBeta_vdd1": 0.0, + "iBeta_vdd2": 0.0 + }, + "memimpedancespec": { + "ck_termination": true, + "ck_R_eq": 1e6, + "ck_dyn_E": 1e-12, + + "ca_termination": true, + "ca_R_eq": 1e6, + "ca_dyn_E": 1e-12, + + "rdq_termination": true, + "rdq_R_eq": 1e6, + "rdq_dyn_E": 1e-12, + "wdq_termination": true, + "wdq_R_eq": 1e6, + "wdq_dyn_E": 1e-12, + + "wdqs_termination": true, + "wdqs_R_eq": 1e6, + "wdqs_dyn_E": 1e-12, + "rdqs_termination": true, + "rdqs_R_eq": 1e6, + "rdqs_dyn_E": 1e-12 + }, + "bankwisespec": { + "factRho": 1, + "factSigma": 1, + "pasrMode": 0, + "hasPASR": false } } } diff --git a/configs/memspec/JEDEC_1Gbx16_LPDDR4-1600.json b/configs/memspec/JEDEC_1Gbx16_LPDDR4-1600.json index bd5bf24d..94518d60 100644 --- a/configs/memspec/JEDEC_1Gbx16_LPDDR4-1600.json +++ b/configs/memspec/JEDEC_1Gbx16_LPDDR4-1600.json @@ -9,7 +9,9 @@ "nbrOfRows": 131072, "width": 16, "nbrOfDevices": 1, - "nbrOfChannels": 1 + "nbrOfChannels": 1, + "nbrOfBankGroups": 1, + "maxBurstLength": 16 }, "memoryId": "JEDEC_1Gbx16_LPDDR4-1600", "memoryType": "LPDDR4", @@ -26,15 +28,15 @@ "PPD": 4, "RCD": 15, "REFI": 3123, - "REFIPB": 390, - "RFCAB": 304, - "RFCPB": 152, + "REFIpb": 390, + "RFCab": 304, + "RFCpb": 152, "RL": 14, "RAS": 34, - "RPAB": 17, - "RPPB": 15, - "RCAB": 51, - "RCPB": 49, + "RPab": 17, + "RPpb": 15, + "RCab": 51, + "RCpb": 49, "RPST": 0, "RRD": 8, "RTP": 8, @@ -46,7 +48,63 @@ "XP": 6, "XSR": 310, "RTRS": 1, - "tCK": 1250 + "tCK": 1250e-12 + }, + "mempowerspec": { + "vdd1": 0.0, + "idd01": 0.0, + "idd2n1": 0.0, + "idd3n1": 0.0, + "idd4r1": 0.0, + "idd4w1": 0.0, + "idd51": 0.0, + "idd5pb1": 0.0, + "idd61": 0.0, + "idd2p1": 0.0, + "idd3p1": 0.0, + "vdd2": 0.0, + "idd02": 0.0, + "idd2n2": 0.0, + "idd3n2": 0.0, + "idd4r2": 0.0, + "idd4w2": 0.0, + "idd52": 0.0, + "idd5pb2": 0.0, + "idd62": 0.0, + "idd2p2": 0.0, + "idd3p2": 0.0, + "vddq": 0.0, + "iBeta_vdd1": 0.0, + "iBeta_vdd2": 0.0 + }, + "memimpedancespec": { + "ck_termination": true, + "ck_R_eq": 1e6, + "ck_dyn_E": 1e-12, + + "ca_termination": true, + "ca_R_eq": 1e6, + "ca_dyn_E": 1e-12, + + "rdq_termination": true, + "rdq_R_eq": 1e6, + "rdq_dyn_E": 1e-12, + "wdq_termination": true, + "wdq_R_eq": 1e6, + "wdq_dyn_E": 1e-12, + + "wdqs_termination": true, + "wdqs_R_eq": 1e6, + "wdqs_dyn_E": 1e-12, + "rdqs_termination": true, + "rdqs_R_eq": 1e6, + "rdqs_dyn_E": 1e-12 + }, + "bankwisespec": { + "factRho": 1, + "factSigma": 1, + "pasrMode": 0, + "hasPASR": false } } } diff --git a/configs/memspec/JEDEC_1Gbx16_LPDDR4-2133.json b/configs/memspec/JEDEC_1Gbx16_LPDDR4-2133.json index d9755c6e..ef6b70e4 100644 --- a/configs/memspec/JEDEC_1Gbx16_LPDDR4-2133.json +++ b/configs/memspec/JEDEC_1Gbx16_LPDDR4-2133.json @@ -9,7 +9,9 @@ "nbrOfRows": 131072, "width": 16, "nbrOfDevices": 1, - "nbrOfChannels": 1 + "nbrOfChannels": 1, + "nbrOfBankGroups": 1, + "maxBurstLength": 16 }, "memoryId": "JEDEC_1Gbx16_LPDDR4-2133", "memoryType": "LPDDR4", @@ -26,15 +28,15 @@ "PPD": 4, "RCD": 20, "REFI": 4166, - "REFIPB": 520, - "RFCAB": 406, - "RFCPB": 203, + "REFIpb": 520, + "RFCab": 406, + "RFCpb": 203, "RL": 20, "RAS": 45, - "RPAB": 23, - "RPPB": 20, - "RCAB": 68, - "RCPB": 65, + "RPab": 23, + "RPpb": 20, + "RCab": 68, + "RCpb": 65, "RPST": 0, "RRD": 11, "RTP": 9, @@ -46,7 +48,63 @@ "XP": 9, "XSR": 414, "RTRS": 1, - "tCK": 938 + "tCK": 938e-12 + }, + "mempowerspec": { + "vdd1": 0.0, + "idd01": 0.0, + "idd2n1": 0.0, + "idd3n1": 0.0, + "idd4r1": 0.0, + "idd4w1": 0.0, + "idd51": 0.0, + "idd5pb1": 0.0, + "idd61": 0.0, + "idd2p1": 0.0, + "idd3p1": 0.0, + "vdd2": 0.0, + "idd02": 0.0, + "idd2n2": 0.0, + "idd3n2": 0.0, + "idd4r2": 0.0, + "idd4w2": 0.0, + "idd52": 0.0, + "idd5pb2": 0.0, + "idd62": 0.0, + "idd2p2": 0.0, + "idd3p2": 0.0, + "vddq": 0.0, + "iBeta_vdd1": 0.0, + "iBeta_vdd2": 0.0 + }, + "memimpedancespec": { + "ck_termination": true, + "ck_R_eq": 1e6, + "ck_dyn_E": 1e-12, + + "ca_termination": true, + "ca_R_eq": 1e6, + "ca_dyn_E": 1e-12, + + "rdq_termination": true, + "rdq_R_eq": 1e6, + "rdq_dyn_E": 1e-12, + "wdq_termination": true, + "wdq_R_eq": 1e6, + "wdq_dyn_E": 1e-12, + + "wdqs_termination": true, + "wdqs_R_eq": 1e6, + "wdqs_dyn_E": 1e-12, + "rdqs_termination": true, + "rdqs_R_eq": 1e6, + "rdqs_dyn_E": 1e-12 + }, + "bankwisespec": { + "factRho": 1, + "factSigma": 1, + "pasrMode": 0, + "hasPASR": false } } } diff --git a/configs/memspec/JEDEC_1Gbx16_LPDDR4-2666.json b/configs/memspec/JEDEC_1Gbx16_LPDDR4-2666.json index ea1e6890..111d8d3c 100644 --- a/configs/memspec/JEDEC_1Gbx16_LPDDR4-2666.json +++ b/configs/memspec/JEDEC_1Gbx16_LPDDR4-2666.json @@ -9,7 +9,9 @@ "nbrOfRows": 131072, "width": 16, "nbrOfDevices": 1, - "nbrOfChannels": 1 + "nbrOfChannels": 1, + "nbrOfBankGroups": 1, + "maxBurstLength": 16 }, "memoryId": "JEDEC_1Gbx16_LPDDR4-2666", "memoryType": "LPDDR4", @@ -26,15 +28,15 @@ "PPD": 4, "RCD": 24, "REFI": 5205, - "REFIPB": 650, - "RFCAB": 507, - "RFCPB": 254, + "REFIpb": 650, + "RFCab": 507, + "RFCpb": 254, "RL": 24, "RAS": 56, - "RPAB": 28, - "RPPB": 24, - "RCAB": 84, - "RCPB": 80, + "RPab": 28, + "RPpb": 24, + "RCab": 84, + "RCpb": 80, "RPST": 0, "RRD": 14, "RTP": 10, @@ -46,7 +48,63 @@ "XP": 10, "XSR": 517, "RTRS": 1, - "tCK": 750 + "tCK": 750e-12 + }, + "mempowerspec": { + "vdd1": 0.0, + "idd01": 0.0, + "idd2n1": 0.0, + "idd3n1": 0.0, + "idd4r1": 0.0, + "idd4w1": 0.0, + "idd51": 0.0, + "idd5pb1": 0.0, + "idd61": 0.0, + "idd2p1": 0.0, + "idd3p1": 0.0, + "vdd2": 0.0, + "idd02": 0.0, + "idd2n2": 0.0, + "idd3n2": 0.0, + "idd4r2": 0.0, + "idd4w2": 0.0, + "idd52": 0.0, + "idd5pb2": 0.0, + "idd62": 0.0, + "idd2p2": 0.0, + "idd3p2": 0.0, + "vddq": 0.0, + "iBeta_vdd1": 0.0, + "iBeta_vdd2": 0.0 + }, + "memimpedancespec": { + "ck_termination": true, + "ck_R_eq": 1e6, + "ck_dyn_E": 1e-12, + + "ca_termination": true, + "ca_R_eq": 1e6, + "ca_dyn_E": 1e-12, + + "rdq_termination": true, + "rdq_R_eq": 1e6, + "rdq_dyn_E": 1e-12, + "wdq_termination": true, + "wdq_R_eq": 1e6, + "wdq_dyn_E": 1e-12, + + "wdqs_termination": true, + "wdqs_R_eq": 1e6, + "wdqs_dyn_E": 1e-12, + "rdqs_termination": true, + "rdqs_R_eq": 1e6, + "rdqs_dyn_E": 1e-12 + }, + "bankwisespec": { + "factRho": 1, + "factSigma": 1, + "pasrMode": 0, + "hasPASR": false } } } diff --git a/configs/memspec/JEDEC_1Gbx16_LPDDR4-3200.json b/configs/memspec/JEDEC_1Gbx16_LPDDR4-3200.json index 4ad59d9e..a4795cbb 100644 --- a/configs/memspec/JEDEC_1Gbx16_LPDDR4-3200.json +++ b/configs/memspec/JEDEC_1Gbx16_LPDDR4-3200.json @@ -9,7 +9,9 @@ "nbrOfRows": 131072, "width": 16, "nbrOfDevices": 1, - "nbrOfChannels": 1 + "nbrOfChannels": 1, + "nbrOfBankGroups": 1, + "maxBurstLength": 16 }, "memoryId": "JEDEC_1Gbx16_LPDDR4-3200", "memoryType": "LPDDR4", @@ -26,15 +28,15 @@ "PPD": 4, "RCD": 29, "REFI": 6246, - "REFIPB": 780, - "RFCAB": 608, - "RFCPB": 304, + "REFIpb": 780, + "RFCab": 608, + "RFCpb": 304, "RL": 28, "RAS": 68, - "RPAB": 34, - "RPPB": 29, - "RCAB": 102, - "RCPB": 97, + "RPab": 34, + "RPpb": 29, + "RCab": 102, + "RCpb": 97, "RPST": 0, "RRD": 16, "RTP": 12, @@ -46,7 +48,63 @@ "XP": 12, "XSR": 460, "RTRS": 1, - "tCK": 625 + "tCK": 625e-12 + }, + "mempowerspec": { + "vdd1": 0.0, + "idd01": 0.0, + "idd2n1": 0.0, + "idd3n1": 0.0, + "idd4r1": 0.0, + "idd4w1": 0.0, + "idd51": 0.0, + "idd5pb1": 0.0, + "idd61": 0.0, + "idd2p1": 0.0, + "idd3p1": 0.0, + "vdd2": 0.0, + "idd02": 0.0, + "idd2n2": 0.0, + "idd3n2": 0.0, + "idd4r2": 0.0, + "idd4w2": 0.0, + "idd52": 0.0, + "idd5pb2": 0.0, + "idd62": 0.0, + "idd2p2": 0.0, + "idd3p2": 0.0, + "vddq": 0.0, + "iBeta_vdd1": 0.0, + "iBeta_vdd2": 0.0 + }, + "memimpedancespec": { + "ck_termination": true, + "ck_R_eq": 1e6, + "ck_dyn_E": 1e-12, + + "ca_termination": true, + "ca_R_eq": 1e6, + "ca_dyn_E": 1e-12, + + "rdq_termination": true, + "rdq_R_eq": 1e6, + "rdq_dyn_E": 1e-12, + "wdq_termination": true, + "wdq_R_eq": 1e6, + "wdq_dyn_E": 1e-12, + + "wdqs_termination": true, + "wdqs_R_eq": 1e6, + "wdqs_dyn_E": 1e-12, + "rdqs_termination": true, + "rdqs_R_eq": 1e6, + "rdqs_dyn_E": 1e-12 + }, + "bankwisespec": { + "factRho": 1, + "factSigma": 1, + "pasrMode": 0, + "hasPASR": false } } } diff --git a/configs/memspec/JEDEC_1Gbx16_LPDDR4-3733.json b/configs/memspec/JEDEC_1Gbx16_LPDDR4-3733.json index db5bd5e7..85310cf7 100644 --- a/configs/memspec/JEDEC_1Gbx16_LPDDR4-3733.json +++ b/configs/memspec/JEDEC_1Gbx16_LPDDR4-3733.json @@ -9,7 +9,9 @@ "nbrOfRows": 131072, "width": 16, "nbrOfDevices": 1, - "nbrOfChannels": 1 + "nbrOfChannels": 1, + "nbrOfBankGroups": 1, + "maxBurstLength": 16 }, "memoryId": "JEDEC_1Gbx16_LPDDR4-3733", "memoryType": "LPDDR4", @@ -26,15 +28,15 @@ "PPD": 4, "RCD": 34, "REFI": 7297, - "REFIPB": 912, - "RFCAB": 711, - "RFCPB": 356, + "REFIpb": 912, + "RFCab": 711, + "RFCpb": 356, "RL": 32, "RAS": 79, - "RPAB": 40, - "RPPB": 34, - "RCAB": 119, - "RCPB": 113, + "RPab": 40, + "RPpb": 34, + "RCab": 119, + "RCpb": 113, "RPST": 0, "RRD": 19, "RTP": 15, @@ -46,7 +48,63 @@ "XP": 15, "XSR": 725, "RTRS": 1, - "tCK": 536 + "tCK": 536e-12 + }, + "mempowerspec": { + "vdd1": 0.0, + "idd01": 0.0, + "idd2n1": 0.0, + "idd3n1": 0.0, + "idd4r1": 0.0, + "idd4w1": 0.0, + "idd51": 0.0, + "idd5pb1": 0.0, + "idd61": 0.0, + "idd2p1": 0.0, + "idd3p1": 0.0, + "vdd2": 0.0, + "idd02": 0.0, + "idd2n2": 0.0, + "idd3n2": 0.0, + "idd4r2": 0.0, + "idd4w2": 0.0, + "idd52": 0.0, + "idd5pb2": 0.0, + "idd62": 0.0, + "idd2p2": 0.0, + "idd3p2": 0.0, + "vddq": 0.0, + "iBeta_vdd1": 0.0, + "iBeta_vdd2": 0.0 + }, + "memimpedancespec": { + "ck_termination": true, + "ck_R_eq": 1e6, + "ck_dyn_E": 1e-12, + + "ca_termination": true, + "ca_R_eq": 1e6, + "ca_dyn_E": 1e-12, + + "rdq_termination": true, + "rdq_R_eq": 1e6, + "rdq_dyn_E": 1e-12, + "wdq_termination": true, + "wdq_R_eq": 1e6, + "wdq_dyn_E": 1e-12, + + "wdqs_termination": true, + "wdqs_R_eq": 1e6, + "wdqs_dyn_E": 1e-12, + "rdqs_termination": true, + "rdqs_R_eq": 1e6, + "rdqs_dyn_E": 1e-12 + }, + "bankwisespec": { + "factRho": 1, + "factSigma": 1, + "pasrMode": 0, + "hasPASR": false } } } diff --git a/configs/memspec/JEDEC_1Gbx16_LPDDR4-4266.json b/configs/memspec/JEDEC_1Gbx16_LPDDR4-4266.json index 4557aadc..1bd71f42 100644 --- a/configs/memspec/JEDEC_1Gbx16_LPDDR4-4266.json +++ b/configs/memspec/JEDEC_1Gbx16_LPDDR4-4266.json @@ -9,7 +9,9 @@ "nbrOfRows": 131072, "width": 16, "nbrOfDevices": 1, - "nbrOfChannels": 1 + "nbrOfChannels": 1, + "nbrOfBankGroups": 1, + "maxBurstLength": 16 }, "memoryId": "JEDEC_1Gbx16_LPDDR4-4266", "memoryType": "LPDDR4", @@ -26,15 +28,15 @@ "PPD": 4, "RCD": 39, "REFI": 8341, - "REFIPB": 1042, - "RFCAB": 812, - "RFCPB": 406, + "REFIpb": 1042, + "RFCab": 812, + "RFCpb": 406, "RL": 36, "RAS": 90, - "RPAB": 45, - "RPPB": 39, - "RCAB": 135, - "RCPB": 129, + "RPab": 45, + "RPpb": 39, + "RCab": 135, + "RCpb": 129, "RPST": 0, "RRD": 22, "RTP": 17, @@ -46,7 +48,63 @@ "XP": 17, "XSR": 828, "RTRS": 1, - "tCK": 469 + "tCK": 469e-12 + }, + "mempowerspec": { + "vdd1": 0.0, + "idd01": 0.0, + "idd2n1": 0.0, + "idd3n1": 0.0, + "idd4r1": 0.0, + "idd4w1": 0.0, + "idd51": 0.0, + "idd5pb1": 0.0, + "idd61": 0.0, + "idd2p1": 0.0, + "idd3p1": 0.0, + "vdd2": 0.0, + "idd02": 0.0, + "idd2n2": 0.0, + "idd3n2": 0.0, + "idd4r2": 0.0, + "idd4w2": 0.0, + "idd52": 0.0, + "idd5pb2": 0.0, + "idd62": 0.0, + "idd2p2": 0.0, + "idd3p2": 0.0, + "vddq": 0.0, + "iBeta_vdd1": 0.0, + "iBeta_vdd2": 0.0 + }, + "memimpedancespec": { + "ck_termination": true, + "ck_R_eq": 1e6, + "ck_dyn_E": 1e-12, + + "ca_termination": true, + "ca_R_eq": 1e6, + "ca_dyn_E": 1e-12, + + "rdq_termination": true, + "rdq_R_eq": 1e6, + "rdq_dyn_E": 1e-12, + "wdq_termination": true, + "wdq_R_eq": 1e6, + "wdq_dyn_E": 1e-12, + + "wdqs_termination": true, + "wdqs_R_eq": 1e6, + "wdqs_dyn_E": 1e-12, + "rdqs_termination": true, + "rdqs_R_eq": 1e6, + "rdqs_dyn_E": 1e-12 + }, + "bankwisespec": { + "factRho": 1, + "factSigma": 1, + "pasrMode": 0, + "hasPASR": false } } } diff --git a/configs/memspec/JEDEC_256Mb_WIDEIO-200_128bit.json b/configs/memspec/JEDEC_256Mb_WIDEIO-200_128bit.json index c5d29da0..7e5aafa8 100644 --- a/configs/memspec/JEDEC_256Mb_WIDEIO-200_128bit.json +++ b/configs/memspec/JEDEC_256Mb_WIDEIO-200_128bit.json @@ -9,33 +9,34 @@ "nbrOfRows": 4096, "width": 128, "nbrOfDevices": 1, - "nbrOfChannels": 4 + "nbrOfChannels": 4, + "maxBurstLength": 4 }, "memoryId": "JEDEC_256Mb_WIDEIO_SDR-200_128bit", "memoryType": "WIDEIO_SDR", "mempowerspec": { - "idd0": 5.88, - "idd02": 21.18, - "idd2n": 0.13, - "idd2n2": 4.04, - "idd2p0": 0.05, - "idd2p02": 0.17, - "idd2p1": 0.05, - "idd2p12": 0.17, - "idd3n": 0.52, - "idd3n2": 6.55, - "idd3p0": 0.25, - "idd3p02": 1.49, - "idd3p1": 0.25, - "idd3p12": 1.49, - "idd4r": 1.41, - "idd4r2": 85.73, - "idd4w": 1.42, - "idd4w2": 60.79, - "idd5": 14.43, - "idd52": 48.17, - "idd6": 0.07, - "idd62": 0.27, + "idd0": 5.88e-3, + "idd02": 21.18e-3, + "idd2n": 0.13e-3, + "idd2n2": 4.04e-3, + "idd2p0": 0.05e-3, + "idd2p02": 0.17e-3, + "idd2p1": 0.05e-3, + "idd2p12": 0.17e-3, + "idd3n": 0.52e-3, + "idd3n2": 6.55e-3, + "idd3p0": 0.25e-3, + "idd3p02": 1.49e-3, + "idd3p1": 0.25e-3, + "idd3p12": 1.49e-3, + "idd4r": 1.41e-3, + "idd4r2": 85.73e-3, + "idd4w": 1.42e-3, + "idd4w2": 60.79e-3, + "idd5": 14.43e-3, + "idd52": 48.17e-3, + "idd6": 0.07e-3, + "idd62": 0.27e-3, "vdd": 1.8, "vdd2": 1.2 }, @@ -61,7 +62,7 @@ "XP": 2, "XSR": 20, "RTRS": 1, - "tCK": 5000 + "tCK": 5000e-12 } } } diff --git a/configs/memspec/JEDEC_256Mb_WIDEIO-266_128bit.json b/configs/memspec/JEDEC_256Mb_WIDEIO-266_128bit.json index 1b43b653..3e5757aa 100644 --- a/configs/memspec/JEDEC_256Mb_WIDEIO-266_128bit.json +++ b/configs/memspec/JEDEC_256Mb_WIDEIO-266_128bit.json @@ -9,33 +9,34 @@ "nbrOfRows": 4096, "width": 128, "nbrOfDevices": 1, - "nbrOfChannels": 4 + "nbrOfChannels": 4, + "maxBurstLength": 4 }, "memoryId": "JEDEC_256Mb_WIDEIO_SDR-266_128bit", "memoryType": "WIDEIO_SDR", "mempowerspec": { - "idd0": 6.06, - "idd02": 21.82, - "idd2n": 0.16, - "idd2n2": 4.76, - "idd2p0": 0.05, - "idd2p02": 0.17, - "idd2p1": 0.05, - "idd2p12": 0.17, - "idd3n": 0.58, - "idd3n2": 7.24, - "idd3p0": 0.25, - "idd3p02": 1.49, - "idd3p1": 0.25, - "idd3p12": 1.49, - "idd4r": 1.82, - "idd4r2": 111.22, - "idd4w": 1.82, - "idd4w2": 78.0, - "idd5": 14.48, - "idd52": 48.34, - "idd6": 0.07, - "idd62": 0.27, + "idd0": 6.06e-3, + "idd02": 21.82e-3, + "idd2n": 0.16e-3, + "idd2n2": 4.76e-3, + "idd2p0": 0.05e-3, + "idd2p02": 0.17e-3, + "idd2p1": 0.05e-3, + "idd2p12": 0.17e-3, + "idd3n": 0.58e-3, + "idd3n2": 7.24e-3, + "idd3p0": 0.25e-3, + "idd3p02": 1.49e-3, + "idd3p1": 0.25e-3, + "idd3p12": 1.49e-3, + "idd4r": 1.82e-3, + "idd4r2": 111.22e-3, + "idd4w": 1.82e-3, + "idd4w2": 78.0e-3, + "idd5": 14.48e-3, + "idd52": 48.34e-3, + "idd6": 0.07e-3, + "idd62": 0.27e-3, "vdd": 1.8, "vdd2": 1.2 }, @@ -61,7 +62,7 @@ "XP": 3, "XSR": 27, "RTRS": 1, - "tCK": 3759 + "tCK": 3759e-12 } } } diff --git a/configs/memspec/JEDEC_2x2x8x4Gbx4_DDR5-3200A.json b/configs/memspec/JEDEC_2x2x8x4Gbx4_DDR5-3200A.json index 2ba1a07d..e86b1359 100644 --- a/configs/memspec/JEDEC_2x2x8x4Gbx4_DDR5-3200A.json +++ b/configs/memspec/JEDEC_2x2x8x4Gbx4_DDR5-3200A.json @@ -15,10 +15,11 @@ "nbrOfDevices": 8, "nbrOfChannels": 2, "cmdMode": 1, - "refMode": 1, + "RefMode": 1, "RAAIMT" : 16, "RAAMMT" : 96, - "RAADEC" : 16 + "RAADEC" : 16, + "maxBurstLength": 16 }, "memoryId": "JEDEC_2x8x2Gbx4_DDR5-3200A", "memoryType": "DDR5", @@ -74,7 +75,67 @@ "ACTPDEN": 2, "PRPDEN": 2, "REFPDEN": 2, - "tCK": 625 + "tCK": 625e-12 + }, + "mempowerspec": { + "vdd": 1.2, + "idd0": 1.0e-3, + "idd2n": 1.0e-3, + "idd3n": 1.0e-3, + "idd4r": 1.0e-3, + "idd4w": 1.0e-3, + "idd5c": 1.0e-3, + "idd6n": 1.0e-3, + "idd2p": 1.0e-3, + "idd3p": 1.0e-3, + "vpp": 1.2, + "ipp0": 1.0e-3, + "ipp2n": 1.0e-3, + "ipp3n": 1.0e-3, + "ipp4r": 1.0e-3, + "ipp4w": 1.0e-3, + "ipp5c": 1.0e-3, + "ipp6n": 1.0e-3, + "ipp2p": 1.0e-3, + "ipp3p": 1.0e-3, + "idd5b": 1.0e-3, + "idd5f": 1.0e-3, + "ipp5b": 1.0e-3, + "ipp5f": 1.0e-3, + "vddq": 1.2, + "iBeta_vdd": 1.0e-3, + "iBeta_vpp": 1.0e-3 + }, + "memimpedancespec": { + "ck_termination": true, + "ck_R_eq": 1e6, + "ck_dyn_E": 1e-12, + + "ca_termination": true, + "ca_R_eq": 1e6, + "ca_dyn_E": 1e-12, + + "rdq_termination": true, + "rdq_R_eq": 1e6, + "rdq_dyn_E": 1e-12, + "wdq_termination": true, + "wdq_R_eq": 1e6, + "wdq_dyn_E": 1e-12, + + "wdqs_termination": true, + "wdqs_R_eq": 1e6, + "wdqs_dyn_E": 1e-12, + "rdqs_termination": true, + "rdqs_R_eq": 1e6, + "rdqs_dyn_E": 1e-12 + }, + "dataratespec": { + "ca_bus_rate": 2, + "dq_bus_rate": 2, + "dqs_bus_rate": 2 + }, + "bankwisespec": { + "factRho": 1 } } } diff --git a/configs/memspec/JEDEC_2x4x1Gbx8_DDR5-3200A.json b/configs/memspec/JEDEC_2x4x1Gbx8_DDR5-3200A.json index 4410602f..68f1b23b 100644 --- a/configs/memspec/JEDEC_2x4x1Gbx8_DDR5-3200A.json +++ b/configs/memspec/JEDEC_2x4x1Gbx8_DDR5-3200A.json @@ -15,10 +15,11 @@ "nbrOfDevices": 4, "nbrOfChannels": 2, "cmdMode": 1, - "refMode": 1, + "RefMode": 1, "RAAIMT" : 16, "RAAMMT" : 96, - "RAADEC" : 16 + "RAADEC" : 16, + "maxBurstLength": 16 }, "memoryId": "JEDEC_2x4x1Gbx8_DDR5-3200A", "memoryType": "DDR5", @@ -74,7 +75,67 @@ "ACTPDEN": 2, "PRPDEN": 2, "REFPDEN": 2, - "tCK": 625 + "tCK": 625e-12 + }, + "mempowerspec": { + "vdd": 0.0, + "idd0": 0.0, + "idd2n": 0.0, + "idd3n": 0.0, + "idd4r": 0.0, + "idd4w": 0.0, + "idd5c": 0.0, + "idd6n": 0.0, + "idd2p": 0.0, + "idd3p": 0.0, + "vpp": 0.0, + "ipp0": 0.0, + "ipp2n": 0.0, + "ipp3n": 0.0, + "ipp4r": 0.0, + "ipp4w": 0.0, + "ipp5c": 0.0, + "ipp6n": 0.0, + "ipp2p": 0.0, + "ipp3p": 0.0, + "idd5b": 0.0, + "idd5f": 0.0, + "ipp5b": 0.0, + "ipp5f": 0.0, + "vddq": 0.0, + "iBeta_vdd": 0.0, + "iBeta_vpp": 0.0 + }, + "memimpedancespec": { + "ck_termination": true, + "ck_R_eq": 1e6, + "ck_dyn_E": 1e-12, + + "ca_termination": true, + "ca_R_eq": 1e6, + "ca_dyn_E": 1e-12, + + "rdq_termination": true, + "rdq_R_eq": 1e6, + "rdq_dyn_E": 1e-12, + "wdq_termination": true, + "wdq_R_eq": 1e6, + "wdq_dyn_E": 1e-12, + + "wdqs_termination": true, + "wdqs_R_eq": 1e6, + "wdqs_dyn_E": 1e-12, + "rdqs_termination": true, + "rdqs_R_eq": 1e6, + "rdqs_dyn_E": 1e-12 + }, + "dataratespec": { + "ca_bus_rate": 2, + "dq_bus_rate": 2, + "dqs_bus_rate": 2 + }, + "bankwisespec": { + "factRho": 1 } } } diff --git a/configs/memspec/JEDEC_2x4x1Gbx8_DDR5-3600A.json b/configs/memspec/JEDEC_2x4x1Gbx8_DDR5-3600A.json index 9515d6df..57fa6410 100644 --- a/configs/memspec/JEDEC_2x4x1Gbx8_DDR5-3600A.json +++ b/configs/memspec/JEDEC_2x4x1Gbx8_DDR5-3600A.json @@ -15,10 +15,11 @@ "nbrOfDevices": 4, "nbrOfChannels": 2, "cmdMode": 1, - "refMode": 1, + "RefMode": 1, "RAAIMT" : 16, "RAAMMT" : 96, - "RAADEC" : 16 + "RAADEC" : 16, + "maxBurstLength": 16 }, "memoryId": "JEDEC_2x4x1Gbx8_DDR5-3600A", "memoryType": "DDR5", @@ -74,7 +75,67 @@ "ACTPDEN": 2, "PRPDEN": 2, "REFPDEN": 2, - "tCK": 556 + "tCK": 556e-12 + }, + "mempowerspec": { + "vdd": 0.0, + "idd0": 0.0, + "idd2n": 0.0, + "idd3n": 0.0, + "idd4r": 0.0, + "idd4w": 0.0, + "idd5c": 0.0, + "idd6n": 0.0, + "idd2p": 0.0, + "idd3p": 0.0, + "vpp": 0.0, + "ipp0": 0.0, + "ipp2n": 0.0, + "ipp3n": 0.0, + "ipp4r": 0.0, + "ipp4w": 0.0, + "ipp5c": 0.0, + "ipp6n": 0.0, + "ipp2p": 0.0, + "ipp3p": 0.0, + "idd5b": 0.0, + "idd5f": 0.0, + "ipp5b": 0.0, + "ipp5f": 0.0, + "vddq": 0.0, + "iBeta_vdd": 0.0, + "iBeta_vpp": 0.0 + }, + "memimpedancespec": { + "ck_termination": true, + "ck_R_eq": 1e6, + "ck_dyn_E": 1e-12, + + "ca_termination": true, + "ca_R_eq": 1e6, + "ca_dyn_E": 1e-12, + + "rdq_termination": true, + "rdq_R_eq": 1e6, + "rdq_dyn_E": 1e-12, + "wdq_termination": true, + "wdq_R_eq": 1e6, + "wdq_dyn_E": 1e-12, + + "wdqs_termination": true, + "wdqs_R_eq": 1e6, + "wdqs_dyn_E": 1e-12, + "rdqs_termination": true, + "rdqs_R_eq": 1e6, + "rdqs_dyn_E": 1e-12 + }, + "dataratespec": { + "ca_bus_rate": 2, + "dq_bus_rate": 2, + "dqs_bus_rate": 2 + }, + "bankwisespec": { + "factRho": 1 } } } diff --git a/configs/memspec/JEDEC_2x4x1Gbx8_DDR5-4000A.json b/configs/memspec/JEDEC_2x4x1Gbx8_DDR5-4000A.json index 9bcf4c7c..d61a58ec 100644 --- a/configs/memspec/JEDEC_2x4x1Gbx8_DDR5-4000A.json +++ b/configs/memspec/JEDEC_2x4x1Gbx8_DDR5-4000A.json @@ -15,10 +15,11 @@ "nbrOfDevices": 4, "nbrOfChannels": 2, "cmdMode": 1, - "refMode": 1, + "RefMode": 1, "RAAIMT" : 16, "RAAMMT" : 96, - "RAADEC" : 16 + "RAADEC" : 16, + "maxBurstLength": 16 }, "memoryId": "JEDEC_2x4x1Gbx8_DDR5-4000A", "memoryType": "DDR5", @@ -74,7 +75,67 @@ "ACTPDEN": 2, "PRPDEN": 2, "REFPDEN": 2, - "tCK": 500 + "tCK": 500e-12 + }, + "mempowerspec": { + "vdd": 0.0, + "idd0": 0.0, + "idd2n": 0.0, + "idd3n": 0.0, + "idd4r": 0.0, + "idd4w": 0.0, + "idd5c": 0.0, + "idd6n": 0.0, + "idd2p": 0.0, + "idd3p": 0.0, + "vpp": 0.0, + "ipp0": 0.0, + "ipp2n": 0.0, + "ipp3n": 0.0, + "ipp4r": 0.0, + "ipp4w": 0.0, + "ipp5c": 0.0, + "ipp6n": 0.0, + "ipp2p": 0.0, + "ipp3p": 0.0, + "idd5b": 0.0, + "idd5f": 0.0, + "ipp5b": 0.0, + "ipp5f": 0.0, + "vddq": 0.0, + "iBeta_vdd": 0.0, + "iBeta_vpp": 0.0 + }, + "memimpedancespec": { + "ck_termination": true, + "ck_R_eq": 1e6, + "ck_dyn_E": 1e-12, + + "ca_termination": true, + "ca_R_eq": 1e6, + "ca_dyn_E": 1e-12, + + "rdq_termination": true, + "rdq_R_eq": 1e6, + "rdq_dyn_E": 1e-12, + "wdq_termination": true, + "wdq_R_eq": 1e6, + "wdq_dyn_E": 1e-12, + + "wdqs_termination": true, + "wdqs_R_eq": 1e6, + "wdqs_dyn_E": 1e-12, + "rdqs_termination": true, + "rdqs_R_eq": 1e6, + "rdqs_dyn_E": 1e-12 + }, + "dataratespec": { + "ca_bus_rate": 2, + "dq_bus_rate": 2, + "dqs_bus_rate": 2 + }, + "bankwisespec": { + "factRho": 1 } } } diff --git a/configs/memspec/JEDEC_2x4x1Gbx8_DDR5-4400A.json b/configs/memspec/JEDEC_2x4x1Gbx8_DDR5-4400A.json index 0caa823d..e598ab16 100644 --- a/configs/memspec/JEDEC_2x4x1Gbx8_DDR5-4400A.json +++ b/configs/memspec/JEDEC_2x4x1Gbx8_DDR5-4400A.json @@ -15,10 +15,11 @@ "nbrOfDevices": 4, "nbrOfChannels": 2, "cmdMode": 1, - "refMode": 1, + "RefMode": 1, "RAAIMT" : 16, "RAAMMT" : 96, - "RAADEC" : 16 + "RAADEC" : 16, + "maxBurstLength": 16 }, "memoryId": "JEDEC_2x4x1Gbx8_DDR5-4400A", "memoryType": "DDR5", @@ -74,7 +75,67 @@ "ACTPDEN": 2, "PRPDEN": 2, "REFPDEN": 2, - "tCK": 455 + "tCK": 455e-12 + }, + "mempowerspec": { + "vdd": 0.0, + "idd0": 0.0, + "idd2n": 0.0, + "idd3n": 0.0, + "idd4r": 0.0, + "idd4w": 0.0, + "idd5c": 0.0, + "idd6n": 0.0, + "idd2p": 0.0, + "idd3p": 0.0, + "vpp": 0.0, + "ipp0": 0.0, + "ipp2n": 0.0, + "ipp3n": 0.0, + "ipp4r": 0.0, + "ipp4w": 0.0, + "ipp5c": 0.0, + "ipp6n": 0.0, + "ipp2p": 0.0, + "ipp3p": 0.0, + "idd5b": 0.0, + "idd5f": 0.0, + "ipp5b": 0.0, + "ipp5f": 0.0, + "vddq": 0.0, + "iBeta_vdd": 0.0, + "iBeta_vpp": 0.0 + }, + "memimpedancespec": { + "ck_termination": true, + "ck_R_eq": 1e6, + "ck_dyn_E": 1e-12, + + "ca_termination": true, + "ca_R_eq": 1e6, + "ca_dyn_E": 1e-12, + + "rdq_termination": true, + "rdq_R_eq": 1e6, + "rdq_dyn_E": 1e-12, + "wdq_termination": true, + "wdq_R_eq": 1e6, + "wdq_dyn_E": 1e-12, + + "wdqs_termination": true, + "wdqs_R_eq": 1e6, + "wdqs_dyn_E": 1e-12, + "rdqs_termination": true, + "rdqs_R_eq": 1e6, + "rdqs_dyn_E": 1e-12 + }, + "dataratespec": { + "ca_bus_rate": 2, + "dq_bus_rate": 2, + "dqs_bus_rate": 2 + }, + "bankwisespec": { + "factRho": 1 } } } diff --git a/configs/memspec/JEDEC_2x4x1Gbx8_DDR5-4800A.json b/configs/memspec/JEDEC_2x4x1Gbx8_DDR5-4800A.json index 14daaa46..cce94d3f 100644 --- a/configs/memspec/JEDEC_2x4x1Gbx8_DDR5-4800A.json +++ b/configs/memspec/JEDEC_2x4x1Gbx8_DDR5-4800A.json @@ -15,10 +15,11 @@ "nbrOfDevices": 4, "nbrOfChannels": 2, "cmdMode": 1, - "refMode": 1, + "RefMode": 1, "RAAIMT" : 16, "RAAMMT" : 96, - "RAADEC" : 16 + "RAADEC" : 16, + "maxBurstLength": 16 }, "memoryId": "JEDEC_2x4x1Gbx8_DDR5-4800A", "memoryType": "DDR5", @@ -74,7 +75,67 @@ "ACTPDEN": 2, "PRPDEN": 2, "REFPDEN": 2, - "tCK": 417 + "tCK": 417e-12 + }, + "mempowerspec": { + "vdd": 0.0, + "idd0": 0.0, + "idd2n": 0.0, + "idd3n": 0.0, + "idd4r": 0.0, + "idd4w": 0.0, + "idd5c": 0.0, + "idd6n": 0.0, + "idd2p": 0.0, + "idd3p": 0.0, + "vpp": 0.0, + "ipp0": 0.0, + "ipp2n": 0.0, + "ipp3n": 0.0, + "ipp4r": 0.0, + "ipp4w": 0.0, + "ipp5c": 0.0, + "ipp6n": 0.0, + "ipp2p": 0.0, + "ipp3p": 0.0, + "idd5b": 0.0, + "idd5f": 0.0, + "ipp5b": 0.0, + "ipp5f": 0.0, + "vddq": 0.0, + "iBeta_vdd": 0.0, + "iBeta_vpp": 0.0 + }, + "memimpedancespec": { + "ck_termination": true, + "ck_R_eq": 1e6, + "ck_dyn_E": 1e-12, + + "ca_termination": true, + "ca_R_eq": 1e6, + "ca_dyn_E": 1e-12, + + "rdq_termination": true, + "rdq_R_eq": 1e6, + "rdq_dyn_E": 1e-12, + "wdq_termination": true, + "wdq_R_eq": 1e6, + "wdq_dyn_E": 1e-12, + + "wdqs_termination": true, + "wdqs_R_eq": 1e6, + "wdqs_dyn_E": 1e-12, + "rdqs_termination": true, + "rdqs_R_eq": 1e6, + "rdqs_dyn_E": 1e-12 + }, + "dataratespec": { + "ca_bus_rate": 2, + "dq_bus_rate": 2, + "dqs_bus_rate": 2 + }, + "bankwisespec": { + "factRho": 1 } } } diff --git a/configs/memspec/JEDEC_2x4x1Gbx8_DDR5-5200A.json b/configs/memspec/JEDEC_2x4x1Gbx8_DDR5-5200A.json index 12933de2..ad963db1 100644 --- a/configs/memspec/JEDEC_2x4x1Gbx8_DDR5-5200A.json +++ b/configs/memspec/JEDEC_2x4x1Gbx8_DDR5-5200A.json @@ -15,10 +15,11 @@ "nbrOfDevices": 4, "nbrOfChannels": 2, "cmdMode": 1, - "refMode": 1, + "RefMode": 1, "RAAIMT" : 16, "RAAMMT" : 96, - "RAADEC" : 16 + "RAADEC" : 16, + "maxBurstLength": 16 }, "memoryId": "JEDEC_2x4x1Gbx8_DDR5-5200A", "memoryType": "DDR5", @@ -74,7 +75,67 @@ "ACTPDEN": 2, "PRPDEN": 2, "REFPDEN": 2, - "tCK": 385 + "tCK": 385e-12 + }, + "mempowerspec": { + "vdd": 0.0, + "idd0": 0.0, + "idd2n": 0.0, + "idd3n": 0.0, + "idd4r": 0.0, + "idd4w": 0.0, + "idd5c": 0.0, + "idd6n": 0.0, + "idd2p": 0.0, + "idd3p": 0.0, + "vpp": 0.0, + "ipp0": 0.0, + "ipp2n": 0.0, + "ipp3n": 0.0, + "ipp4r": 0.0, + "ipp4w": 0.0, + "ipp5c": 0.0, + "ipp6n": 0.0, + "ipp2p": 0.0, + "ipp3p": 0.0, + "idd5b": 0.0, + "idd5f": 0.0, + "ipp5b": 0.0, + "ipp5f": 0.0, + "vddq": 0.0, + "iBeta_vdd": 0.0, + "iBeta_vpp": 0.0 + }, + "memimpedancespec": { + "ck_termination": true, + "ck_R_eq": 1e6, + "ck_dyn_E": 1e-12, + + "ca_termination": true, + "ca_R_eq": 1e6, + "ca_dyn_E": 1e-12, + + "rdq_termination": true, + "rdq_R_eq": 1e6, + "rdq_dyn_E": 1e-12, + "wdq_termination": true, + "wdq_R_eq": 1e6, + "wdq_dyn_E": 1e-12, + + "wdqs_termination": true, + "wdqs_R_eq": 1e6, + "wdqs_dyn_E": 1e-12, + "rdqs_termination": true, + "rdqs_R_eq": 1e6, + "rdqs_dyn_E": 1e-12 + }, + "dataratespec": { + "ca_bus_rate": 2, + "dq_bus_rate": 2, + "dqs_bus_rate": 2 + }, + "bankwisespec": { + "factRho": 1 } } } diff --git a/configs/memspec/JEDEC_2x4x1Gbx8_DDR5-5600A.json b/configs/memspec/JEDEC_2x4x1Gbx8_DDR5-5600A.json index 2d55d046..2fff5d40 100644 --- a/configs/memspec/JEDEC_2x4x1Gbx8_DDR5-5600A.json +++ b/configs/memspec/JEDEC_2x4x1Gbx8_DDR5-5600A.json @@ -15,10 +15,11 @@ "nbrOfDevices": 4, "nbrOfChannels": 2, "cmdMode": 1, - "refMode": 1, + "RefMode": 1, "RAAIMT" : 16, "RAAMMT" : 96, - "RAADEC" : 16 + "RAADEC" : 16, + "maxBurstLength": 16 }, "memoryId": "JEDEC_2x4x1Gbx8_DDR5-5600A", "memoryType": "DDR5", @@ -74,7 +75,67 @@ "ACTPDEN": 2, "PRPDEN": 2, "REFPDEN": 2, - "tCK": 357 + "tCK": 357e-12 + }, + "mempowerspec": { + "vdd": 0.0, + "idd0": 0.0, + "idd2n": 0.0, + "idd3n": 0.0, + "idd4r": 0.0, + "idd4w": 0.0, + "idd5c": 0.0, + "idd6n": 0.0, + "idd2p": 0.0, + "idd3p": 0.0, + "vpp": 0.0, + "ipp0": 0.0, + "ipp2n": 0.0, + "ipp3n": 0.0, + "ipp4r": 0.0, + "ipp4w": 0.0, + "ipp5c": 0.0, + "ipp6n": 0.0, + "ipp2p": 0.0, + "ipp3p": 0.0, + "idd5b": 0.0, + "idd5f": 0.0, + "ipp5b": 0.0, + "ipp5f": 0.0, + "vddq": 0.0, + "iBeta_vdd": 0.0, + "iBeta_vpp": 0.0 + }, + "memimpedancespec": { + "ck_termination": true, + "ck_R_eq": 1e6, + "ck_dyn_E": 1e-12, + + "ca_termination": true, + "ca_R_eq": 1e6, + "ca_dyn_E": 1e-12, + + "rdq_termination": true, + "rdq_R_eq": 1e6, + "rdq_dyn_E": 1e-12, + "wdq_termination": true, + "wdq_R_eq": 1e6, + "wdq_dyn_E": 1e-12, + + "wdqs_termination": true, + "wdqs_R_eq": 1e6, + "wdqs_dyn_E": 1e-12, + "rdqs_termination": true, + "rdqs_R_eq": 1e6, + "rdqs_dyn_E": 1e-12 + }, + "dataratespec": { + "ca_bus_rate": 2, + "dq_bus_rate": 2, + "dqs_bus_rate": 2 + }, + "bankwisespec": { + "factRho": 1 } } } diff --git a/configs/memspec/JEDEC_2x4x1Gbx8_DDR5-6000A.json b/configs/memspec/JEDEC_2x4x1Gbx8_DDR5-6000A.json index 1279e63f..e4110e4e 100644 --- a/configs/memspec/JEDEC_2x4x1Gbx8_DDR5-6000A.json +++ b/configs/memspec/JEDEC_2x4x1Gbx8_DDR5-6000A.json @@ -15,10 +15,11 @@ "nbrOfDevices": 4, "nbrOfChannels": 2, "cmdMode": 1, - "refMode": 1, + "RefMode": 1, "RAAIMT" : 16, "RAAMMT" : 96, - "RAADEC" : 16 + "RAADEC" : 16, + "maxBurstLength": 16 }, "memoryId": "JEDEC_2x4x1Gbx8_DDR5-6000A", "memoryType": "DDR5", @@ -74,7 +75,67 @@ "ACTPDEN": 2, "PRPDEN": 2, "REFPDEN": 2, - "tCK": 333 + "tCK": 333e-12 + }, + "mempowerspec": { + "vdd": 0.0, + "idd0": 0.0, + "idd2n": 0.0, + "idd3n": 0.0, + "idd4r": 0.0, + "idd4w": 0.0, + "idd5c": 0.0, + "idd6n": 0.0, + "idd2p": 0.0, + "idd3p": 0.0, + "vpp": 0.0, + "ipp0": 0.0, + "ipp2n": 0.0, + "ipp3n": 0.0, + "ipp4r": 0.0, + "ipp4w": 0.0, + "ipp5c": 0.0, + "ipp6n": 0.0, + "ipp2p": 0.0, + "ipp3p": 0.0, + "idd5b": 0.0, + "idd5f": 0.0, + "ipp5b": 0.0, + "ipp5f": 0.0, + "vddq": 0.0, + "iBeta_vdd": 0.0, + "iBeta_vpp": 0.0 + }, + "memimpedancespec": { + "ck_termination": true, + "ck_R_eq": 1e6, + "ck_dyn_E": 1e-12, + + "ca_termination": true, + "ca_R_eq": 1e6, + "ca_dyn_E": 1e-12, + + "rdq_termination": true, + "rdq_R_eq": 1e6, + "rdq_dyn_E": 1e-12, + "wdq_termination": true, + "wdq_R_eq": 1e6, + "wdq_dyn_E": 1e-12, + + "wdqs_termination": true, + "wdqs_R_eq": 1e6, + "wdqs_dyn_E": 1e-12, + "rdqs_termination": true, + "rdqs_R_eq": 1e6, + "rdqs_dyn_E": 1e-12 + }, + "dataratespec": { + "ca_bus_rate": 2, + "dq_bus_rate": 2, + "dqs_bus_rate": 2 + }, + "bankwisespec": { + "factRho": 1 } } } diff --git a/configs/memspec/JEDEC_2x4x1Gbx8_DDR5-6400A.json b/configs/memspec/JEDEC_2x4x1Gbx8_DDR5-6400A.json index 5c80e3b2..6b72cbe1 100644 --- a/configs/memspec/JEDEC_2x4x1Gbx8_DDR5-6400A.json +++ b/configs/memspec/JEDEC_2x4x1Gbx8_DDR5-6400A.json @@ -15,10 +15,11 @@ "nbrOfDevices": 4, "nbrOfChannels": 2, "cmdMode": 1, - "refMode": 1, + "RefMode": 1, "RAAIMT" : 16, "RAAMMT" : 96, - "RAADEC" : 16 + "RAADEC" : 16, + "maxBurstLength": 16 }, "memoryId": "JEDEC_2x4x1Gbx8_DDR5-6400A", "memoryType": "DDR5", @@ -74,7 +75,67 @@ "ACTPDEN": 2, "PRPDEN": 2, "REFPDEN": 2, - "tCK": 313 + "tCK": 313e-12 + }, + "mempowerspec": { + "vdd": 0.0, + "idd0": 0.0, + "idd2n": 0.0, + "idd3n": 0.0, + "idd4r": 0.0, + "idd4w": 0.0, + "idd5c": 0.0, + "idd6n": 0.0, + "idd2p": 0.0, + "idd3p": 0.0, + "vpp": 0.0, + "ipp0": 0.0, + "ipp2n": 0.0, + "ipp3n": 0.0, + "ipp4r": 0.0, + "ipp4w": 0.0, + "ipp5c": 0.0, + "ipp6n": 0.0, + "ipp2p": 0.0, + "ipp3p": 0.0, + "idd5b": 0.0, + "idd5f": 0.0, + "ipp5b": 0.0, + "ipp5f": 0.0, + "vddq": 0.0, + "iBeta_vdd": 0.0, + "iBeta_vpp": 0.0 + }, + "memimpedancespec": { + "ck_termination": true, + "ck_R_eq": 1e6, + "ck_dyn_E": 1e-12, + + "ca_termination": true, + "ca_R_eq": 1e6, + "ca_dyn_E": 1e-12, + + "rdq_termination": true, + "rdq_R_eq": 1e6, + "rdq_dyn_E": 1e-12, + "wdq_termination": true, + "wdq_R_eq": 1e6, + "wdq_dyn_E": 1e-12, + + "wdqs_termination": true, + "wdqs_R_eq": 1e6, + "wdqs_dyn_E": 1e-12, + "rdqs_termination": true, + "rdqs_R_eq": 1e6, + "rdqs_dyn_E": 1e-12 + }, + "dataratespec": { + "ca_bus_rate": 2, + "dq_bus_rate": 2, + "dqs_bus_rate": 2 + }, + "bankwisespec": { + "factRho": 1 } } } diff --git a/configs/memspec/JEDEC_2x8x2Gbx4_DDR5-3200A.json b/configs/memspec/JEDEC_2x8x2Gbx4_DDR5-3200A.json index 2e0bdbaf..8b421e86 100644 --- a/configs/memspec/JEDEC_2x8x2Gbx4_DDR5-3200A.json +++ b/configs/memspec/JEDEC_2x8x2Gbx4_DDR5-3200A.json @@ -15,10 +15,11 @@ "nbrOfDevices": 8, "nbrOfChannels": 2, "cmdMode": 1, - "refMode": 1, + "RefMode": 1, "RAAIMT" : 32, "RAAMMT" : 96, - "RAADEC" : 16 + "RAADEC" : 16, + "maxBurstLength": 16 }, "memoryId": "JEDEC_2x8x2Gbx4_DDR5-3200A", "memoryType": "DDR5", @@ -74,7 +75,67 @@ "ACTPDEN": 2, "PRPDEN": 2, "REFPDEN": 2, - "tCK": 625 + "tCK": 625e-12 + }, + "mempowerspec": { + "vdd": 1.2, + "idd0": 1e-3, + "idd2n": 1e-3, + "idd3n": 1e-3, + "idd4r": 1e-3, + "idd4w": 1e-3, + "idd5c": 1e-3, + "idd6n": 1e-3, + "idd2p": 1e-3, + "idd3p": 1e-3, + "vpp": 1.2, + "ipp0": 1e-3, + "ipp2n": 1e-3, + "ipp3n": 1e-3, + "ipp4r": 1e-3, + "ipp4w": 1e-3, + "ipp5c": 1e-3, + "ipp6n": 1e-3, + "ipp2p": 1e-3, + "ipp3p": 1e-3, + "idd5b": 1e-3, + "idd5f": 1e-3, + "ipp5b": 1e-3, + "ipp5f": 1e-3, + "vddq": 1.2, + "iBeta_vdd": 0.0, + "iBeta_vpp": 0.0 + }, + "memimpedancespec": { + "ck_termination": true, + "ck_R_eq": 1e6, + "ck_dyn_E": 1e-12, + + "ca_termination": true, + "ca_R_eq": 1e6, + "ca_dyn_E": 1e-12, + + "rdq_termination": true, + "rdq_R_eq": 1e6, + "rdq_dyn_E": 1e-12, + "wdq_termination": true, + "wdq_R_eq": 1e6, + "wdq_dyn_E": 1e-12, + + "wdqs_termination": true, + "wdqs_R_eq": 1e6, + "wdqs_dyn_E": 1e-12, + "rdqs_termination": true, + "rdqs_R_eq": 1e6, + "rdqs_dyn_E": 1e-12 + }, + "dataratespec": { + "ca_bus_rate": 2, + "dq_bus_rate": 2, + "dqs_bus_rate": 2 + }, + "bankwisespec": { + "factRho": 1 } } } diff --git a/configs/memspec/JEDEC_2x8x2Gbx4_DDR5-3600A.json b/configs/memspec/JEDEC_2x8x2Gbx4_DDR5-3600A.json index c50fb3c2..748f6d8e 100644 --- a/configs/memspec/JEDEC_2x8x2Gbx4_DDR5-3600A.json +++ b/configs/memspec/JEDEC_2x8x2Gbx4_DDR5-3600A.json @@ -15,10 +15,11 @@ "nbrOfDevices": 8, "nbrOfChannels": 2, "cmdMode": 1, - "refMode": 1, + "RefMode": 1, "RAAIMT" : 16, "RAAMMT" : 96, - "RAADEC" : 16 + "RAADEC" : 16, + "maxBurstLength": 16 }, "memoryId": "JEDEC_2x8x2Gbx4_DDR5-3600A", "memoryType": "DDR5", @@ -74,7 +75,67 @@ "ACTPDEN": 2, "PRPDEN": 2, "REFPDEN": 2, - "tCK": 556 + "tCK": 556e-12 + }, + "mempowerspec": { + "vdd": 0.0, + "idd0": 0.0, + "idd2n": 0.0, + "idd3n": 0.0, + "idd4r": 0.0, + "idd4w": 0.0, + "idd5c": 0.0, + "idd6n": 0.0, + "idd2p": 0.0, + "idd3p": 0.0, + "vpp": 0.0, + "ipp0": 0.0, + "ipp2n": 0.0, + "ipp3n": 0.0, + "ipp4r": 0.0, + "ipp4w": 0.0, + "ipp5c": 0.0, + "ipp6n": 0.0, + "ipp2p": 0.0, + "ipp3p": 0.0, + "idd5b": 0.0, + "idd5f": 0.0, + "ipp5b": 0.0, + "ipp5f": 0.0, + "vddq": 0.0, + "iBeta_vdd": 0.0, + "iBeta_vpp": 0.0 + }, + "memimpedancespec": { + "ck_termination": true, + "ck_R_eq": 1e6, + "ck_dyn_E": 1e-12, + + "ca_termination": true, + "ca_R_eq": 1e6, + "ca_dyn_E": 1e-12, + + "rdq_termination": true, + "rdq_R_eq": 1e6, + "rdq_dyn_E": 1e-12, + "wdq_termination": true, + "wdq_R_eq": 1e6, + "wdq_dyn_E": 1e-12, + + "wdqs_termination": true, + "wdqs_R_eq": 1e6, + "wdqs_dyn_E": 1e-12, + "rdqs_termination": true, + "rdqs_R_eq": 1e6, + "rdqs_dyn_E": 1e-12 + }, + "dataratespec": { + "ca_bus_rate": 2, + "dq_bus_rate": 2, + "dqs_bus_rate": 2 + }, + "bankwisespec": { + "factRho": 1 } } } diff --git a/configs/memspec/JEDEC_2x8x2Gbx4_DDR5-4000A.json b/configs/memspec/JEDEC_2x8x2Gbx4_DDR5-4000A.json index 1927808a..f4b1d26f 100644 --- a/configs/memspec/JEDEC_2x8x2Gbx4_DDR5-4000A.json +++ b/configs/memspec/JEDEC_2x8x2Gbx4_DDR5-4000A.json @@ -15,10 +15,11 @@ "nbrOfDevices": 8, "nbrOfChannels": 2, "cmdMode": 1, - "refMode": 1, + "RefMode": 1, "RAAIMT" : 16, "RAAMMT" : 96, - "RAADEC" : 16 + "RAADEC" : 16, + "maxBurstLength": 16 }, "memoryId": "JEDEC_2x8x2Gbx4_DDR5-4000A", "memoryType": "DDR5", @@ -74,7 +75,67 @@ "ACTPDEN": 2, "PRPDEN": 2, "REFPDEN": 2, - "tCK": 500 + "tCK": 500e-12 + }, + "mempowerspec": { + "vdd": 0.0, + "idd0": 0.0, + "idd2n": 0.0, + "idd3n": 0.0, + "idd4r": 0.0, + "idd4w": 0.0, + "idd5c": 0.0, + "idd6n": 0.0, + "idd2p": 0.0, + "idd3p": 0.0, + "vpp": 0.0, + "ipp0": 0.0, + "ipp2n": 0.0, + "ipp3n": 0.0, + "ipp4r": 0.0, + "ipp4w": 0.0, + "ipp5c": 0.0, + "ipp6n": 0.0, + "ipp2p": 0.0, + "ipp3p": 0.0, + "idd5b": 0.0, + "idd5f": 0.0, + "ipp5b": 0.0, + "ipp5f": 0.0, + "vddq": 0.0, + "iBeta_vdd": 0.0, + "iBeta_vpp": 0.0 + }, + "memimpedancespec": { + "ck_termination": true, + "ck_R_eq": 1e6, + "ck_dyn_E": 1e-12, + + "ca_termination": true, + "ca_R_eq": 1e6, + "ca_dyn_E": 1e-12, + + "rdq_termination": true, + "rdq_R_eq": 1e6, + "rdq_dyn_E": 1e-12, + "wdq_termination": true, + "wdq_R_eq": 1e6, + "wdq_dyn_E": 1e-12, + + "wdqs_termination": true, + "wdqs_R_eq": 1e6, + "wdqs_dyn_E": 1e-12, + "rdqs_termination": true, + "rdqs_R_eq": 1e6, + "rdqs_dyn_E": 1e-12 + }, + "dataratespec": { + "ca_bus_rate": 2, + "dq_bus_rate": 2, + "dqs_bus_rate": 2 + }, + "bankwisespec": { + "factRho": 1 } } } diff --git a/configs/memspec/JEDEC_2x8x2Gbx4_DDR5-4400A.json b/configs/memspec/JEDEC_2x8x2Gbx4_DDR5-4400A.json index 353a3a73..1e39e643 100644 --- a/configs/memspec/JEDEC_2x8x2Gbx4_DDR5-4400A.json +++ b/configs/memspec/JEDEC_2x8x2Gbx4_DDR5-4400A.json @@ -15,10 +15,11 @@ "nbrOfDevices": 8, "nbrOfChannels": 2, "cmdMode": 1, - "refMode": 1, + "RefMode": 1, "RAAIMT" : 16, "RAAMMT" : 96, - "RAADEC" : 16 + "RAADEC" : 16, + "maxBurstLength": 16 }, "memoryId": "JEDEC_2x8x2Gbx4_DDR5-4400A", "memoryType": "DDR5", @@ -74,7 +75,67 @@ "ACTPDEN": 2, "PRPDEN": 2, "REFPDEN": 2, - "tCK": 455 + "tCK": 455e-12 + }, + "mempowerspec": { + "vdd": 0.0, + "idd0": 0.0, + "idd2n": 0.0, + "idd3n": 0.0, + "idd4r": 0.0, + "idd4w": 0.0, + "idd5c": 0.0, + "idd6n": 0.0, + "idd2p": 0.0, + "idd3p": 0.0, + "vpp": 0.0, + "ipp0": 0.0, + "ipp2n": 0.0, + "ipp3n": 0.0, + "ipp4r": 0.0, + "ipp4w": 0.0, + "ipp5c": 0.0, + "ipp6n": 0.0, + "ipp2p": 0.0, + "ipp3p": 0.0, + "idd5b": 0.0, + "idd5f": 0.0, + "ipp5b": 0.0, + "ipp5f": 0.0, + "vddq": 0.0, + "iBeta_vdd": 0.0, + "iBeta_vpp": 0.0 + }, + "memimpedancespec": { + "ck_termination": true, + "ck_R_eq": 1e6, + "ck_dyn_E": 1e-12, + + "ca_termination": true, + "ca_R_eq": 1e6, + "ca_dyn_E": 1e-12, + + "rdq_termination": true, + "rdq_R_eq": 1e6, + "rdq_dyn_E": 1e-12, + "wdq_termination": true, + "wdq_R_eq": 1e6, + "wdq_dyn_E": 1e-12, + + "wdqs_termination": true, + "wdqs_R_eq": 1e6, + "wdqs_dyn_E": 1e-12, + "rdqs_termination": true, + "rdqs_R_eq": 1e6, + "rdqs_dyn_E": 1e-12 + }, + "dataratespec": { + "ca_bus_rate": 2, + "dq_bus_rate": 2, + "dqs_bus_rate": 2 + }, + "bankwisespec": { + "factRho": 1 } } } diff --git a/configs/memspec/JEDEC_2x8x2Gbx4_DDR5-4800A.json b/configs/memspec/JEDEC_2x8x2Gbx4_DDR5-4800A.json index 99b494e1..0616f602 100644 --- a/configs/memspec/JEDEC_2x8x2Gbx4_DDR5-4800A.json +++ b/configs/memspec/JEDEC_2x8x2Gbx4_DDR5-4800A.json @@ -15,10 +15,11 @@ "nbrOfDevices": 8, "nbrOfChannels": 2, "cmdMode": 1, - "refMode": 1, + "RefMode": 1, "RAAIMT" : 16, "RAAMMT" : 96, - "RAADEC" : 16 + "RAADEC" : 16, + "maxBurstLength": 16 }, "memoryId": "JEDEC_2x8x2Gbx4_DDR5-4800A", "memoryType": "DDR5", @@ -74,7 +75,67 @@ "ACTPDEN": 2, "PRPDEN": 2, "REFPDEN": 2, - "tCK": 417 + "tCK": 417e-12 + }, + "mempowerspec": { + "vdd": 0.0, + "idd0": 0.0, + "idd2n": 0.0, + "idd3n": 0.0, + "idd4r": 0.0, + "idd4w": 0.0, + "idd5c": 0.0, + "idd6n": 0.0, + "idd2p": 0.0, + "idd3p": 0.0, + "vpp": 0.0, + "ipp0": 0.0, + "ipp2n": 0.0, + "ipp3n": 0.0, + "ipp4r": 0.0, + "ipp4w": 0.0, + "ipp5c": 0.0, + "ipp6n": 0.0, + "ipp2p": 0.0, + "ipp3p": 0.0, + "idd5b": 0.0, + "idd5f": 0.0, + "ipp5b": 0.0, + "ipp5f": 0.0, + "vddq": 0.0, + "iBeta_vdd": 0.0, + "iBeta_vpp": 0.0 + }, + "memimpedancespec": { + "ck_termination": true, + "ck_R_eq": 1e6, + "ck_dyn_E": 1e-12, + + "ca_termination": true, + "ca_R_eq": 1e6, + "ca_dyn_E": 1e-12, + + "rdq_termination": true, + "rdq_R_eq": 1e6, + "rdq_dyn_E": 1e-12, + "wdq_termination": true, + "wdq_R_eq": 1e6, + "wdq_dyn_E": 1e-12, + + "wdqs_termination": true, + "wdqs_R_eq": 1e6, + "wdqs_dyn_E": 1e-12, + "rdqs_termination": true, + "rdqs_R_eq": 1e6, + "rdqs_dyn_E": 1e-12 + }, + "dataratespec": { + "ca_bus_rate": 2, + "dq_bus_rate": 2, + "dqs_bus_rate": 2 + }, + "bankwisespec": { + "factRho": 1 } } } diff --git a/configs/memspec/JEDEC_2x8x2Gbx4_DDR5-5200A.json b/configs/memspec/JEDEC_2x8x2Gbx4_DDR5-5200A.json index 471a83a0..52fbe213 100644 --- a/configs/memspec/JEDEC_2x8x2Gbx4_DDR5-5200A.json +++ b/configs/memspec/JEDEC_2x8x2Gbx4_DDR5-5200A.json @@ -15,10 +15,11 @@ "nbrOfDevices": 8, "nbrOfChannels": 2, "cmdMode": 1, - "refMode": 1, + "RefMode": 1, "RAAIMT" : 16, "RAAMMT" : 96, - "RAADEC" : 16 + "RAADEC" : 16, + "maxBurstLength": 16 }, "memoryId": "JEDEC_2x8x2Gbx4_DDR5-5200A", "memoryType": "DDR5", @@ -74,7 +75,67 @@ "ACTPDEN": 2, "PRPDEN": 2, "REFPDEN": 2, - "tCK": 385 + "tCK": 385e-12 + }, + "mempowerspec": { + "vdd": 0.0, + "idd0": 0.0, + "idd2n": 0.0, + "idd3n": 0.0, + "idd4r": 0.0, + "idd4w": 0.0, + "idd5c": 0.0, + "idd6n": 0.0, + "idd2p": 0.0, + "idd3p": 0.0, + "vpp": 0.0, + "ipp0": 0.0, + "ipp2n": 0.0, + "ipp3n": 0.0, + "ipp4r": 0.0, + "ipp4w": 0.0, + "ipp5c": 0.0, + "ipp6n": 0.0, + "ipp2p": 0.0, + "ipp3p": 0.0, + "idd5b": 0.0, + "idd5f": 0.0, + "ipp5b": 0.0, + "ipp5f": 0.0, + "vddq": 0.0, + "iBeta_vdd": 0.0, + "iBeta_vpp": 0.0 + }, + "memimpedancespec": { + "ck_termination": true, + "ck_R_eq": 1e6, + "ck_dyn_E": 1e-12, + + "ca_termination": true, + "ca_R_eq": 1e6, + "ca_dyn_E": 1e-12, + + "rdq_termination": true, + "rdq_R_eq": 1e6, + "rdq_dyn_E": 1e-12, + "wdq_termination": true, + "wdq_R_eq": 1e6, + "wdq_dyn_E": 1e-12, + + "wdqs_termination": true, + "wdqs_R_eq": 1e6, + "wdqs_dyn_E": 1e-12, + "rdqs_termination": true, + "rdqs_R_eq": 1e6, + "rdqs_dyn_E": 1e-12 + }, + "dataratespec": { + "ca_bus_rate": 2, + "dq_bus_rate": 2, + "dqs_bus_rate": 2 + }, + "bankwisespec": { + "factRho": 1 } } } diff --git a/configs/memspec/JEDEC_2x8x2Gbx4_DDR5-5600A.json b/configs/memspec/JEDEC_2x8x2Gbx4_DDR5-5600A.json index a7f83827..504ca05c 100644 --- a/configs/memspec/JEDEC_2x8x2Gbx4_DDR5-5600A.json +++ b/configs/memspec/JEDEC_2x8x2Gbx4_DDR5-5600A.json @@ -15,10 +15,11 @@ "nbrOfDevices": 8, "nbrOfChannels": 2, "cmdMode": 1, - "refMode": 1, + "RefMode": 1, "RAAIMT" : 16, "RAAMMT" : 96, - "RAADEC" : 16 + "RAADEC" : 16, + "maxBurstLength": 16 }, "memoryId": "JEDEC_2x8x2Gbx4_DDR5-5600A", "memoryType": "DDR5", @@ -74,7 +75,67 @@ "ACTPDEN": 2, "PRPDEN": 2, "REFPDEN": 2, - "tCK": 357 + "tCK": 357e-12 + }, + "mempowerspec": { + "vdd": 0.0, + "idd0": 0.0, + "idd2n": 0.0, + "idd3n": 0.0, + "idd4r": 0.0, + "idd4w": 0.0, + "idd5c": 0.0, + "idd6n": 0.0, + "idd2p": 0.0, + "idd3p": 0.0, + "vpp": 0.0, + "ipp0": 0.0, + "ipp2n": 0.0, + "ipp3n": 0.0, + "ipp4r": 0.0, + "ipp4w": 0.0, + "ipp5c": 0.0, + "ipp6n": 0.0, + "ipp2p": 0.0, + "ipp3p": 0.0, + "idd5b": 0.0, + "idd5f": 0.0, + "ipp5b": 0.0, + "ipp5f": 0.0, + "vddq": 0.0, + "iBeta_vdd": 0.0, + "iBeta_vpp": 0.0 + }, + "memimpedancespec": { + "ck_termination": true, + "ck_R_eq": 1e6, + "ck_dyn_E": 1e-12, + + "ca_termination": true, + "ca_R_eq": 1e6, + "ca_dyn_E": 1e-12, + + "rdq_termination": true, + "rdq_R_eq": 1e6, + "rdq_dyn_E": 1e-12, + "wdq_termination": true, + "wdq_R_eq": 1e6, + "wdq_dyn_E": 1e-12, + + "wdqs_termination": true, + "wdqs_R_eq": 1e6, + "wdqs_dyn_E": 1e-12, + "rdqs_termination": true, + "rdqs_R_eq": 1e6, + "rdqs_dyn_E": 1e-12 + }, + "dataratespec": { + "ca_bus_rate": 2, + "dq_bus_rate": 2, + "dqs_bus_rate": 2 + }, + "bankwisespec": { + "factRho": 1 } } } diff --git a/configs/memspec/JEDEC_2x8x2Gbx4_DDR5-6000A.json b/configs/memspec/JEDEC_2x8x2Gbx4_DDR5-6000A.json index 6e09cc97..76fb4b4e 100644 --- a/configs/memspec/JEDEC_2x8x2Gbx4_DDR5-6000A.json +++ b/configs/memspec/JEDEC_2x8x2Gbx4_DDR5-6000A.json @@ -15,10 +15,11 @@ "nbrOfDevices": 8, "nbrOfChannels": 2, "cmdMode": 1, - "refMode": 1, + "RefMode": 1, "RAAIMT" : 16, "RAAMMT" : 96, - "RAADEC" : 16 + "RAADEC" : 16, + "maxBurstLength": 16 }, "memoryId": "JEDEC_2x8x2Gbx4_DDR5-6000A", "memoryType": "DDR5", @@ -74,7 +75,67 @@ "ACTPDEN": 2, "PRPDEN": 2, "REFPDEN": 2, - "tCK": 333 + "tCK": 333e-12 + }, + "mempowerspec": { + "vdd": 0.0, + "idd0": 0.0, + "idd2n": 0.0, + "idd3n": 0.0, + "idd4r": 0.0, + "idd4w": 0.0, + "idd5c": 0.0, + "idd6n": 0.0, + "idd2p": 0.0, + "idd3p": 0.0, + "vpp": 0.0, + "ipp0": 0.0, + "ipp2n": 0.0, + "ipp3n": 0.0, + "ipp4r": 0.0, + "ipp4w": 0.0, + "ipp5c": 0.0, + "ipp6n": 0.0, + "ipp2p": 0.0, + "ipp3p": 0.0, + "idd5b": 0.0, + "idd5f": 0.0, + "ipp5b": 0.0, + "ipp5f": 0.0, + "vddq": 0.0, + "iBeta_vdd": 0.0, + "iBeta_vpp": 0.0 + }, + "memimpedancespec": { + "ck_termination": true, + "ck_R_eq": 1e6, + "ck_dyn_E": 1e-12, + + "ca_termination": true, + "ca_R_eq": 1e6, + "ca_dyn_E": 1e-12, + + "rdq_termination": true, + "rdq_R_eq": 1e6, + "rdq_dyn_E": 1e-12, + "wdq_termination": true, + "wdq_R_eq": 1e6, + "wdq_dyn_E": 1e-12, + + "wdqs_termination": true, + "wdqs_R_eq": 1e6, + "wdqs_dyn_E": 1e-12, + "rdqs_termination": true, + "rdqs_R_eq": 1e6, + "rdqs_dyn_E": 1e-12 + }, + "dataratespec": { + "ca_bus_rate": 2, + "dq_bus_rate": 2, + "dqs_bus_rate": 2 + }, + "bankwisespec": { + "factRho": 1 } } } diff --git a/configs/memspec/JEDEC_2x8x2Gbx4_DDR5-6400A.json b/configs/memspec/JEDEC_2x8x2Gbx4_DDR5-6400A.json index 53e6945d..8472159e 100644 --- a/configs/memspec/JEDEC_2x8x2Gbx4_DDR5-6400A.json +++ b/configs/memspec/JEDEC_2x8x2Gbx4_DDR5-6400A.json @@ -15,10 +15,11 @@ "nbrOfDevices": 8, "nbrOfChannels": 2, "cmdMode": 1, - "refMode": 1, + "RefMode": 1, "RAAIMT" : 16, "RAAMMT" : 96, - "RAADEC" : 16 + "RAADEC" : 16, + "maxBurstLength": 16 }, "memoryId": "JEDEC_2x8x2Gbx4_DDR5-6400A", "memoryType": "DDR5", @@ -74,7 +75,67 @@ "ACTPDEN": 2, "PRPDEN": 2, "REFPDEN": 2, - "tCK": 313 + "tCK": 313e-12 + }, + "mempowerspec": { + "vdd": 0.0, + "idd0": 0.0, + "idd2n": 0.0, + "idd3n": 0.0, + "idd4r": 0.0, + "idd4w": 0.0, + "idd5c": 0.0, + "idd6n": 0.0, + "idd2p": 0.0, + "idd3p": 0.0, + "vpp": 0.0, + "ipp0": 0.0, + "ipp2n": 0.0, + "ipp3n": 0.0, + "ipp4r": 0.0, + "ipp4w": 0.0, + "ipp5c": 0.0, + "ipp6n": 0.0, + "ipp2p": 0.0, + "ipp3p": 0.0, + "idd5b": 0.0, + "idd5f": 0.0, + "ipp5b": 0.0, + "ipp5f": 0.0, + "vddq": 0.0, + "iBeta_vdd": 0.0, + "iBeta_vpp": 0.0 + }, + "memimpedancespec": { + "ck_termination": true, + "ck_R_eq": 1e6, + "ck_dyn_E": 1e-12, + + "ca_termination": true, + "ca_R_eq": 1e6, + "ca_dyn_E": 1e-12, + + "rdq_termination": true, + "rdq_R_eq": 1e6, + "rdq_dyn_E": 1e-12, + "wdq_termination": true, + "wdq_R_eq": 1e6, + "wdq_dyn_E": 1e-12, + + "wdqs_termination": true, + "wdqs_R_eq": 1e6, + "wdqs_dyn_E": 1e-12, + "rdqs_termination": true, + "rdqs_R_eq": 1e6, + "rdqs_dyn_E": 1e-12 + }, + "dataratespec": { + "ca_bus_rate": 2, + "dq_bus_rate": 2, + "dqs_bus_rate": 2 + }, + "bankwisespec": { + "factRho": 1 } } } diff --git a/configs/memspec/JEDEC_2x8x8x2Gbx4_DDR5-3200A.json b/configs/memspec/JEDEC_2x8x8x2Gbx4_DDR5-3200A.json index 85588a6b..dc992f3b 100644 --- a/configs/memspec/JEDEC_2x8x8x2Gbx4_DDR5-3200A.json +++ b/configs/memspec/JEDEC_2x8x8x2Gbx4_DDR5-3200A.json @@ -15,10 +15,11 @@ "nbrOfDevices": 8, "nbrOfChannels": 2, "cmdMode": 1, - "refMode": 1, + "RefMode": 1, "RAAIMT" : 16, "RAAMMT" : 96, - "RAADEC" : 16 + "RAADEC" : 16, + "maxBurstLength": 16 }, "memoryId": "JEDEC_2x8x8x8Gbx4_DDR5-3200A_4bit", "memoryType": "DDR5", @@ -74,7 +75,67 @@ "ACTPDEN": 2, "PRPDEN": 2, "REFPDEN": 2, - "tCK": 625 + "tCK": 625e-12 + }, + "mempowerspec": { + "vdd": 0.0, + "idd0": 0.0, + "idd2n": 0.0, + "idd3n": 0.0, + "idd4r": 0.0, + "idd4w": 0.0, + "idd5c": 0.0, + "idd6n": 0.0, + "idd2p": 0.0, + "idd3p": 0.0, + "vpp": 0.0, + "ipp0": 0.0, + "ipp2n": 0.0, + "ipp3n": 0.0, + "ipp4r": 0.0, + "ipp4w": 0.0, + "ipp5c": 0.0, + "ipp6n": 0.0, + "ipp2p": 0.0, + "ipp3p": 0.0, + "idd5b": 0.0, + "idd5f": 0.0, + "ipp5b": 0.0, + "ipp5f": 0.0, + "vddq": 0.0, + "iBeta_vdd": 0.0, + "iBeta_vpp": 0.0 + }, + "memimpedancespec": { + "ck_termination": true, + "ck_R_eq": 1e6, + "ck_dyn_E": 1e-12, + + "ca_termination": true, + "ca_R_eq": 1e6, + "ca_dyn_E": 1e-12, + + "rdq_termination": true, + "rdq_R_eq": 1e6, + "rdq_dyn_E": 1e-12, + "wdq_termination": true, + "wdq_R_eq": 1e6, + "wdq_dyn_E": 1e-12, + + "wdqs_termination": true, + "wdqs_R_eq": 1e6, + "wdqs_dyn_E": 1e-12, + "rdqs_termination": true, + "rdqs_R_eq": 1e6, + "rdqs_dyn_E": 1e-12 + }, + "dataratespec": { + "ca_bus_rate": 2, + "dq_bus_rate": 2, + "dqs_bus_rate": 2 + }, + "bankwisespec": { + "factRho": 1 } } } diff --git a/configs/memspec/JEDEC_4Gb_DDR4-1866_8bit_A.json b/configs/memspec/JEDEC_4Gb_DDR4-1866_8bit_A.json index 7b9a216c..ebc838ad 100644 --- a/configs/memspec/JEDEC_4Gb_DDR4-1866_8bit_A.json +++ b/configs/memspec/JEDEC_4Gb_DDR4-1866_8bit_A.json @@ -9,27 +9,44 @@ "nbrOfRanks": 1, "nbrOfRows": 32768, "width": 8, + "RefMode": 1, "nbrOfDevices": 8, - "nbrOfChannels": 1 + "nbrOfChannels": 1, + "maxBurstLength": 8 }, "memoryId": "MICRON_4Gb_DDR4-1866_8bit_A", "memoryType": "DDR4", "mempowerspec": { - "idd0": 56.25, - "idd02": 4.05, - "idd2n": 33.75, - "idd2p0": 17.0, - "idd2p1": 17.0, - "idd3n": 39.5, - "idd3p0": 22.5, - "idd3p1": 22.5, - "idd4r": 157.5, - "idd4w": 135.0, - "idd5": 118.0, - "idd6": 20.25, - "idd62": 2.6, "vdd": 1.2, - "vdd2": 2.5 + "idd0": 56.25e-3, + "idd2n": 33.75e-3, + "idd3n": 39.5e-3, + "idd4r": 157.5e-3, + "idd4w": 135.0e-3, + "idd6n": 20.25e-3, + "idd2p": 17.0e-3, + "idd3p": 22.5e-3, + + "vpp": 2.5, + "ipp0": 4.05e-3, + "ipp2n": 0, + "ipp3n": 0, + "ipp4r": 0, + "ipp4w": 0, + "ipp6n": 2.6e-3, + "ipp2p": 17.0e-3, + "ipp3p": 22.5e-3, + + "idd5B": 118.0e-3, + "ipp5B": 0.0, + "idd5F2": 0.0, + "ipp5F2": 0.0, + "idd5F4": 0.0, + "ipp5F4": 0.0, + "vddq": 0.0, + + "iBeta_vdd": 56.25e-3, + "iBeta_vpp": 4.05e-3 }, "memtimingspec": { "AL": 0, @@ -45,7 +62,7 @@ "RCD": 13, "REFM": 1, "REFI": 7280, - "RFC": 243, + "RFC1": 243, "RFC2": 150, "RFC4": 103, "RL": 13, @@ -67,7 +84,45 @@ "PRPDEN": 1, "REFPDEN": 1, "RTRS": 1, - "tCK": 1072 + "tCK": 1072e-12 + }, + "bankwisespec": { + "factRho": 1.0 + }, + "memimpedancespec": { + "ck_termination": true, + "ck_R_eq": 1e6, + "ck_dyn_E": 1e-12, + + "ca_termination": true, + "ca_R_eq": 1e6, + "ca_dyn_E": 1e-12, + + "rdq_termination": true, + "rdq_R_eq": 1e6, + "rdq_dyn_E": 1e-12, + "wdq_termination": true, + "wdq_R_eq": 1e6, + "wdq_dyn_E": 1e-12, + + "wdqs_termination": true, + "wdqs_R_eq": 1e6, + "wdqs_dyn_E": 1e-12, + "rdqs_termination": true, + "rdqs_R_eq": 1e6, + "rdqs_dyn_E": 1e-12 + }, + "prepostamble": { + "read_zeroes": 0.0, + "write_zeroes": 0.0, + "read_ones": 0.0, + "write_ones": 0.0, + "read_zeroes_to_ones": 0, + "write_zeroes_to_ones": 0, + "write_ones_to_zeroes": 0, + "read_ones_to_zeroes": 0, + "readMinTccd": 0, + "writeMinTccd": 0 } } } diff --git a/configs/memspec/JEDEC_4Gb_DDR4-2400_8bit_A.json b/configs/memspec/JEDEC_4Gb_DDR4-2400_8bit_A.json index e82028c8..2c950fe0 100644 --- a/configs/memspec/JEDEC_4Gb_DDR4-2400_8bit_A.json +++ b/configs/memspec/JEDEC_4Gb_DDR4-2400_8bit_A.json @@ -10,26 +10,43 @@ "nbrOfRows": 32768, "width": 8, "nbrOfDevices": 8, - "nbrOfChannels": 1 + "nbrOfChannels": 1, + "RefMode": 1, + "maxBurstLength": 8 }, "memoryId": "MICRON_4Gb_DDR4-2400_8bit_A", "memoryType": "DDR4", "mempowerspec": { - "idd0": 60.75, - "idd02": 4.05, - "idd2n": 38.25, - "idd2p0": 17.0, - "idd2p1": 17.0, - "idd3n": 44.0, - "idd3p0": 22.5, - "idd3p1": 22.5, - "idd4r": 184.5, - "idd4w": 168.75, - "idd5": 118.0, - "idd6": 20.25, - "idd62": 2.6, "vdd": 1.2, - "vdd2": 2.5 + "idd0": 60.75e-3, + "idd2n": 38.25e-3, + "idd3n": 44.0e-3, + "idd4r": 184.5e-3, + "idd4w": 168.75e-3, + "idd6n": 20.25e-3, + "idd2p": 17.0e-3, + "idd3p": 22.5e-3, + + "vpp": 2.5, + "ipp0": 4.05e-3, + "ipp2n": 0, + "ipp3n": 0, + "ipp4r": 0, + "ipp4w": 0, + "ipp6n": 2.6e-3, + "ipp2p": 17.0e-3, + "ipp3p": 22.5e-3, + + "idd5B": 118.0e-3, + "ipp5B": 0.0, + "idd5F2": 0.0, + "ipp5F2": 0.0, + "idd5F4": 0.0, + "ipp5F4": 0.0, + "vddq": 0.0, + + "iBeta_vdd": 60.75e-3, + "iBeta_vpp": 4.05e-3 }, "memtimingspec": { "AL": 0, @@ -45,7 +62,7 @@ "RCD": 16, "REFM": 1, "REFI": 9360, - "RFC": 312, + "RFC1": 312, "RFC2": 192, "RFC4": 132, "RL": 16, @@ -67,7 +84,45 @@ "PRPDEN": 2, "REFPDEN": 2, "RTRS": 1, - "tCK": 833 + "tCK": 833e-12 + }, + "bankwisespec": { + "factRho": 1.0 + }, + "memimpedancespec": { + "ck_termination": true, + "ck_R_eq": 1e6, + "ck_dyn_E": 1e-12, + + "ca_termination": true, + "ca_R_eq": 1e6, + "ca_dyn_E": 1e-12, + + "rdq_termination": true, + "rdq_R_eq": 1e6, + "rdq_dyn_E": 1e-12, + "wdq_termination": true, + "wdq_R_eq": 1e6, + "wdq_dyn_E": 1e-12, + + "wdqs_termination": true, + "wdqs_R_eq": 1e6, + "wdqs_dyn_E": 1e-12, + "rdqs_termination": true, + "rdqs_R_eq": 1e6, + "rdqs_dyn_E": 1e-12 + }, + "prepostamble": { + "read_zeroes": 0.0, + "write_zeroes": 0.0, + "read_ones": 0.0, + "write_ones": 0.0, + "read_zeroes_to_ones": 0, + "write_zeroes_to_ones": 0, + "write_ones_to_zeroes": 0, + "read_ones_to_zeroes": 0, + "readMinTccd": 0, + "writeMinTccd": 0 } } } diff --git a/configs/memspec/JEDEC_4x64_2Gb_WIDEIO2-400_64bit.json b/configs/memspec/JEDEC_4x64_2Gb_WIDEIO2-400_64bit.json index c755675b..630df1dd 100644 --- a/configs/memspec/JEDEC_4x64_2Gb_WIDEIO2-400_64bit.json +++ b/configs/memspec/JEDEC_4x64_2Gb_WIDEIO2-400_64bit.json @@ -9,7 +9,8 @@ "nbrOfRows": 8192, "width": 64, "nbrOfDevices": 1, - "nbrOfChannels": 4 + "nbrOfChannels": 4, + "maxBurstLength": 4 }, "memoryId": "JEDEC_4x64_2Gb_WIDEIO2-400_64bit", "memoryType": "WIDEIO2", @@ -38,7 +39,10 @@ "XP": 3, "XSR": 76, "RTRS": 1, - "tCK": 2500 + "tCK": 2500e-12, + + "DQSCK": 0, + "DQSS": 0 } } } diff --git a/configs/memspec/JEDEC_4x64_2Gb_WIDEIO2-533_64bit.json b/configs/memspec/JEDEC_4x64_2Gb_WIDEIO2-533_64bit.json index 9df9e7f6..20e0ad79 100644 --- a/configs/memspec/JEDEC_4x64_2Gb_WIDEIO2-533_64bit.json +++ b/configs/memspec/JEDEC_4x64_2Gb_WIDEIO2-533_64bit.json @@ -9,7 +9,8 @@ "nbrOfRows": 8192, "width": 64, "nbrOfDevices": 1, - "nbrOfChannels": 4 + "nbrOfChannels": 4, + "maxBurstLength": 4 }, "memoryId": "JEDEC_4x64_2Gb_WIDEIO2-533_64bit", "memoryType": "WIDEIO2", @@ -38,7 +39,10 @@ "XP": 4, "XSR": 102, "RTRS": 1, - "tCK": 1876 + "tCK": 1876e-12, + + "DQSCK": 0, + "DQSS": 0 } } } diff --git a/configs/memspec/JEDEC_512Mbx16_16B_LPDDR5-0533.json b/configs/memspec/JEDEC_512Mbx16_16B_LPDDR5-0533.json index 694df813..563d15bb 100644 --- a/configs/memspec/JEDEC_512Mbx16_16B_LPDDR5-0533.json +++ b/configs/memspec/JEDEC_512Mbx16_16B_LPDDR5-0533.json @@ -11,7 +11,77 @@ "nbrOfDevices": 1, "nbrOfChannels": 1, "width": 16, - "per2BankOffset": 8 + "per2BankOffset": 8, + "WCKalwaysOn": false, + "maxBurstLength": 16 + }, + "mempowerspec": { + "vdd1": 0.0, + "idd01": 0.0, + "idd2n1": 0.0, + "idd3n1": 0.0, + "idd4r1": 0.0, + "idd4w1": 0.0, + "idd51": 0.0, + "idd5pb1": 0.0, + "idd61": 0.0, + "idd6ds1": 0.0, + "idd2p1": 0.0, + "idd3p1": 0.0, + "vdd2h": 0.0, + "idd02h": 0.0, + "idd2n2h": 0.0, + "idd3n2h": 0.0, + "idd4r2h": 0.0, + "idd4w2h": 0.0, + "idd52h": 0.0, + "idd5pb2h": 0.0, + "idd62h": 0.0, + "idd6ds2h": 0.0, + "idd2p2h": 0.0, + "idd3p2h": 0.0, + "vdd2l": 0.0, + "idd02l": 0.0, + "idd2n2l": 0.0, + "idd3n2l": 0.0, + "idd4r2l": 0.0, + "idd4w2l": 0.0, + "idd52l": 0.0, + "idd5pb2l": 0.0, + "idd62l": 0.0, + "idd6ds2l": 0.0, + "idd2p2l": 0.0, + "idd3p2l": 0.0, + "vddq": 0.0, + "iBeta_vdd1": 0.0, + "iBeta_vdd2h": 0.0, + "iBeta_vdd2l": 0.0 + }, + "bankwisespec": { + "factRho": 1.0 + }, + "memimpedancespec": { + "ck_termination": true, + "ck_R_eq": 1e6, + "ck_dyn_E": 1e-12, + + "ca_termination": true, + "ca_R_eq": 1e6, + "ca_dyn_E": 1e-12, + + "rdq_termination": true, + "rdq_R_eq": 1e6, + "rdq_dyn_E": 1e-12, + "wdq_termination": true, + "wdq_R_eq": 1e6, + "wdq_dyn_E": 1e-12, + + "wck_termination": true, + "wck_R_eq": 1e6, + "wck_dyn_E": 1e-12, + "rdqs_termination": true, + "rdqs_R_eq": 1e6, + "rdqs_dyn_E": 1e-12 }, "memoryId": "JEDEC_512Mbx16_16B_LPDDR5-0533", "memoryType": "LPDDR5", @@ -55,7 +125,7 @@ "BL_n_S_32": 8, "pbR2act": 1, "pbR2pbR": 12, - "tCK": 7519 + "tCK": 7519e-12 } } } diff --git a/configs/memspec/JEDEC_512Mbx16_16B_LPDDR5-1067.json b/configs/memspec/JEDEC_512Mbx16_16B_LPDDR5-1067.json index 99265fea..00ecb888 100644 --- a/configs/memspec/JEDEC_512Mbx16_16B_LPDDR5-1067.json +++ b/configs/memspec/JEDEC_512Mbx16_16B_LPDDR5-1067.json @@ -11,7 +11,77 @@ "nbrOfDevices": 1, "nbrOfChannels": 1, "width": 16, - "per2BankOffset": 8 + "per2BankOffset": 8, + "WCKalwaysOn": false, + "maxBurstLength": 16 + }, + "mempowerspec": { + "vdd1": 0.0, + "idd01": 0.0, + "idd2n1": 0.0, + "idd3n1": 0.0, + "idd4r1": 0.0, + "idd4w1": 0.0, + "idd51": 0.0, + "idd5pb1": 0.0, + "idd61": 0.0, + "idd6ds1": 0.0, + "idd2p1": 0.0, + "idd3p1": 0.0, + "vdd2h": 0.0, + "idd02h": 0.0, + "idd2n2h": 0.0, + "idd3n2h": 0.0, + "idd4r2h": 0.0, + "idd4w2h": 0.0, + "idd52h": 0.0, + "idd5pb2h": 0.0, + "idd62h": 0.0, + "idd6ds2h": 0.0, + "idd2p2h": 0.0, + "idd3p2h": 0.0, + "vdd2l": 0.0, + "idd02l": 0.0, + "idd2n2l": 0.0, + "idd3n2l": 0.0, + "idd4r2l": 0.0, + "idd4w2l": 0.0, + "idd52l": 0.0, + "idd5pb2l": 0.0, + "idd62l": 0.0, + "idd6ds2l": 0.0, + "idd2p2l": 0.0, + "idd3p2l": 0.0, + "vddq": 0.0, + "iBeta_vdd1": 0.0, + "iBeta_vdd2h": 0.0, + "iBeta_vdd2l": 0.0 + }, + "bankwisespec": { + "factRho": 1.0 + }, + "memimpedancespec": { + "ck_termination": true, + "ck_R_eq": 1e6, + "ck_dyn_E": 1e-12, + + "ca_termination": true, + "ca_R_eq": 1e6, + "ca_dyn_E": 1e-12, + + "rdq_termination": true, + "rdq_R_eq": 1e6, + "rdq_dyn_E": 1e-12, + "wdq_termination": true, + "wdq_R_eq": 1e6, + "wdq_dyn_E": 1e-12, + + "wck_termination": true, + "wck_R_eq": 1e6, + "wck_dyn_E": 1e-12, + "rdqs_termination": true, + "rdqs_R_eq": 1e6, + "rdqs_dyn_E": 1e-12 }, "memoryId": "JEDEC_512Mbx16_16B_LPDDR5-1067", "memoryType": "LPDDR5", @@ -55,7 +125,7 @@ "BL_n_S_32": 8, "pbR2act": 2, "pbR2pbR": 24, - "tCK": 3745 + "tCK": 3745e-12 } } } diff --git a/configs/memspec/JEDEC_512Mbx16_16B_LPDDR5-1600.json b/configs/memspec/JEDEC_512Mbx16_16B_LPDDR5-1600.json index 15fa9a2d..470dc4f7 100644 --- a/configs/memspec/JEDEC_512Mbx16_16B_LPDDR5-1600.json +++ b/configs/memspec/JEDEC_512Mbx16_16B_LPDDR5-1600.json @@ -11,7 +11,77 @@ "nbrOfDevices": 1, "nbrOfChannels": 1, "width": 16, - "per2BankOffset": 8 + "per2BankOffset": 8, + "WCKalwaysOn": false, + "maxBurstLength": 16 + }, + "mempowerspec": { + "vdd1": 0.0, + "idd01": 0.0, + "idd2n1": 0.0, + "idd3n1": 0.0, + "idd4r1": 0.0, + "idd4w1": 0.0, + "idd51": 0.0, + "idd5pb1": 0.0, + "idd61": 0.0, + "idd6ds1": 0.0, + "idd2p1": 0.0, + "idd3p1": 0.0, + "vdd2h": 0.0, + "idd02h": 0.0, + "idd2n2h": 0.0, + "idd3n2h": 0.0, + "idd4r2h": 0.0, + "idd4w2h": 0.0, + "idd52h": 0.0, + "idd5pb2h": 0.0, + "idd62h": 0.0, + "idd6ds2h": 0.0, + "idd2p2h": 0.0, + "idd3p2h": 0.0, + "vdd2l": 0.0, + "idd02l": 0.0, + "idd2n2l": 0.0, + "idd3n2l": 0.0, + "idd4r2l": 0.0, + "idd4w2l": 0.0, + "idd52l": 0.0, + "idd5pb2l": 0.0, + "idd62l": 0.0, + "idd6ds2l": 0.0, + "idd2p2l": 0.0, + "idd3p2l": 0.0, + "vddq": 0.0, + "iBeta_vdd1": 0.0, + "iBeta_vdd2h": 0.0, + "iBeta_vdd2l": 0.0 + }, + "bankwisespec": { + "factRho": 1.0 + }, + "memimpedancespec": { + "ck_termination": true, + "ck_R_eq": 1e6, + "ck_dyn_E": 1e-12, + + "ca_termination": true, + "ca_R_eq": 1e6, + "ca_dyn_E": 1e-12, + + "rdq_termination": true, + "rdq_R_eq": 1e6, + "rdq_dyn_E": 1e-12, + "wdq_termination": true, + "wdq_R_eq": 1e6, + "wdq_dyn_E": 1e-12, + + "wck_termination": true, + "wck_R_eq": 1e6, + "wck_dyn_E": 1e-12, + "rdqs_termination": true, + "rdqs_R_eq": 1e6, + "rdqs_dyn_E": 1e-12 }, "memoryId": "JEDEC_512Mbx16_16B_LPDDR5-1600", "memoryType": "LPDDR5", @@ -55,7 +125,7 @@ "BL_n_S_32": 8, "pbR2act": 3, "pbR2pbR": 36, - "tCK": 2500 + "tCK": 2500e-12 } } } diff --git a/configs/memspec/JEDEC_512Mbx16_16B_LPDDR5-2133.json b/configs/memspec/JEDEC_512Mbx16_16B_LPDDR5-2133.json index 501b5e11..82840225 100644 --- a/configs/memspec/JEDEC_512Mbx16_16B_LPDDR5-2133.json +++ b/configs/memspec/JEDEC_512Mbx16_16B_LPDDR5-2133.json @@ -11,7 +11,77 @@ "nbrOfDevices": 1, "nbrOfChannels": 1, "width": 16, - "per2BankOffset": 8 + "per2BankOffset": 8, + "WCKalwaysOn": false, + "maxBurstLength": 16 + }, + "mempowerspec": { + "vdd1": 0.0, + "idd01": 0.0, + "idd2n1": 0.0, + "idd3n1": 0.0, + "idd4r1": 0.0, + "idd4w1": 0.0, + "idd51": 0.0, + "idd5pb1": 0.0, + "idd61": 0.0, + "idd6ds1": 0.0, + "idd2p1": 0.0, + "idd3p1": 0.0, + "vdd2h": 0.0, + "idd02h": 0.0, + "idd2n2h": 0.0, + "idd3n2h": 0.0, + "idd4r2h": 0.0, + "idd4w2h": 0.0, + "idd52h": 0.0, + "idd5pb2h": 0.0, + "idd62h": 0.0, + "idd6ds2h": 0.0, + "idd2p2h": 0.0, + "idd3p2h": 0.0, + "vdd2l": 0.0, + "idd02l": 0.0, + "idd2n2l": 0.0, + "idd3n2l": 0.0, + "idd4r2l": 0.0, + "idd4w2l": 0.0, + "idd52l": 0.0, + "idd5pb2l": 0.0, + "idd62l": 0.0, + "idd6ds2l": 0.0, + "idd2p2l": 0.0, + "idd3p2l": 0.0, + "vddq": 0.0, + "iBeta_vdd1": 0.0, + "iBeta_vdd2h": 0.0, + "iBeta_vdd2l": 0.0 + }, + "bankwisespec": { + "factRho": 1.0 + }, + "memimpedancespec": { + "ck_termination": true, + "ck_R_eq": 1e6, + "ck_dyn_E": 1e-12, + + "ca_termination": true, + "ca_R_eq": 1e6, + "ca_dyn_E": 1e-12, + + "rdq_termination": true, + "rdq_R_eq": 1e6, + "rdq_dyn_E": 1e-12, + "wdq_termination": true, + "wdq_R_eq": 1e6, + "wdq_dyn_E": 1e-12, + + "wck_termination": true, + "wck_R_eq": 1e6, + "wck_dyn_E": 1e-12, + "rdqs_termination": true, + "rdqs_R_eq": 1e6, + "rdqs_dyn_E": 1e-12 }, "memoryId": "JEDEC_512Mbx16_16B_LPDDR5-2133", "memoryType": "LPDDR5", @@ -55,7 +125,7 @@ "BL_n_S_32": 8, "pbR2act": 4, "pbR2pbR": 48, - "tCK": 1876 + "tCK": 1876e-12 } } } diff --git a/configs/memspec/JEDEC_512Mbx16_16B_LPDDR5-2750.json b/configs/memspec/JEDEC_512Mbx16_16B_LPDDR5-2750.json index c5958ac5..d1b75611 100644 --- a/configs/memspec/JEDEC_512Mbx16_16B_LPDDR5-2750.json +++ b/configs/memspec/JEDEC_512Mbx16_16B_LPDDR5-2750.json @@ -11,7 +11,77 @@ "nbrOfDevices": 1, "nbrOfChannels": 1, "width": 16, - "per2BankOffset": 8 + "per2BankOffset": 8, + "WCKalwaysOn": false, + "maxBurstLength": 16 + }, + "mempowerspec": { + "vdd1": 0.0, + "idd01": 0.0, + "idd2n1": 0.0, + "idd3n1": 0.0, + "idd4r1": 0.0, + "idd4w1": 0.0, + "idd51": 0.0, + "idd5pb1": 0.0, + "idd61": 0.0, + "idd6ds1": 0.0, + "idd2p1": 0.0, + "idd3p1": 0.0, + "vdd2h": 0.0, + "idd02h": 0.0, + "idd2n2h": 0.0, + "idd3n2h": 0.0, + "idd4r2h": 0.0, + "idd4w2h": 0.0, + "idd52h": 0.0, + "idd5pb2h": 0.0, + "idd62h": 0.0, + "idd6ds2h": 0.0, + "idd2p2h": 0.0, + "idd3p2h": 0.0, + "vdd2l": 0.0, + "idd02l": 0.0, + "idd2n2l": 0.0, + "idd3n2l": 0.0, + "idd4r2l": 0.0, + "idd4w2l": 0.0, + "idd52l": 0.0, + "idd5pb2l": 0.0, + "idd62l": 0.0, + "idd6ds2l": 0.0, + "idd2p2l": 0.0, + "idd3p2l": 0.0, + "vddq": 0.0, + "iBeta_vdd1": 0.0, + "iBeta_vdd2h": 0.0, + "iBeta_vdd2l": 0.0 + }, + "bankwisespec": { + "factRho": 1.0 + }, + "memimpedancespec": { + "ck_termination": true, + "ck_R_eq": 1e6, + "ck_dyn_E": 1e-12, + + "ca_termination": true, + "ca_R_eq": 1e6, + "ca_dyn_E": 1e-12, + + "rdq_termination": true, + "rdq_R_eq": 1e6, + "rdq_dyn_E": 1e-12, + "wdq_termination": true, + "wdq_R_eq": 1e6, + "wdq_dyn_E": 1e-12, + + "wck_termination": true, + "wck_R_eq": 1e6, + "wck_dyn_E": 1e-12, + "rdqs_termination": true, + "rdqs_R_eq": 1e6, + "rdqs_dyn_E": 1e-12 }, "memoryId": "JEDEC_512Mbx16_16B_LPDDR5-2750", "memoryType": "LPDDR5", @@ -55,7 +125,7 @@ "BL_n_S_32": 8, "pbR2act": 6, "pbR2pbR": 62, - "tCK": 1453 + "tCK": 1453e-12 } } } diff --git a/configs/memspec/JEDEC_512Mbx16_16B_LPDDR5-3200.json b/configs/memspec/JEDEC_512Mbx16_16B_LPDDR5-3200.json index 75e8bfb9..66533d03 100644 --- a/configs/memspec/JEDEC_512Mbx16_16B_LPDDR5-3200.json +++ b/configs/memspec/JEDEC_512Mbx16_16B_LPDDR5-3200.json @@ -11,7 +11,77 @@ "nbrOfDevices": 1, "nbrOfChannels": 1, "width": 16, - "per2BankOffset": 8 + "per2BankOffset": 8, + "WCKalwaysOn": false, + "maxBurstLength": 16 + }, + "mempowerspec": { + "vdd1": 0.0, + "idd01": 0.0, + "idd2n1": 0.0, + "idd3n1": 0.0, + "idd4r1": 0.0, + "idd4w1": 0.0, + "idd51": 0.0, + "idd5pb1": 0.0, + "idd61": 0.0, + "idd6ds1": 0.0, + "idd2p1": 0.0, + "idd3p1": 0.0, + "vdd2h": 0.0, + "idd02h": 0.0, + "idd2n2h": 0.0, + "idd3n2h": 0.0, + "idd4r2h": 0.0, + "idd4w2h": 0.0, + "idd52h": 0.0, + "idd5pb2h": 0.0, + "idd62h": 0.0, + "idd6ds2h": 0.0, + "idd2p2h": 0.0, + "idd3p2h": 0.0, + "vdd2l": 0.0, + "idd02l": 0.0, + "idd2n2l": 0.0, + "idd3n2l": 0.0, + "idd4r2l": 0.0, + "idd4w2l": 0.0, + "idd52l": 0.0, + "idd5pb2l": 0.0, + "idd62l": 0.0, + "idd6ds2l": 0.0, + "idd2p2l": 0.0, + "idd3p2l": 0.0, + "vddq": 0.0, + "iBeta_vdd1": 0.0, + "iBeta_vdd2h": 0.0, + "iBeta_vdd2l": 0.0 + }, + "bankwisespec": { + "factRho": 1.0 + }, + "memimpedancespec": { + "ck_termination": true, + "ck_R_eq": 1e6, + "ck_dyn_E": 1e-12, + + "ca_termination": true, + "ca_R_eq": 1e6, + "ca_dyn_E": 1e-12, + + "rdq_termination": true, + "rdq_R_eq": 1e6, + "rdq_dyn_E": 1e-12, + "wdq_termination": true, + "wdq_R_eq": 1e6, + "wdq_dyn_E": 1e-12, + + "wck_termination": true, + "wck_R_eq": 1e6, + "wck_dyn_E": 1e-12, + "rdqs_termination": true, + "rdqs_R_eq": 1e6, + "rdqs_dyn_E": 1e-12 }, "memoryId": "JEDEC_512Mbx16_16B_LPDDR5-3200", "memoryType": "LPDDR5", @@ -55,7 +125,7 @@ "BL_n_S_32": 8, "pbR2act": 6, "pbR2pbR": 72, - "tCK": 1250 + "tCK": 1250e-12 } } } diff --git a/configs/memspec/JEDEC_512Mbx16_16B_LPDDR5X-0533.json b/configs/memspec/JEDEC_512Mbx16_16B_LPDDR5X-0533.json index 00517e2b..10208959 100644 --- a/configs/memspec/JEDEC_512Mbx16_16B_LPDDR5X-0533.json +++ b/configs/memspec/JEDEC_512Mbx16_16B_LPDDR5X-0533.json @@ -11,7 +11,77 @@ "nbrOfDevices": 1, "nbrOfChannels": 1, "width": 16, - "per2BankOffset": 8 + "per2BankOffset": 8, + "WCKalwaysOn": false, + "maxBurstLength": 16 + }, + "mempowerspec": { + "vdd1": 0.0, + "idd01": 0.0, + "idd2n1": 0.0, + "idd3n1": 0.0, + "idd4r1": 0.0, + "idd4w1": 0.0, + "idd51": 0.0, + "idd5pb1": 0.0, + "idd61": 0.0, + "idd6ds1": 0.0, + "idd2p1": 0.0, + "idd3p1": 0.0, + "vdd2h": 0.0, + "idd02h": 0.0, + "idd2n2h": 0.0, + "idd3n2h": 0.0, + "idd4r2h": 0.0, + "idd4w2h": 0.0, + "idd52h": 0.0, + "idd5pb2h": 0.0, + "idd62h": 0.0, + "idd6ds2h": 0.0, + "idd2p2h": 0.0, + "idd3p2h": 0.0, + "vdd2l": 0.0, + "idd02l": 0.0, + "idd2n2l": 0.0, + "idd3n2l": 0.0, + "idd4r2l": 0.0, + "idd4w2l": 0.0, + "idd52l": 0.0, + "idd5pb2l": 0.0, + "idd62l": 0.0, + "idd6ds2l": 0.0, + "idd2p2l": 0.0, + "idd3p2l": 0.0, + "vddq": 0.0, + "iBeta_vdd1": 0.0, + "iBeta_vdd2h": 0.0, + "iBeta_vdd2l": 0.0 + }, + "bankwisespec": { + "factRho": 1.0 + }, + "memimpedancespec": { + "ck_termination": true, + "ck_R_eq": 1e6, + "ck_dyn_E": 1e-12, + + "ca_termination": true, + "ca_R_eq": 1e6, + "ca_dyn_E": 1e-12, + + "rdq_termination": true, + "rdq_R_eq": 1e6, + "rdq_dyn_E": 1e-12, + "wdq_termination": true, + "wdq_R_eq": 1e6, + "wdq_dyn_E": 1e-12, + + "wck_termination": true, + "wck_R_eq": 1e6, + "wck_dyn_E": 1e-12, + "rdqs_termination": true, + "rdqs_R_eq": 1e6, + "rdqs_dyn_E": 1e-12 }, "memoryId": "JEDEC_512Mbx16_16B_LPDDR5X-0533", "memoryType": "LPDDR5", @@ -57,7 +127,7 @@ "BL_n_S_32": 4, "pbR2act": 1, "pbR2pbR": 7, - "tCK": 14925 + "tCK": 14925e-12 } } } diff --git a/configs/memspec/JEDEC_512Mbx16_16B_LPDDR5X-1067.json b/configs/memspec/JEDEC_512Mbx16_16B_LPDDR5X-1067.json index 0eb4f9e1..6ac65765 100644 --- a/configs/memspec/JEDEC_512Mbx16_16B_LPDDR5X-1067.json +++ b/configs/memspec/JEDEC_512Mbx16_16B_LPDDR5X-1067.json @@ -11,7 +11,77 @@ "nbrOfDevices": 1, "nbrOfChannels": 1, "width": 16, - "per2BankOffset": 8 + "per2BankOffset": 8, + "WCKalwaysOn": false, + "maxBurstLength": 16 + }, + "mempowerspec": { + "vdd1": 0.0, + "idd01": 0.0, + "idd2n1": 0.0, + "idd3n1": 0.0, + "idd4r1": 0.0, + "idd4w1": 0.0, + "idd51": 0.0, + "idd5pb1": 0.0, + "idd61": 0.0, + "idd6ds1": 0.0, + "idd2p1": 0.0, + "idd3p1": 0.0, + "vdd2h": 0.0, + "idd02h": 0.0, + "idd2n2h": 0.0, + "idd3n2h": 0.0, + "idd4r2h": 0.0, + "idd4w2h": 0.0, + "idd52h": 0.0, + "idd5pb2h": 0.0, + "idd62h": 0.0, + "idd6ds2h": 0.0, + "idd2p2h": 0.0, + "idd3p2h": 0.0, + "vdd2l": 0.0, + "idd02l": 0.0, + "idd2n2l": 0.0, + "idd3n2l": 0.0, + "idd4r2l": 0.0, + "idd4w2l": 0.0, + "idd52l": 0.0, + "idd5pb2l": 0.0, + "idd62l": 0.0, + "idd6ds2l": 0.0, + "idd2p2l": 0.0, + "idd3p2l": 0.0, + "vddq": 0.0, + "iBeta_vdd1": 0.0, + "iBeta_vdd2h": 0.0, + "iBeta_vdd2l": 0.0 + }, + "bankwisespec": { + "factRho": 1.0 + }, + "memimpedancespec": { + "ck_termination": true, + "ck_R_eq": 1e6, + "ck_dyn_E": 1e-12, + + "ca_termination": true, + "ca_R_eq": 1e6, + "ca_dyn_E": 1e-12, + + "rdq_termination": true, + "rdq_R_eq": 1e6, + "rdq_dyn_E": 1e-12, + "wdq_termination": true, + "wdq_R_eq": 1e6, + "wdq_dyn_E": 1e-12, + + "wck_termination": true, + "wck_R_eq": 1e6, + "wck_dyn_E": 1e-12, + "rdqs_termination": true, + "rdqs_R_eq": 1e6, + "rdqs_dyn_E": 1e-12 }, "memoryId": "JEDEC_512Mbx16_16B_LPDDR5X-1067", "memoryType": "LPDDR5", @@ -57,7 +127,7 @@ "BL_n_S_32": 4, "pbR2act": 1, "pbR2pbR": 12, - "tCK": 7519 + "tCK": 7519e-12 } } } diff --git a/configs/memspec/JEDEC_512Mbx16_16B_LPDDR5X-1600.json b/configs/memspec/JEDEC_512Mbx16_16B_LPDDR5X-1600.json index 260f4540..b1798ff9 100644 --- a/configs/memspec/JEDEC_512Mbx16_16B_LPDDR5X-1600.json +++ b/configs/memspec/JEDEC_512Mbx16_16B_LPDDR5X-1600.json @@ -11,7 +11,77 @@ "nbrOfDevices": 1, "nbrOfChannels": 1, "width": 16, - "per2BankOffset": 8 + "per2BankOffset": 8, + "WCKalwaysOn": false, + "maxBurstLength": 16 + }, + "mempowerspec": { + "vdd1": 0.0, + "idd01": 0.0, + "idd2n1": 0.0, + "idd3n1": 0.0, + "idd4r1": 0.0, + "idd4w1": 0.0, + "idd51": 0.0, + "idd5pb1": 0.0, + "idd61": 0.0, + "idd6ds1": 0.0, + "idd2p1": 0.0, + "idd3p1": 0.0, + "vdd2h": 0.0, + "idd02h": 0.0, + "idd2n2h": 0.0, + "idd3n2h": 0.0, + "idd4r2h": 0.0, + "idd4w2h": 0.0, + "idd52h": 0.0, + "idd5pb2h": 0.0, + "idd62h": 0.0, + "idd6ds2h": 0.0, + "idd2p2h": 0.0, + "idd3p2h": 0.0, + "vdd2l": 0.0, + "idd02l": 0.0, + "idd2n2l": 0.0, + "idd3n2l": 0.0, + "idd4r2l": 0.0, + "idd4w2l": 0.0, + "idd52l": 0.0, + "idd5pb2l": 0.0, + "idd62l": 0.0, + "idd6ds2l": 0.0, + "idd2p2l": 0.0, + "idd3p2l": 0.0, + "vddq": 0.0, + "iBeta_vdd1": 0.0, + "iBeta_vdd2h": 0.0, + "iBeta_vdd2l": 0.0 + }, + "bankwisespec": { + "factRho": 1.0 + }, + "memimpedancespec": { + "ck_termination": true, + "ck_R_eq": 1e6, + "ck_dyn_E": 1e-12, + + "ca_termination": true, + "ca_R_eq": 1e6, + "ca_dyn_E": 1e-12, + + "rdq_termination": true, + "rdq_R_eq": 1e6, + "rdq_dyn_E": 1e-12, + "wdq_termination": true, + "wdq_R_eq": 1e6, + "wdq_dyn_E": 1e-12, + + "wck_termination": true, + "wck_R_eq": 1e6, + "wck_dyn_E": 1e-12, + "rdqs_termination": true, + "rdqs_R_eq": 1e6, + "rdqs_dyn_E": 1e-12 }, "memoryId": "JEDEC_512Mbx16_16B_LPDDR5X-1600", "memoryType": "LPDDR5", @@ -57,7 +127,7 @@ "BL_n_S_32": 4, "pbR2act": 2, "pbR2pbR": 18, - "tCK": 5000 + "tCK": 5000e-12 } } } diff --git a/configs/memspec/JEDEC_512Mbx16_16B_LPDDR5X-2133.json b/configs/memspec/JEDEC_512Mbx16_16B_LPDDR5X-2133.json index 9e1678b1..aefd4257 100644 --- a/configs/memspec/JEDEC_512Mbx16_16B_LPDDR5X-2133.json +++ b/configs/memspec/JEDEC_512Mbx16_16B_LPDDR5X-2133.json @@ -11,7 +11,77 @@ "nbrOfDevices": 1, "nbrOfChannels": 1, "width": 16, - "per2BankOffset": 8 + "per2BankOffset": 8, + "WCKalwaysOn": false, + "maxBurstLength": 16 + }, + "mempowerspec": { + "vdd1": 0.0, + "idd01": 0.0, + "idd2n1": 0.0, + "idd3n1": 0.0, + "idd4r1": 0.0, + "idd4w1": 0.0, + "idd51": 0.0, + "idd5pb1": 0.0, + "idd61": 0.0, + "idd6ds1": 0.0, + "idd2p1": 0.0, + "idd3p1": 0.0, + "vdd2h": 0.0, + "idd02h": 0.0, + "idd2n2h": 0.0, + "idd3n2h": 0.0, + "idd4r2h": 0.0, + "idd4w2h": 0.0, + "idd52h": 0.0, + "idd5pb2h": 0.0, + "idd62h": 0.0, + "idd6ds2h": 0.0, + "idd2p2h": 0.0, + "idd3p2h": 0.0, + "vdd2l": 0.0, + "idd02l": 0.0, + "idd2n2l": 0.0, + "idd3n2l": 0.0, + "idd4r2l": 0.0, + "idd4w2l": 0.0, + "idd52l": 0.0, + "idd5pb2l": 0.0, + "idd62l": 0.0, + "idd6ds2l": 0.0, + "idd2p2l": 0.0, + "idd3p2l": 0.0, + "vddq": 0.0, + "iBeta_vdd1": 0.0, + "iBeta_vdd2h": 0.0, + "iBeta_vdd2l": 0.0 + }, + "bankwisespec": { + "factRho": 1.0 + }, + "memimpedancespec": { + "ck_termination": true, + "ck_R_eq": 1e6, + "ck_dyn_E": 1e-12, + + "ca_termination": true, + "ca_R_eq": 1e6, + "ca_dyn_E": 1e-12, + + "rdq_termination": true, + "rdq_R_eq": 1e6, + "rdq_dyn_E": 1e-12, + "wdq_termination": true, + "wdq_R_eq": 1e6, + "wdq_dyn_E": 1e-12, + + "wck_termination": true, + "wck_R_eq": 1e6, + "wck_dyn_E": 1e-12, + "rdqs_termination": true, + "rdqs_R_eq": 1e6, + "rdqs_dyn_E": 1e-12 }, "memoryId": "JEDEC_512Mbx16_16B_LPDDR5X-2133", "memoryType": "LPDDR5", @@ -57,7 +127,7 @@ "BL_n_S_32": 4, "pbR2act": 2, "pbR2pbR": 24, - "tCK": 3745 + "tCK": 3745e-12 } } } diff --git a/configs/memspec/JEDEC_512Mbx16_16B_LPDDR5X-2750.json b/configs/memspec/JEDEC_512Mbx16_16B_LPDDR5X-2750.json index 62a1e795..399dbf6e 100644 --- a/configs/memspec/JEDEC_512Mbx16_16B_LPDDR5X-2750.json +++ b/configs/memspec/JEDEC_512Mbx16_16B_LPDDR5X-2750.json @@ -11,7 +11,77 @@ "nbrOfDevices": 1, "nbrOfChannels": 1, "width": 16, - "per2BankOffset": 8 + "per2BankOffset": 8, + "WCKalwaysOn": false, + "maxBurstLength": 16 + }, + "mempowerspec": { + "vdd1": 0.0, + "idd01": 0.0, + "idd2n1": 0.0, + "idd3n1": 0.0, + "idd4r1": 0.0, + "idd4w1": 0.0, + "idd51": 0.0, + "idd5pb1": 0.0, + "idd61": 0.0, + "idd6ds1": 0.0, + "idd2p1": 0.0, + "idd3p1": 0.0, + "vdd2h": 0.0, + "idd02h": 0.0, + "idd2n2h": 0.0, + "idd3n2h": 0.0, + "idd4r2h": 0.0, + "idd4w2h": 0.0, + "idd52h": 0.0, + "idd5pb2h": 0.0, + "idd62h": 0.0, + "idd6ds2h": 0.0, + "idd2p2h": 0.0, + "idd3p2h": 0.0, + "vdd2l": 0.0, + "idd02l": 0.0, + "idd2n2l": 0.0, + "idd3n2l": 0.0, + "idd4r2l": 0.0, + "idd4w2l": 0.0, + "idd52l": 0.0, + "idd5pb2l": 0.0, + "idd62l": 0.0, + "idd6ds2l": 0.0, + "idd2p2l": 0.0, + "idd3p2l": 0.0, + "vddq": 0.0, + "iBeta_vdd1": 0.0, + "iBeta_vdd2h": 0.0, + "iBeta_vdd2l": 0.0 + }, + "bankwisespec": { + "factRho": 1.0 + }, + "memimpedancespec": { + "ck_termination": true, + "ck_R_eq": 1e6, + "ck_dyn_E": 1e-12, + + "ca_termination": true, + "ca_R_eq": 1e6, + "ca_dyn_E": 1e-12, + + "rdq_termination": true, + "rdq_R_eq": 1e6, + "rdq_dyn_E": 1e-12, + "wdq_termination": true, + "wdq_R_eq": 1e6, + "wdq_dyn_E": 1e-12, + + "wck_termination": true, + "wck_R_eq": 1e6, + "wck_dyn_E": 1e-12, + "rdqs_termination": true, + "rdqs_R_eq": 1e6, + "rdqs_dyn_E": 1e-12 }, "memoryId": "JEDEC_512Mbx16_16B_LPDDR5X-2750", "memoryType": "LPDDR5", @@ -57,7 +127,7 @@ "BL_n_S_32": 4, "pbR2act": 3, "pbR2pbR": 32, - "tCK": 2907 + "tCK": 2907e-12 } } } diff --git a/configs/memspec/JEDEC_512Mbx16_16B_LPDDR5X-3200.json b/configs/memspec/JEDEC_512Mbx16_16B_LPDDR5X-3200.json index cb23edac..79834d88 100644 --- a/configs/memspec/JEDEC_512Mbx16_16B_LPDDR5X-3200.json +++ b/configs/memspec/JEDEC_512Mbx16_16B_LPDDR5X-3200.json @@ -11,7 +11,77 @@ "nbrOfDevices": 1, "nbrOfChannels": 1, "width": 16, - "per2BankOffset": 8 + "per2BankOffset": 8, + "WCKalwaysOn": false, + "maxBurstLength": 16 + }, + "mempowerspec": { + "vdd1": 0.0, + "idd01": 0.0, + "idd2n1": 0.0, + "idd3n1": 0.0, + "idd4r1": 0.0, + "idd4w1": 0.0, + "idd51": 0.0, + "idd5pb1": 0.0, + "idd61": 0.0, + "idd6ds1": 0.0, + "idd2p1": 0.0, + "idd3p1": 0.0, + "vdd2h": 0.0, + "idd02h": 0.0, + "idd2n2h": 0.0, + "idd3n2h": 0.0, + "idd4r2h": 0.0, + "idd4w2h": 0.0, + "idd52h": 0.0, + "idd5pb2h": 0.0, + "idd62h": 0.0, + "idd6ds2h": 0.0, + "idd2p2h": 0.0, + "idd3p2h": 0.0, + "vdd2l": 0.0, + "idd02l": 0.0, + "idd2n2l": 0.0, + "idd3n2l": 0.0, + "idd4r2l": 0.0, + "idd4w2l": 0.0, + "idd52l": 0.0, + "idd5pb2l": 0.0, + "idd62l": 0.0, + "idd6ds2l": 0.0, + "idd2p2l": 0.0, + "idd3p2l": 0.0, + "vddq": 0.0, + "iBeta_vdd1": 0.0, + "iBeta_vdd2h": 0.0, + "iBeta_vdd2l": 0.0 + }, + "bankwisespec": { + "factRho": 1.0 + }, + "memimpedancespec": { + "ck_termination": true, + "ck_R_eq": 1e6, + "ck_dyn_E": 1e-12, + + "ca_termination": true, + "ca_R_eq": 1e6, + "ca_dyn_E": 1e-12, + + "rdq_termination": true, + "rdq_R_eq": 1e6, + "rdq_dyn_E": 1e-12, + "wdq_termination": true, + "wdq_R_eq": 1e6, + "wdq_dyn_E": 1e-12, + + "wck_termination": true, + "wck_R_eq": 1e6, + "wck_dyn_E": 1e-12, + "rdqs_termination": true, + "rdqs_R_eq": 1e6, + "rdqs_dyn_E": 1e-12 }, "memoryId": "JEDEC_512Mbx16_16B_LPDDR5X-3200", "memoryType": "LPDDR5", @@ -57,7 +127,7 @@ "BL_n_S_32": 4, "pbR2act": 3, "pbR2pbR": 36, - "tCK": 2500 + "tCK": 2500e-12 } } } diff --git a/configs/memspec/JEDEC_512Mbx16_8B_LPDDR5-0533.json b/configs/memspec/JEDEC_512Mbx16_8B_LPDDR5-0533.json index f9d25b36..7ac710fa 100644 --- a/configs/memspec/JEDEC_512Mbx16_8B_LPDDR5-0533.json +++ b/configs/memspec/JEDEC_512Mbx16_8B_LPDDR5-0533.json @@ -11,7 +11,77 @@ "nbrOfDevices": 1, "nbrOfChannels": 1, "width": 16, - "per2BankOffset": 8 + "per2BankOffset": 8, + "WCKalwaysOn": false, + "maxBurstLength": 32 + }, + "mempowerspec": { + "vdd1": 0.0, + "idd01": 0.0, + "idd2n1": 0.0, + "idd3n1": 0.0, + "idd4r1": 0.0, + "idd4w1": 0.0, + "idd51": 0.0, + "idd5pb1": 0.0, + "idd61": 0.0, + "idd6ds1": 0.0, + "idd2p1": 0.0, + "idd3p1": 0.0, + "vdd2h": 0.0, + "idd02h": 0.0, + "idd2n2h": 0.0, + "idd3n2h": 0.0, + "idd4r2h": 0.0, + "idd4w2h": 0.0, + "idd52h": 0.0, + "idd5pb2h": 0.0, + "idd62h": 0.0, + "idd6ds2h": 0.0, + "idd2p2h": 0.0, + "idd3p2h": 0.0, + "vdd2l": 0.0, + "idd02l": 0.0, + "idd2n2l": 0.0, + "idd3n2l": 0.0, + "idd4r2l": 0.0, + "idd4w2l": 0.0, + "idd52l": 0.0, + "idd5pb2l": 0.0, + "idd62l": 0.0, + "idd6ds2l": 0.0, + "idd2p2l": 0.0, + "idd3p2l": 0.0, + "vddq": 0.0, + "iBeta_vdd1": 0.0, + "iBeta_vdd2h": 0.0, + "iBeta_vdd2l": 0.0 + }, + "bankwisespec": { + "factRho": 1.0 + }, + "memimpedancespec": { + "ck_termination": true, + "ck_R_eq": 1e6, + "ck_dyn_E": 1e-12, + + "ca_termination": true, + "ca_R_eq": 1e6, + "ca_dyn_E": 1e-12, + + "rdq_termination": true, + "rdq_R_eq": 1e6, + "rdq_dyn_E": 1e-12, + "wdq_termination": true, + "wdq_R_eq": 1e6, + "wdq_dyn_E": 1e-12, + + "wck_termination": true, + "wck_R_eq": 1e6, + "wck_dyn_E": 1e-12, + "rdqs_termination": true, + "rdqs_R_eq": 1e6, + "rdqs_dyn_E": 1e-12 }, "memoryId": "JEDEC_512Mbx16_8B_LPDDR5-0533", "memoryType": "LPDDR5", @@ -55,7 +125,7 @@ "BL_n_S_32": 8, "pbR2act": 2, "pbR2pbR": 12, - "tCK": 7519 + "tCK": 7519e-12 } } } diff --git a/configs/memspec/JEDEC_512Mbx16_8B_LPDDR5-1067.json b/configs/memspec/JEDEC_512Mbx16_8B_LPDDR5-1067.json index a56328fc..79d14915 100644 --- a/configs/memspec/JEDEC_512Mbx16_8B_LPDDR5-1067.json +++ b/configs/memspec/JEDEC_512Mbx16_8B_LPDDR5-1067.json @@ -11,7 +11,77 @@ "nbrOfDevices": 1, "nbrOfChannels": 1, "width": 16, - "per2BankOffset": 8 + "per2BankOffset": 8, + "WCKalwaysOn": false, + "maxBurstLength": 32 + }, + "mempowerspec": { + "vdd1": 0.0, + "idd01": 0.0, + "idd2n1": 0.0, + "idd3n1": 0.0, + "idd4r1": 0.0, + "idd4w1": 0.0, + "idd51": 0.0, + "idd5pb1": 0.0, + "idd61": 0.0, + "idd6ds1": 0.0, + "idd2p1": 0.0, + "idd3p1": 0.0, + "vdd2h": 0.0, + "idd02h": 0.0, + "idd2n2h": 0.0, + "idd3n2h": 0.0, + "idd4r2h": 0.0, + "idd4w2h": 0.0, + "idd52h": 0.0, + "idd5pb2h": 0.0, + "idd62h": 0.0, + "idd6ds2h": 0.0, + "idd2p2h": 0.0, + "idd3p2h": 0.0, + "vdd2l": 0.0, + "idd02l": 0.0, + "idd2n2l": 0.0, + "idd3n2l": 0.0, + "idd4r2l": 0.0, + "idd4w2l": 0.0, + "idd52l": 0.0, + "idd5pb2l": 0.0, + "idd62l": 0.0, + "idd6ds2l": 0.0, + "idd2p2l": 0.0, + "idd3p2l": 0.0, + "vddq": 0.0, + "iBeta_vdd1": 0.0, + "iBeta_vdd2h": 0.0, + "iBeta_vdd2l": 0.0 + }, + "bankwisespec": { + "factRho": 1.0 + }, + "memimpedancespec": { + "ck_termination": true, + "ck_R_eq": 1e6, + "ck_dyn_E": 1e-12, + + "ca_termination": true, + "ca_R_eq": 1e6, + "ca_dyn_E": 1e-12, + + "rdq_termination": true, + "rdq_R_eq": 1e6, + "rdq_dyn_E": 1e-12, + "wdq_termination": true, + "wdq_R_eq": 1e6, + "wdq_dyn_E": 1e-12, + + "wck_termination": true, + "wck_R_eq": 1e6, + "wck_dyn_E": 1e-12, + "rdqs_termination": true, + "rdqs_R_eq": 1e6, + "rdqs_dyn_E": 1e-12 }, "memoryId": "JEDEC_512Mbx16_8B_LPDDR5-1067", "memoryType": "LPDDR5", @@ -55,7 +125,7 @@ "BL_n_S_32": 8, "pbR2act": 3, "pbR2pbR": 24, - "tCK": 3745 + "tCK": 3745e-12 } } } diff --git a/configs/memspec/JEDEC_512Mbx16_8B_LPDDR5-1600.json b/configs/memspec/JEDEC_512Mbx16_8B_LPDDR5-1600.json index 0c338caa..339cbcc4 100644 --- a/configs/memspec/JEDEC_512Mbx16_8B_LPDDR5-1600.json +++ b/configs/memspec/JEDEC_512Mbx16_8B_LPDDR5-1600.json @@ -11,7 +11,77 @@ "nbrOfDevices": 1, "nbrOfChannels": 1, "width": 16, - "per2BankOffset": 8 + "per2BankOffset": 8, + "WCKalwaysOn": false, + "maxBurstLength": 32 + }, + "mempowerspec": { + "vdd1": 0.0, + "idd01": 0.0, + "idd2n1": 0.0, + "idd3n1": 0.0, + "idd4r1": 0.0, + "idd4w1": 0.0, + "idd51": 0.0, + "idd5pb1": 0.0, + "idd61": 0.0, + "idd6ds1": 0.0, + "idd2p1": 0.0, + "idd3p1": 0.0, + "vdd2h": 0.0, + "idd02h": 0.0, + "idd2n2h": 0.0, + "idd3n2h": 0.0, + "idd4r2h": 0.0, + "idd4w2h": 0.0, + "idd52h": 0.0, + "idd5pb2h": 0.0, + "idd62h": 0.0, + "idd6ds2h": 0.0, + "idd2p2h": 0.0, + "idd3p2h": 0.0, + "vdd2l": 0.0, + "idd02l": 0.0, + "idd2n2l": 0.0, + "idd3n2l": 0.0, + "idd4r2l": 0.0, + "idd4w2l": 0.0, + "idd52l": 0.0, + "idd5pb2l": 0.0, + "idd62l": 0.0, + "idd6ds2l": 0.0, + "idd2p2l": 0.0, + "idd3p2l": 0.0, + "vddq": 0.0, + "iBeta_vdd1": 0.0, + "iBeta_vdd2h": 0.0, + "iBeta_vdd2l": 0.0 + }, + "bankwisespec": { + "factRho": 1.0 + }, + "memimpedancespec": { + "ck_termination": true, + "ck_R_eq": 1e6, + "ck_dyn_E": 1e-12, + + "ca_termination": true, + "ca_R_eq": 1e6, + "ca_dyn_E": 1e-12, + + "rdq_termination": true, + "rdq_R_eq": 1e6, + "rdq_dyn_E": 1e-12, + "wdq_termination": true, + "wdq_R_eq": 1e6, + "wdq_dyn_E": 1e-12, + + "wck_termination": true, + "wck_R_eq": 1e6, + "wck_dyn_E": 1e-12, + "rdqs_termination": true, + "rdqs_R_eq": 1e6, + "rdqs_dyn_E": 1e-12 }, "memoryId": "JEDEC_512Mbx16_8B_LPDDR5-1600", "memoryType": "LPDDR5", @@ -55,7 +125,7 @@ "BL_n_S_32": 8, "pbR2act": 4, "pbR2pbR": 36, - "tCK": 2500 + "tCK": 2500e-12 } } } diff --git a/configs/memspec/JEDEC_512Mbx16_8B_LPDDR5-2133.json b/configs/memspec/JEDEC_512Mbx16_8B_LPDDR5-2133.json index 0028f12f..dcfdb298 100644 --- a/configs/memspec/JEDEC_512Mbx16_8B_LPDDR5-2133.json +++ b/configs/memspec/JEDEC_512Mbx16_8B_LPDDR5-2133.json @@ -11,7 +11,77 @@ "nbrOfDevices": 1, "nbrOfChannels": 1, "width": 16, - "per2BankOffset": 8 + "per2BankOffset": 8, + "WCKalwaysOn": false, + "maxBurstLength": 32 + }, + "mempowerspec": { + "vdd1": 0.0, + "idd01": 0.0, + "idd2n1": 0.0, + "idd3n1": 0.0, + "idd4r1": 0.0, + "idd4w1": 0.0, + "idd51": 0.0, + "idd5pb1": 0.0, + "idd61": 0.0, + "idd6ds1": 0.0, + "idd2p1": 0.0, + "idd3p1": 0.0, + "vdd2h": 0.0, + "idd02h": 0.0, + "idd2n2h": 0.0, + "idd3n2h": 0.0, + "idd4r2h": 0.0, + "idd4w2h": 0.0, + "idd52h": 0.0, + "idd5pb2h": 0.0, + "idd62h": 0.0, + "idd6ds2h": 0.0, + "idd2p2h": 0.0, + "idd3p2h": 0.0, + "vdd2l": 0.0, + "idd02l": 0.0, + "idd2n2l": 0.0, + "idd3n2l": 0.0, + "idd4r2l": 0.0, + "idd4w2l": 0.0, + "idd52l": 0.0, + "idd5pb2l": 0.0, + "idd62l": 0.0, + "idd6ds2l": 0.0, + "idd2p2l": 0.0, + "idd3p2l": 0.0, + "vddq": 0.0, + "iBeta_vdd1": 0.0, + "iBeta_vdd2h": 0.0, + "iBeta_vdd2l": 0.0 + }, + "bankwisespec": { + "factRho": 1.0 + }, + "memimpedancespec": { + "ck_termination": true, + "ck_R_eq": 1e6, + "ck_dyn_E": 1e-12, + + "ca_termination": true, + "ca_R_eq": 1e6, + "ca_dyn_E": 1e-12, + + "rdq_termination": true, + "rdq_R_eq": 1e6, + "rdq_dyn_E": 1e-12, + "wdq_termination": true, + "wdq_R_eq": 1e6, + "wdq_dyn_E": 1e-12, + + "wck_termination": true, + "wck_R_eq": 1e6, + "wck_dyn_E": 1e-12, + "rdqs_termination": true, + "rdqs_R_eq": 1e6, + "rdqs_dyn_E": 1e-12 }, "memoryId": "JEDEC_512Mbx16_8B_LPDDR5-2133", "memoryType": "LPDDR5", @@ -55,7 +125,7 @@ "BL_n_S_32": 8, "pbR2act": 6, "pbR2pbR": 48, - "tCK": 1876 + "tCK": 1876e-12 } } } diff --git a/configs/memspec/JEDEC_512Mbx16_8B_LPDDR5-2750.json b/configs/memspec/JEDEC_512Mbx16_8B_LPDDR5-2750.json index 812bbf23..26deb7ff 100644 --- a/configs/memspec/JEDEC_512Mbx16_8B_LPDDR5-2750.json +++ b/configs/memspec/JEDEC_512Mbx16_8B_LPDDR5-2750.json @@ -11,7 +11,77 @@ "nbrOfDevices": 1, "nbrOfChannels": 1, "width": 16, - "per2BankOffset": 8 + "per2BankOffset": 8, + "WCKalwaysOn": false, + "maxBurstLength": 32 + }, + "mempowerspec": { + "vdd1": 0.0, + "idd01": 0.0, + "idd2n1": 0.0, + "idd3n1": 0.0, + "idd4r1": 0.0, + "idd4w1": 0.0, + "idd51": 0.0, + "idd5pb1": 0.0, + "idd61": 0.0, + "idd6ds1": 0.0, + "idd2p1": 0.0, + "idd3p1": 0.0, + "vdd2h": 0.0, + "idd02h": 0.0, + "idd2n2h": 0.0, + "idd3n2h": 0.0, + "idd4r2h": 0.0, + "idd4w2h": 0.0, + "idd52h": 0.0, + "idd5pb2h": 0.0, + "idd62h": 0.0, + "idd6ds2h": 0.0, + "idd2p2h": 0.0, + "idd3p2h": 0.0, + "vdd2l": 0.0, + "idd02l": 0.0, + "idd2n2l": 0.0, + "idd3n2l": 0.0, + "idd4r2l": 0.0, + "idd4w2l": 0.0, + "idd52l": 0.0, + "idd5pb2l": 0.0, + "idd62l": 0.0, + "idd6ds2l": 0.0, + "idd2p2l": 0.0, + "idd3p2l": 0.0, + "vddq": 0.0, + "iBeta_vdd1": 0.0, + "iBeta_vdd2h": 0.0, + "iBeta_vdd2l": 0.0 + }, + "bankwisespec": { + "factRho": 1.0 + }, + "memimpedancespec": { + "ck_termination": true, + "ck_R_eq": 1e6, + "ck_dyn_E": 1e-12, + + "ca_termination": true, + "ca_R_eq": 1e6, + "ca_dyn_E": 1e-12, + + "rdq_termination": true, + "rdq_R_eq": 1e6, + "rdq_dyn_E": 1e-12, + "wdq_termination": true, + "wdq_R_eq": 1e6, + "wdq_dyn_E": 1e-12, + + "wck_termination": true, + "wck_R_eq": 1e6, + "wck_dyn_E": 1e-12, + "rdqs_termination": true, + "rdqs_R_eq": 1e6, + "rdqs_dyn_E": 1e-12 }, "memoryId": "JEDEC_512Mbx16_8B_LPDDR5-2750", "memoryType": "LPDDR5", @@ -55,7 +125,7 @@ "BL_n_S_32": 8, "pbR2act": 7, "pbR2pbR": 62, - "tCK": 1453 + "tCK": 1453e-12 } } } diff --git a/configs/memspec/JEDEC_512Mbx16_8B_LPDDR5-3200.json b/configs/memspec/JEDEC_512Mbx16_8B_LPDDR5-3200.json index d0038ec2..0eba8dd0 100644 --- a/configs/memspec/JEDEC_512Mbx16_8B_LPDDR5-3200.json +++ b/configs/memspec/JEDEC_512Mbx16_8B_LPDDR5-3200.json @@ -11,7 +11,77 @@ "nbrOfDevices": 1, "nbrOfChannels": 1, "width": 16, - "per2BankOffset": 8 + "per2BankOffset": 8, + "WCKalwaysOn": false, + "maxBurstLength": 32 + }, + "mempowerspec": { + "vdd1": 0.0, + "idd01": 0.0, + "idd2n1": 0.0, + "idd3n1": 0.0, + "idd4r1": 0.0, + "idd4w1": 0.0, + "idd51": 0.0, + "idd5pb1": 0.0, + "idd61": 0.0, + "idd6ds1": 0.0, + "idd2p1": 0.0, + "idd3p1": 0.0, + "vdd2h": 0.0, + "idd02h": 0.0, + "idd2n2h": 0.0, + "idd3n2h": 0.0, + "idd4r2h": 0.0, + "idd4w2h": 0.0, + "idd52h": 0.0, + "idd5pb2h": 0.0, + "idd62h": 0.0, + "idd6ds2h": 0.0, + "idd2p2h": 0.0, + "idd3p2h": 0.0, + "vdd2l": 0.0, + "idd02l": 0.0, + "idd2n2l": 0.0, + "idd3n2l": 0.0, + "idd4r2l": 0.0, + "idd4w2l": 0.0, + "idd52l": 0.0, + "idd5pb2l": 0.0, + "idd62l": 0.0, + "idd6ds2l": 0.0, + "idd2p2l": 0.0, + "idd3p2l": 0.0, + "vddq": 0.0, + "iBeta_vdd1": 0.0, + "iBeta_vdd2h": 0.0, + "iBeta_vdd2l": 0.0 + }, + "bankwisespec": { + "factRho": 1.0 + }, + "memimpedancespec": { + "ck_termination": true, + "ck_R_eq": 1e6, + "ck_dyn_E": 1e-12, + + "ca_termination": true, + "ca_R_eq": 1e6, + "ca_dyn_E": 1e-12, + + "rdq_termination": true, + "rdq_R_eq": 1e6, + "rdq_dyn_E": 1e-12, + "wdq_termination": true, + "wdq_R_eq": 1e6, + "wdq_dyn_E": 1e-12, + + "wck_termination": true, + "wck_R_eq": 1e6, + "wck_dyn_E": 1e-12, + "rdqs_termination": true, + "rdqs_R_eq": 1e6, + "rdqs_dyn_E": 1e-12 }, "memoryId": "JEDEC_512Mbx16_8B_LPDDR5-3200", "memoryType": "LPDDR5", @@ -55,7 +125,7 @@ "BL_n_S_32": 8, "pbR2act": 8, "pbR2pbR": 72, - "tCK": 1250 + "tCK": 1250e-12 } } } diff --git a/configs/memspec/JEDEC_512Mbx16_8B_LPDDR5-3733.json b/configs/memspec/JEDEC_512Mbx16_8B_LPDDR5-3733.json index c126ee26..fbc2e734 100644 --- a/configs/memspec/JEDEC_512Mbx16_8B_LPDDR5-3733.json +++ b/configs/memspec/JEDEC_512Mbx16_8B_LPDDR5-3733.json @@ -11,7 +11,77 @@ "nbrOfDevices": 1, "nbrOfChannels": 1, "width": 16, - "per2BankOffset": 8 + "per2BankOffset": 8, + "WCKalwaysOn": false, + "maxBurstLength": 32 + }, + "mempowerspec": { + "vdd1": 0.0, + "idd01": 0.0, + "idd2n1": 0.0, + "idd3n1": 0.0, + "idd4r1": 0.0, + "idd4w1": 0.0, + "idd51": 0.0, + "idd5pb1": 0.0, + "idd61": 0.0, + "idd6ds1": 0.0, + "idd2p1": 0.0, + "idd3p1": 0.0, + "vdd2h": 0.0, + "idd02h": 0.0, + "idd2n2h": 0.0, + "idd3n2h": 0.0, + "idd4r2h": 0.0, + "idd4w2h": 0.0, + "idd52h": 0.0, + "idd5pb2h": 0.0, + "idd62h": 0.0, + "idd6ds2h": 0.0, + "idd2p2h": 0.0, + "idd3p2h": 0.0, + "vdd2l": 0.0, + "idd02l": 0.0, + "idd2n2l": 0.0, + "idd3n2l": 0.0, + "idd4r2l": 0.0, + "idd4w2l": 0.0, + "idd52l": 0.0, + "idd5pb2l": 0.0, + "idd62l": 0.0, + "idd6ds2l": 0.0, + "idd2p2l": 0.0, + "idd3p2l": 0.0, + "vddq": 0.0, + "iBeta_vdd1": 0.0, + "iBeta_vdd2h": 0.0, + "iBeta_vdd2l": 0.0 + }, + "bankwisespec": { + "factRho": 1.0 + }, + "memimpedancespec": { + "ck_termination": true, + "ck_R_eq": 1e6, + "ck_dyn_E": 1e-12, + + "ca_termination": true, + "ca_R_eq": 1e6, + "ca_dyn_E": 1e-12, + + "rdq_termination": true, + "rdq_R_eq": 1e6, + "rdq_dyn_E": 1e-12, + "wdq_termination": true, + "wdq_R_eq": 1e6, + "wdq_dyn_E": 1e-12, + + "wck_termination": true, + "wck_R_eq": 1e6, + "wck_dyn_E": 1e-12, + "rdqs_termination": true, + "rdqs_R_eq": 1e6, + "rdqs_dyn_E": 1e-12 }, "memoryId": "JEDEC_512Mbx16_8B_LPDDR5-3733", "memoryType": "LPDDR5", @@ -55,7 +125,7 @@ "BL_n_S_32": 4, "pbR2act": 5, "pbR2pbR": 42, - "tCK": 2141 + "tCK": 2141e-12 } } } diff --git a/configs/memspec/JEDEC_512Mbx16_8B_LPDDR5-4267.json b/configs/memspec/JEDEC_512Mbx16_8B_LPDDR5-4267.json index db3f4c0f..db273701 100644 --- a/configs/memspec/JEDEC_512Mbx16_8B_LPDDR5-4267.json +++ b/configs/memspec/JEDEC_512Mbx16_8B_LPDDR5-4267.json @@ -11,7 +11,77 @@ "nbrOfDevices": 1, "nbrOfChannels": 1, "width": 16, - "per2BankOffset": 8 + "per2BankOffset": 8, + "WCKalwaysOn": false, + "maxBurstLength": 32 + }, + "mempowerspec": { + "vdd1": 0.0, + "idd01": 0.0, + "idd2n1": 0.0, + "idd3n1": 0.0, + "idd4r1": 0.0, + "idd4w1": 0.0, + "idd51": 0.0, + "idd5pb1": 0.0, + "idd61": 0.0, + "idd6ds1": 0.0, + "idd2p1": 0.0, + "idd3p1": 0.0, + "vdd2h": 0.0, + "idd02h": 0.0, + "idd2n2h": 0.0, + "idd3n2h": 0.0, + "idd4r2h": 0.0, + "idd4w2h": 0.0, + "idd52h": 0.0, + "idd5pb2h": 0.0, + "idd62h": 0.0, + "idd6ds2h": 0.0, + "idd2p2h": 0.0, + "idd3p2h": 0.0, + "vdd2l": 0.0, + "idd02l": 0.0, + "idd2n2l": 0.0, + "idd3n2l": 0.0, + "idd4r2l": 0.0, + "idd4w2l": 0.0, + "idd52l": 0.0, + "idd5pb2l": 0.0, + "idd62l": 0.0, + "idd6ds2l": 0.0, + "idd2p2l": 0.0, + "idd3p2l": 0.0, + "vddq": 0.0, + "iBeta_vdd1": 0.0, + "iBeta_vdd2h": 0.0, + "iBeta_vdd2l": 0.0 + }, + "bankwisespec": { + "factRho": 1.0 + }, + "memimpedancespec": { + "ck_termination": true, + "ck_R_eq": 1e6, + "ck_dyn_E": 1e-12, + + "ca_termination": true, + "ca_R_eq": 1e6, + "ca_dyn_E": 1e-12, + + "rdq_termination": true, + "rdq_R_eq": 1e6, + "rdq_dyn_E": 1e-12, + "wdq_termination": true, + "wdq_R_eq": 1e6, + "wdq_dyn_E": 1e-12, + + "wck_termination": true, + "wck_R_eq": 1e6, + "wck_dyn_E": 1e-12, + "rdqs_termination": true, + "rdqs_R_eq": 1e6, + "rdqs_dyn_E": 1e-12 }, "memoryId": "JEDEC_512Mbx16_8B_LPDDR5-4267", "memoryType": "LPDDR5", @@ -55,7 +125,7 @@ "BL_n_S_32": 4, "pbR2act": 6, "pbR2pbR": 48, - "tCK": 1876 + "tCK": 1876e-12 } } } diff --git a/configs/memspec/JEDEC_512Mbx16_8B_LPDDR5-4800.json b/configs/memspec/JEDEC_512Mbx16_8B_LPDDR5-4800.json index 24daf7d3..e53f619e 100644 --- a/configs/memspec/JEDEC_512Mbx16_8B_LPDDR5-4800.json +++ b/configs/memspec/JEDEC_512Mbx16_8B_LPDDR5-4800.json @@ -11,7 +11,77 @@ "nbrOfDevices": 1, "nbrOfChannels": 1, "width": 16, - "per2BankOffset": 8 + "per2BankOffset": 8, + "WCKalwaysOn": false, + "maxBurstLength": 32 + }, + "mempowerspec": { + "vdd1": 0.0, + "idd01": 0.0, + "idd2n1": 0.0, + "idd3n1": 0.0, + "idd4r1": 0.0, + "idd4w1": 0.0, + "idd51": 0.0, + "idd5pb1": 0.0, + "idd61": 0.0, + "idd6ds1": 0.0, + "idd2p1": 0.0, + "idd3p1": 0.0, + "vdd2h": 0.0, + "idd02h": 0.0, + "idd2n2h": 0.0, + "idd3n2h": 0.0, + "idd4r2h": 0.0, + "idd4w2h": 0.0, + "idd52h": 0.0, + "idd5pb2h": 0.0, + "idd62h": 0.0, + "idd6ds2h": 0.0, + "idd2p2h": 0.0, + "idd3p2h": 0.0, + "vdd2l": 0.0, + "idd02l": 0.0, + "idd2n2l": 0.0, + "idd3n2l": 0.0, + "idd4r2l": 0.0, + "idd4w2l": 0.0, + "idd52l": 0.0, + "idd5pb2l": 0.0, + "idd62l": 0.0, + "idd6ds2l": 0.0, + "idd2p2l": 0.0, + "idd3p2l": 0.0, + "vddq": 0.0, + "iBeta_vdd1": 0.0, + "iBeta_vdd2h": 0.0, + "iBeta_vdd2l": 0.0 + }, + "bankwisespec": { + "factRho": 1.0 + }, + "memimpedancespec": { + "ck_termination": true, + "ck_R_eq": 1e6, + "ck_dyn_E": 1e-12, + + "ca_termination": true, + "ca_R_eq": 1e6, + "ca_dyn_E": 1e-12, + + "rdq_termination": true, + "rdq_R_eq": 1e6, + "rdq_dyn_E": 1e-12, + "wdq_termination": true, + "wdq_R_eq": 1e6, + "wdq_dyn_E": 1e-12, + + "wck_termination": true, + "wck_R_eq": 1e6, + "wck_dyn_E": 1e-12, + "rdqs_termination": true, + "rdqs_R_eq": 1e6, + "rdqs_dyn_E": 1e-12 }, "memoryId": "JEDEC_512Mbx16_8B_LPDDR5-4800", "memoryType": "LPDDR5", @@ -55,7 +125,7 @@ "BL_n_S_32": 4, "pbR2act": 6, "pbR2pbR": 54, - "tCK": 1667 + "tCK": 1667e-12 } } } diff --git a/configs/memspec/JEDEC_512Mbx16_8B_LPDDR5-5500.json b/configs/memspec/JEDEC_512Mbx16_8B_LPDDR5-5500.json index a6c530ae..9fa89b30 100644 --- a/configs/memspec/JEDEC_512Mbx16_8B_LPDDR5-5500.json +++ b/configs/memspec/JEDEC_512Mbx16_8B_LPDDR5-5500.json @@ -11,7 +11,77 @@ "nbrOfDevices": 1, "nbrOfChannels": 1, "width": 16, - "per2BankOffset": 8 + "per2BankOffset": 8, + "WCKalwaysOn": false, + "maxBurstLength": 32 + }, + "mempowerspec": { + "vdd1": 0.0, + "idd01": 0.0, + "idd2n1": 0.0, + "idd3n1": 0.0, + "idd4r1": 0.0, + "idd4w1": 0.0, + "idd51": 0.0, + "idd5pb1": 0.0, + "idd61": 0.0, + "idd6ds1": 0.0, + "idd2p1": 0.0, + "idd3p1": 0.0, + "vdd2h": 0.0, + "idd02h": 0.0, + "idd2n2h": 0.0, + "idd3n2h": 0.0, + "idd4r2h": 0.0, + "idd4w2h": 0.0, + "idd52h": 0.0, + "idd5pb2h": 0.0, + "idd62h": 0.0, + "idd6ds2h": 0.0, + "idd2p2h": 0.0, + "idd3p2h": 0.0, + "vdd2l": 0.0, + "idd02l": 0.0, + "idd2n2l": 0.0, + "idd3n2l": 0.0, + "idd4r2l": 0.0, + "idd4w2l": 0.0, + "idd52l": 0.0, + "idd5pb2l": 0.0, + "idd62l": 0.0, + "idd6ds2l": 0.0, + "idd2p2l": 0.0, + "idd3p2l": 0.0, + "vddq": 0.0, + "iBeta_vdd1": 0.0, + "iBeta_vdd2h": 0.0, + "iBeta_vdd2l": 0.0 + }, + "bankwisespec": { + "factRho": 1.0 + }, + "memimpedancespec": { + "ck_termination": true, + "ck_R_eq": 1e6, + "ck_dyn_E": 1e-12, + + "ca_termination": true, + "ca_R_eq": 1e6, + "ca_dyn_E": 1e-12, + + "rdq_termination": true, + "rdq_R_eq": 1e6, + "rdq_dyn_E": 1e-12, + "wdq_termination": true, + "wdq_R_eq": 1e6, + "wdq_dyn_E": 1e-12, + + "wck_termination": true, + "wck_R_eq": 1e6, + "wck_dyn_E": 1e-12, + "rdqs_termination": true, + "rdqs_R_eq": 1e6, + "rdqs_dyn_E": 1e-12 }, "memoryId": "JEDEC_512Mbx16_8B_LPDDR5-5500", "memoryType": "LPDDR5", @@ -55,7 +125,7 @@ "BL_n_S_32": 4, "pbR2act": 7, "pbR2pbR": 62, - "tCK": 1453 + "tCK": 1453e-12 } } } diff --git a/configs/memspec/JEDEC_512Mbx16_8B_LPDDR5-6000.json b/configs/memspec/JEDEC_512Mbx16_8B_LPDDR5-6000.json index a93be6a3..cb2766d2 100644 --- a/configs/memspec/JEDEC_512Mbx16_8B_LPDDR5-6000.json +++ b/configs/memspec/JEDEC_512Mbx16_8B_LPDDR5-6000.json @@ -11,7 +11,77 @@ "nbrOfDevices": 1, "nbrOfChannels": 1, "width": 16, - "per2BankOffset": 8 + "per2BankOffset": 8, + "WCKalwaysOn": false, + "maxBurstLength": 32 + }, + "mempowerspec": { + "vdd1": 0.0, + "idd01": 0.0, + "idd2n1": 0.0, + "idd3n1": 0.0, + "idd4r1": 0.0, + "idd4w1": 0.0, + "idd51": 0.0, + "idd5pb1": 0.0, + "idd61": 0.0, + "idd6ds1": 0.0, + "idd2p1": 0.0, + "idd3p1": 0.0, + "vdd2h": 0.0, + "idd02h": 0.0, + "idd2n2h": 0.0, + "idd3n2h": 0.0, + "idd4r2h": 0.0, + "idd4w2h": 0.0, + "idd52h": 0.0, + "idd5pb2h": 0.0, + "idd62h": 0.0, + "idd6ds2h": 0.0, + "idd2p2h": 0.0, + "idd3p2h": 0.0, + "vdd2l": 0.0, + "idd02l": 0.0, + "idd2n2l": 0.0, + "idd3n2l": 0.0, + "idd4r2l": 0.0, + "idd4w2l": 0.0, + "idd52l": 0.0, + "idd5pb2l": 0.0, + "idd62l": 0.0, + "idd6ds2l": 0.0, + "idd2p2l": 0.0, + "idd3p2l": 0.0, + "vddq": 0.0, + "iBeta_vdd1": 0.0, + "iBeta_vdd2h": 0.0, + "iBeta_vdd2l": 0.0 + }, + "bankwisespec": { + "factRho": 1.0 + }, + "memimpedancespec": { + "ck_termination": true, + "ck_R_eq": 1e6, + "ck_dyn_E": 1e-12, + + "ca_termination": true, + "ca_R_eq": 1e6, + "ca_dyn_E": 1e-12, + + "rdq_termination": true, + "rdq_R_eq": 1e6, + "rdq_dyn_E": 1e-12, + "wdq_termination": true, + "wdq_R_eq": 1e6, + "wdq_dyn_E": 1e-12, + + "wck_termination": true, + "wck_R_eq": 1e6, + "wck_dyn_E": 1e-12, + "rdqs_termination": true, + "rdqs_R_eq": 1e6, + "rdqs_dyn_E": 1e-12 }, "memoryId": "JEDEC_512Mbx16_8B_LPDDR5-6000", "memoryType": "LPDDR5", @@ -55,7 +125,7 @@ "BL_n_S_32": 4, "pbR2act": 8, "pbR2pbR": 68, - "tCK": 1333 + "tCK": 1333e-12 } } } diff --git a/configs/memspec/JEDEC_512Mbx16_8B_LPDDR5-6400.json b/configs/memspec/JEDEC_512Mbx16_8B_LPDDR5-6400.json index a9769f02..31aaa926 100644 --- a/configs/memspec/JEDEC_512Mbx16_8B_LPDDR5-6400.json +++ b/configs/memspec/JEDEC_512Mbx16_8B_LPDDR5-6400.json @@ -11,7 +11,77 @@ "nbrOfDevices": 1, "nbrOfChannels": 1, "width": 16, - "per2BankOffset": 8 + "per2BankOffset": 8, + "WCKalwaysOn": false, + "maxBurstLength": 32 + }, + "mempowerspec": { + "vdd1": 0.0, + "idd01": 0.0, + "idd2n1": 0.0, + "idd3n1": 0.0, + "idd4r1": 0.0, + "idd4w1": 0.0, + "idd51": 0.0, + "idd5pb1": 0.0, + "idd61": 0.0, + "idd6ds1": 0.0, + "idd2p1": 0.0, + "idd3p1": 0.0, + "vdd2h": 0.0, + "idd02h": 0.0, + "idd2n2h": 0.0, + "idd3n2h": 0.0, + "idd4r2h": 0.0, + "idd4w2h": 0.0, + "idd52h": 0.0, + "idd5pb2h": 0.0, + "idd62h": 0.0, + "idd6ds2h": 0.0, + "idd2p2h": 0.0, + "idd3p2h": 0.0, + "vdd2l": 0.0, + "idd02l": 0.0, + "idd2n2l": 0.0, + "idd3n2l": 0.0, + "idd4r2l": 0.0, + "idd4w2l": 0.0, + "idd52l": 0.0, + "idd5pb2l": 0.0, + "idd62l": 0.0, + "idd6ds2l": 0.0, + "idd2p2l": 0.0, + "idd3p2l": 0.0, + "vddq": 0.0, + "iBeta_vdd1": 0.0, + "iBeta_vdd2h": 0.0, + "iBeta_vdd2l": 0.0 + }, + "bankwisespec": { + "factRho": 1.0 + }, + "memimpedancespec": { + "ck_termination": true, + "ck_R_eq": 1e6, + "ck_dyn_E": 1e-12, + + "ca_termination": true, + "ca_R_eq": 1e6, + "ca_dyn_E": 1e-12, + + "rdq_termination": true, + "rdq_R_eq": 1e6, + "rdq_dyn_E": 1e-12, + "wdq_termination": true, + "wdq_R_eq": 1e6, + "wdq_dyn_E": 1e-12, + + "wck_termination": true, + "wck_R_eq": 1e6, + "wck_dyn_E": 1e-12, + "rdqs_termination": true, + "rdqs_R_eq": 1e6, + "rdqs_dyn_E": 1e-12 }, "memoryId": "JEDEC_512Mbx16_8B_LPDDR5-6400", "memoryType": "LPDDR5", @@ -55,7 +125,7 @@ "BL_n_S_32": 4, "pbR2act": 8, "pbR2pbR": 72, - "tCK": 1250 + "tCK": 1250e-12 } } } diff --git a/configs/memspec/JEDEC_512Mbx16_BG_LPDDR5-3733.json b/configs/memspec/JEDEC_512Mbx16_BG_LPDDR5-3733.json index 9784b5ca..4b0ac6c7 100644 --- a/configs/memspec/JEDEC_512Mbx16_BG_LPDDR5-3733.json +++ b/configs/memspec/JEDEC_512Mbx16_BG_LPDDR5-3733.json @@ -11,7 +11,77 @@ "nbrOfDevices": 1, "nbrOfChannels": 1, "width": 16, - "per2BankOffset": 8 + "per2BankOffset": 8, + "WCKalwaysOn": false, + "maxBurstLength": 16 + }, + "mempowerspec": { + "vdd1": 0.0, + "idd01": 0.0, + "idd2n1": 0.0, + "idd3n1": 0.0, + "idd4r1": 0.0, + "idd4w1": 0.0, + "idd51": 0.0, + "idd5pb1": 0.0, + "idd61": 0.0, + "idd6ds1": 0.0, + "idd2p1": 0.0, + "idd3p1": 0.0, + "vdd2h": 0.0, + "idd02h": 0.0, + "idd2n2h": 0.0, + "idd3n2h": 0.0, + "idd4r2h": 0.0, + "idd4w2h": 0.0, + "idd52h": 0.0, + "idd5pb2h": 0.0, + "idd62h": 0.0, + "idd6ds2h": 0.0, + "idd2p2h": 0.0, + "idd3p2h": 0.0, + "vdd2l": 0.0, + "idd02l": 0.0, + "idd2n2l": 0.0, + "idd3n2l": 0.0, + "idd4r2l": 0.0, + "idd4w2l": 0.0, + "idd52l": 0.0, + "idd5pb2l": 0.0, + "idd62l": 0.0, + "idd6ds2l": 0.0, + "idd2p2l": 0.0, + "idd3p2l": 0.0, + "vddq": 0.0, + "iBeta_vdd1": 0.0, + "iBeta_vdd2h": 0.0, + "iBeta_vdd2l": 0.0 + }, + "bankwisespec": { + "factRho": 1.0 + }, + "memimpedancespec": { + "ck_termination": true, + "ck_R_eq": 1e6, + "ck_dyn_E": 1e-12, + + "ca_termination": true, + "ca_R_eq": 1e6, + "ca_dyn_E": 1e-12, + + "rdq_termination": true, + "rdq_R_eq": 1e6, + "rdq_dyn_E": 1e-12, + "wdq_termination": true, + "wdq_R_eq": 1e6, + "wdq_dyn_E": 1e-12, + + "wck_termination": true, + "wck_R_eq": 1e6, + "wck_dyn_E": 1e-12, + "rdqs_termination": true, + "rdqs_R_eq": 1e6, + "rdqs_dyn_E": 1e-12 }, "memoryId": "JEDEC_512Mbx16_BG_LPDDR5-3733", "memoryType": "LPDDR5", @@ -55,7 +125,7 @@ "BL_n_S_32": 2, "pbR2act": 4, "pbR2pbR": 42, - "tCK": 2141 + "tCK": 2141e-12 } } } diff --git a/configs/memspec/JEDEC_512Mbx16_BG_LPDDR5-4267.json b/configs/memspec/JEDEC_512Mbx16_BG_LPDDR5-4267.json index d3e58ea7..527ab2c1 100644 --- a/configs/memspec/JEDEC_512Mbx16_BG_LPDDR5-4267.json +++ b/configs/memspec/JEDEC_512Mbx16_BG_LPDDR5-4267.json @@ -11,7 +11,77 @@ "nbrOfDevices": 1, "nbrOfChannels": 1, "width": 16, - "per2BankOffset": 8 + "per2BankOffset": 8, + "WCKalwaysOn": false, + "maxBurstLength": 16 + }, + "mempowerspec": { + "vdd1": 0.0, + "idd01": 0.0, + "idd2n1": 0.0, + "idd3n1": 0.0, + "idd4r1": 0.0, + "idd4w1": 0.0, + "idd51": 0.0, + "idd5pb1": 0.0, + "idd61": 0.0, + "idd6ds1": 0.0, + "idd2p1": 0.0, + "idd3p1": 0.0, + "vdd2h": 0.0, + "idd02h": 0.0, + "idd2n2h": 0.0, + "idd3n2h": 0.0, + "idd4r2h": 0.0, + "idd4w2h": 0.0, + "idd52h": 0.0, + "idd5pb2h": 0.0, + "idd62h": 0.0, + "idd6ds2h": 0.0, + "idd2p2h": 0.0, + "idd3p2h": 0.0, + "vdd2l": 0.0, + "idd02l": 0.0, + "idd2n2l": 0.0, + "idd3n2l": 0.0, + "idd4r2l": 0.0, + "idd4w2l": 0.0, + "idd52l": 0.0, + "idd5pb2l": 0.0, + "idd62l": 0.0, + "idd6ds2l": 0.0, + "idd2p2l": 0.0, + "idd3p2l": 0.0, + "vddq": 0.0, + "iBeta_vdd1": 0.0, + "iBeta_vdd2h": 0.0, + "iBeta_vdd2l": 0.0 + }, + "bankwisespec": { + "factRho": 1.0 + }, + "memimpedancespec": { + "ck_termination": true, + "ck_R_eq": 1e6, + "ck_dyn_E": 1e-12, + + "ca_termination": true, + "ca_R_eq": 1e6, + "ca_dyn_E": 1e-12, + + "rdq_termination": true, + "rdq_R_eq": 1e6, + "rdq_dyn_E": 1e-12, + "wdq_termination": true, + "wdq_R_eq": 1e6, + "wdq_dyn_E": 1e-12, + + "wck_termination": true, + "wck_R_eq": 1e6, + "wck_dyn_E": 1e-12, + "rdqs_termination": true, + "rdqs_R_eq": 1e6, + "rdqs_dyn_E": 1e-12 }, "memoryId": "JEDEC_512Mbx16_BG_LPDDR5-4267", "memoryType": "LPDDR5", @@ -55,7 +125,7 @@ "BL_n_S_32": 2, "pbR2act": 4, "pbR2pbR": 48, - "tCK": 1876 + "tCK": 1876e-12 } } } diff --git a/configs/memspec/JEDEC_512Mbx16_BG_LPDDR5-4800.json b/configs/memspec/JEDEC_512Mbx16_BG_LPDDR5-4800.json index 6a06bce5..72e50058 100644 --- a/configs/memspec/JEDEC_512Mbx16_BG_LPDDR5-4800.json +++ b/configs/memspec/JEDEC_512Mbx16_BG_LPDDR5-4800.json @@ -11,7 +11,77 @@ "nbrOfDevices": 1, "nbrOfChannels": 1, "width": 16, - "per2BankOffset": 8 + "per2BankOffset": 8, + "WCKalwaysOn": false, + "maxBurstLength": 16 + }, + "mempowerspec": { + "vdd1": 0.0, + "idd01": 0.0, + "idd2n1": 0.0, + "idd3n1": 0.0, + "idd4r1": 0.0, + "idd4w1": 0.0, + "idd51": 0.0, + "idd5pb1": 0.0, + "idd61": 0.0, + "idd6ds1": 0.0, + "idd2p1": 0.0, + "idd3p1": 0.0, + "vdd2h": 0.0, + "idd02h": 0.0, + "idd2n2h": 0.0, + "idd3n2h": 0.0, + "idd4r2h": 0.0, + "idd4w2h": 0.0, + "idd52h": 0.0, + "idd5pb2h": 0.0, + "idd62h": 0.0, + "idd6ds2h": 0.0, + "idd2p2h": 0.0, + "idd3p2h": 0.0, + "vdd2l": 0.0, + "idd02l": 0.0, + "idd2n2l": 0.0, + "idd3n2l": 0.0, + "idd4r2l": 0.0, + "idd4w2l": 0.0, + "idd52l": 0.0, + "idd5pb2l": 0.0, + "idd62l": 0.0, + "idd6ds2l": 0.0, + "idd2p2l": 0.0, + "idd3p2l": 0.0, + "vddq": 0.0, + "iBeta_vdd1": 0.0, + "iBeta_vdd2h": 0.0, + "iBeta_vdd2l": 0.0 + }, + "bankwisespec": { + "factRho": 1.0 + }, + "memimpedancespec": { + "ck_termination": true, + "ck_R_eq": 1e6, + "ck_dyn_E": 1e-12, + + "ca_termination": true, + "ca_R_eq": 1e6, + "ca_dyn_E": 1e-12, + + "rdq_termination": true, + "rdq_R_eq": 1e6, + "rdq_dyn_E": 1e-12, + "wdq_termination": true, + "wdq_R_eq": 1e6, + "wdq_dyn_E": 1e-12, + + "wck_termination": true, + "wck_R_eq": 1e6, + "wck_dyn_E": 1e-12, + "rdqs_termination": true, + "rdqs_R_eq": 1e6, + "rdqs_dyn_E": 1e-12 }, "memoryId": "JEDEC_512Mbx16_BG_LPDDR5-4800", "memoryType": "LPDDR5", @@ -55,7 +125,7 @@ "BL_n_S_32": 2, "pbR2act": 5, "pbR2pbR": 54, - "tCK": 1667 + "tCK": 1667e-12 } } } diff --git a/configs/memspec/JEDEC_512Mbx16_BG_LPDDR5-5500.json b/configs/memspec/JEDEC_512Mbx16_BG_LPDDR5-5500.json index 2585925d..8acaf662 100644 --- a/configs/memspec/JEDEC_512Mbx16_BG_LPDDR5-5500.json +++ b/configs/memspec/JEDEC_512Mbx16_BG_LPDDR5-5500.json @@ -11,7 +11,77 @@ "nbrOfDevices": 1, "nbrOfChannels": 1, "width": 16, - "per2BankOffset": 8 + "per2BankOffset": 8, + "WCKalwaysOn": false, + "maxBurstLength": 16 + }, + "mempowerspec": { + "vdd1": 0.0, + "idd01": 0.0, + "idd2n1": 0.0, + "idd3n1": 0.0, + "idd4r1": 0.0, + "idd4w1": 0.0, + "idd51": 0.0, + "idd5pb1": 0.0, + "idd61": 0.0, + "idd6ds1": 0.0, + "idd2p1": 0.0, + "idd3p1": 0.0, + "vdd2h": 0.0, + "idd02h": 0.0, + "idd2n2h": 0.0, + "idd3n2h": 0.0, + "idd4r2h": 0.0, + "idd4w2h": 0.0, + "idd52h": 0.0, + "idd5pb2h": 0.0, + "idd62h": 0.0, + "idd6ds2h": 0.0, + "idd2p2h": 0.0, + "idd3p2h": 0.0, + "vdd2l": 0.0, + "idd02l": 0.0, + "idd2n2l": 0.0, + "idd3n2l": 0.0, + "idd4r2l": 0.0, + "idd4w2l": 0.0, + "idd52l": 0.0, + "idd5pb2l": 0.0, + "idd62l": 0.0, + "idd6ds2l": 0.0, + "idd2p2l": 0.0, + "idd3p2l": 0.0, + "vddq": 0.0, + "iBeta_vdd1": 0.0, + "iBeta_vdd2h": 0.0, + "iBeta_vdd2l": 0.0 + }, + "bankwisespec": { + "factRho": 1.0 + }, + "memimpedancespec": { + "ck_termination": true, + "ck_R_eq": 1e6, + "ck_dyn_E": 1e-12, + + "ca_termination": true, + "ca_R_eq": 1e6, + "ca_dyn_E": 1e-12, + + "rdq_termination": true, + "rdq_R_eq": 1e6, + "rdq_dyn_E": 1e-12, + "wdq_termination": true, + "wdq_R_eq": 1e6, + "wdq_dyn_E": 1e-12, + + "wck_termination": true, + "wck_R_eq": 1e6, + "wck_dyn_E": 1e-12, + "rdqs_termination": true, + "rdqs_R_eq": 1e6, + "rdqs_dyn_E": 1e-12 }, "memoryId": "JEDEC_512Mbx16_BG_LPDDR5-5500", "memoryType": "LPDDR5", @@ -55,7 +125,7 @@ "BL_n_S_32": 2, "pbR2act": 6, "pbR2pbR": 62, - "tCK": 1453 + "tCK": 1453e-12 } } } diff --git a/configs/memspec/JEDEC_512Mbx16_BG_LPDDR5-6000.json b/configs/memspec/JEDEC_512Mbx16_BG_LPDDR5-6000.json index 3da16e77..b6d30adb 100644 --- a/configs/memspec/JEDEC_512Mbx16_BG_LPDDR5-6000.json +++ b/configs/memspec/JEDEC_512Mbx16_BG_LPDDR5-6000.json @@ -11,7 +11,77 @@ "nbrOfDevices": 1, "nbrOfChannels": 1, "width": 16, - "per2BankOffset": 8 + "per2BankOffset": 8, + "WCKalwaysOn": false, + "maxBurstLength": 16 + }, + "mempowerspec": { + "vdd1": 0.0, + "idd01": 0.0, + "idd2n1": 0.0, + "idd3n1": 0.0, + "idd4r1": 0.0, + "idd4w1": 0.0, + "idd51": 0.0, + "idd5pb1": 0.0, + "idd61": 0.0, + "idd6ds1": 0.0, + "idd2p1": 0.0, + "idd3p1": 0.0, + "vdd2h": 0.0, + "idd02h": 0.0, + "idd2n2h": 0.0, + "idd3n2h": 0.0, + "idd4r2h": 0.0, + "idd4w2h": 0.0, + "idd52h": 0.0, + "idd5pb2h": 0.0, + "idd62h": 0.0, + "idd6ds2h": 0.0, + "idd2p2h": 0.0, + "idd3p2h": 0.0, + "vdd2l": 0.0, + "idd02l": 0.0, + "idd2n2l": 0.0, + "idd3n2l": 0.0, + "idd4r2l": 0.0, + "idd4w2l": 0.0, + "idd52l": 0.0, + "idd5pb2l": 0.0, + "idd62l": 0.0, + "idd6ds2l": 0.0, + "idd2p2l": 0.0, + "idd3p2l": 0.0, + "vddq": 0.0, + "iBeta_vdd1": 0.0, + "iBeta_vdd2h": 0.0, + "iBeta_vdd2l": 0.0 + }, + "bankwisespec": { + "factRho": 1.0 + }, + "memimpedancespec": { + "ck_termination": true, + "ck_R_eq": 1e6, + "ck_dyn_E": 1e-12, + + "ca_termination": true, + "ca_R_eq": 1e6, + "ca_dyn_E": 1e-12, + + "rdq_termination": true, + "rdq_R_eq": 1e6, + "rdq_dyn_E": 1e-12, + "wdq_termination": true, + "wdq_R_eq": 1e6, + "wdq_dyn_E": 1e-12, + + "wck_termination": true, + "wck_R_eq": 1e6, + "wck_dyn_E": 1e-12, + "rdqs_termination": true, + "rdqs_R_eq": 1e6, + "rdqs_dyn_E": 1e-12 }, "memoryId": "JEDEC_512Mbx16_BG_LPDDR5-6000", "memoryType": "LPDDR5", @@ -55,7 +125,7 @@ "BL_n_S_32": 2, "pbR2act": 6, "pbR2pbR": 68, - "tCK": 1333 + "tCK": 1333e-12 } } } diff --git a/configs/memspec/JEDEC_512Mbx16_BG_LPDDR5-6400.json b/configs/memspec/JEDEC_512Mbx16_BG_LPDDR5-6400.json index 13eacee2..5c2e362a 100644 --- a/configs/memspec/JEDEC_512Mbx16_BG_LPDDR5-6400.json +++ b/configs/memspec/JEDEC_512Mbx16_BG_LPDDR5-6400.json @@ -11,7 +11,77 @@ "nbrOfDevices": 1, "nbrOfChannels": 1, "width": 16, - "per2BankOffset": 8 + "per2BankOffset": 8, + "WCKalwaysOn": false, + "maxBurstLength": 16 + }, + "mempowerspec": { + "vdd1": 0.0, + "idd01": 0.0, + "idd2n1": 0.0, + "idd3n1": 0.0, + "idd4r1": 0.0, + "idd4w1": 0.0, + "idd51": 0.0, + "idd5pb1": 0.0, + "idd61": 0.0, + "idd6ds1": 0.0, + "idd2p1": 0.0, + "idd3p1": 0.0, + "vdd2h": 0.0, + "idd02h": 0.0, + "idd2n2h": 0.0, + "idd3n2h": 0.0, + "idd4r2h": 0.0, + "idd4w2h": 0.0, + "idd52h": 0.0, + "idd5pb2h": 0.0, + "idd62h": 0.0, + "idd6ds2h": 0.0, + "idd2p2h": 0.0, + "idd3p2h": 0.0, + "vdd2l": 0.0, + "idd02l": 0.0, + "idd2n2l": 0.0, + "idd3n2l": 0.0, + "idd4r2l": 0.0, + "idd4w2l": 0.0, + "idd52l": 0.0, + "idd5pb2l": 0.0, + "idd62l": 0.0, + "idd6ds2l": 0.0, + "idd2p2l": 0.0, + "idd3p2l": 0.0, + "vddq": 0.0, + "iBeta_vdd1": 0.0, + "iBeta_vdd2h": 0.0, + "iBeta_vdd2l": 0.0 + }, + "bankwisespec": { + "factRho": 1.0 + }, + "memimpedancespec": { + "ck_termination": true, + "ck_R_eq": 1e6, + "ck_dyn_E": 1e-12, + + "ca_termination": true, + "ca_R_eq": 1e6, + "ca_dyn_E": 1e-12, + + "rdq_termination": true, + "rdq_R_eq": 1e6, + "rdq_dyn_E": 1e-12, + "wdq_termination": true, + "wdq_R_eq": 1e6, + "wdq_dyn_E": 1e-12, + + "wck_termination": true, + "wck_R_eq": 1e6, + "wck_dyn_E": 1e-12, + "rdqs_termination": true, + "rdqs_R_eq": 1e6, + "rdqs_dyn_E": 1e-12 }, "memoryId": "JEDEC_512Mbx16_BG_LPDDR5-6400", "memoryType": "LPDDR5", @@ -55,7 +125,7 @@ "BL_n_S_32": 2, "pbR2act": 6, "pbR2pbR": 72, - "tCK": 1250 + "tCK": 1250e-12 } } } diff --git a/configs/memspec/JEDEC_512Mbx16_BG_LPDDR5X-3733.json b/configs/memspec/JEDEC_512Mbx16_BG_LPDDR5X-3733.json index c80278b5..6dabd6ac 100644 --- a/configs/memspec/JEDEC_512Mbx16_BG_LPDDR5X-3733.json +++ b/configs/memspec/JEDEC_512Mbx16_BG_LPDDR5X-3733.json @@ -11,7 +11,77 @@ "nbrOfDevices": 1, "nbrOfChannels": 1, "width": 16, - "per2BankOffset": 8 + "per2BankOffset": 8, + "WCKalwaysOn": false, + "maxBurstLength": 16 + }, + "mempowerspec": { + "vdd1": 0.0, + "idd01": 0.0, + "idd2n1": 0.0, + "idd3n1": 0.0, + "idd4r1": 0.0, + "idd4w1": 0.0, + "idd51": 0.0, + "idd5pb1": 0.0, + "idd61": 0.0, + "idd6ds1": 0.0, + "idd2p1": 0.0, + "idd3p1": 0.0, + "vdd2h": 0.0, + "idd02h": 0.0, + "idd2n2h": 0.0, + "idd3n2h": 0.0, + "idd4r2h": 0.0, + "idd4w2h": 0.0, + "idd52h": 0.0, + "idd5pb2h": 0.0, + "idd62h": 0.0, + "idd6ds2h": 0.0, + "idd2p2h": 0.0, + "idd3p2h": 0.0, + "vdd2l": 0.0, + "idd02l": 0.0, + "idd2n2l": 0.0, + "idd3n2l": 0.0, + "idd4r2l": 0.0, + "idd4w2l": 0.0, + "idd52l": 0.0, + "idd5pb2l": 0.0, + "idd62l": 0.0, + "idd6ds2l": 0.0, + "idd2p2l": 0.0, + "idd3p2l": 0.0, + "vddq": 0.0, + "iBeta_vdd1": 0.0, + "iBeta_vdd2h": 0.0, + "iBeta_vdd2l": 0.0 + }, + "bankwisespec": { + "factRho": 1.0 + }, + "memimpedancespec": { + "ck_termination": true, + "ck_R_eq": 1e6, + "ck_dyn_E": 1e-12, + + "ca_termination": true, + "ca_R_eq": 1e6, + "ca_dyn_E": 1e-12, + + "rdq_termination": true, + "rdq_R_eq": 1e6, + "rdq_dyn_E": 1e-12, + "wdq_termination": true, + "wdq_R_eq": 1e6, + "wdq_dyn_E": 1e-12, + + "wck_termination": true, + "wck_R_eq": 1e6, + "wck_dyn_E": 1e-12, + "rdqs_termination": true, + "rdqs_R_eq": 1e6, + "rdqs_dyn_E": 1e-12 }, "memoryId": "JEDEC_512Mbx16_BG_LPDDR5X-3733", "memoryType": "LPDDR5", @@ -57,7 +127,7 @@ "BL_n_S_32": 4, "pbR2act": 4, "pbR2pbR": 42, - "tCK": 2141 + "tCK": 2141e-12 } } } diff --git a/configs/memspec/JEDEC_512Mbx16_BG_LPDDR5X-4267.json b/configs/memspec/JEDEC_512Mbx16_BG_LPDDR5X-4267.json index 1a61b97c..0de8b2c2 100644 --- a/configs/memspec/JEDEC_512Mbx16_BG_LPDDR5X-4267.json +++ b/configs/memspec/JEDEC_512Mbx16_BG_LPDDR5X-4267.json @@ -11,7 +11,77 @@ "nbrOfDevices": 1, "nbrOfChannels": 1, "width": 16, - "per2BankOffset": 8 + "per2BankOffset": 8, + "WCKalwaysOn": false, + "maxBurstLength": 16 + }, + "mempowerspec": { + "vdd1": 0.0, + "idd01": 0.0, + "idd2n1": 0.0, + "idd3n1": 0.0, + "idd4r1": 0.0, + "idd4w1": 0.0, + "idd51": 0.0, + "idd5pb1": 0.0, + "idd61": 0.0, + "idd6ds1": 0.0, + "idd2p1": 0.0, + "idd3p1": 0.0, + "vdd2h": 0.0, + "idd02h": 0.0, + "idd2n2h": 0.0, + "idd3n2h": 0.0, + "idd4r2h": 0.0, + "idd4w2h": 0.0, + "idd52h": 0.0, + "idd5pb2h": 0.0, + "idd62h": 0.0, + "idd6ds2h": 0.0, + "idd2p2h": 0.0, + "idd3p2h": 0.0, + "vdd2l": 0.0, + "idd02l": 0.0, + "idd2n2l": 0.0, + "idd3n2l": 0.0, + "idd4r2l": 0.0, + "idd4w2l": 0.0, + "idd52l": 0.0, + "idd5pb2l": 0.0, + "idd62l": 0.0, + "idd6ds2l": 0.0, + "idd2p2l": 0.0, + "idd3p2l": 0.0, + "vddq": 0.0, + "iBeta_vdd1": 0.0, + "iBeta_vdd2h": 0.0, + "iBeta_vdd2l": 0.0 + }, + "bankwisespec": { + "factRho": 1.0 + }, + "memimpedancespec": { + "ck_termination": true, + "ck_R_eq": 1e6, + "ck_dyn_E": 1e-12, + + "ca_termination": true, + "ca_R_eq": 1e6, + "ca_dyn_E": 1e-12, + + "rdq_termination": true, + "rdq_R_eq": 1e6, + "rdq_dyn_E": 1e-12, + "wdq_termination": true, + "wdq_R_eq": 1e6, + "wdq_dyn_E": 1e-12, + + "wck_termination": true, + "wck_R_eq": 1e6, + "wck_dyn_E": 1e-12, + "rdqs_termination": true, + "rdqs_R_eq": 1e6, + "rdqs_dyn_E": 1e-12 }, "memoryId": "JEDEC_512Mbx16_BG_LPDDR5X-4267", "memoryType": "LPDDR5", @@ -57,7 +127,7 @@ "BL_n_S_32": 4, "pbR2act": 4, "pbR2pbR": 48, - "tCK": 1876 + "tCK": 1876e-12 } } } diff --git a/configs/memspec/JEDEC_512Mbx16_BG_LPDDR5X-4800.json b/configs/memspec/JEDEC_512Mbx16_BG_LPDDR5X-4800.json index 92a74653..a81c31e7 100644 --- a/configs/memspec/JEDEC_512Mbx16_BG_LPDDR5X-4800.json +++ b/configs/memspec/JEDEC_512Mbx16_BG_LPDDR5X-4800.json @@ -11,7 +11,77 @@ "nbrOfDevices": 1, "nbrOfChannels": 1, "width": 16, - "per2BankOffset": 8 + "per2BankOffset": 8, + "WCKalwaysOn": false, + "maxBurstLength": 16 + }, + "mempowerspec": { + "vdd1": 0.0, + "idd01": 0.0, + "idd2n1": 0.0, + "idd3n1": 0.0, + "idd4r1": 0.0, + "idd4w1": 0.0, + "idd51": 0.0, + "idd5pb1": 0.0, + "idd61": 0.0, + "idd6ds1": 0.0, + "idd2p1": 0.0, + "idd3p1": 0.0, + "vdd2h": 0.0, + "idd02h": 0.0, + "idd2n2h": 0.0, + "idd3n2h": 0.0, + "idd4r2h": 0.0, + "idd4w2h": 0.0, + "idd52h": 0.0, + "idd5pb2h": 0.0, + "idd62h": 0.0, + "idd6ds2h": 0.0, + "idd2p2h": 0.0, + "idd3p2h": 0.0, + "vdd2l": 0.0, + "idd02l": 0.0, + "idd2n2l": 0.0, + "idd3n2l": 0.0, + "idd4r2l": 0.0, + "idd4w2l": 0.0, + "idd52l": 0.0, + "idd5pb2l": 0.0, + "idd62l": 0.0, + "idd6ds2l": 0.0, + "idd2p2l": 0.0, + "idd3p2l": 0.0, + "vddq": 0.0, + "iBeta_vdd1": 0.0, + "iBeta_vdd2h": 0.0, + "iBeta_vdd2l": 0.0 + }, + "bankwisespec": { + "factRho": 1.0 + }, + "memimpedancespec": { + "ck_termination": true, + "ck_R_eq": 1e6, + "ck_dyn_E": 1e-12, + + "ca_termination": true, + "ca_R_eq": 1e6, + "ca_dyn_E": 1e-12, + + "rdq_termination": true, + "rdq_R_eq": 1e6, + "rdq_dyn_E": 1e-12, + "wdq_termination": true, + "wdq_R_eq": 1e6, + "wdq_dyn_E": 1e-12, + + "wck_termination": true, + "wck_R_eq": 1e6, + "wck_dyn_E": 1e-12, + "rdqs_termination": true, + "rdqs_R_eq": 1e6, + "rdqs_dyn_E": 1e-12 }, "memoryId": "JEDEC_512Mbx16_BG_LPDDR5X-4800", "memoryType": "LPDDR5", @@ -57,7 +127,7 @@ "BL_n_S_32": 4, "pbR2act": 5, "pbR2pbR": 54, - "tCK": 1667 + "tCK": 1667e-12 } } } diff --git a/configs/memspec/JEDEC_512Mbx16_BG_LPDDR5X-5500.json b/configs/memspec/JEDEC_512Mbx16_BG_LPDDR5X-5500.json index 1e6cf417..20d9fe15 100644 --- a/configs/memspec/JEDEC_512Mbx16_BG_LPDDR5X-5500.json +++ b/configs/memspec/JEDEC_512Mbx16_BG_LPDDR5X-5500.json @@ -11,7 +11,77 @@ "nbrOfDevices": 1, "nbrOfChannels": 1, "width": 16, - "per2BankOffset": 8 + "per2BankOffset": 8, + "WCKalwaysOn": false, + "maxBurstLength": 16 + }, + "mempowerspec": { + "vdd1": 0.0, + "idd01": 0.0, + "idd2n1": 0.0, + "idd3n1": 0.0, + "idd4r1": 0.0, + "idd4w1": 0.0, + "idd51": 0.0, + "idd5pb1": 0.0, + "idd61": 0.0, + "idd6ds1": 0.0, + "idd2p1": 0.0, + "idd3p1": 0.0, + "vdd2h": 0.0, + "idd02h": 0.0, + "idd2n2h": 0.0, + "idd3n2h": 0.0, + "idd4r2h": 0.0, + "idd4w2h": 0.0, + "idd52h": 0.0, + "idd5pb2h": 0.0, + "idd62h": 0.0, + "idd6ds2h": 0.0, + "idd2p2h": 0.0, + "idd3p2h": 0.0, + "vdd2l": 0.0, + "idd02l": 0.0, + "idd2n2l": 0.0, + "idd3n2l": 0.0, + "idd4r2l": 0.0, + "idd4w2l": 0.0, + "idd52l": 0.0, + "idd5pb2l": 0.0, + "idd62l": 0.0, + "idd6ds2l": 0.0, + "idd2p2l": 0.0, + "idd3p2l": 0.0, + "vddq": 0.0, + "iBeta_vdd1": 0.0, + "iBeta_vdd2h": 0.0, + "iBeta_vdd2l": 0.0 + }, + "bankwisespec": { + "factRho": 1.0 + }, + "memimpedancespec": { + "ck_termination": true, + "ck_R_eq": 1e6, + "ck_dyn_E": 1e-12, + + "ca_termination": true, + "ca_R_eq": 1e6, + "ca_dyn_E": 1e-12, + + "rdq_termination": true, + "rdq_R_eq": 1e6, + "rdq_dyn_E": 1e-12, + "wdq_termination": true, + "wdq_R_eq": 1e6, + "wdq_dyn_E": 1e-12, + + "wck_termination": true, + "wck_R_eq": 1e6, + "wck_dyn_E": 1e-12, + "rdqs_termination": true, + "rdqs_R_eq": 1e6, + "rdqs_dyn_E": 1e-12 }, "memoryId": "JEDEC_512Mbx16_BG_LPDDR5X-5500", "memoryType": "LPDDR5", @@ -57,7 +127,7 @@ "BL_n_S_32": 4, "pbR2act": 6, "pbR2pbR": 62, - "tCK": 1453 + "tCK": 1453e-12 } } } diff --git a/configs/memspec/JEDEC_512Mbx16_BG_LPDDR5X-6000.json b/configs/memspec/JEDEC_512Mbx16_BG_LPDDR5X-6000.json index e6111090..3a76f6ea 100644 --- a/configs/memspec/JEDEC_512Mbx16_BG_LPDDR5X-6000.json +++ b/configs/memspec/JEDEC_512Mbx16_BG_LPDDR5X-6000.json @@ -11,7 +11,77 @@ "nbrOfDevices": 1, "nbrOfChannels": 1, "width": 16, - "per2BankOffset": 8 + "per2BankOffset": 8, + "WCKalwaysOn": false, + "maxBurstLength": 16 + }, + "mempowerspec": { + "vdd1": 0.0, + "idd01": 0.0, + "idd2n1": 0.0, + "idd3n1": 0.0, + "idd4r1": 0.0, + "idd4w1": 0.0, + "idd51": 0.0, + "idd5pb1": 0.0, + "idd61": 0.0, + "idd6ds1": 0.0, + "idd2p1": 0.0, + "idd3p1": 0.0, + "vdd2h": 0.0, + "idd02h": 0.0, + "idd2n2h": 0.0, + "idd3n2h": 0.0, + "idd4r2h": 0.0, + "idd4w2h": 0.0, + "idd52h": 0.0, + "idd5pb2h": 0.0, + "idd62h": 0.0, + "idd6ds2h": 0.0, + "idd2p2h": 0.0, + "idd3p2h": 0.0, + "vdd2l": 0.0, + "idd02l": 0.0, + "idd2n2l": 0.0, + "idd3n2l": 0.0, + "idd4r2l": 0.0, + "idd4w2l": 0.0, + "idd52l": 0.0, + "idd5pb2l": 0.0, + "idd62l": 0.0, + "idd6ds2l": 0.0, + "idd2p2l": 0.0, + "idd3p2l": 0.0, + "vddq": 0.0, + "iBeta_vdd1": 0.0, + "iBeta_vdd2h": 0.0, + "iBeta_vdd2l": 0.0 + }, + "bankwisespec": { + "factRho": 1.0 + }, + "memimpedancespec": { + "ck_termination": true, + "ck_R_eq": 1e6, + "ck_dyn_E": 1e-12, + + "ca_termination": true, + "ca_R_eq": 1e6, + "ca_dyn_E": 1e-12, + + "rdq_termination": true, + "rdq_R_eq": 1e6, + "rdq_dyn_E": 1e-12, + "wdq_termination": true, + "wdq_R_eq": 1e6, + "wdq_dyn_E": 1e-12, + + "wck_termination": true, + "wck_R_eq": 1e6, + "wck_dyn_E": 1e-12, + "rdqs_termination": true, + "rdqs_R_eq": 1e6, + "rdqs_dyn_E": 1e-12 }, "memoryId": "JEDEC_512Mbx16_BG_LPDDR5X-6000", "memoryType": "LPDDR5", @@ -57,7 +127,7 @@ "BL_n_S_32": 4, "pbR2act": 6, "pbR2pbR": 68, - "tCK": 1333 + "tCK": 1333e-12 } } } diff --git a/configs/memspec/JEDEC_512Mbx16_BG_LPDDR5X-6400.json b/configs/memspec/JEDEC_512Mbx16_BG_LPDDR5X-6400.json index a416ef4b..4242da9f 100644 --- a/configs/memspec/JEDEC_512Mbx16_BG_LPDDR5X-6400.json +++ b/configs/memspec/JEDEC_512Mbx16_BG_LPDDR5X-6400.json @@ -11,7 +11,77 @@ "nbrOfDevices": 1, "nbrOfChannels": 1, "width": 16, - "per2BankOffset": 8 + "per2BankOffset": 8, + "WCKalwaysOn": false, + "maxBurstLength": 16 + }, + "mempowerspec": { + "vdd1": 0.0, + "idd01": 0.0, + "idd2n1": 0.0, + "idd3n1": 0.0, + "idd4r1": 0.0, + "idd4w1": 0.0, + "idd51": 0.0, + "idd5pb1": 0.0, + "idd61": 0.0, + "idd6ds1": 0.0, + "idd2p1": 0.0, + "idd3p1": 0.0, + "vdd2h": 0.0, + "idd02h": 0.0, + "idd2n2h": 0.0, + "idd3n2h": 0.0, + "idd4r2h": 0.0, + "idd4w2h": 0.0, + "idd52h": 0.0, + "idd5pb2h": 0.0, + "idd62h": 0.0, + "idd6ds2h": 0.0, + "idd2p2h": 0.0, + "idd3p2h": 0.0, + "vdd2l": 0.0, + "idd02l": 0.0, + "idd2n2l": 0.0, + "idd3n2l": 0.0, + "idd4r2l": 0.0, + "idd4w2l": 0.0, + "idd52l": 0.0, + "idd5pb2l": 0.0, + "idd62l": 0.0, + "idd6ds2l": 0.0, + "idd2p2l": 0.0, + "idd3p2l": 0.0, + "vddq": 0.0, + "iBeta_vdd1": 0.0, + "iBeta_vdd2h": 0.0, + "iBeta_vdd2l": 0.0 + }, + "bankwisespec": { + "factRho": 1.0 + }, + "memimpedancespec": { + "ck_termination": true, + "ck_R_eq": 1e6, + "ck_dyn_E": 1e-12, + + "ca_termination": true, + "ca_R_eq": 1e6, + "ca_dyn_E": 1e-12, + + "rdq_termination": true, + "rdq_R_eq": 1e6, + "rdq_dyn_E": 1e-12, + "wdq_termination": true, + "wdq_R_eq": 1e6, + "wdq_dyn_E": 1e-12, + + "wck_termination": true, + "wck_R_eq": 1e6, + "wck_dyn_E": 1e-12, + "rdqs_termination": true, + "rdqs_R_eq": 1e6, + "rdqs_dyn_E": 1e-12 }, "memoryId": "JEDEC_512Mbx16_BG_LPDDR5X-6400", "memoryType": "LPDDR5", @@ -57,7 +127,7 @@ "BL_n_S_32": 4, "pbR2act": 6, "pbR2pbR": 72, - "tCK": 1250 + "tCK": 1250e-12 } } } diff --git a/configs/memspec/JEDEC_512Mbx16_BG_LPDDR5X-7500.json b/configs/memspec/JEDEC_512Mbx16_BG_LPDDR5X-7500.json index 0fea8c55..efd4e915 100644 --- a/configs/memspec/JEDEC_512Mbx16_BG_LPDDR5X-7500.json +++ b/configs/memspec/JEDEC_512Mbx16_BG_LPDDR5X-7500.json @@ -11,7 +11,77 @@ "nbrOfDevices": 1, "nbrOfChannels": 1, "width": 16, - "per2BankOffset": 8 + "per2BankOffset": 8, + "WCKalwaysOn": false, + "maxBurstLength": 16 + }, + "mempowerspec": { + "vdd1": 0.0, + "idd01": 0.0, + "idd2n1": 0.0, + "idd3n1": 0.0, + "idd4r1": 0.0, + "idd4w1": 0.0, + "idd51": 0.0, + "idd5pb1": 0.0, + "idd61": 0.0, + "idd6ds1": 0.0, + "idd2p1": 0.0, + "idd3p1": 0.0, + "vdd2h": 0.0, + "idd02h": 0.0, + "idd2n2h": 0.0, + "idd3n2h": 0.0, + "idd4r2h": 0.0, + "idd4w2h": 0.0, + "idd52h": 0.0, + "idd5pb2h": 0.0, + "idd62h": 0.0, + "idd6ds2h": 0.0, + "idd2p2h": 0.0, + "idd3p2h": 0.0, + "vdd2l": 0.0, + "idd02l": 0.0, + "idd2n2l": 0.0, + "idd3n2l": 0.0, + "idd4r2l": 0.0, + "idd4w2l": 0.0, + "idd52l": 0.0, + "idd5pb2l": 0.0, + "idd62l": 0.0, + "idd6ds2l": 0.0, + "idd2p2l": 0.0, + "idd3p2l": 0.0, + "vddq": 0.0, + "iBeta_vdd1": 0.0, + "iBeta_vdd2h": 0.0, + "iBeta_vdd2l": 0.0 + }, + "bankwisespec": { + "factRho": 1.0 + }, + "memimpedancespec": { + "ck_termination": true, + "ck_R_eq": 1e6, + "ck_dyn_E": 1e-12, + + "ca_termination": true, + "ca_R_eq": 1e6, + "ca_dyn_E": 1e-12, + + "rdq_termination": true, + "rdq_R_eq": 1e6, + "rdq_dyn_E": 1e-12, + "wdq_termination": true, + "wdq_R_eq": 1e6, + "wdq_dyn_E": 1e-12, + + "wck_termination": true, + "wck_R_eq": 1e6, + "wck_dyn_E": 1e-12, + "rdqs_termination": true, + "rdqs_R_eq": 1e6, + "rdqs_dyn_E": 1e-12 }, "memoryId": "JEDEC_512Mbx16_BG_LPDDR5X-7500", "memoryType": "LPDDR5", @@ -57,7 +127,7 @@ "BL_n_S_32": 4, "pbR2act": 8, "pbR2pbR": 85, - "tCK": 1066 + "tCK": 1066e-12 } } } diff --git a/configs/memspec/JEDEC_512Mbx16_BG_LPDDR5X-8533.json b/configs/memspec/JEDEC_512Mbx16_BG_LPDDR5X-8533.json index 78b6acda..d111af92 100644 --- a/configs/memspec/JEDEC_512Mbx16_BG_LPDDR5X-8533.json +++ b/configs/memspec/JEDEC_512Mbx16_BG_LPDDR5X-8533.json @@ -11,7 +11,77 @@ "nbrOfDevices": 1, "nbrOfChannels": 1, "width": 16, - "per2BankOffset": 8 + "per2BankOffset": 8, + "WCKalwaysOn": false, + "maxBurstLength": 16 + }, + "mempowerspec": { + "vdd1": 0.0, + "idd01": 0.0, + "idd2n1": 0.0, + "idd3n1": 0.0, + "idd4r1": 0.0, + "idd4w1": 0.0, + "idd51": 0.0, + "idd5pb1": 0.0, + "idd61": 0.0, + "idd6ds1": 0.0, + "idd2p1": 0.0, + "idd3p1": 0.0, + "vdd2h": 0.0, + "idd02h": 0.0, + "idd2n2h": 0.0, + "idd3n2h": 0.0, + "idd4r2h": 0.0, + "idd4w2h": 0.0, + "idd52h": 0.0, + "idd5pb2h": 0.0, + "idd62h": 0.0, + "idd6ds2h": 0.0, + "idd2p2h": 0.0, + "idd3p2h": 0.0, + "vdd2l": 0.0, + "idd02l": 0.0, + "idd2n2l": 0.0, + "idd3n2l": 0.0, + "idd4r2l": 0.0, + "idd4w2l": 0.0, + "idd52l": 0.0, + "idd5pb2l": 0.0, + "idd62l": 0.0, + "idd6ds2l": 0.0, + "idd2p2l": 0.0, + "idd3p2l": 0.0, + "vddq": 0.0, + "iBeta_vdd1": 0.0, + "iBeta_vdd2h": 0.0, + "iBeta_vdd2l": 0.0 + }, + "bankwisespec": { + "factRho": 1.0 + }, + "memimpedancespec": { + "ck_termination": true, + "ck_R_eq": 1e6, + "ck_dyn_E": 1e-12, + + "ca_termination": true, + "ca_R_eq": 1e6, + "ca_dyn_E": 1e-12, + + "rdq_termination": true, + "rdq_R_eq": 1e6, + "rdq_dyn_E": 1e-12, + "wdq_termination": true, + "wdq_R_eq": 1e6, + "wdq_dyn_E": 1e-12, + + "wck_termination": true, + "wck_R_eq": 1e6, + "wck_dyn_E": 1e-12, + "rdqs_termination": true, + "rdqs_R_eq": 1e6, + "rdqs_dyn_E": 1e-12 }, "memoryId": "JEDEC_512Mbx16_BG_LPDDR5X-8533", "memoryType": "LPDDR5", @@ -57,7 +127,7 @@ "BL_n_S_32": 4, "pbR2act": 8, "pbR2pbR": 96, - "tCK": 937 + "tCK": 937e-12 } } } diff --git a/configs/memspec/JEDEC_512Mbx16_LPDDR4-0533.json b/configs/memspec/JEDEC_512Mbx16_LPDDR4-0533.json index 556d67fb..86bf4493 100644 --- a/configs/memspec/JEDEC_512Mbx16_LPDDR4-0533.json +++ b/configs/memspec/JEDEC_512Mbx16_LPDDR4-0533.json @@ -9,7 +9,9 @@ "nbrOfRows": 65536, "width": 16, "nbrOfDevices": 1, - "nbrOfChannels": 1 + "nbrOfChannels": 1, + "nbrOfBankGroups": 1, + "maxBurstLength": 16 }, "memoryId": "JEDEC_512Mbx16_LPDDR4-0533", "memoryType": "LPDDR4", @@ -26,15 +28,15 @@ "PPD": 4, "RCD": 5, "REFI": 1041, - "REFIPB": 130, - "RFCAB": 75, - "RFCPB": 38, + "REFIpb": 130, + "RFCab": 75, + "RFCpb": 38, "RL": 6, "RAS": 12, - "RPAB": 6, - "RPPB": 5, - "RCAB": 18, - "RCPB": 17, + "RPab": 6, + "RPpb": 5, + "RCab": 18, + "RCpb": 17, "RPST": 0, "RRD": 4, "RTP": 8, @@ -46,7 +48,63 @@ "XP": 5, "XSR": 77, "RTRS": 1, - "tCK": 3759 + "tCK": 3759e-12 + }, + "mempowerspec": { + "vdd1": 0.0, + "idd01": 0.0, + "idd2n1": 0.0, + "idd3n1": 0.0, + "idd4r1": 0.0, + "idd4w1": 0.0, + "idd51": 0.0, + "idd5pb1": 0.0, + "idd61": 0.0, + "idd2p1": 0.0, + "idd3p1": 0.0, + "vdd2": 0.0, + "idd02": 0.0, + "idd2n2": 0.0, + "idd3n2": 0.0, + "idd4r2": 0.0, + "idd4w2": 0.0, + "idd52": 0.0, + "idd5pb2": 0.0, + "idd62": 0.0, + "idd2p2": 0.0, + "idd3p2": 0.0, + "vddq": 0.0, + "iBeta_vdd1": 0.0, + "iBeta_vdd2": 0.0 + }, + "memimpedancespec": { + "ck_termination": true, + "ck_R_eq": 1e6, + "ck_dyn_E": 1e-12, + + "ca_termination": true, + "ca_R_eq": 1e6, + "ca_dyn_E": 1e-12, + + "rdq_termination": true, + "rdq_R_eq": 1e6, + "rdq_dyn_E": 1e-12, + "wdq_termination": true, + "wdq_R_eq": 1e6, + "wdq_dyn_E": 1e-12, + + "wdqs_termination": true, + "wdqs_R_eq": 1e6, + "wdqs_dyn_E": 1e-12, + "rdqs_termination": true, + "rdqs_R_eq": 1e6, + "rdqs_dyn_E": 1e-12 + }, + "bankwisespec": { + "factRho": 1, + "factSigma": 1, + "pasrMode": 0, + "hasPASR": false } } } diff --git a/configs/memspec/JEDEC_512Mbx16_LPDDR4-1066.json b/configs/memspec/JEDEC_512Mbx16_LPDDR4-1066.json index fa387e2d..b4f6fbef 100644 --- a/configs/memspec/JEDEC_512Mbx16_LPDDR4-1066.json +++ b/configs/memspec/JEDEC_512Mbx16_LPDDR4-1066.json @@ -9,7 +9,9 @@ "nbrOfRows": 65536, "width": 16, "nbrOfDevices": 1, - "nbrOfChannels": 1 + "nbrOfChannels": 1, + "nbrOfBankGroups": 1, + "maxBurstLength": 16 }, "memoryId": "JEDEC_512Mbx16_LPDDR4-1066", "memoryType": "LPDDR4", @@ -26,15 +28,15 @@ "PPD": 4, "RCD": 10, "REFI": 2082, - "REFIPB": 260, - "RFCAB": 150, - "RFCPB": 75, + "REFIpb": 260, + "RFCab": 150, + "RFCpb": 75, "RL": 10, "RAS": 23, - "RPAB": 12, - "RPPB": 10, - "RCAB": 35, - "RCPB": 33, + "RPab": 12, + "RPpb": 10, + "RCab": 35, + "RCpb": 33, "RPST": 0, "RRD": 6, "RTP": 8, @@ -46,7 +48,63 @@ "XP": 5, "XSR": 154, "RTRS": 1, - "tCK": 1876 + "tCK": 1876e-12 + }, + "mempowerspec": { + "vdd1": 0.0, + "idd01": 0.0, + "idd2n1": 0.0, + "idd3n1": 0.0, + "idd4r1": 0.0, + "idd4w1": 0.0, + "idd51": 0.0, + "idd5pb1": 0.0, + "idd61": 0.0, + "idd2p1": 0.0, + "idd3p1": 0.0, + "vdd2": 0.0, + "idd02": 0.0, + "idd2n2": 0.0, + "idd3n2": 0.0, + "idd4r2": 0.0, + "idd4w2": 0.0, + "idd52": 0.0, + "idd5pb2": 0.0, + "idd62": 0.0, + "idd2p2": 0.0, + "idd3p2": 0.0, + "vddq": 0.0, + "iBeta_vdd1": 0.0, + "iBeta_vdd2": 0.0 + }, + "memimpedancespec": { + "ck_termination": true, + "ck_R_eq": 1e6, + "ck_dyn_E": 1e-12, + + "ca_termination": true, + "ca_R_eq": 1e6, + "ca_dyn_E": 1e-12, + + "rdq_termination": true, + "rdq_R_eq": 1e6, + "rdq_dyn_E": 1e-12, + "wdq_termination": true, + "wdq_R_eq": 1e6, + "wdq_dyn_E": 1e-12, + + "wdqs_termination": true, + "wdqs_R_eq": 1e6, + "wdqs_dyn_E": 1e-12, + "rdqs_termination": true, + "rdqs_R_eq": 1e6, + "rdqs_dyn_E": 1e-12 + }, + "bankwisespec": { + "factRho": 1, + "factSigma": 1, + "pasrMode": 0, + "hasPASR": false } } } diff --git a/configs/memspec/JEDEC_512Mbx16_LPDDR4-1600.json b/configs/memspec/JEDEC_512Mbx16_LPDDR4-1600.json index c26f8133..d5b8e300 100644 --- a/configs/memspec/JEDEC_512Mbx16_LPDDR4-1600.json +++ b/configs/memspec/JEDEC_512Mbx16_LPDDR4-1600.json @@ -9,7 +9,9 @@ "nbrOfRows": 65536, "width": 16, "nbrOfDevices": 1, - "nbrOfChannels": 1 + "nbrOfChannels": 1, + "nbrOfBankGroups": 1, + "maxBurstLength": 16 }, "memoryId": "JEDEC_512Mbx16_LPDDR4-1600", "memoryType": "LPDDR4", @@ -26,15 +28,15 @@ "PPD": 4, "RCD": 15, "REFI": 3123, - "REFIPB": 390, - "RFCAB": 224, - "RFCPB": 112, + "REFIpb": 390, + "RFCab": 224, + "RFCpb": 112, "RL": 14, "RAS": 34, - "RPAB": 17, - "RPPB": 15, - "RCAB": 51, - "RCPB": 49, + "RPab": 17, + "RPpb": 15, + "RCab": 51, + "RCpb": 49, "RPST": 0, "RRD": 8, "RTP": 8, @@ -46,7 +48,63 @@ "XP": 6, "XSR": 230, "RTRS": 1, - "tCK": 1250 + "tCK": 1250e-12 + }, + "mempowerspec": { + "vdd1": 0.0, + "idd01": 0.0, + "idd2n1": 0.0, + "idd3n1": 0.0, + "idd4r1": 0.0, + "idd4w1": 0.0, + "idd51": 0.0, + "idd5pb1": 0.0, + "idd61": 0.0, + "idd2p1": 0.0, + "idd3p1": 0.0, + "vdd2": 0.0, + "idd02": 0.0, + "idd2n2": 0.0, + "idd3n2": 0.0, + "idd4r2": 0.0, + "idd4w2": 0.0, + "idd52": 0.0, + "idd5pb2": 0.0, + "idd62": 0.0, + "idd2p2": 0.0, + "idd3p2": 0.0, + "vddq": 0.0, + "iBeta_vdd1": 0.0, + "iBeta_vdd2": 0.0 + }, + "memimpedancespec": { + "ck_termination": true, + "ck_R_eq": 1e6, + "ck_dyn_E": 1e-12, + + "ca_termination": true, + "ca_R_eq": 1e6, + "ca_dyn_E": 1e-12, + + "rdq_termination": true, + "rdq_R_eq": 1e6, + "rdq_dyn_E": 1e-12, + "wdq_termination": true, + "wdq_R_eq": 1e6, + "wdq_dyn_E": 1e-12, + + "wdqs_termination": true, + "wdqs_R_eq": 1e6, + "wdqs_dyn_E": 1e-12, + "rdqs_termination": true, + "rdqs_R_eq": 1e6, + "rdqs_dyn_E": 1e-12 + }, + "bankwisespec": { + "factRho": 1, + "factSigma": 1, + "pasrMode": 0, + "hasPASR": false } } } diff --git a/configs/memspec/JEDEC_512Mbx16_LPDDR4-2133.json b/configs/memspec/JEDEC_512Mbx16_LPDDR4-2133.json index 1ec1702d..81351693 100644 --- a/configs/memspec/JEDEC_512Mbx16_LPDDR4-2133.json +++ b/configs/memspec/JEDEC_512Mbx16_LPDDR4-2133.json @@ -9,7 +9,9 @@ "nbrOfRows": 65536, "width": 16, "nbrOfDevices": 1, - "nbrOfChannels": 1 + "nbrOfChannels": 1, + "nbrOfBankGroups": 1, + "maxBurstLength": 16 }, "memoryId": "JEDEC_512Mbx16_LPDDR4-2133", "memoryType": "LPDDR4", @@ -26,15 +28,15 @@ "PPD": 4, "RCD": 20, "REFI": 4166, - "REFIPB": 520, - "RFCAB": 299, - "RFCPB": 150, + "REFIpb": 520, + "RFCab": 299, + "RFCpb": 150, "RL": 20, "RAS": 45, - "RPAB": 23, - "RPPB": 20, - "RCAB": 68, - "RCPB": 65, + "RPab": 23, + "RPpb": 20, + "RCab": 68, + "RCpb": 65, "RPST": 0, "RRD": 11, "RTP": 9, @@ -46,7 +48,63 @@ "XP": 9, "XSR": 307, "RTRS": 1, - "tCK": 938 + "tCK": 938e-12 + }, + "mempowerspec": { + "vdd1": 0.0, + "idd01": 0.0, + "idd2n1": 0.0, + "idd3n1": 0.0, + "idd4r1": 0.0, + "idd4w1": 0.0, + "idd51": 0.0, + "idd5pb1": 0.0, + "idd61": 0.0, + "idd2p1": 0.0, + "idd3p1": 0.0, + "vdd2": 0.0, + "idd02": 0.0, + "idd2n2": 0.0, + "idd3n2": 0.0, + "idd4r2": 0.0, + "idd4w2": 0.0, + "idd52": 0.0, + "idd5pb2": 0.0, + "idd62": 0.0, + "idd2p2": 0.0, + "idd3p2": 0.0, + "vddq": 0.0, + "iBeta_vdd1": 0.0, + "iBeta_vdd2": 0.0 + }, + "memimpedancespec": { + "ck_termination": true, + "ck_R_eq": 1e6, + "ck_dyn_E": 1e-12, + + "ca_termination": true, + "ca_R_eq": 1e6, + "ca_dyn_E": 1e-12, + + "rdq_termination": true, + "rdq_R_eq": 1e6, + "rdq_dyn_E": 1e-12, + "wdq_termination": true, + "wdq_R_eq": 1e6, + "wdq_dyn_E": 1e-12, + + "wdqs_termination": true, + "wdqs_R_eq": 1e6, + "wdqs_dyn_E": 1e-12, + "rdqs_termination": true, + "rdqs_R_eq": 1e6, + "rdqs_dyn_E": 1e-12 + }, + "bankwisespec": { + "factRho": 1, + "factSigma": 1, + "pasrMode": 0, + "hasPASR": false } } } diff --git a/configs/memspec/JEDEC_512Mbx16_LPDDR4-2666.json b/configs/memspec/JEDEC_512Mbx16_LPDDR4-2666.json index 4eb32330..b9f0d459 100644 --- a/configs/memspec/JEDEC_512Mbx16_LPDDR4-2666.json +++ b/configs/memspec/JEDEC_512Mbx16_LPDDR4-2666.json @@ -9,7 +9,9 @@ "nbrOfRows": 65536, "width": 16, "nbrOfDevices": 1, - "nbrOfChannels": 1 + "nbrOfChannels": 1, + "nbrOfBankGroups": 1, + "maxBurstLength": 16 }, "memoryId": "JEDEC_512Mbx16_LPDDR4-2666", "memoryType": "LPDDR4", @@ -26,15 +28,15 @@ "PPD": 4, "RCD": 24, "REFI": 5205, - "REFIPB": 650, - "RFCAB": 374, - "RFCPB": 187, + "REFIpb": 650, + "RFCab": 374, + "RFCpb": 187, "RL": 24, "RAS": 56, - "RPAB": 28, - "RPPB": 24, - "RCAB": 84, - "RCPB": 80, + "RPab": 28, + "RPpb": 24, + "RCab": 84, + "RCpb": 80, "RPST": 0, "RRD": 14, "RTP": 10, @@ -46,7 +48,63 @@ "XP": 10, "XSR": 384, "RTRS": 1, - "tCK": 750 + "tCK": 750e-12 + }, + "mempowerspec": { + "vdd1": 0.0, + "idd01": 0.0, + "idd2n1": 0.0, + "idd3n1": 0.0, + "idd4r1": 0.0, + "idd4w1": 0.0, + "idd51": 0.0, + "idd5pb1": 0.0, + "idd61": 0.0, + "idd2p1": 0.0, + "idd3p1": 0.0, + "vdd2": 0.0, + "idd02": 0.0, + "idd2n2": 0.0, + "idd3n2": 0.0, + "idd4r2": 0.0, + "idd4w2": 0.0, + "idd52": 0.0, + "idd5pb2": 0.0, + "idd62": 0.0, + "idd2p2": 0.0, + "idd3p2": 0.0, + "vddq": 0.0, + "iBeta_vdd1": 0.0, + "iBeta_vdd2": 0.0 + }, + "memimpedancespec": { + "ck_termination": true, + "ck_R_eq": 1e6, + "ck_dyn_E": 1e-12, + + "ca_termination": true, + "ca_R_eq": 1e6, + "ca_dyn_E": 1e-12, + + "rdq_termination": true, + "rdq_R_eq": 1e6, + "rdq_dyn_E": 1e-12, + "wdq_termination": true, + "wdq_R_eq": 1e6, + "wdq_dyn_E": 1e-12, + + "wdqs_termination": true, + "wdqs_R_eq": 1e6, + "wdqs_dyn_E": 1e-12, + "rdqs_termination": true, + "rdqs_R_eq": 1e6, + "rdqs_dyn_E": 1e-12 + }, + "bankwisespec": { + "factRho": 1, + "factSigma": 1, + "pasrMode": 0, + "hasPASR": false } } } diff --git a/configs/memspec/JEDEC_512Mbx16_LPDDR4-3200.json b/configs/memspec/JEDEC_512Mbx16_LPDDR4-3200.json index 54ce463a..887d50d8 100644 --- a/configs/memspec/JEDEC_512Mbx16_LPDDR4-3200.json +++ b/configs/memspec/JEDEC_512Mbx16_LPDDR4-3200.json @@ -9,7 +9,9 @@ "nbrOfRows": 65536, "width": 16, "nbrOfDevices": 1, - "nbrOfChannels": 1 + "nbrOfChannels": 1, + "nbrOfBankGroups": 1, + "maxBurstLength": 16 }, "memoryId": "JEDEC_512Mbx16_LPDDR4-3200", "memoryType": "LPDDR4", @@ -26,15 +28,15 @@ "PPD": 4, "RCD": 29, "REFI": 6246, - "REFIPB": 780, - "RFCAB": 448, - "RFCPB": 224, + "REFIpb": 780, + "RFCab": 448, + "RFCpb": 224, "RL": 28, "RAS": 68, - "RPAB": 34, - "RPPB": 29, - "RCAB": 102, - "RCPB": 97, + "RPab": 34, + "RPpb": 29, + "RCab": 102, + "RCpb": 97, "RPST": 0, "RRD": 16, "RTP": 12, @@ -46,7 +48,63 @@ "XP": 12, "XSR": 460, "RTRS": 1, - "tCK": 625 + "tCK": 625e-12 + }, + "mempowerspec": { + "vdd1": 0.0, + "idd01": 0.0, + "idd2n1": 0.0, + "idd3n1": 0.0, + "idd4r1": 0.0, + "idd4w1": 0.0, + "idd51": 0.0, + "idd5pb1": 0.0, + "idd61": 0.0, + "idd2p1": 0.0, + "idd3p1": 0.0, + "vdd2": 0.0, + "idd02": 0.0, + "idd2n2": 0.0, + "idd3n2": 0.0, + "idd4r2": 0.0, + "idd4w2": 0.0, + "idd52": 0.0, + "idd5pb2": 0.0, + "idd62": 0.0, + "idd2p2": 0.0, + "idd3p2": 0.0, + "vddq": 0.0, + "iBeta_vdd1": 0.0, + "iBeta_vdd2": 0.0 + }, + "memimpedancespec": { + "ck_termination": true, + "ck_R_eq": 1e6, + "ck_dyn_E": 1e-12, + + "ca_termination": true, + "ca_R_eq": 1e6, + "ca_dyn_E": 1e-12, + + "rdq_termination": true, + "rdq_R_eq": 1e6, + "rdq_dyn_E": 1e-12, + "wdq_termination": true, + "wdq_R_eq": 1e6, + "wdq_dyn_E": 1e-12, + + "wdqs_termination": true, + "wdqs_R_eq": 1e6, + "wdqs_dyn_E": 1e-12, + "rdqs_termination": true, + "rdqs_R_eq": 1e6, + "rdqs_dyn_E": 1e-12 + }, + "bankwisespec": { + "factRho": 1, + "factSigma": 1, + "pasrMode": 0, + "hasPASR": false } } } diff --git a/configs/memspec/JEDEC_512Mbx16_LPDDR4-3733.json b/configs/memspec/JEDEC_512Mbx16_LPDDR4-3733.json index c38fec29..898f4bcc 100644 --- a/configs/memspec/JEDEC_512Mbx16_LPDDR4-3733.json +++ b/configs/memspec/JEDEC_512Mbx16_LPDDR4-3733.json @@ -9,7 +9,9 @@ "nbrOfRows": 65536, "width": 16, "nbrOfDevices": 1, - "nbrOfChannels": 1 + "nbrOfChannels": 1, + "nbrOfBankGroups": 1, + "maxBurstLength": 16 }, "memoryId": "JEDEC_512Mbx16_LPDDR4-3733", "memoryType": "LPDDR4", @@ -26,15 +28,15 @@ "PPD": 4, "RCD": 34, "REFI": 7297, - "REFIPB": 912, - "RFCAB": 524, - "RFCPB": 262, + "REFIpb": 912, + "RFCab": 524, + "RFCpb": 262, "RL": 32, "RAS": 79, - "RPAB": 40, - "RPPB": 34, - "RCAB": 119, - "RCPB": 113, + "RPab": 40, + "RPpb": 34, + "RCab": 119, + "RCpb": 113, "RPST": 0, "RRD": 19, "RTP": 15, @@ -46,7 +48,63 @@ "XP": 15, "XSR": 538, "RTRS": 1, - "tCK": 536 + "tCK": 536e-12 + }, + "mempowerspec": { + "vdd1": 0.0, + "idd01": 0.0, + "idd2n1": 0.0, + "idd3n1": 0.0, + "idd4r1": 0.0, + "idd4w1": 0.0, + "idd51": 0.0, + "idd5pb1": 0.0, + "idd61": 0.0, + "idd2p1": 0.0, + "idd3p1": 0.0, + "vdd2": 0.0, + "idd02": 0.0, + "idd2n2": 0.0, + "idd3n2": 0.0, + "idd4r2": 0.0, + "idd4w2": 0.0, + "idd52": 0.0, + "idd5pb2": 0.0, + "idd62": 0.0, + "idd2p2": 0.0, + "idd3p2": 0.0, + "vddq": 0.0, + "iBeta_vdd1": 0.0, + "iBeta_vdd2": 0.0 + }, + "memimpedancespec": { + "ck_termination": true, + "ck_R_eq": 1e6, + "ck_dyn_E": 1e-12, + + "ca_termination": true, + "ca_R_eq": 1e6, + "ca_dyn_E": 1e-12, + + "rdq_termination": true, + "rdq_R_eq": 1e6, + "rdq_dyn_E": 1e-12, + "wdq_termination": true, + "wdq_R_eq": 1e6, + "wdq_dyn_E": 1e-12, + + "wdqs_termination": true, + "wdqs_R_eq": 1e6, + "wdqs_dyn_E": 1e-12, + "rdqs_termination": true, + "rdqs_R_eq": 1e6, + "rdqs_dyn_E": 1e-12 + }, + "bankwisespec": { + "factRho": 1, + "factSigma": 1, + "pasrMode": 0, + "hasPASR": false } } } diff --git a/configs/memspec/JEDEC_512Mbx16_LPDDR4-4266.json b/configs/memspec/JEDEC_512Mbx16_LPDDR4-4266.json index 54355a27..2842cfa6 100644 --- a/configs/memspec/JEDEC_512Mbx16_LPDDR4-4266.json +++ b/configs/memspec/JEDEC_512Mbx16_LPDDR4-4266.json @@ -9,7 +9,9 @@ "nbrOfRows": 65536, "width": 16, "nbrOfDevices": 1, - "nbrOfChannels": 1 + "nbrOfChannels": 1, + "nbrOfBankGroups": 1, + "maxBurstLength": 16 }, "memoryId": "JEDEC_512Mbx16_LPDDR4-4266", "memoryType": "LPDDR4", @@ -26,15 +28,15 @@ "PPD": 4, "RCD": 39, "REFI": 8341, - "REFIPB": 1042, - "RFCAB": 599, - "RFCPB": 300, + "REFIpb": 1042, + "RFCab": 599, + "RFCpb": 300, "RL": 36, "RAS": 90, - "RPAB": 45, - "RPPB": 39, - "RCAB": 135, - "RCPB": 129, + "RPab": 45, + "RPpb": 39, + "RCab": 135, + "RCpb": 129, "RPST": 0, "RRD": 22, "RTP": 17, @@ -46,7 +48,63 @@ "XP": 17, "XSR": 615, "RTRS": 1, - "tCK": 469 + "tCK": 469e-12 + }, + "mempowerspec": { + "vdd1": 0.0, + "idd01": 0.0, + "idd2n1": 0.0, + "idd3n1": 0.0, + "idd4r1": 0.0, + "idd4w1": 0.0, + "idd51": 0.0, + "idd5pb1": 0.0, + "idd61": 0.0, + "idd2p1": 0.0, + "idd3p1": 0.0, + "vdd2": 0.0, + "idd02": 0.0, + "idd2n2": 0.0, + "idd3n2": 0.0, + "idd4r2": 0.0, + "idd4w2": 0.0, + "idd52": 0.0, + "idd5pb2": 0.0, + "idd62": 0.0, + "idd2p2": 0.0, + "idd3p2": 0.0, + "vddq": 0.0, + "iBeta_vdd1": 0.0, + "iBeta_vdd2": 0.0 + }, + "memimpedancespec": { + "ck_termination": true, + "ck_R_eq": 1e6, + "ck_dyn_E": 1e-12, + + "ca_termination": true, + "ca_R_eq": 1e6, + "ca_dyn_E": 1e-12, + + "rdq_termination": true, + "rdq_R_eq": 1e6, + "rdq_dyn_E": 1e-12, + "wdq_termination": true, + "wdq_R_eq": 1e6, + "wdq_dyn_E": 1e-12, + + "wdqs_termination": true, + "wdqs_R_eq": 1e6, + "wdqs_dyn_E": 1e-12, + "rdqs_termination": true, + "rdqs_R_eq": 1e6, + "rdqs_dyn_E": 1e-12 + }, + "bankwisespec": { + "factRho": 1, + "factSigma": 1, + "pasrMode": 0, + "hasPASR": false } } } diff --git a/configs/memspec/JEDEC_8Gb_LPDDR4-3200_16bit.json b/configs/memspec/JEDEC_8Gb_LPDDR4-3200_16bit.json index c38ff822..bcc13605 100644 --- a/configs/memspec/JEDEC_8Gb_LPDDR4-3200_16bit.json +++ b/configs/memspec/JEDEC_8Gb_LPDDR4-3200_16bit.json @@ -9,59 +9,63 @@ "nbrOfRows": 65536, "width": 16, "nbrOfDevices": 1, - "nbrOfChannels": 1 + "nbrOfChannels": 1, + "nbrOfBankGroups": 1, + "maxBurstLength": 16 }, "memoryId": "JEDEC_8Gb_LPDDR4-3200_16bit", "memoryType": "LPDDR4", "mempowerspec": { - "idd0": 3.5, - "idd02": 45.0, - "idd0ql": 0.75, - "idd2n": 2.0, - "idd2n2": 27.0, - "idd2nQ": 0.75, - "idd2ns": 2.0, - "idd2ns2": 23.0, - "idd2nsq": 0.75, - "idd2p": 1.2, - "idd2p2": 3.0, - "idd2pQ": 0.75, - "idd2ps": 1.2, - "idd2ps2": 3.0, - "idd2psq": 0.75, - "idd3n": 2.25, - "idd3n2": 30.0, - "idd3nQ": 0.75, - "idd3ns": 2.25, - "idd3ns2": 30.0, - "idd3nsq": 0.75, - "idd3p": 1.2, - "idd3p2": 9.0, - "idd3pQ": 0.75, - "idd3ps": 1.2, - "idd3ps2": 9.0, - "idd3psq": 0.75, - "idd4r": 2.25, - "idd4r2": 275.0, - "idd4rq": 150.0, - "idd4w": 2.25, - "idd4w2": 210.0, - "idd4wq": 55.0, - "idd5": 10.0, - "idd52": 90.0, - "idd5ab": 2.5, - "idd5ab2": 30.0, - "idd5abq": 0.75, - "idd5b": 2.5, - "idd5b2": 30.0, - "idd5bq": 0.75, - "idd5q": 0.75, - "idd6": 0.3, - "idd62": 0.5, - "idd6q": 0.1, - "vdd": 1.8, + "idd01": 3.5e-3, + "idd02": 45.0e-3, + "idd0ql": 0.75e-3, + "idd2n1": 2.0e-3, + "idd2n2": 27.0e-3, + "idd2nQ": 0.75e-3, + "idd2ns1": 2.0e-3, + "idd2ns2": 23.0e-3, + "idd2nsq": 0.75e-3, + "idd2p1": 1.2e-3, + "idd2p2": 3.0e-3, + "idd2pQ": 0.75e-3, + "idd2ps1": 1.2e-3, + "idd2ps2": 3.0e-3, + "idd2psq": 0.75e-3, + "idd3n1": 2.25e-3, + "idd3n2": 30.0e-3, + "idd3nQ": 0.75e-3, + "idd3ns1": 2.25e-3, + "idd3ns2": 30.0e-3, + "idd3nsq": 0.75e-3, + "idd3p1": 1.2e-3, + "idd3p2": 9.0e-3, + "idd3pQ": 0.75e-3, + "idd3ps1": 1.2e-3, + "idd3ps2": 9.0e-3, + "idd3psq": 0.75e-3, + "idd4r1": 2.25e-3, + "idd4r2": 275.0e-3, + "idd4rq": 150.0e-3, + "idd4w1": 2.25e-3, + "idd4w2": 210.0e-3, + "idd4wq": 55.0e-3, + "idd51": 10.0e-3, + "idd52": 90.0e-3, + "idd5ab1": 2.5e-3, + "idd5ab2": 30.0e-3, + "idd5abq": 0.75e-3, + "idd5pb1": 2.5e-3, + "idd5pb2": 30.0e-3, + "idd5pbq": 0.75e-3, + "idd5q": 0.75e-3, + "idd61": 0.3e-3, + "idd62": 0.5e-3, + "idd6q": 0.1e-3, + "vdd1": 1.8, "vdd2": 1.1, - "vddq": 1.1 + "vddq": 1.1, + "iBeta_vdd1": 3.5e-3, + "iBeta_vdd2": 45.0e-3 }, "memtimingspec": { "CCD": 8, @@ -76,15 +80,15 @@ "PPD": 4, "RCD": 29, "REFI": 6246, - "REFIPB": 780, - "RFCAB": 448, - "RFCPB": 224, + "REFIpb": 780, + "RFCab": 448, + "RFCpb": 224, "RL": 28, "RAS": 68, - "RPAB": 34, - "RPPB": 29, - "RCAB": 102, - "RCPB": 97, + "RPab": 34, + "RPpb": 29, + "RCab": 102, + "RCpb": 97, "RPST": 0, "RRD": 16, "RTP": 12, @@ -96,7 +100,36 @@ "XP": 12, "XSR": 460, "RTRS": 1, - "tCK": 625 + "tCK": 625e-12 + }, + "memimpedancespec": { + "ck_termination": true, + "ck_R_eq": 1e6, + "ck_dyn_E": 1e-12, + + "ca_termination": true, + "ca_R_eq": 1e6, + "ca_dyn_E": 1e-12, + + "rdq_termination": true, + "rdq_R_eq": 1e6, + "rdq_dyn_E": 1e-12, + "wdq_termination": true, + "wdq_R_eq": 1e6, + "wdq_dyn_E": 1e-12, + + "wdqs_termination": true, + "wdqs_R_eq": 1e6, + "wdqs_dyn_E": 1e-12, + "rdqs_termination": true, + "rdqs_R_eq": 1e6, + "rdqs_dyn_E": 1e-12 + }, + "bankwisespec": { + "factRho": 1, + "factSigma": 1, + "pasrMode": 0, + "hasPASR": false } } } diff --git a/configs/memspec/MICRON_1Gb_DDR2-1066_16bit_H.json b/configs/memspec/MICRON_1Gb_DDR2-1066_16bit_H.json index 94a6d27d..cf369c4b 100644 --- a/configs/memspec/MICRON_1Gb_DDR2-1066_16bit_H.json +++ b/configs/memspec/MICRON_1Gb_DDR2-1066_16bit_H.json @@ -14,17 +14,17 @@ "memoryId": "MICRON_1Gb_DDR2-1066_16bit_H", "memoryType": "DDR2", "mempowerspec": { - "idd0": 90.0, - "idd2n": 36.0, - "idd2p0": 7.0, - "idd2p1": 7.0, - "idd3n": 42.0, - "idd3p0": 10.0, - "idd3p1": 23.0, - "idd4r": 180.0, - "idd4w": 185.0, - "idd5": 160.0, - "idd6": 7.0, + "idd0": 90.0e-3, + "idd2n": 36.0e-3, + "idd2p0": 7.0e-3, + "idd2p1": 7.0e-3, + "idd3n": 42.0e-3, + "idd3p0": 10.0e-3, + "idd3p1": 23.0e-3, + "idd4r": 180.0e-3, + "idd4w": 185.0e-3, + "idd5": 160.0e-3, + "idd6": 7.0e-3, "vdd": 1.8 }, "memtimingspec": { @@ -51,7 +51,7 @@ "XPDLL": 10, "XS": 74, "XSDLL": 200, - "tCK": 1876 + "tCK": 1876e-12 } } } diff --git a/configs/memspec/MICRON_1Gb_DDR2-800_16bit_H.json b/configs/memspec/MICRON_1Gb_DDR2-800_16bit_H.json index 3cd58398..8863a37d 100644 --- a/configs/memspec/MICRON_1Gb_DDR2-800_16bit_H.json +++ b/configs/memspec/MICRON_1Gb_DDR2-800_16bit_H.json @@ -14,17 +14,17 @@ "memoryId": "MICRON_1Gb_DDR2-800_16bit_H", "memoryType": "DDR2", "mempowerspec": { - "idd0": 80.0, - "idd2n": 30.0, - "idd2p0": 7.0, - "idd2p1": 7.0, - "idd3n": 35.0, - "idd3p0": 10.0, - "idd3p1": 20.0, - "idd4r": 150.0, - "idd4w": 160.0, - "idd5": 150.0, - "idd6": 7.0, + "idd0": 80.0e-3, + "idd2n": 30.0e-3, + "idd2p0": 7.0e-3, + "idd2p1": 7.0e-3, + "idd3n": 35.0e-3, + "idd3p0": 10.0e-3, + "idd3p1": 20.0e-3, + "idd4r": 150.0e-3, + "idd4w": 160.0e-3, + "idd5": 150.0e-3, + "idd6": 7.0e-3, "vdd": 1.8 }, "memtimingspec": { @@ -51,7 +51,7 @@ "XPDLL": 8, "XS": 55, "XSDLL": 200, - "tCK": 2500 + "tCK": 2500e-12 } } } diff --git a/configs/memspec/MICRON_1Gb_DDR3-1066_16bit_G.json b/configs/memspec/MICRON_1Gb_DDR3-1066_16bit_G.json index 8fbaa9de..e9d9abca 100644 --- a/configs/memspec/MICRON_1Gb_DDR3-1066_16bit_G.json +++ b/configs/memspec/MICRON_1Gb_DDR3-1066_16bit_G.json @@ -9,22 +9,23 @@ "nbrOfRows": 8192, "width": 16, "nbrOfDevices": 4, - "nbrOfChannels": 1 + "nbrOfChannels": 1, + "maxBurstLength": 8 }, "memoryId": "MICRON_1Gb_DDR3-1066_16bit_G", "memoryType": "DDR3", "mempowerspec": { - "idd0": 75.0, - "idd2n": 35.0, - "idd2p0": 12.0, - "idd2p1": 25.0, - "idd3n": 45.0, - "idd3p0": 30.0, - "idd3p1": 30.0, - "idd4r": 140.0, - "idd4w": 155.0, - "idd5": 160.0, - "idd6": 8.0, + "idd0": 75.0e-3, + "idd2n": 35.0e-3, + "idd2p0": 12.0e-3, + "idd2p1": 25.0e-3, + "idd3n": 45.0e-3, + "idd3p0": 30.0e-3, + "idd3p1": 30.0e-3, + "idd4r": 140.0e-3, + "idd4w": 155.0e-3, + "idd5": 160.0e-3, + "idd6": 8.0e-3, "vdd": 1.5 }, "memtimingspec": { @@ -55,7 +56,7 @@ "PRPDEN": 1, "REFPDEN": 1, "RTRS": 1, - "tCK": 1876 + "tCK": 1876e-12 } } } diff --git a/configs/memspec/MICRON_1Gb_DDR3-1066_16bit_G_2s.json b/configs/memspec/MICRON_1Gb_DDR3-1066_16bit_G_2s.json index 7d7cff20..dab78d5b 100644 --- a/configs/memspec/MICRON_1Gb_DDR3-1066_16bit_G_2s.json +++ b/configs/memspec/MICRON_1Gb_DDR3-1066_16bit_G_2s.json @@ -9,22 +9,23 @@ "nbrOfRows": 8192, "width": 16, "nbrOfDevices": 4, - "nbrOfChannels": 1 + "nbrOfChannels": 1, + "maxBurstLength": 8 }, "memoryId": "MICRON_1Gb_DDR3-1066_16bit_G_2s", "memoryType": "DDR3", "mempowerspec": { - "idd0": 70.22, - "idd2n": 30.95, - "idd2p0": 9.07, - "idd2p1": 18.9, - "idd3n": 39.0, - "idd3p0": 26.0, - "idd3p1": 26.0, - "idd4r": 128.59, - "idd4w": 144.31, - "idd5": 150.64, - "idd6": 6.02, + "idd0": 70.22e-3, + "idd2n": 30.95e-3, + "idd2p0": 9.07e-3, + "idd2p1": 18.9e-3, + "idd3n": 39.0e-3, + "idd3p0": 26.0e-3, + "idd3p1": 26.0e-3, + "idd4r": 128.59e-3, + "idd4w": 144.31e-3, + "idd5": 150.64e-3, + "idd6": 6.02e-3, "vdd": 1.5 }, "memtimingspec": { @@ -55,7 +56,7 @@ "PRPDEN": 1, "REFPDEN": 1, "RTRS": 1, - "tCK": 1876 + "tCK": 1876e-12 } } } diff --git a/configs/memspec/MICRON_1Gb_DDR3-1066_16bit_G_3s.json b/configs/memspec/MICRON_1Gb_DDR3-1066_16bit_G_3s.json index 5e8a549c..c44258cb 100644 --- a/configs/memspec/MICRON_1Gb_DDR3-1066_16bit_G_3s.json +++ b/configs/memspec/MICRON_1Gb_DDR3-1066_16bit_G_3s.json @@ -9,22 +9,23 @@ "nbrOfRows": 8192, "width": 16, "nbrOfDevices": 4, - "nbrOfChannels": 1 + "nbrOfChannels": 1, + "maxBurstLength": 8 }, "memoryId": "MICRON_1Gb_DDR3-1066_16bit_G_3s", "memoryType": "DDR3", "mempowerspec": { - "idd0": 71.81, - "idd2n": 32.3, - "idd2p0": 10.04, - "idd2p1": 20.93, - "idd3n": 41.0, - "idd3p0": 27.33, - "idd3p1": 27.33, - "idd4r": 132.39, - "idd4w": 147.87, - "idd5": 153.76, - "idd6": 6.68, + "idd0": 71.81e-3, + "idd2n": 32.3e-3, + "idd2p0": 10.04e-3, + "idd2p1": 20.93e-3, + "idd3n": 41.0e-3, + "idd3p0": 27.33e-3, + "idd3p1": 27.33e-3, + "idd4r": 132.39e-3, + "idd4w": 147.87e-3, + "idd5": 153.76e-3, + "idd6": 6.68e-3, "vdd": 1.5 }, "memtimingspec": { @@ -55,7 +56,7 @@ "PRPDEN": 1, "REFPDEN": 1, "RTRS": 1, - "tCK": 1876 + "tCK": 1876e-12 } } } diff --git a/configs/memspec/MICRON_1Gb_DDR3-1066_16bit_G_mu.json b/configs/memspec/MICRON_1Gb_DDR3-1066_16bit_G_mu.json index bfce141e..639504a4 100644 --- a/configs/memspec/MICRON_1Gb_DDR3-1066_16bit_G_mu.json +++ b/configs/memspec/MICRON_1Gb_DDR3-1066_16bit_G_mu.json @@ -9,22 +9,23 @@ "nbrOfRows": 8192, "width": 16, "nbrOfDevices": 4, - "nbrOfChannels": 1 + "nbrOfChannels": 1, + "maxBurstLength": 8 }, "memoryId": "MICRON_1Gb_DDR3-1066_16bit_G_mu", "memoryType": "DDR3", "mempowerspec": { - "idd0": 67.04, - "idd2n": 28.25, - "idd2p0": 7.12, - "idd2p1": 14.83, - "idd3n": 35.01, - "idd3p0": 23.34, - "idd3p1": 23.34, - "idd4r": 120.98, - "idd4w": 137.19, - "idd5": 144.41, - "idd6": 4.7, + "idd0": 67.04e-3, + "idd2n": 28.25e-3, + "idd2p0": 7.12e-3, + "idd2p1": 14.83e-3, + "idd3n": 35.01e-3, + "idd3p0": 23.34e-3, + "idd3p1": 23.34e-3, + "idd4r": 120.98e-3, + "idd4w": 137.19e-3, + "idd5": 144.41e-3, + "idd6": 4.7e-3, "vdd": 1.5 }, "memtimingspec": { @@ -55,7 +56,7 @@ "PRPDEN": 1, "REFPDEN": 1, "RTRS": 1, - "tCK": 1876 + "tCK": 1876e-12 } } } diff --git a/configs/memspec/MICRON_1Gb_DDR3-1066_8bit_G.json b/configs/memspec/MICRON_1Gb_DDR3-1066_8bit_G.json index ace6fc93..9f2a7102 100644 --- a/configs/memspec/MICRON_1Gb_DDR3-1066_8bit_G.json +++ b/configs/memspec/MICRON_1Gb_DDR3-1066_8bit_G.json @@ -9,22 +9,23 @@ "nbrOfRows": 16384, "width": 8, "nbrOfDevices": 8, - "nbrOfChannels": 1 + "nbrOfChannels": 1, + "maxBurstLength": 8 }, "memoryId": "MICRON_1Gb_DDR3-1066_8bit_G", "memoryType": "DDR3", "mempowerspec": { - "idd0": 60.0, - "idd2n": 35.0, - "idd2p0": 12.0, - "idd2p1": 25.0, - "idd3n": 40.0, - "idd3p0": 30.0, - "idd3p1": 30.0, - "idd4r": 105.0, - "idd4w": 110.0, - "idd5": 160.0, - "idd6": 8.0, + "idd0": 60.0e-3, + "idd2n": 35.0e-3, + "idd2p0": 12.0e-3, + "idd2p1": 25.0e-3, + "idd3n": 40.0e-3, + "idd3p0": 30.0e-3, + "idd3p1": 30.0e-3, + "idd4r": 105.0e-3, + "idd4w": 110.0e-3, + "idd5": 160.0e-3, + "idd6": 8.0e-3, "vdd": 1.5 }, "memtimingspec": { @@ -55,7 +56,7 @@ "PRPDEN": 1, "REFPDEN": 1, "RTRS": 1, - "tCK": 1876 + "tCK": 1876e-12 } } } diff --git a/configs/memspec/MICRON_1Gb_DDR3-1066_8bit_G_2s.json b/configs/memspec/MICRON_1Gb_DDR3-1066_8bit_G_2s.json index 333aaf51..616686df 100644 --- a/configs/memspec/MICRON_1Gb_DDR3-1066_8bit_G_2s.json +++ b/configs/memspec/MICRON_1Gb_DDR3-1066_8bit_G_2s.json @@ -9,22 +9,23 @@ "nbrOfRows": 16384, "width": 8, "nbrOfDevices": 8, - "nbrOfChannels": 1 + "nbrOfChannels": 1, + "maxBurstLength": 8 }, "memoryId": "MICRON_1Gb_DDR3-1066_8bit_G_2s", "memoryType": "DDR3", "mempowerspec": { - "idd0": 56.18, - "idd2n": 30.95, - "idd2p0": 9.07, - "idd2p1": 18.9, - "idd3n": 34.67, - "idd3p0": 26.0, - "idd3p1": 26.0, - "idd4r": 96.88, - "idd4w": 102.0, - "idd5": 150.64, - "idd6": 6.02, + "idd0": 56.18e-3, + "idd2n": 30.95e-3, + "idd2p0": 9.07e-3, + "idd2p1": 18.9e-3, + "idd3n": 34.67e-3, + "idd3p0": 26.0e-3, + "idd3p1": 26.0e-3, + "idd4r": 96.88e-3, + "idd4w": 102.0e-3, + "idd5": 150.64e-3, + "idd6": 6.02e-3, "vdd": 1.5 }, "memtimingspec": { @@ -55,7 +56,7 @@ "PRPDEN": 1, "REFPDEN": 1, "RTRS": 1, - "tCK": 1876 + "tCK": 1876e-12 } } } diff --git a/configs/memspec/MICRON_1Gb_DDR3-1066_8bit_G_3s.json b/configs/memspec/MICRON_1Gb_DDR3-1066_8bit_G_3s.json index 368891e7..c94985b4 100644 --- a/configs/memspec/MICRON_1Gb_DDR3-1066_8bit_G_3s.json +++ b/configs/memspec/MICRON_1Gb_DDR3-1066_8bit_G_3s.json @@ -9,22 +9,23 @@ "nbrOfRows": 16384, "width": 8, "nbrOfDevices": 8, - "nbrOfChannels": 1 + "nbrOfChannels": 1, + "maxBurstLength": 8 }, "memoryId": "MICRON_1Gb_DDR3-1066_8bit_G_3s", "memoryType": "DDR3", "mempowerspec": { - "idd0": 57.45, - "idd2n": 32.3, - "idd2p0": 10.04, - "idd2p1": 20.93, - "idd3n": 36.45, - "idd3p0": 27.33, - "idd3p1": 27.33, - "idd4r": 99.59, - "idd4w": 104.67, - "idd5": 153.76, - "idd6": 6.68, + "idd0": 57.45e-3, + "idd2n": 32.3e-3, + "idd2p0": 10.04e-3, + "idd2p1": 20.93e-3, + "idd3n": 36.45e-3, + "idd3p0": 27.33e-3, + "idd3p1": 27.33e-3, + "idd4r": 99.59e-3, + "idd4w": 104.67e-3, + "idd5": 153.76e-3, + "idd6": 6.68e-3, "vdd": 1.5 }, "memtimingspec": { @@ -55,7 +56,7 @@ "PRPDEN": 1, "REFPDEN": 1, "RTRS": 1, - "tCK": 1876 + "tCK": 1876e-12 } } } diff --git a/configs/memspec/MICRON_1Gb_DDR3-1066_8bit_G_mu.json b/configs/memspec/MICRON_1Gb_DDR3-1066_8bit_G_mu.json index 3f4aaa46..75ec4d08 100644 --- a/configs/memspec/MICRON_1Gb_DDR3-1066_8bit_G_mu.json +++ b/configs/memspec/MICRON_1Gb_DDR3-1066_8bit_G_mu.json @@ -9,22 +9,23 @@ "nbrOfRows": 16384, "width": 8, "nbrOfDevices": 8, - "nbrOfChannels": 1 + "nbrOfChannels": 1, + "maxBurstLength": 8 }, "memoryId": "MICRON_1Gb_DDR3-1066_8bit_G_mu", "memoryType": "DDR3", "mempowerspec": { - "idd0": 53.63, - "idd2n": 28.25, - "idd2p0": 7.12, - "idd2p1": 14.83, - "idd3n": 31.12, - "idd3p0": 23.34, - "idd3p1": 23.34, - "idd4r": 91.47, - "idd4w": 96.68, - "idd5": 144.41, - "idd6": 4.7, + "idd0": 53.63e-3, + "idd2n": 28.25e-3, + "idd2p0": 7.12e-3, + "idd2p1": 14.83e-3, + "idd3n": 31.12e-3, + "idd3p0": 23.34e-3, + "idd3p1": 23.34e-3, + "idd4r": 91.47e-3, + "idd4w": 96.68e-3, + "idd5": 144.41e-3, + "idd6": 4.7e-3, "vdd": 1.5 }, "memtimingspec": { @@ -55,7 +56,7 @@ "PRPDEN": 1, "REFPDEN": 1, "RTRS": 1, - "tCK": 1876 + "tCK": 1876e-12 } } } diff --git a/configs/memspec/MICRON_1Gb_DDR3-1600_8bit_G.json b/configs/memspec/MICRON_1Gb_DDR3-1600_8bit_G.json index d66da75f..cfe47aeb 100644 --- a/configs/memspec/MICRON_1Gb_DDR3-1600_8bit_G.json +++ b/configs/memspec/MICRON_1Gb_DDR3-1600_8bit_G.json @@ -9,22 +9,23 @@ "nbrOfRows": 16384, "width": 8, "nbrOfDevices": 8, - "nbrOfChannels": 1 + "nbrOfChannels": 1, + "maxBurstLength": 8 }, "memoryId": "MICRON_1Gb_DDR3-1600_8bit_G", "memoryType": "DDR3", "mempowerspec": { - "idd0": 70.0, - "idd2n": 45.0, - "idd2p0": 12.0, - "idd2p1": 30.0, - "idd3n": 45.0, - "idd3p0": 35.0, - "idd3p1": 35.0, - "idd4r": 140.0, - "idd4w": 145.0, - "idd5": 170.0, - "idd6": 8.0, + "idd0": 70.0e-3, + "idd2n": 45.0e-3, + "idd2p0": 12.0e-3, + "idd2p1": 30.0e-3, + "idd3n": 45.0e-3, + "idd3p0": 35.0e-3, + "idd3p1": 35.0e-3, + "idd4r": 140.0e-3, + "idd4w": 145.0e-3, + "idd5": 170.0e-3, + "idd6": 8.0e-3, "vdd": 1.5 }, "memtimingspec": { @@ -55,7 +56,7 @@ "PRPDEN": 1, "REFPDEN": 1, "RTRS": 1, - "tCK": 1250 + "tCK": 1250e-12 } } } diff --git a/configs/memspec/MICRON_1Gb_DDR3-1600_8bit_G_2s.json b/configs/memspec/MICRON_1Gb_DDR3-1600_8bit_G_2s.json index c3270bfa..6047cffe 100644 --- a/configs/memspec/MICRON_1Gb_DDR3-1600_8bit_G_2s.json +++ b/configs/memspec/MICRON_1Gb_DDR3-1600_8bit_G_2s.json @@ -9,22 +9,23 @@ "nbrOfRows": 16384, "width": 8, "nbrOfDevices": 8, - "nbrOfChannels": 1 + "nbrOfChannels": 1, + "maxBurstLength": 8 }, "memoryId": "MICRON_1Gb_DDR3-1600_8bit_G_2s", "memoryType": "DDR3", "mempowerspec": { - "idd0": 65.19, - "idd2n": 40.0, - "idd2p0": 9.07, - "idd2p1": 22.68, - "idd3n": 40.07, - "idd3p0": 31.16, - "idd3p1": 31.16, - "idd4r": 127.49, - "idd4w": 130.17, - "idd5": 159.28, - "idd6": 6.02, + "idd0": 65.19e-3, + "idd2n": 40.0e-3, + "idd2p0": 9.07e-3, + "idd2p1": 22.68e-3, + "idd3n": 40.07e-3, + "idd3p0": 31.16e-3, + "idd3p1": 31.16e-3, + "idd4r": 127.49e-3, + "idd4w": 130.17e-3, + "idd5": 159.28e-3, + "idd6": 6.02e-3, "vdd": 1.5 }, "memtimingspec": { @@ -55,7 +56,7 @@ "PRPDEN": 1, "REFPDEN": 1, "RTRS": 1, - "tCK": 1250 + "tCK": 1250e-12 } } } diff --git a/configs/memspec/MICRON_1Gb_DDR3-1600_8bit_G_3s.json b/configs/memspec/MICRON_1Gb_DDR3-1600_8bit_G_3s.json index 09bf44ba..e04e739c 100644 --- a/configs/memspec/MICRON_1Gb_DDR3-1600_8bit_G_3s.json +++ b/configs/memspec/MICRON_1Gb_DDR3-1600_8bit_G_3s.json @@ -9,22 +9,23 @@ "nbrOfRows": 16384, "width": 8, "nbrOfDevices": 8, - "nbrOfChannels": 1 + "nbrOfChannels": 1, + "maxBurstLength": 8 }, "memoryId": "MICRON_1Gb_DDR3-1600_8bit_G_3s", "memoryType": "DDR3", "mempowerspec": { - "idd0": 66.79, - "idd2n": 41.67, - "idd2p0": 10.04, - "idd2p1": 25.12, - "idd3n": 41.71, - "idd3p0": 32.44, - "idd3p1": 32.44, - "idd4r": 131.66, - "idd4w": 135.11, - "idd5": 162.85, - "idd6": 6.68, + "idd0": 66.79e-3, + "idd2n": 41.67e-3, + "idd2p0": 10.04e-3, + "idd2p1": 25.12e-3, + "idd3n": 41.71e-3, + "idd3p0": 32.44e-3, + "idd3p1": 32.44e-3, + "idd4r": 131.66e-3, + "idd4w": 135.11e-3, + "idd5": 162.85e-3, + "idd6": 6.68e-3, "vdd": 1.5 }, "memtimingspec": { @@ -55,7 +56,7 @@ "PRPDEN": 1, "REFPDEN": 1, "RTRS": 1, - "tCK": 1250 + "tCK": 1250e-12 } } } diff --git a/configs/memspec/MICRON_1Gb_DDR3-1600_8bit_G_less_refresh.json b/configs/memspec/MICRON_1Gb_DDR3-1600_8bit_G_less_refresh.json index 711b3bc7..f4eaef28 100644 --- a/configs/memspec/MICRON_1Gb_DDR3-1600_8bit_G_less_refresh.json +++ b/configs/memspec/MICRON_1Gb_DDR3-1600_8bit_G_less_refresh.json @@ -9,22 +9,23 @@ "nbrOfRows": 16384, "width": 8, "nbrOfDevices": 8, - "nbrOfChannels": 1 + "nbrOfChannels": 1, + "maxBurstLength": 8 }, "memoryId": "MICRON_1Gb_DDR3-1600_8bit_G", "memoryType": "DDR3", "mempowerspec": { - "idd0": 70.0, - "idd2n": 45.0, - "idd2p0": 12.0, - "idd2p1": 30.0, - "idd3n": 45.0, - "idd3p0": 35.0, - "idd3p1": 35.0, - "idd4r": 140.0, - "idd4w": 145.0, - "idd5": 170.0, - "idd6": 8.0, + "idd0": 70.0e-3, + "idd2n": 45.0e-3, + "idd2p0": 12.0e-3, + "idd2p1": 30.0e-3, + "idd3n": 45.0e-3, + "idd3p0": 35.0e-3, + "idd3p1": 35.0e-3, + "idd4r": 140.0e-3, + "idd4w": 145.0e-3, + "idd5": 170.0e-3, + "idd6": 8.0e-3, "vdd": 1.5 }, "memtimingspec": { @@ -55,7 +56,7 @@ "PRPDEN": 1, "REFPDEN": 1, "RTRS": 1, - "tCK": 1250 + "tCK": 1250e-12 } } } diff --git a/configs/memspec/MICRON_1Gb_DDR3-1600_8bit_G_mu.json b/configs/memspec/MICRON_1Gb_DDR3-1600_8bit_G_mu.json index 62406b49..f8aa221f 100644 --- a/configs/memspec/MICRON_1Gb_DDR3-1600_8bit_G_mu.json +++ b/configs/memspec/MICRON_1Gb_DDR3-1600_8bit_G_mu.json @@ -9,22 +9,23 @@ "nbrOfRows": 16384, "width": 8, "nbrOfDevices": 8, - "nbrOfChannels": 1 + "nbrOfChannels": 1, + "maxBurstLength": 8 }, "memoryId": "MICRON_1Gb_DDR3-1600_8bit_G_mu", "memoryType": "DDR3", "mempowerspec": { - "idd0": 61.99, - "idd2n": 36.68, - "idd2p0": 7.12, - "idd2p1": 17.8, - "idd3n": 36.78, - "idd3p0": 28.61, - "idd3p1": 28.61, - "idd4r": 119.16, - "idd4w": 120.28, - "idd5": 152.13, - "idd6": 4.7, + "idd0": 61.99e-3, + "idd2n": 36.68e-3, + "idd2p0": 7.12e-3, + "idd2p1": 17.8e-3, + "idd3n": 36.78e-3, + "idd3p0": 28.61e-3, + "idd3p1": 28.61e-3, + "idd4r": 119.16e-3, + "idd4w": 120.28e-3, + "idd5": 152.13e-3, + "idd6": 4.7e-3, "vdd": 1.5 }, "memtimingspec": { @@ -55,7 +56,7 @@ "PRPDEN": 1, "REFPDEN": 1, "RTRS": 1, - "tCK": 1250 + "tCK": 1250e-12 } } } diff --git a/configs/memspec/MICRON_1Gb_DDR3-800_8bit_G.json b/configs/memspec/MICRON_1Gb_DDR3-800_8bit_G.json index 9f1f1c08..9c0f2f6c 100644 --- a/configs/memspec/MICRON_1Gb_DDR3-800_8bit_G.json +++ b/configs/memspec/MICRON_1Gb_DDR3-800_8bit_G.json @@ -9,22 +9,23 @@ "nbrOfRows": 16384, "width": 8, "nbrOfDevices": 8, - "nbrOfChannels": 1 + "nbrOfChannels": 1, + "maxBurstLength": 8 }, "memoryId": "MICRON_1Gb_DDR3-800_8bit_G", "memoryType": "DDR3", "mempowerspec": { - "idd0": 60.0, - "idd2n": 35.0, - "idd2p0": 12.0, - "idd2p1": 25.0, - "idd3n": 40.0, - "idd3p0": 30.0, - "idd3p1": 30.0, - "idd4r": 105.0, - "idd4w": 110.0, - "idd5": 160.0, - "idd6": 8.0, + "idd0": 60.0e-3, + "idd2n": 35.0e-3, + "idd2p0": 12.0e-3, + "idd2p1": 25.0e-3, + "idd3n": 40.0e-3, + "idd3p0": 30.0e-3, + "idd3p1": 30.0e-3, + "idd4r": 105.0e-3, + "idd4w": 110.0e-3, + "idd5": 160.0e-3, + "idd6": 8.0e-3, "vdd": 1.5 }, "memtimingspec": { @@ -55,7 +56,7 @@ "PRPDEN": 1, "REFPDEN": 1, "RTRS": 1, - "tCK": 2500 + "tCK": 2500e-12 } } } diff --git a/configs/memspec/MICRON_2GB_DDR3-1066_64bit_D_SODIMM.json b/configs/memspec/MICRON_2GB_DDR3-1066_64bit_D_SODIMM.json index 869ffbd6..8c9edadd 100644 --- a/configs/memspec/MICRON_2GB_DDR3-1066_64bit_D_SODIMM.json +++ b/configs/memspec/MICRON_2GB_DDR3-1066_64bit_D_SODIMM.json @@ -9,22 +9,23 @@ "nbrOfRows": 16384, "width": 64, "nbrOfDevices": 1, - "nbrOfChannels": 1 + "nbrOfChannels": 1, + "maxBurstLength": 8 }, "memoryId": "MICRON_2GB_DDR3-1066_64bit_D_SODIMM", "memoryType": "DDR3", "mempowerspec": { - "idd0": 720.0, - "idd2n": 400.0, - "idd2p0": 80.0, - "idd2p1": 200.0, - "idd3n": 440.0, - "idd3p0": 240.0, - "idd3p1": 240.0, - "idd4r": 1200.0, - "idd4w": 1200.0, - "idd5": 1760.0, - "idd6": 48.0, + "idd0": 720.0e-3, + "idd2n": 400.0e-3, + "idd2p0": 80.0e-3, + "idd2p1": 200.0e-3, + "idd3n": 440.0e-3, + "idd3p0": 240.0e-3, + "idd3p1": 240.0e-3, + "idd4r": 1200.0e-3, + "idd4w": 1200.0e-3, + "idd5": 1760.0e-3, + "idd6": 48.0e-3, "vdd": 1.5 }, "memtimingspec": { @@ -55,7 +56,7 @@ "PRPDEN": 1, "REFPDEN": 1, "RTRS": 1, - "tCK": 1876 + "tCK": 1876e-12 } } } diff --git a/configs/memspec/MICRON_2GB_DDR3-1066_64bit_G_UDIMM.json b/configs/memspec/MICRON_2GB_DDR3-1066_64bit_G_UDIMM.json index ce25df12..01decf86 100644 --- a/configs/memspec/MICRON_2GB_DDR3-1066_64bit_G_UDIMM.json +++ b/configs/memspec/MICRON_2GB_DDR3-1066_64bit_G_UDIMM.json @@ -9,22 +9,23 @@ "nbrOfRows": 16384, "width": 64, "nbrOfDevices": 1, - "nbrOfChannels": 1 + "nbrOfChannels": 1, + "maxBurstLength": 8 }, "memoryId": "MICRON_2GB_DDR3-1066_64bit_G_UDIMM", "memoryType": "DDR3", "mempowerspec": { - "idd0": 432.0, - "idd2n": 315.0, - "idd2p0": 108.0, - "idd2p1": 225.0, - "idd3n": 360.0, - "idd3p0": 270.0, - "idd3p1": 270.0, - "idd4r": 882.0, - "idd4w": 837.0, - "idd5": 1332.0, - "idd6": 90.0, + "idd0": 432.0e-3, + "idd2n": 315.0e-3, + "idd2p0": 108.0e-3, + "idd2p1": 225.0e-3, + "idd3n": 360.0e-3, + "idd3p0": 270.0e-3, + "idd3p1": 270.0e-3, + "idd4r": 882.0e-3, + "idd4w": 837.0e-3, + "idd5": 1332.0e-3, + "idd6": 90.0e-3, "vdd": 1.5 }, "memtimingspec": { @@ -55,7 +56,7 @@ "PRPDEN": 1, "REFPDEN": 1, "RTRS": 1, - "tCK": 1876 + "tCK": 1876e-12 } } } diff --git a/configs/memspec/MICRON_2GB_DDR3-1333_64bit_D_SODIMM.json b/configs/memspec/MICRON_2GB_DDR3-1333_64bit_D_SODIMM.json index 3aa3e591..17a78097 100644 --- a/configs/memspec/MICRON_2GB_DDR3-1333_64bit_D_SODIMM.json +++ b/configs/memspec/MICRON_2GB_DDR3-1333_64bit_D_SODIMM.json @@ -9,22 +9,23 @@ "nbrOfRows": 16384, "width": 64, "nbrOfDevices": 1, - "nbrOfChannels": 1 + "nbrOfChannels": 1, + "maxBurstLength": 8 }, "memoryId": "MICRON_2GB_DDR3-1333_64bit_D_SODIMM", "memoryType": "DDR3", "mempowerspec": { - "idd0": 800.0, - "idd2n": 440.0, - "idd2p0": 80.0, - "idd2p1": 200.0, - "idd3n": 480.0, - "idd3p0": 280.0, - "idd3p1": 280.0, - "idd4r": 1440.0, - "idd4w": 1520.0, - "idd5": 1920.0, - "idd6": 48.0, + "idd0": 800.0e-3, + "idd2n": 440.0e-3, + "idd2p0": 80.0e-3, + "idd2p1": 200.0e-3, + "idd3n": 480.0e-3, + "idd3p0": 280.0e-3, + "idd3p1": 280.0e-3, + "idd4r": 1440.0e-3, + "idd4w": 1520.0e-3, + "idd5": 1920.0e-3, + "idd6": 48.0e-3, "vdd": 1.5 }, "memtimingspec": { @@ -55,7 +56,7 @@ "PRPDEN": 1, "REFPDEN": 1, "RTRS": 1, - "tCK": 1502 + "tCK": 1502e-12 } } } diff --git a/configs/memspec/MICRON_2GB_DDR3-1600_64bit_G_UDIMM.json b/configs/memspec/MICRON_2GB_DDR3-1600_64bit_G_UDIMM.json index d86753ff..4fe93627 100644 --- a/configs/memspec/MICRON_2GB_DDR3-1600_64bit_G_UDIMM.json +++ b/configs/memspec/MICRON_2GB_DDR3-1600_64bit_G_UDIMM.json @@ -9,22 +9,23 @@ "nbrOfRows": 16384, "width": 64, "nbrOfDevices": 1, - "nbrOfChannels": 1 + "nbrOfChannels": 1, + "maxBurstLength": 8 }, "memoryId": "MICRON_2GB_DDR3-1600_64bit_G_UDIMM", "memoryType": "DDR3", "mempowerspec": { - "idd0": 522.0, - "idd2n": 405.0, - "idd2p0": 108.0, - "idd2p1": 270.0, - "idd3n": 405.0, - "idd3p0": 315.0, - "idd3p1": 315.0, - "idd4r": 1197.0, - "idd4w": 1152.0, - "idd5": 1422.0, - "idd6": 90.0, + "idd0": 522.0e-3, + "idd2n": 405.0e-3, + "idd2p0": 108.0e-3, + "idd2p1": 270.0e-3, + "idd3n": 405.0e-3, + "idd3p0": 315.0e-3, + "idd3p1": 315.0e-3, + "idd4r": 1197.0e-3, + "idd4w": 1152.0e-3, + "idd5": 1422.0e-3, + "idd6": 90.0e-3, "vdd": 1.5 }, "memtimingspec": { @@ -55,7 +56,7 @@ "PRPDEN": 1, "REFPDEN": 1, "RTRS": 1, - "tCK": 1250 + "tCK": 1250e-12 } } } diff --git a/configs/memspec/MICRON_2Gb_DDR3-1066_8bit_D.json b/configs/memspec/MICRON_2Gb_DDR3-1066_8bit_D.json index 920dc9ec..c369ceee 100644 --- a/configs/memspec/MICRON_2Gb_DDR3-1066_8bit_D.json +++ b/configs/memspec/MICRON_2Gb_DDR3-1066_8bit_D.json @@ -9,22 +9,23 @@ "nbrOfRows": 32768, "width": 8, "nbrOfDevices": 8, - "nbrOfChannels": 1 + "nbrOfChannels": 1, + "maxBurstLength": 8 }, "memoryId": "MICRON_2Gb_DDR3-1066_8bit_D", "memoryType": "DDR3", "mempowerspec": { - "idd0": 75.0, - "idd2n": 32.0, - "idd2p0": 12.0, - "idd2p1": 25.0, - "idd3n": 35.0, - "idd3p0": 30.0, - "idd3p1": 30.0, - "idd4r": 140.0, - "idd4w": 145.0, - "idd5": 190.0, - "idd6": 12.0, + "idd0": 75.0e-3, + "idd2n": 32.0e-3, + "idd2p0": 12.0e-3, + "idd2p1": 25.0e-3, + "idd3n": 35.0e-3, + "idd3p0": 30.0e-3, + "idd3p1": 30.0e-3, + "idd4r": 140.0e-3, + "idd4w": 145.0e-3, + "idd5": 190.0e-3, + "idd6": 12.0e-3, "vdd": 1.5 }, "memtimingspec": { @@ -55,7 +56,7 @@ "PRPDEN": 1, "REFPDEN": 1, "RTRS": 1, - "tCK": 1876 + "tCK": 1876e-12 } } } diff --git a/configs/memspec/MICRON_2Gb_DDR3-1066_8bit_D_2s.json b/configs/memspec/MICRON_2Gb_DDR3-1066_8bit_D_2s.json index 45c52ced..d6da9ff0 100644 --- a/configs/memspec/MICRON_2Gb_DDR3-1066_8bit_D_2s.json +++ b/configs/memspec/MICRON_2Gb_DDR3-1066_8bit_D_2s.json @@ -9,22 +9,23 @@ "nbrOfRows": 32768, "width": 8, "nbrOfDevices": 8, - "nbrOfChannels": 1 + "nbrOfChannels": 1, + "maxBurstLength": 8 }, "memoryId": "MICRON_2Gb_DDR3-1066_8bit_D_2s", "memoryType": "DDR3", "mempowerspec": { - "idd0": 70.08, - "idd2n": 27.52, - "idd2p0": 8.78, - "idd2p1": 18.29, - "idd3n": 30.6, - "idd3p0": 26.23, - "idd3p1": 26.23, - "idd4r": 128.07, - "idd4w": 131.42, - "idd5": 178.56, - "idd6": 8.41, + "idd0": 70.08e-3, + "idd2n": 27.52e-3, + "idd2p0": 8.78e-3, + "idd2p1": 18.29e-3, + "idd3n": 30.6e-3, + "idd3p0": 26.23e-3, + "idd3p1": 26.23e-3, + "idd4r": 128.07e-3, + "idd4w": 131.42e-3, + "idd5": 178.56e-3, + "idd6": 8.41e-3, "vdd": 1.5 }, "memtimingspec": { @@ -55,7 +56,7 @@ "PRPDEN": 1, "REFPDEN": 1, "RTRS": 1, - "tCK": 1876 + "tCK": 1876e-12 } } } diff --git a/configs/memspec/MICRON_2Gb_DDR3-1066_8bit_D_3s.json b/configs/memspec/MICRON_2Gb_DDR3-1066_8bit_D_3s.json index fa9b9a8a..26447c76 100644 --- a/configs/memspec/MICRON_2Gb_DDR3-1066_8bit_D_3s.json +++ b/configs/memspec/MICRON_2Gb_DDR3-1066_8bit_D_3s.json @@ -9,22 +9,23 @@ "nbrOfRows": 32768, "width": 8, "nbrOfDevices": 8, - "nbrOfChannels": 1 + "nbrOfChannels": 1, + "maxBurstLength": 8 }, "memoryId": "MICRON_2Gb_DDR3-1066_8bit_D_3s", "memoryType": "DDR3", "mempowerspec": { - "idd0": 71.72, - "idd2n": 29.02, - "idd2p0": 9.85, - "idd2p1": 20.53, - "idd3n": 32.06, - "idd3p0": 27.48, - "idd3p1": 27.48, - "idd4r": 132.05, - "idd4w": 135.95, - "idd5": 182.37, - "idd6": 9.6, + "idd0": 71.72e-3, + "idd2n": 29.02e-3, + "idd2p0": 9.85e-3, + "idd2p1": 20.53e-3, + "idd3n": 32.06e-3, + "idd3p0": 27.48e-3, + "idd3p1": 27.48e-3, + "idd4r": 132.05e-3, + "idd4w": 135.95e-3, + "idd5": 182.37e-3, + "idd6": 9.6e-3, "vdd": 1.5 }, "memtimingspec": { @@ -55,7 +56,7 @@ "PRPDEN": 1, "REFPDEN": 1, "RTRS": 1, - "tCK": 1876 + "tCK": 1876e-12 } } } diff --git a/configs/memspec/MICRON_2Gb_DDR3-1066_8bit_D_mu.json b/configs/memspec/MICRON_2Gb_DDR3-1066_8bit_D_mu.json index 679c1a4b..89094f72 100644 --- a/configs/memspec/MICRON_2Gb_DDR3-1066_8bit_D_mu.json +++ b/configs/memspec/MICRON_2Gb_DDR3-1066_8bit_D_mu.json @@ -9,22 +9,23 @@ "nbrOfRows": 32768, "width": 8, "nbrOfDevices": 8, - "nbrOfChannels": 1 + "nbrOfChannels": 1, + "maxBurstLength": 8 }, "memoryId": "MICRON_2Gb_DDR3-1066_8bit_D_mu", "memoryType": "DDR3", "mempowerspec": { - "idd0": 66.8, - "idd2n": 24.54, - "idd2p0": 6.63, - "idd2p1": 13.82, - "idd3n": 27.67, - "idd3p0": 23.71, - "idd3p1": 23.71, - "idd4r": 120.13, - "idd4w": 122.38, - "idd5": 170.93, - "idd6": 6.01, + "idd0": 66.8e-3, + "idd2n": 24.54e-3, + "idd2p0": 6.63e-3, + "idd2p1": 13.82e-3, + "idd3n": 27.67e-3, + "idd3p0": 23.71e-3, + "idd3p1": 23.71e-3, + "idd4r": 120.13e-3, + "idd4w": 122.38e-3, + "idd5": 170.93e-3, + "idd6": 6.01e-3, "vdd": 1.5 }, "memtimingspec": { @@ -55,7 +56,7 @@ "PRPDEN": 1, "REFPDEN": 1, "RTRS": 1, - "tCK": 1876 + "tCK": 1876e-12 } } } diff --git a/configs/memspec/MICRON_2Gb_DDR3-1600_16bit_D.json b/configs/memspec/MICRON_2Gb_DDR3-1600_16bit_D.json index fe5d593e..18850904 100644 --- a/configs/memspec/MICRON_2Gb_DDR3-1600_16bit_D.json +++ b/configs/memspec/MICRON_2Gb_DDR3-1600_16bit_D.json @@ -9,22 +9,23 @@ "nbrOfRows": 16384, "width": 16, "nbrOfDevices": 4, - "nbrOfChannels": 1 + "nbrOfChannels": 1, + "maxBurstLength": 8 }, "memoryId": "MICRON_2Gb_DDR3-1600_16bit_D", "memoryType": "DDR3", "mempowerspec": { - "idd0": 110.0, - "idd2n": 42.0, - "idd2p0": 12.0, - "idd2p1": 40.0, - "idd3n": 45.0, - "idd3p0": 45.0, - "idd3p1": 45.0, - "idd4r": 270.0, - "idd4w": 280.0, - "idd5": 215.0, - "idd6": 12.0, + "idd0": 110.0e-3, + "idd2n": 42.0e-3, + "idd2p0": 12.0e-3, + "idd2p1": 40.0e-3, + "idd3n": 45.0e-3, + "idd3p0": 45.0e-3, + "idd3p1": 45.0e-3, + "idd4r": 270.0e-3, + "idd4w": 280.0e-3, + "idd5": 215.0e-3, + "idd6": 12.0e-3, "vdd": 1.5 }, "memtimingspec": { @@ -55,7 +56,7 @@ "PRPDEN": 1, "REFPDEN": 1, "RTRS": 1, - "tCK": 1250 + "tCK": 1250e-12 } } } diff --git a/configs/memspec/MICRON_2Gb_DDR3-1600_16bit_D_2s.json b/configs/memspec/MICRON_2Gb_DDR3-1600_16bit_D_2s.json index 04335775..41f668fe 100644 --- a/configs/memspec/MICRON_2Gb_DDR3-1600_16bit_D_2s.json +++ b/configs/memspec/MICRON_2Gb_DDR3-1600_16bit_D_2s.json @@ -9,22 +9,23 @@ "nbrOfRows": 16384, "width": 16, "nbrOfDevices": 4, - "nbrOfChannels": 1 + "nbrOfChannels": 1, + "maxBurstLength": 8 }, "memoryId": "MICRON_2Gb_DDR3-1600_16bit_D_2s", "memoryType": "DDR3", "mempowerspec": { - "idd0": 102.83, - "idd2n": 36.89, - "idd2p0": 8.77, - "idd2p1": 29.25, - "idd3n": 38.75, - "idd3p0": 38.75, - "idd3p1": 38.75, - "idd4r": 247.34, - "idd4w": 260.04, - "idd5": 202.17, - "idd6": 8.67, + "idd0": 102.83e-3, + "idd2n": 36.89e-3, + "idd2p0": 8.77e-3, + "idd2p1": 29.25e-3, + "idd3n": 38.75e-3, + "idd3p0": 38.75e-3, + "idd3p1": 38.75e-3, + "idd4r": 247.34e-3, + "idd4w": 260.04e-3, + "idd5": 202.17e-3, + "idd6": 8.67e-3, "vdd": 1.5 }, "memtimingspec": { @@ -55,7 +56,7 @@ "PRPDEN": 1, "REFPDEN": 1, "RTRS": 1, - "tCK": 1250 + "tCK": 1250e-12 } } } diff --git a/configs/memspec/MICRON_2Gb_DDR3-1600_16bit_D_3s.json b/configs/memspec/MICRON_2Gb_DDR3-1600_16bit_D_3s.json index 4f8c5cb5..e860fb72 100644 --- a/configs/memspec/MICRON_2Gb_DDR3-1600_16bit_D_3s.json +++ b/configs/memspec/MICRON_2Gb_DDR3-1600_16bit_D_3s.json @@ -9,22 +9,23 @@ "nbrOfRows": 16384, "width": 16, "nbrOfDevices": 4, - "nbrOfChannels": 1 + "nbrOfChannels": 1, + "maxBurstLength": 8 }, "memoryId": "MICRON_2Gb_DDR3-1600_16bit_D_3s", "memoryType": "DDR3", "mempowerspec": { - "idd0": 105.25, - "idd2n": 38.59, - "idd2p0": 9.85, - "idd2p1": 32.83, - "idd3n": 40.83, - "idd3p0": 40.83, - "idd3p1": 40.83, - "idd4r": 254.89, - "idd4w": 266.69, - "idd5": 206.44, - "idd6": 9.78, + "idd0": 105.25e-3, + "idd2n": 38.59e-3, + "idd2p0": 9.85e-3, + "idd2p1": 32.83e-3, + "idd3n": 40.83e-3, + "idd3p0": 40.83e-3, + "idd3p1": 40.83e-3, + "idd4r": 254.89e-3, + "idd4w": 266.69e-3, + "idd5": 206.44e-3, + "idd6": 9.78e-3, "vdd": 1.5 }, "memtimingspec": { @@ -55,7 +56,7 @@ "PRPDEN": 1, "REFPDEN": 1, "RTRS": 1, - "tCK": 1250 + "tCK": 1250e-12 } } } diff --git a/configs/memspec/MICRON_2Gb_DDR3-1600_16bit_D_mu.json b/configs/memspec/MICRON_2Gb_DDR3-1600_16bit_D_mu.json index 86e989e8..6e28b8a9 100644 --- a/configs/memspec/MICRON_2Gb_DDR3-1600_16bit_D_mu.json +++ b/configs/memspec/MICRON_2Gb_DDR3-1600_16bit_D_mu.json @@ -9,22 +9,23 @@ "nbrOfRows": 16384, "width": 16, "nbrOfDevices": 4, - "nbrOfChannels": 1 + "nbrOfChannels": 1, + "maxBurstLength": 8 }, "memoryId": "MICRON_2Gb_DDR3-1600_16bit_D_mu", "memoryType": "DDR3", "mempowerspec": { - "idd0": 98.06, - "idd2n": 33.49, - "idd2p0": 6.62, - "idd2p1": 22.09, - "idd3n": 34.59, - "idd3p0": 34.59, - "idd3p1": 34.59, - "idd4r": 232.24, - "idd4w": 246.74, - "idd5": 193.62, - "idd6": 6.45, + "idd0": 98.06e-3, + "idd2n": 33.49e-3, + "idd2p0": 6.62e-3, + "idd2p1": 22.09e-3, + "idd3n": 34.59e-3, + "idd3p0": 34.59e-3, + "idd3p1": 34.59e-3, + "idd4r": 232.24e-3, + "idd4w": 246.74e-3, + "idd5": 193.62e-3, + "idd6": 6.45e-3, "vdd": 1.5 }, "memtimingspec": { @@ -55,7 +56,7 @@ "PRPDEN": 1, "REFPDEN": 1, "RTRS": 1, - "tCK": 1250 + "tCK": 1250e-12 } } } diff --git a/configs/memspec/MICRON_2Gb_LPDDR-266_16bit_A.json b/configs/memspec/MICRON_2Gb_LPDDR-266_16bit_A.json index a0ea1b1a..d16b4c3d 100644 --- a/configs/memspec/MICRON_2Gb_LPDDR-266_16bit_A.json +++ b/configs/memspec/MICRON_2Gb_LPDDR-266_16bit_A.json @@ -14,17 +14,17 @@ "memoryId": "MICRON_2Gb_LPDDR-266_16bit_A", "memoryType": "LPDDR", "mempowerspec": { - "idd0": 70.0, - "idd2n": 12.0, - "idd2p0": 0.6, - "idd2p1": 0.6, - "idd3n": 16.0, - "idd3p0": 3.6, - "idd3p1": 3.6, - "idd4r": 105.0, - "idd4w": 105.0, - "idd5": 170.0, - "idd6": 1.7, + "idd0": 70.0e-3, + "idd2n": 12.0e-3, + "idd2p0": 0.6e-3, + "idd2p1": 0.6e-3, + "idd3n": 16.0e-3, + "idd3p0": 3.6e-3, + "idd3p1": 3.6e-3, + "idd4r": 105.0e-3, + "idd4w": 105.0e-3, + "idd5": 170.0e-3, + "idd6": 1.7e-3, "vdd": 1.8 }, "memtimingspec": { @@ -50,7 +50,7 @@ "XPDLL": 1, "XS": 15, "XSDLL": 15, - "tCK": 7519 + "tCK": 7519e-12 } } } diff --git a/configs/memspec/MICRON_2Gb_LPDDR-333_16bit_A.json b/configs/memspec/MICRON_2Gb_LPDDR-333_16bit_A.json index 705a9142..a5b731d8 100644 --- a/configs/memspec/MICRON_2Gb_LPDDR-333_16bit_A.json +++ b/configs/memspec/MICRON_2Gb_LPDDR-333_16bit_A.json @@ -14,17 +14,17 @@ "memoryId": "MICRON_2Gb_LPDDR-333_16bit_A", "memoryType": "LPDDR", "mempowerspec": { - "idd0": 100.0, - "idd2n": 15.0, - "idd2p0": 0.6, - "idd2p1": 0.6, - "idd3n": 18.0, - "idd3p0": 3.6, - "idd3p1": 3.6, - "idd4r": 115.0, - "idd4w": 115.0, - "idd5": 170.0, - "idd6": 1.7, + "idd0": 100.0e-3, + "idd2n": 15.0e-3, + "idd2p0": 0.6e-3, + "idd2p1": 0.6e-3, + "idd3n": 18.0e-3, + "idd3p0": 3.6e-3, + "idd3p1": 3.6e-3, + "idd4r": 115.0e-3, + "idd4w": 115.0e-3, + "idd5": 170.0e-3, + "idd6": 1.7e-3, "vdd": 1.8 }, "memtimingspec": { @@ -50,7 +50,7 @@ "XPDLL": 1, "XS": 19, "XSDLL": 19, - "tCK": 6024 + "tCK": 6024e-12 } } } diff --git a/configs/memspec/MICRON_2Gb_LPDDR2-1066-S4_16bit_A.json b/configs/memspec/MICRON_2Gb_LPDDR2-1066-S4_16bit_A.json index 6beac308..f2c51e26 100644 --- a/configs/memspec/MICRON_2Gb_LPDDR2-1066-S4_16bit_A.json +++ b/configs/memspec/MICRON_2Gb_LPDDR2-1066-S4_16bit_A.json @@ -14,28 +14,28 @@ "memoryId": "MICRON_2Gb_LPDDR2-1066-S4_16bit_A", "memoryType": "LPDDR2", "mempowerspec": { - "idd0": 20.0, - "idd02": 71.0, - "idd2n": 1.7, - "idd2n2": 22.0, - "idd2p0": 0.5, - "idd2p02": 1.7, - "idd2p1": 0.5, - "idd2p12": 1.7, - "idd3n": 1.2, - "idd3n2": 30.0, - "idd3p0": 1.2, - "idd3p02": 4.12, - "idd3p1": 1.2, - "idd3p12": 4.12, - "idd4r": 5.0, - "idd4r2": 226.0, - "idd4w": 10.0, - "idd4w2": 208.0, - "idd5": 15.0, - "idd52": 136.0, - "idd6": 1.2, - "idd62": 2.6, + "idd0": 20.0e-3, + "idd02": 71.0e-3, + "idd2n": 1.7e-3, + "idd2n2": 22.0e-3, + "idd2p0": 0.5e-3, + "idd2p02": 1.7e-3, + "idd2p1": 0.5e-3, + "idd2p12": 1.7e-3, + "idd3n": 1.2e-3, + "idd3n2": 30.0e-3, + "idd3p0": 1.2e-3, + "idd3p02": 4.12e-3, + "idd3p1": 1.2e-3, + "idd3p12": 4.12e-3, + "idd4r": 5.0e-3, + "idd4r2": 226.0e-3, + "idd4w": 10.0e-3, + "idd4w2": 208.0e-3, + "idd5": 15.0e-3, + "idd52": 136.0e-3, + "idd6": 1.2e-3, + "idd62": 2.6e-3, "vdd": 1.8, "vdd2": 1.2 }, @@ -63,7 +63,7 @@ "XPDLL": 4, "XS": 75, "XSDLL": 75, - "tCK": 1876 + "tCK": 1876e-12 } } } diff --git a/configs/memspec/MICRON_2Gb_LPDDR2-800-S4_16bit_A.json b/configs/memspec/MICRON_2Gb_LPDDR2-800-S4_16bit_A.json index 52cb669e..88d65899 100644 --- a/configs/memspec/MICRON_2Gb_LPDDR2-800-S4_16bit_A.json +++ b/configs/memspec/MICRON_2Gb_LPDDR2-800-S4_16bit_A.json @@ -14,28 +14,28 @@ "memoryId": "MICRON_2Gb_LPDDR2-800-S4_16bit_A", "memoryType": "LPDDR2", "mempowerspec": { - "idd0": 20.0, - "idd02": 56.0, - "idd2n": 1.7, - "idd2n2": 21.0, - "idd2p0": 0.5, - "idd2p02": 1.7, - "idd2p1": 0.5, - "idd2p12": 1.7, - "idd3n": 1.2, - "idd3n2": 29.0, - "idd3p0": 1.2, - "idd3p02": 4.12, - "idd3p1": 1.2, - "idd3p12": 4.12, - "idd4r": 5.0, - "idd4r2": 216.0, - "idd4w": 10.0, - "idd4w2": 203.0, - "idd5": 15.0, - "idd52": 136.0, - "idd6": 1.2, - "idd62": 2.6, + "idd0": 20.0e-3, + "idd02": 56.0e-3, + "idd2n": 1.7e-3, + "idd2n2": 21.0e-3, + "idd2p0": 0.5e-3, + "idd2p02": 1.7e-3, + "idd2p1": 0.5e-3, + "idd2p12": 1.7e-3, + "idd3n": 1.2e-3, + "idd3n2": 29.0e-3, + "idd3p0": 1.2e-3, + "idd3p02": 4.12e-3, + "idd3p1": 1.2e-3, + "idd3p12": 4.12e-3, + "idd4r": 5.0e-3, + "idd4r2": 216.0e-3, + "idd4w": 10.0e-3, + "idd4w2": 203.0e-3, + "idd5": 15.0e-3, + "idd52": 136.0e-3, + "idd6": 1.2e-3, + "idd62": 2.6e-3, "vdd": 1.8, "vdd2": 1.2 }, @@ -63,7 +63,7 @@ "XPDLL": 3, "XS": 56, "XSDLL": 56, - "tCK": 2500 + "tCK": 2500e-12 } } } diff --git a/configs/memspec/MICRON_4Gb_DDR4-1866_8bit_A.json b/configs/memspec/MICRON_4Gb_DDR4-1866_8bit_A.json index ce5b351f..053af75e 100644 --- a/configs/memspec/MICRON_4Gb_DDR4-1866_8bit_A.json +++ b/configs/memspec/MICRON_4Gb_DDR4-1866_8bit_A.json @@ -10,26 +10,44 @@ "nbrOfRows": 32768, "width": 8, "nbrOfDevices": 8, - "nbrOfChannels": 1 + "nbrOfChannels": 1, + "RefMode": 1, + "maxBurstLength": 8 }, "memoryId": "MICRON_4Gb_DDR4-1866_8bit_A", "memoryType": "DDR4", "mempowerspec": { - "idd0": 56.25, - "idd02": 4.05, - "idd2n": 33.75, - "idd2p0": 17.0, - "idd2p1": 17.0, - "idd3n": 39.5, - "idd3p0": 22.5, - "idd3p1": 22.5, - "idd4r": 157.5, - "idd4w": 135.0, - "idd5": 118.0, - "idd6": 20.25, - "idd62": 2.6, "vdd": 1.2, - "vdd2": 2.5 + "idd0": 56.25e-3, + "idd2n": 33.75e-3, + "idd3n": 39.5e-3, + "idd4r": 157.5e-3, + "idd4w": 135.0e-3, + "idd6n": 20.25e-3, + "idd2p": 17.0e-3, + "idd3p": 22.5e-3, + + "vpp": 2.5, + "ipp0": 4.05e-3, + "ipp2n": 0, + "ipp3n": 0, + "ipp4r": 0, + "ipp4w": 0, + "ipp6n": 2.6e-3, + "ipp2p": 17.0e-3, + "ipp3p": 22.5e-3, + + "idd5B": 118.0e-3, + "ipp5B": 0.0, + "idd5F2": 0.0, + "ipp5F2": 0.0, + "idd5F4": 0.0, + "ipp5F4": 0.0, + "vddq": 0.0, + + "iBeta_vdd": 56.25e-3, + "iBeta_vpp": 4.05e-3 + }, "memtimingspec": { "AL": 0, @@ -45,7 +63,9 @@ "RCD": 13, "REFM": 1, "REFI": 3644, - "RFC": 243, + "RFC1": 243, + "RFC2": 0, + "RFC4": 0, "RL": 13, "RPRE": 1, "RP": 13, @@ -65,7 +85,45 @@ "PRPDEN": 1, "REFPDEN": 1, "RTRS": 1, - "tCK": 1072 + "tCK": 1072e-12 + }, + "bankwisespec": { + "factRho": 1.0 + }, + "memimpedancespec": { + "ck_termination": true, + "ck_R_eq": 1e6, + "ck_dyn_E": 1e-12, + + "ca_termination": true, + "ca_R_eq": 1e6, + "ca_dyn_E": 1e-12, + + "rdq_termination": true, + "rdq_R_eq": 1e6, + "rdq_dyn_E": 1e-12, + "wdq_termination": true, + "wdq_R_eq": 1e6, + "wdq_dyn_E": 1e-12, + + "wdqs_termination": true, + "wdqs_R_eq": 1e6, + "wdqs_dyn_E": 1e-12, + "rdqs_termination": true, + "rdqs_R_eq": 1e6, + "rdqs_dyn_E": 1e-12 + }, + "prepostamble": { + "read_zeroes": 0.0, + "write_zeroes": 0.0, + "read_ones": 0.0, + "write_ones": 0.0, + "read_zeroes_to_ones": 0, + "write_zeroes_to_ones": 0, + "write_ones_to_zeroes": 0, + "read_ones_to_zeroes": 0, + "readMinTccd": 0, + "writeMinTccd": 0 } } } diff --git a/configs/memspec/MICRON_4Gb_DDR4-2400_8bit_A.json b/configs/memspec/MICRON_4Gb_DDR4-2400_8bit_A.json index e1c5d429..1a2d08ad 100644 --- a/configs/memspec/MICRON_4Gb_DDR4-2400_8bit_A.json +++ b/configs/memspec/MICRON_4Gb_DDR4-2400_8bit_A.json @@ -10,26 +10,43 @@ "nbrOfRows": 32768, "width": 8, "nbrOfDevices": 8, - "nbrOfChannels": 1 + "nbrOfChannels": 1, + "RefMode": 1, + "maxBurstLength": 8 }, "memoryId": "MICRON_4Gb_DDR4-2400_8bit_A", "memoryType": "DDR4", "mempowerspec": { - "idd0": 60.75, - "idd02": 4.05, - "idd2n": 38.25, - "idd2p0": 17.0, - "idd2p1": 17.0, - "idd3n": 44.0, - "idd3p0": 22.5, - "idd3p1": 22.5, - "idd4r": 184.5, - "idd4w": 168.75, - "idd5": 118.0, - "idd6": 20.25, - "idd62": 2.6, "vdd": 1.2, - "vdd2": 2.5 + "idd0": 60.75e-3, + "idd2n": 38.25e-3, + "idd3n": 44.0e-3, + "idd4r": 184.5e-3, + "idd4w": 168.75e-3, + "idd6n": 20.25e-3, + "idd2p": 17.0e-3, + "idd3p": 22.5e-3, + + "vpp": 2.5, + "ipp0": 4.05e-3, + "ipp2n": 0, + "ipp3n": 0, + "ipp4r": 0, + "ipp4w": 0, + "ipp6n": 2.6e-3, + "ipp2p": 17.0e-3, + "ipp3p": 22.5e-3, + + "idd5B": 118.0e-3, + "ipp5B": 0.0, + "idd5F2": 0.0, + "ipp5F2": 0.0, + "idd5F4": 0.0, + "ipp5F4": 0.0, + "vddq": 0.0, + + "iBeta_vdd": 60.75e-3, + "iBeta_vpp": 4.05e-3 }, "memtimingspec": { "AL": 0, @@ -45,7 +62,9 @@ "RCD": 16, "REFM": 1, "REFI": 4680, - "RFC": 313, + "RFC1": 313, + "RFC2": 0, + "RFC4": 0, "RL": 16, "RPRE": 1, "RP": 16, @@ -65,7 +84,45 @@ "PRPDEN": 2, "REFPDEN": 2, "RTRS": 1, - "tCK": 833 + "tCK": 833e-12 + }, + "bankwisespec": { + "factRho": 1.0 + }, + "memimpedancespec": { + "ck_termination": true, + "ck_R_eq": 1e6, + "ck_dyn_E": 1e-12, + + "ca_termination": true, + "ca_R_eq": 1e6, + "ca_dyn_E": 1e-12, + + "rdq_termination": true, + "rdq_R_eq": 1e6, + "rdq_dyn_E": 1e-12, + "wdq_termination": true, + "wdq_R_eq": 1e6, + "wdq_dyn_E": 1e-12, + + "wdqs_termination": true, + "wdqs_R_eq": 1e6, + "wdqs_dyn_E": 1e-12, + "rdqs_termination": true, + "rdqs_R_eq": 1e6, + "rdqs_dyn_E": 1e-12 + }, + "prepostamble": { + "read_zeroes": 0.0, + "write_zeroes": 0.0, + "read_ones": 0.0, + "write_ones": 0.0, + "read_zeroes_to_ones": 0, + "write_zeroes_to_ones": 0, + "write_ones_to_zeroes": 0, + "read_ones_to_zeroes": 0, + "readMinTccd": 0, + "writeMinTccd": 0 } } } diff --git a/configs/memspec/MICRON_4Gb_LPDDR3-1333_32bit_A.json b/configs/memspec/MICRON_4Gb_LPDDR3-1333_32bit_A.json index 17b4e42d..27b53ce8 100644 --- a/configs/memspec/MICRON_4Gb_LPDDR3-1333_32bit_A.json +++ b/configs/memspec/MICRON_4Gb_LPDDR3-1333_32bit_A.json @@ -14,28 +14,28 @@ "memoryId": "MICRON_4Gb_LPDDR3-1333_32bit_A", "memoryType": "LPDDR3", "mempowerspec": { - "idd0": 15.0, - "idd02": 78.0, - "idd2n": 2.0, - "idd2n2": 36.0, - "idd2p0": 0.6, - "idd2p02": 0.87, - "idd2p1": 0.6, - "idd2p12": 0.87, - "idd3n": 2.0, - "idd3n2": 38.0, - "idd3p0": 1.2, - "idd3p02": 8.15, - "idd3p1": 1.2, - "idd3p12": 8.15, - "idd4r": 5.0, - "idd4r2": 243.0, - "idd4w": 10.0, - "idd4w2": 265.0, - "idd5": 40.0, - "idd52": 158.0, - "idd6": 1.0, - "idd62": 3.27, + "idd0": 15.0e-3, + "idd02": 78.0e-3, + "idd2n": 2.0e-3, + "idd2n2": 36.0e-3, + "idd2p0": 0.6e-3, + "idd2p02": 0.87e-3, + "idd2p1": 0.6e-3, + "idd2p12": 0.87e-3, + "idd3n": 2.0e-3, + "idd3n2": 38.0e-3, + "idd3p0": 1.2e-3, + "idd3p02": 8.15e-3, + "idd3p1": 1.2e-3, + "idd3p12": 8.15e-3, + "idd4r": 5.0e-3, + "idd4r2": 243.0e-3, + "idd4w": 10.0e-3, + "idd4w2": 265.0e-3, + "idd5": 40.0e-3, + "idd52": 158.0e-3, + "idd6": 1.0e-3, + "idd62": 3.27e-3, "vdd": 1.8, "vdd2": 1.2 }, @@ -63,7 +63,7 @@ "XPDLL": 6, "XS": 94, "XSDLL": 94, - "tCK": 1499 + "tCK": 1499e-12 } } } diff --git a/configs/memspec/MICRON_4Gb_LPDDR3-1600_32bit_A.json b/configs/memspec/MICRON_4Gb_LPDDR3-1600_32bit_A.json index 574d94eb..82889196 100644 --- a/configs/memspec/MICRON_4Gb_LPDDR3-1600_32bit_A.json +++ b/configs/memspec/MICRON_4Gb_LPDDR3-1600_32bit_A.json @@ -14,28 +14,28 @@ "memoryId": "MICRON_4Gb_LPDDR3-1600_32bit_A", "memoryType": "LPDDR3", "mempowerspec": { - "idd0": 15.0, - "idd02": 80.0, - "idd2n": 2.0, - "idd2n2": 38.0, - "idd2p0": 0.6, - "idd2p02": 0.87, - "idd2p1": 0.6, - "idd2p12": 0.87, - "idd3n": 2.0, - "idd3n2": 45.0, - "idd3p0": 1.2, - "idd3p02": 8.15, - "idd3p1": 1.2, - "idd3p12": 8.15, - "idd4r": 5.0, - "idd4r2": 260.0, - "idd4w": 10.0, - "idd4w2": 284.0, - "idd5": 40.0, - "idd52": 160.0, - "idd6": 1.0, - "idd62": 3.27, + "idd0": 15.0e-3, + "idd02": 80.0e-3, + "idd2n": 2.0e-3, + "idd2n2": 38.0e-3, + "idd2p0": 0.6e-3, + "idd2p02": 0.87e-3, + "idd2p1": 0.6e-3, + "idd2p12": 0.87e-3, + "idd3n": 2.0e-3, + "idd3n2": 45.0e-3, + "idd3p0": 1.2e-3, + "idd3p02": 8.15e-3, + "idd3p1": 1.2e-3, + "idd3p12": 8.15e-3, + "idd4r": 5.0e-3, + "idd4r2": 260.0e-3, + "idd4w": 10.0e-3, + "idd4w2": 284.0e-3, + "idd5": 40.0e-3, + "idd52": 160.0e-3, + "idd6": 1.0e-3, + "idd62": 3.27e-3, "vdd": 1.8, "vdd2": 1.2 }, @@ -63,7 +63,7 @@ "XPDLL": 6, "XS": 112, "XSDLL": 112, - "tCK": 1250 + "tCK": 1250e-12 } } } diff --git a/configs/memspec/MICRON_6Gb_LPDDR4-3200_32bit_A.json b/configs/memspec/MICRON_6Gb_LPDDR4-3200_32bit_A.json index 6974feb9..16fd05d1 100644 --- a/configs/memspec/MICRON_6Gb_LPDDR4-3200_32bit_A.json +++ b/configs/memspec/MICRON_6Gb_LPDDR4-3200_32bit_A.json @@ -9,59 +9,64 @@ "nbrOfRows": 49152, "width": 16, "nbrOfDevices": 1, - "nbrOfChannels": 1 + "nbrOfChannels": 1, + "nbrOfBankGroups": 1, + "maxBurstLength": 16 }, "memoryId": "MICRON_6Gb_LPDDR3-3200_16bit_A", "memoryType": "LPDDR4", "mempowerspec": { - "idd0": 3.5, - "idd02": 45.0, - "idd0ql": 0.75, - "idd2n": 2.0, - "idd2n2": 27.0, - "idd2nQ": 0.75, - "idd2ns": 2.0, - "idd2ns2": 23.0, - "idd2nsq": 0.75, - "idd2p": 1.2, - "idd2p2": 3.0, - "idd2pQ": 0.75, - "idd2ps": 1.2, - "idd2ps2": 3.0, - "idd2psq": 0.75, - "idd3n": 2.25, - "idd3n2": 30.0, - "idd3nQ": 0.75, - "idd3ns": 2.25, - "idd3ns2": 30.0, - "idd3nsq": 0.75, - "idd3p": 1.2, - "idd3p2": 9.0, - "idd3pQ": 0.75, - "idd3ps": 1.2, - "idd3ps2": 9.0, - "idd3psq": 0.75, - "idd4r": 2.25, - "idd4r2": 275.0, - "idd4rq": 150.0, - "idd4w": 2.25, - "idd4w2": 210.0, - "idd4wq": 55.0, - "idd5": 10.0, - "idd52": 90.0, - "idd5ab": 2.5, - "idd5ab2": 30.0, - "idd5abq": 0.75, - "idd5b": 2.5, - "idd5b2": 30.0, - "idd5bq": 0.75, - "idd5q": 0.75, - "idd6": 0.3, - "idd62": 0.5, - "idd6q": 0.1, - "vdd": 1.8, + "idd01": 3.5e-3, + "idd02": 45.0e-3, + "idd0ql": 0.75e-3, + "idd2n1": 2.0e-3, + "idd2n2": 27.0e-3, + "idd2nQ": 0.75e-3, + "idd2ns1": 2.0e-3, + "idd2ns2": 23.0e-3, + "idd2nsq": 0.75e-3, + "idd2p1": 1.2e-3, + "idd2p2": 3.0e-3, + "idd2pQ": 0.75e-3, + "idd2ps1": 1.2e-3, + "idd2ps2": 3.0e-3, + "idd2psq": 0.75e-3, + "idd3n1": 2.25e-3, + "idd3n2": 30.0e-3, + "idd3nQ": 0.75e-3, + "idd3ns1": 2.25e-3, + "idd3ns2": 30.0e-3, + "idd3nsq": 0.75e-3, + "idd3p1": 1.2e-3, + "idd3p2": 9.0e-3, + "idd3pQ": 0.75e-3, + "idd3ps1": 1.2e-3, + "idd3ps2": 9.0e-3, + "idd3psq": 0.75e-3, + "idd4r1": 2.25e-3, + "idd4r2": 275.0e-3, + "idd4rq": 150.0e-3, + "idd4w1": 2.25e-3, + "idd4w2": 210.0e-3, + "idd4wq": 55.0e-3, + "idd51": 10.0e-3, + "idd52": 90.0e-3, + "idd5ab1": 2.5e-3, + "idd5ab2": 30.0e-3, + "idd5abq": 0.75e-3, + "idd5pb1": 2.5e-3, + "idd5pb2": 30.0e-3, + "idd5pbq": 0.75e-3, + "idd5q": 0.75e-3, + "idd61": 0.3e-3, + "idd62": 0.5e-3, + "idd6q": 0.1e-3, + "vdd1": 1.8, "vdd2": 1.1, - "vddq": 1.1 + "vddq": 1.1, + + "iBeta_vdd1": 3.5e-3, + "iBeta_vdd2": 45.0e-3 }, "memtimingspec": { "AL": 0, @@ -77,13 +82,13 @@ "RAS": 68, "RC": 97, "RCD": 29, - "REFIAB": 6246, - "REFIPB": 780, - "RFCAB": 448, - "RFCPB": 224, + "REFI": 6246, + "REFIpb": 780, + "RFCab": 448, + "RFCpb": 224, "RL": 28, - "RPAB": 34, - "RPPB": 29, + "RPab": 34, + "RPpb": 29, "RRD": 16, "RTP": 12, "WL": 14, @@ -91,7 +96,47 @@ "WTR": 16, "XP": 12, "XS": 458, - "tCK": 625 + "tCK": 625, + + "RCpb": 0, + "RCab": 0, + "RPST": 0, + "DQSS": 0, + "DQS2DQ": 0, + "WPRE": 0, + "SR": 0, + "XSR": 0, + "RTRS": 0, + "CMDCKE": 0 + }, + "memimpedancespec": { + "ck_termination": true, + "ck_R_eq": 1e6, + "ck_dyn_E": 1e-12, + + "ca_termination": true, + "ca_R_eq": 1e6, + "ca_dyn_E": 1e-12, + + "rdq_termination": true, + "rdq_R_eq": 1e6, + "rdq_dyn_E": 1e-12, + "wdq_termination": true, + "wdq_R_eq": 1e6, + "wdq_dyn_E": 1e-12, + + "wdqs_termination": true, + "wdqs_R_eq": 1e6, + "wdqs_dyn_E": 1e-12, + "rdqs_termination": true, + "rdqs_R_eq": 1e6, + "rdqs_dyn_E": 1e-12 + }, + "bankwisespec": { + "factRho": 1, + "factSigma": 1, + "pasrMode": 0, + "hasPASR": false } } } diff --git a/configs/memspec/SAMSUNG_K4B1G1646E_1Gb_DDR3-1600_16bit.json b/configs/memspec/SAMSUNG_K4B1G1646E_1Gb_DDR3-1600_16bit.json index e700cd4f..3a5f071a 100644 --- a/configs/memspec/SAMSUNG_K4B1G1646E_1Gb_DDR3-1600_16bit.json +++ b/configs/memspec/SAMSUNG_K4B1G1646E_1Gb_DDR3-1600_16bit.json @@ -10,6 +10,7 @@ "width": 16, "nbrOfChannels": 1, "nbrOfDevices": 1, + "maxBurstLength": 8 }, "memoryId": "SAMSUNG_K4B1G1646E_1Gb_DDR3-1600_16bit", "memoryType": "DDR3", @@ -55,7 +56,7 @@ "PRPDEN": 1, "REFPDEN": 1, "RTRS": 1, - "tCK": 1250 + "tCK": 1250e-12 } } } diff --git a/configs/memspec/SAMSUNG_K4B4G1646Q_4Gb_DDR3-1066_16bit.json b/configs/memspec/SAMSUNG_K4B4G1646Q_4Gb_DDR3-1066_16bit.json index aac43e95..54016e7a 100644 --- a/configs/memspec/SAMSUNG_K4B4G1646Q_4Gb_DDR3-1066_16bit.json +++ b/configs/memspec/SAMSUNG_K4B4G1646Q_4Gb_DDR3-1066_16bit.json @@ -9,7 +9,8 @@ "nbrOfRows": 32768, "width": 16, "nbrOfDevices": 1, - "nbrOfChannels": 1 + "nbrOfChannels": 1, + "maxBurstLength": 8 }, "memoryId": "SAMSUNG_K4B4G1646Q_4Gb_DDR3-1066_16bit", "memoryType": "DDR3", @@ -55,7 +56,7 @@ "PRPDEN": 1, "REFPDEN": 1, "RTRS": 1, - "tCK": 1876 + "tCK": 1876e-12 } } } diff --git a/configs/memspec/STT-MRAM-1.2x.json b/configs/memspec/STT-MRAM-1.2x.json index bbb84c26..98949645 100644 --- a/configs/memspec/STT-MRAM-1.2x.json +++ b/configs/memspec/STT-MRAM-1.2x.json @@ -9,7 +9,8 @@ "nbrOfRows": 32768, "width": 8, "nbrOfDevices": 8, - "nbrOfChannels": 1 + "nbrOfChannels": 1, + "maxBurstLength": 8 }, "memoryId": "STT-MRAM-1.2x", "memoryType": "STT-MRAM", @@ -38,7 +39,7 @@ "ACTPDEN": 2, "PRPDEN": 2, "RTRS": 1, - "tCK": 1250 + "tCK": 1250e-12 } } } diff --git a/configs/memspec/STT-MRAM-1.5x.json b/configs/memspec/STT-MRAM-1.5x.json index 1d89c3d1..4578813c 100644 --- a/configs/memspec/STT-MRAM-1.5x.json +++ b/configs/memspec/STT-MRAM-1.5x.json @@ -9,7 +9,8 @@ "nbrOfRows": 32768, "width": 8, "nbrOfDevices": 8, - "nbrOfChannels": 1 + "nbrOfChannels": 1, + "maxBurstLength": 8 }, "memoryId": "STT-MRAM-1.5x", "memoryType": "STT-MRAM", @@ -38,7 +39,7 @@ "ACTPDEN": 2, "PRPDEN": 2, "RTRS": 1, - "tCK": 1250 + "tCK": 1250e-12 } } } diff --git a/configs/memspec/STT-MRAM-2.0x.json b/configs/memspec/STT-MRAM-2.0x.json index 6a8aaaeb..7e98aebe 100644 --- a/configs/memspec/STT-MRAM-2.0x.json +++ b/configs/memspec/STT-MRAM-2.0x.json @@ -9,7 +9,8 @@ "nbrOfRows": 32768, "width": 8, "nbrOfDevices": 8, - "nbrOfChannels": 1 + "nbrOfChannels": 1, + "maxBurstLength": 8 }, "memoryId": "STT-MRAM-2.0x", "memoryType": "STT-MRAM", @@ -38,7 +39,7 @@ "ACTPDEN": 2, "PRPDEN": 2, "RTRS": 1, - "tCK": 1250 + "tCK": 1250e-12 } } } diff --git a/configs/simconfig/example.json b/configs/simconfig/example.json index 6b65d7d0..8c271130 100644 --- a/configs/simconfig/example.json +++ b/configs/simconfig/example.json @@ -4,12 +4,20 @@ "CheckTLM2Protocol": false, "DatabaseRecording": true, "Debug": false, - "EnableWindowing": false, + "EnableWindowing": true, "PowerAnalysis": false, "SimulationName": "example", "SimulationProgressBar": true, "StoreMode": "NoStorage", "UseMalloc": false, - "WindowSize": 1000 + "WindowSize": 1000, + "TogglingRate": { + "togglingRateRead": 0.5, + "togglingRateWrite": 0.5, + "dutyCycleRead": 0.5, + "dutyCycleWrite": 0.5, + "idlePatternRead": "L", + "idlePatternWrite": "L" + } } } diff --git a/configs/stt-mram-example.json b/configs/stt-mram-example.json index 322af039..8ecf6da2 100644 --- a/configs/stt-mram-example.json +++ b/configs/stt-mram-example.json @@ -7,6 +7,7 @@ "simulationid": "stt-mram-example", "tracesetup": [ { + "type": "player", "clkMhz": 800, "name": "traces/example.stl" } diff --git a/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoDDR5.cpp b/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoDDR5.cpp index c5df55ca..4954495c 100644 --- a/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoDDR5.cpp +++ b/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoDDR5.cpp @@ -47,7 +47,7 @@ void TimeDependenciesInfoDDR5::mInitializeValues() burstLength = mMemspecJson["memarchitecturespec"].toObject()["burstLength"].toInt(); dataRate = mMemspecJson["memarchitecturespec"].toObject()["dataRate"].toInt(); - refMode = mMemspecJson["memarchitecturespec"].toObject()["refMode"].toInt(); + RefMode = mMemspecJson["memarchitecturespec"].toObject()["RefMode"].toInt(); cmdMode = mMemspecJson["memarchitecturespec"].toObject()["cmdMode"].toInt(); bitWidth = mMemspecJson["memarchitecturespec"].toObject()["width"].toInt(); @@ -100,7 +100,7 @@ void TimeDependenciesInfoDDR5::mInitializeValues() tRC = tRAS + tRP; - if (refMode == 1) + if (RefMode == 1) { tRFC_slr = tCK * mMemspecJson["memtimingspec"].toObject()["RFC1_slr"].toInt(); tRFC_dlr = tCK * mMemspecJson["memtimingspec"].toObject()["RFC1_dlr"].toInt(); diff --git a/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoDDR5.h b/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoDDR5.h index b5d6d102..3dbab4f0 100644 --- a/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoDDR5.h +++ b/extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoDDR5.h @@ -33,7 +33,7 @@ protected: uint burstLength; uint dataRate; - uint refMode; + uint RefMode; uint tRCD; uint tPPD; diff --git a/extensions/apps/traceAnalyzer/scripts/tests.py b/extensions/apps/traceAnalyzer/scripts/tests.py index 4f51e98c..370bd78b 100644 --- a/extensions/apps/traceAnalyzer/scripts/tests.py +++ b/extensions/apps/traceAnalyzer/scripts/tests.py @@ -10,7 +10,7 @@ class DramConfig(object): memoryType = "" scheduler = "" bankwiseLogic = 0 - refMode = 1 + RefMode = 1 clk = 0 unitOfTime = "" dataRate = 0 @@ -53,7 +53,7 @@ class DramConfig(object): self.unitOfTime = clkWithUnit[1].lower() self.bankwiseLogic = 0 - self.refMode = 0 + self.RefMode = 0 self.scheduler = mcconfig.getValue("Scheduler") self.numberOfBanks = memspec.getIntValue("memarchitecturespec","nbrOfBanks") @@ -112,10 +112,10 @@ class DramConfig(object): self.tXS = self.clk * memspec.getIntValue("memtimingspec","XS") self.tXSDLL = self.clk * memspec.getIntValue("memtimingspec","XSDLL") self.tAL = self.clk * memspec.getIntValue("memtimingspec","AL") - if (self.refMode == "4"): + if (self.RefMode == "4"): self.tRFC = self.clk * memspec.getIntValue("memtimingspec","RFC4") self.tREFI = self.clk * (memspec.getIntValue("memtimingspec","REFI") / 4) - elif (self.refMode == "2"): + elif (self.RefMode == "2"): self.tRFC = self.clk * memspec.getIntValue("memtimingspec","RFC2") self.tREFI = self.clk * (memspec.getIntValue("memtimingspec","REFI") / 2) else: diff --git a/extensions/standards/DDR5/DRAMSys/configuration/memspec/MemSpecDDR5.cpp b/extensions/standards/DDR5/DRAMSys/configuration/memspec/MemSpecDDR5.cpp index eb729859..ce08b489 100644 --- a/extensions/standards/DDR5/DRAMSys/configuration/memspec/MemSpecDDR5.cpp +++ b/extensions/standards/DDR5/DRAMSys/configuration/memspec/MemSpecDDR5.cpp @@ -4,6 +4,7 @@ * Authors: * Lukas Steiner * Derek Christ + * Marco Mörz */ #include "MemSpecDDR5.h" @@ -18,81 +19,90 @@ using namespace tlm; namespace DRAMSys { -MemSpecDDR5::MemSpecDDR5(const Config::MemSpec& memSpec) : +MemSpecDDR5::MemSpecDDR5(const DRAMUtils::MemSpec::MemSpecDDR5& memSpec) : MemSpec(memSpec, - memSpec.memarchitecturespec.entries.at("nbrOfChannels"), - memSpec.memarchitecturespec.entries.at("nbrOfRanks"), - memSpec.memarchitecturespec.entries.at("nbrOfBanks"), - memSpec.memarchitecturespec.entries.at("nbrOfBankGroups"), - memSpec.memarchitecturespec.entries.at("nbrOfBanks") / - memSpec.memarchitecturespec.entries.at("nbrOfBankGroups"), - memSpec.memarchitecturespec.entries.at("nbrOfBanks") * - memSpec.memarchitecturespec.entries.at("nbrOfRanks"), - memSpec.memarchitecturespec.entries.at("nbrOfBankGroups") * - memSpec.memarchitecturespec.entries.at("nbrOfRanks"), - memSpec.memarchitecturespec.entries.at("nbrOfDevices")), - dimmRanksPerChannel(memSpec.memarchitecturespec.entries.at("nbrOfDIMMRanks")), - physicalRanksPerDimmRank(memSpec.memarchitecturespec.entries.at("nbrOfPhysicalRanks")), + memSpec.memarchitecturespec.nbrOfChannels, + memSpec.memarchitecturespec.nbrOfRanks, + memSpec.memarchitecturespec.nbrOfBanks, + memSpec.memarchitecturespec.nbrOfBankGroups, + memSpec.memarchitecturespec.nbrOfBanks / + memSpec.memarchitecturespec.nbrOfBankGroups, + memSpec.memarchitecturespec.nbrOfBanks * + memSpec.memarchitecturespec.nbrOfRanks, + memSpec.memarchitecturespec.nbrOfBankGroups * + memSpec.memarchitecturespec.nbrOfRanks, + memSpec.memarchitecturespec.nbrOfDevices), + memSpec(memSpec), + dimmRanksPerChannel(memSpec.memarchitecturespec.nbrOfDIMMRanks), + physicalRanksPerDimmRank(memSpec.memarchitecturespec.nbrOfPhysicalRanks), physicalRanksPerChannel(physicalRanksPerDimmRank * dimmRanksPerChannel), - logicalRanksPerPhysicalRank(memSpec.memarchitecturespec.entries.at("nbrOfLogicalRanks")), + logicalRanksPerPhysicalRank(memSpec.memarchitecturespec.nbrOfLogicalRanks), logicalRanksPerChannel(logicalRanksPerPhysicalRank * physicalRanksPerChannel), - cmdMode(memSpec.memarchitecturespec.entries.at("cmdMode")), - refMode(memSpec.memarchitecturespec.entries.at("refMode")), - RAAIMT(memSpec.memarchitecturespec.entries.at("RAAIMT")), - RAAMMT(memSpec.memarchitecturespec.entries.at("RAAMMT")), - RAADEC(memSpec.memarchitecturespec.entries.at("RAADEC")), - tRCD(tCK * memSpec.memtimingspec.entries.at("RCD")), - tPPD(tCK * memSpec.memtimingspec.entries.at("PPD")), - tRP(tCK * memSpec.memtimingspec.entries.at("RP")), - tRAS(tCK * memSpec.memtimingspec.entries.at("RAS")), + cmdMode(memSpec.memarchitecturespec.cmdMode), + RefMode(memSpec.memarchitecturespec.RefMode), + RAAIMT(memSpec.memarchitecturespec.RAAIMT), + RAAMMT(memSpec.memarchitecturespec.RAAMMT), + RAADEC(memSpec.memarchitecturespec.RAADEC), + tRCD(tCK * memSpec.memtimingspec.RCD), + tPPD(tCK * memSpec.memtimingspec.PPD), + tRP(tCK * memSpec.memtimingspec.RP), + tRAS(tCK * memSpec.memtimingspec.RAS), tRC(tRAS + tRP), - tRL(tCK * memSpec.memtimingspec.entries.at("RL")), - tRTP(tCK * memSpec.memtimingspec.entries.at("RTP")), - tRPRE(tCK * memSpec.memtimingspec.entries.at("RPRE")), - tRPST(tCK * memSpec.memtimingspec.entries.at("RPST")), - tRDDQS(tCK * memSpec.memtimingspec.entries.at("RDDQS")), - tWL(tCK * memSpec.memtimingspec.entries.at("WL")), - tWPRE(tCK * memSpec.memtimingspec.entries.at("WPRE")), - tWPST(tCK * memSpec.memtimingspec.entries.at("WPST")), - tWR(tCK * memSpec.memtimingspec.entries.at("WR")), - tCCD_L_slr(tCK * memSpec.memtimingspec.entries.at("CCD_L_slr")), - tCCD_L_WR_slr(tCK * memSpec.memtimingspec.entries.at("CCD_L_WR_slr")), - tCCD_L_WR2_slr(tCK * memSpec.memtimingspec.entries.at("CCD_L_WR2_slr")), - tCCD_M_slr(tCK * memSpec.memtimingspec.entries.at("CCD_M_slr")), - tCCD_M_WR_slr(tCK * memSpec.memtimingspec.entries.at("CCD_M_WR_slr")), - tCCD_S_slr(tCK * memSpec.memtimingspec.entries.at("CCD_S_slr")), - tCCD_S_WR_slr(tCK * memSpec.memtimingspec.entries.at("CCD_S_WR_slr")), - tCCD_dlr(tCK * memSpec.memtimingspec.entries.at("CCD_dlr")), - tCCD_WR_dlr(tCK * memSpec.memtimingspec.entries.at("CCD_WR_dlr")), - tCCD_WR_dpr(tCK * memSpec.memtimingspec.entries.at("CCD_WR_dpr")), - tRRD_L_slr(tCK * memSpec.memtimingspec.entries.at("RRD_L_slr")), - tRRD_S_slr(tCK * memSpec.memtimingspec.entries.at("RRD_S_slr")), - tRRD_dlr(tCK * memSpec.memtimingspec.entries.at("RRD_dlr")), - tFAW_slr(tCK * memSpec.memtimingspec.entries.at("FAW_slr")), - tFAW_dlr(tCK * memSpec.memtimingspec.entries.at("FAW_dlr")), - tWTR_L(tCK * memSpec.memtimingspec.entries.at("WTR_L")), - tWTR_M(tCK * memSpec.memtimingspec.entries.at("WTR_M")), - tWTR_S(tCK * memSpec.memtimingspec.entries.at("WTR_S")), - tRFC_slr((refMode == 1) ? tCK * memSpec.memtimingspec.entries.at("RFC1_slr") - : tCK * memSpec.memtimingspec.entries.at("RFC2_slr")), - tRFC_dlr((refMode == 1) ? tCK * memSpec.memtimingspec.entries.at("RFC1_dlr") - : tCK * memSpec.memtimingspec.entries.at("RFC2_dlr")), - tRFC_dpr((refMode == 1) ? tCK * memSpec.memtimingspec.entries.at("RFC1_dpr") - : tCK * memSpec.memtimingspec.entries.at("RFC2_dpr")), - tRFCsb_slr(tCK * memSpec.memtimingspec.entries.at("RFCsb_slr")), - tRFCsb_dlr(tCK * memSpec.memtimingspec.entries.at("RFCsb_dlr")), - tREFI((refMode == 1) ? tCK * memSpec.memtimingspec.entries.at("REFI1") - : tCK * memSpec.memtimingspec.entries.at("REFI2")), - tREFIsb(tCK * memSpec.memtimingspec.entries.at("REFISB")), - tREFSBRD_slr(tCK * memSpec.memtimingspec.entries.at("REFSBRD_slr")), - tREFSBRD_dlr(tCK * memSpec.memtimingspec.entries.at("REFSBRD_dlr")), - tRTRS(tCK * memSpec.memtimingspec.entries.at("RTRS")), - tCPDED(tCK * memSpec.memtimingspec.entries.at("CPDED")), - tPD(tCK * memSpec.memtimingspec.entries.at("PD")), - tXP(tCK * memSpec.memtimingspec.entries.at("XP")), - tACTPDEN(tCK * memSpec.memtimingspec.entries.at("ACTPDEN")), - tPRPDEN(tCK * memSpec.memtimingspec.entries.at("PRPDEN")), - tREFPDEN(tCK * memSpec.memtimingspec.entries.at("REFPDEN")), + tRL(tCK * memSpec.memtimingspec.RL), + tRTP(tCK * memSpec.memtimingspec.RTP), + tRPRE(tCK * memSpec.memtimingspec.RPRE), + tRPST(tCK * memSpec.memtimingspec.RPST), + tRDDQS(tCK * memSpec.memtimingspec.RDDQS), + tWL(tCK * memSpec.memtimingspec.WL), + tWPRE(tCK * memSpec.memtimingspec.WPRE), + tWPST(tCK * memSpec.memtimingspec.WPST), + tWR(tCK * memSpec.memtimingspec.WR), + tCCD_L_slr(tCK * memSpec.memtimingspec.CCD_L_slr), + tCCD_L_WR_slr(tCK * memSpec.memtimingspec.CCD_L_WR_slr), + tCCD_L_WR2_slr(tCK * memSpec.memtimingspec.CCD_L_WR2_slr), + tCCD_M_slr(tCK * memSpec.memtimingspec.CCD_M_slr), + tCCD_M_WR_slr(tCK * memSpec.memtimingspec.CCD_M_WR_slr), + tCCD_S_slr(tCK * memSpec.memtimingspec.CCD_S_slr), + tCCD_S_WR_slr(tCK * memSpec.memtimingspec.CCD_S_WR_slr), + tCCD_dlr(tCK * memSpec.memtimingspec.CCD_dlr), + tCCD_WR_dlr(tCK * memSpec.memtimingspec.CCD_WR_dlr), + tCCD_WR_dpr(tCK * memSpec.memtimingspec.CCD_WR_dpr), + tRRD_L_slr(tCK * memSpec.memtimingspec.RRD_L_slr), + tRRD_S_slr(tCK * memSpec.memtimingspec.RRD_S_slr), + tRRD_dlr(tCK * memSpec.memtimingspec.RRD_dlr), + tFAW_slr(tCK * memSpec.memtimingspec.FAW_slr), + tFAW_dlr(tCK * memSpec.memtimingspec.FAW_dlr), + tWTR_L(tCK * memSpec.memtimingspec.WTR_L), + tWTR_M(tCK * memSpec.memtimingspec.WTR_M), + tWTR_S(tCK * memSpec.memtimingspec.WTR_S), + tRFC_slr((RefMode == DRAMUtils::MemSpec::RefModeTypeDDR5::REF_MODE_2) ? + tCK * memSpec.memtimingspec.RFC2_slr + // DRAMUtils::MemSpec::RefModeTypeDDR5::REF_MODE_1 || DRAMUtils::MemSpec::RefModeTypeDDR5::INVALID + : tCK * memSpec.memtimingspec.RFC1_slr), + tRFC_dlr((RefMode == DRAMUtils::MemSpec::RefModeTypeDDR5::REF_MODE_2) ? + tCK * memSpec.memtimingspec.RFC2_dlr + // DRAMUtils::MemSpec::RefModeTypeDDR5::REF_MODE_1 || DRAMUtils::MemSpec::RefModeTypeDDR5::INVALID + : tCK * memSpec.memtimingspec.RFC1_dlr), + tRFC_dpr((RefMode == DRAMUtils::MemSpec::RefModeTypeDDR5::REF_MODE_2) ? + tCK * memSpec.memtimingspec.RFC2_dpr + // DRAMUtils::MemSpec::RefModeTypeDDR5::REF_MODE_1 || DRAMUtils::MemSpec::RefModeTypeDDR5::INVALID + : tCK * memSpec.memtimingspec.RFC1_dpr), + tRFCsb_slr(tCK * memSpec.memtimingspec.RFCsb_slr), + tRFCsb_dlr(tCK * memSpec.memtimingspec.RFCsb_dlr), + tREFI((RefMode == DRAMUtils::MemSpec::RefModeTypeDDR5::REF_MODE_2) ? + tCK * memSpec.memtimingspec.REFI2 + // DRAMUtils::MemSpec::RefModeTypeDDR5::REF_MODE_1 || DRAMUtils::MemSpec::RefModeTypeDDR5::INVALID + : tCK * memSpec.memtimingspec.REFI1), + tREFIsb(tCK * memSpec.memtimingspec.REFISB), + tREFSBRD_slr(tCK * memSpec.memtimingspec.REFSBRD_slr), + tREFSBRD_dlr(tCK * memSpec.memtimingspec.REFSBRD_dlr), + tRTRS(tCK * memSpec.memtimingspec.RTRS), + tCPDED(tCK * memSpec.memtimingspec.CPDED), + tPD(tCK * memSpec.memtimingspec.PD), + tXP(tCK * memSpec.memtimingspec.XP), + tACTPDEN(tCK * memSpec.memtimingspec.ACTPDEN), + tPRPDEN(tCK * memSpec.memtimingspec.PRPDEN), + tREFPDEN(tCK * memSpec.memtimingspec.REFPDEN), shortCmdOffset(cmdMode == 2 ? 1 * tCK : 0 * tCK), longCmdOffset(cmdMode == 2 ? 3 * tCK : 1 * tCK), tBURST16(tCK * 8), @@ -134,7 +144,7 @@ MemSpecDDR5::MemSpecDDR5(const Config::MemSpec& memSpec) : else SC_REPORT_FATAL("MemSpecDDR5", "Invalid command mode!"); - if (!(refMode == 1 || refMode == 2)) + if (DRAMUtils::MemSpec::RefModeTypeDDR5::INVALID == RefMode) SC_REPORT_FATAL("MemSpecDDR5", "Invalid refresh mode! " "Set 1 for normal or 2 for fine granularity refresh mode."); @@ -268,4 +278,11 @@ bool MemSpecDDR5::requiresMaskedWrite(const tlm::tlm_generic_payload& payload) c return !allBytesEnabled(payload); } +#ifdef DRAMPOWER +std::unique_ptr> MemSpecDDR5::toDramPowerObject() const +{ + return std::make_unique(std::move(DRAMPower::MemSpecDDR5(memSpec))); +} +#endif + } // namespace DRAMSys diff --git a/extensions/standards/DDR5/DRAMSys/configuration/memspec/MemSpecDDR5.h b/extensions/standards/DDR5/DRAMSys/configuration/memspec/MemSpecDDR5.h index 4720a06c..7a719985 100644 --- a/extensions/standards/DDR5/DRAMSys/configuration/memspec/MemSpecDDR5.h +++ b/extensions/standards/DDR5/DRAMSys/configuration/memspec/MemSpecDDR5.h @@ -4,12 +4,21 @@ * Authors: * Lukas Steiner * Derek Christ + * Marco Mörz */ #ifndef MEMSPECDDR5_H #define MEMSPECDDR5_H #include + +#include + +#ifdef DRAMPOWER +#include +#include +#endif + #include namespace DRAMSys @@ -18,15 +27,16 @@ namespace DRAMSys class MemSpecDDR5 final : public MemSpec { public: - explicit MemSpecDDR5(const Config::MemSpec& memSpec); + explicit MemSpecDDR5(const DRAMUtils::MemSpec::MemSpecDDR5& memSpec); + const DRAMUtils::MemSpec::MemSpecDDR5& memSpec; const unsigned dimmRanksPerChannel; const unsigned physicalRanksPerDimmRank; const unsigned physicalRanksPerChannel; const unsigned logicalRanksPerPhysicalRank; const unsigned logicalRanksPerChannel; const unsigned cmdMode; - const unsigned refMode; + DRAMUtils::MemSpec::RefModeTypeDDR5 RefMode; const unsigned RAAIMT; const unsigned RAAMMT; const unsigned RAADEC; @@ -105,6 +115,11 @@ public: const tlm::tlm_generic_payload& payload) const override; [[nodiscard]] bool requiresMaskedWrite(const tlm::tlm_generic_payload& payload) const override; + +#ifdef DRAMPOWER + [[nodiscard]] std::unique_ptr> toDramPowerObject() const override; +#endif + }; } // namespace DRAMSys diff --git a/extensions/standards/HBM3/DRAMSys/configuration/memspec/MemSpecHBM3.cpp b/extensions/standards/HBM3/DRAMSys/configuration/memspec/MemSpecHBM3.cpp index ca8cbe42..7b697c9b 100644 --- a/extensions/standards/HBM3/DRAMSys/configuration/memspec/MemSpecHBM3.cpp +++ b/extensions/standards/HBM3/DRAMSys/configuration/memspec/MemSpecHBM3.cpp @@ -4,6 +4,7 @@ * Authors: * Lukas Steiner * Derek Christ + * Marco Mörz */ #include @@ -17,54 +18,53 @@ using namespace tlm; namespace DRAMSys { -MemSpecHBM3::MemSpecHBM3(const Config::MemSpec& memSpec) : +MemSpecHBM3::MemSpecHBM3(const DRAMUtils::MemSpec::MemSpecHBM3& memSpec) : MemSpec(memSpec, - memSpec.memarchitecturespec.entries.at("nbrOfChannels"), - memSpec.memarchitecturespec.entries.at("nbrOfPseudoChannels"), - memSpec.memarchitecturespec.entries.at("nbrOfBanks"), - memSpec.memarchitecturespec.entries.at("nbrOfBankGroups"), - memSpec.memarchitecturespec.entries.at("nbrOfBanks") / - memSpec.memarchitecturespec.entries.at("nbrOfBankGroups"), - memSpec.memarchitecturespec.entries.at("nbrOfBanks") * - memSpec.memarchitecturespec.entries.at("nbrOfPseudoChannels"), - memSpec.memarchitecturespec.entries.at("nbrOfBankGroups") * - memSpec.memarchitecturespec.entries.at("nbrOfPseudoChannels"), - memSpec.memarchitecturespec.entries.at("nbrOfDevices")), - stacksPerChannel(memSpec.memarchitecturespec.entries.at("nbrOfStacks")), - RAAIMT(memSpec.memarchitecturespec.entries.at("RAAIMT")), - RAAMMT(memSpec.memarchitecturespec.entries.at("RAAMMT")), - RAADEC(memSpec.memarchitecturespec.entries.at("RAADEC")), - tDQSCK(tCK * memSpec.memtimingspec.entries.at("DQSCK")), - tRC(tCK * memSpec.memtimingspec.entries.at("RC")), - tRAS(tCK * memSpec.memtimingspec.entries.at("RAS")), - tRCDRD(tCK * memSpec.memtimingspec.entries.at("RCDRD")), - tRCDWR(tCK * memSpec.memtimingspec.entries.at("RCDWR")), - tRRDL(tCK * memSpec.memtimingspec.entries.at("RRDL")), - tRRDS(tCK * memSpec.memtimingspec.entries.at("RRDS")), - tFAW(tCK * memSpec.memtimingspec.entries.at("FAW")), - tRTP(tCK * memSpec.memtimingspec.entries.at("RTP")), - tRP(tCK * memSpec.memtimingspec.entries.at("RP")), - tRL(tCK * memSpec.memtimingspec.entries.at("RL")), - tWL(tCK * memSpec.memtimingspec.entries.at("WL")), - tPL(tCK * memSpec.memtimingspec.entries.at("PL")), - tWR(tCK * memSpec.memtimingspec.entries.at("WR")), - tCCDL(tCK * memSpec.memtimingspec.entries.at("CCDL")), - tCCDS(tCK * memSpec.memtimingspec.entries.at("CCDS")), - tCCDR(tCK * memSpec.memtimingspec.entries.at("CCDR")), - tWTRL(tCK * memSpec.memtimingspec.entries.at("WTRL")), - tWTRS(tCK * memSpec.memtimingspec.entries.at("WTRS")), - tRTW(tCK * memSpec.memtimingspec.entries.at("RTW")), - tXP(tCK * memSpec.memtimingspec.entries.at("XP")), - tCKE(tCK * memSpec.memtimingspec.entries.at("CKE")), + memSpec.memarchitecturespec.nbrOfChannels, + memSpec.memarchitecturespec.nbrOfPseudoChannels, + memSpec.memarchitecturespec.nbrOfBanks, + memSpec.memarchitecturespec.nbrOfBankGroups, + memSpec.memarchitecturespec.nbrOfBanks / + memSpec.memarchitecturespec.nbrOfBankGroups, + memSpec.memarchitecturespec.nbrOfBanks * + memSpec.memarchitecturespec.nbrOfPseudoChannels, + memSpec.memarchitecturespec.nbrOfBankGroups * + memSpec.memarchitecturespec.nbrOfPseudoChannels, + memSpec.memarchitecturespec.nbrOfDevices), + stacksPerChannel(memSpec.memarchitecturespec.nbrOfStacks), + RAAIMT(memSpec.memarchitecturespec.RAAIMT), + RAAMMT(memSpec.memarchitecturespec.RAAMMT), + RAADEC(memSpec.memarchitecturespec.RAADEC), + tDQSCK(tCK * memSpec.memtimingspec.DQSCK), + tRC(tCK * memSpec.memtimingspec.RC), + tRAS(tCK * memSpec.memtimingspec.RAS), + tRCDRD(tCK * memSpec.memtimingspec.RCDRD), + tRCDWR(tCK * memSpec.memtimingspec.RCDWR), + tRRDL(tCK * memSpec.memtimingspec.RRDL), + tRRDS(tCK * memSpec.memtimingspec.RRDS), + tFAW(tCK * memSpec.memtimingspec.FAW), + tRTP(tCK * memSpec.memtimingspec.RTP), + tRP(tCK * memSpec.memtimingspec.RP), + tRL(tCK * memSpec.memtimingspec.RL), + tWL(tCK * memSpec.memtimingspec.WL), + tPL(tCK * memSpec.memtimingspec.PL), + tWR(tCK * memSpec.memtimingspec.WR), + tCCDL(tCK * memSpec.memtimingspec.CCDL), + tCCDS(tCK * memSpec.memtimingspec.CCDS), + tWTRL(tCK * memSpec.memtimingspec.WTRL), + tWTRS(tCK * memSpec.memtimingspec.WTRS), + tRTW(tCK * memSpec.memtimingspec.RTW), + tXP(tCK * memSpec.memtimingspec.XP), + tCKE(tCK * memSpec.memtimingspec.CKE), tPD(tCKE), tCKESR(tCKE + tCK), - tXS(tCK * memSpec.memtimingspec.entries.at("XS")), - tRFC(tCK * memSpec.memtimingspec.entries.at("RFC")), - tRFCPB(tCK * memSpec.memtimingspec.entries.at("RFCPB")), - tRREFD(tCK * memSpec.memtimingspec.entries.at("RREFD")), - tREFI(tCK * memSpec.memtimingspec.entries.at("REFI")), - tREFIPB(tCK * memSpec.memtimingspec.entries.at("REFIPB")), - tPPD(tCK * memSpec.memtimingspec.entries.at("PPD")) + tXS(tCK * memSpec.memtimingspec.XS), + tRFC(tCK * memSpec.memtimingspec.RFC), + tRFCPB(tCK * memSpec.memtimingspec.RFCPB), + tRREFD(tCK * memSpec.memtimingspec.RREFD), + tREFI(tCK * memSpec.memtimingspec.REFI), + tREFIPB(tCK * memSpec.memtimingspec.REFIPB), + tPPD(tCK * memSpec.memtimingspec.PPD) { commandLengthInCycles[Command::ACT] = 1.5; commandLengthInCycles[Command::PREPB] = 0.5; diff --git a/extensions/standards/HBM3/DRAMSys/configuration/memspec/MemSpecHBM3.h b/extensions/standards/HBM3/DRAMSys/configuration/memspec/MemSpecHBM3.h index 9ba4951a..6ff00fc0 100644 --- a/extensions/standards/HBM3/DRAMSys/configuration/memspec/MemSpecHBM3.h +++ b/extensions/standards/HBM3/DRAMSys/configuration/memspec/MemSpecHBM3.h @@ -4,12 +4,16 @@ * Authors: * Lukas Steiner * Derek Christ + * Marco Mörz */ #ifndef MemSpecHBM3_H #define MemSpecHBM3_H #include + +#include + #include namespace DRAMSys @@ -18,7 +22,7 @@ namespace DRAMSys class MemSpecHBM3 final : public MemSpec { public: - explicit MemSpecHBM3(const Config::MemSpec& memSpec); + explicit MemSpecHBM3(const DRAMUtils::MemSpec::MemSpecHBM3& memSpec); const unsigned stacksPerChannel; diff --git a/extensions/standards/LPDDR5/DRAMSys/configuration/memspec/MemSpecLPDDR5.cpp b/extensions/standards/LPDDR5/DRAMSys/configuration/memspec/MemSpecLPDDR5.cpp index 2c7d9398..8907af56 100644 --- a/extensions/standards/LPDDR5/DRAMSys/configuration/memspec/MemSpecLPDDR5.cpp +++ b/extensions/standards/LPDDR5/DRAMSys/configuration/memspec/MemSpecLPDDR5.cpp @@ -31,57 +31,55 @@ * * Authors: * Lukas Steiner + * Derek Christ + * Marco Mörz */ #include "MemSpecLPDDR5.h" #include -#include - using namespace sc_core; using namespace tlm; namespace DRAMSys { -MemSpecLPDDR5::MemSpecLPDDR5(const Config::MemSpec& memSpec) : +MemSpecLPDDR5::MemSpecLPDDR5(const DRAMUtils::MemSpec::MemSpecLPDDR5& memSpec) : MemSpec(memSpec, - memSpec.memarchitecturespec.entries.at("nbrOfChannels"), - memSpec.memarchitecturespec.entries.at("nbrOfRanks"), - memSpec.memarchitecturespec.entries.at("nbrOfBanks"), - memSpec.memarchitecturespec.entries.at("nbrOfBankGroups"), - memSpec.memarchitecturespec.entries.at("nbrOfBanks") / - memSpec.memarchitecturespec.entries.at("nbrOfBankGroups"), - memSpec.memarchitecturespec.entries.at("nbrOfBanks") * - memSpec.memarchitecturespec.entries.at("nbrOfRanks"), - memSpec.memarchitecturespec.entries.at("nbrOfBankGroups") * - memSpec.memarchitecturespec.entries.at("nbrOfRanks"), - memSpec.memarchitecturespec.entries.at("nbrOfDevices")), - tREFI(tCK * memSpec.memtimingspec.entries.at("REFI")), - tREFIpb(tCK * memSpec.memtimingspec.entries.at("REFIpb")), - tRFCab(tCK * memSpec.memtimingspec.entries.at("RFCab")), - tRFCpb(tCK * memSpec.memtimingspec.entries.at("RFCpb")), - tRAS(tCK * memSpec.memtimingspec.entries.at("RAS")), - tRPab(tCK * memSpec.memtimingspec.entries.at("RPab")), - tRPpb(tCK * memSpec.memtimingspec.entries.at("RPpb")), - tRCpb(tCK * memSpec.memtimingspec.entries.at("RCpb")), - tRCab(tCK * memSpec.memtimingspec.entries.at("RCab")), - tPPD(tCK * memSpec.memtimingspec.entries.at("PPD")), - tRCD_L(tCK * memSpec.memtimingspec.entries.at("RCD_L")), - tRCD_S(tCK * memSpec.memtimingspec.entries.at("RCD_S")), - tFAW(tCK * memSpec.memtimingspec.entries.at("FAW")), - tRRD(tCK * memSpec.memtimingspec.entries.at("RRD")), - tRL(tCK * memSpec.memtimingspec.entries.at("RL")), + memSpec.memarchitecturespec.nbrOfChannels, + memSpec.memarchitecturespec.nbrOfRanks, + memSpec.memarchitecturespec.nbrOfBanks, + memSpec.memarchitecturespec.nbrOfBankGroups, + memSpec.memarchitecturespec.nbrOfBanks / memSpec.memarchitecturespec.nbrOfBankGroups, + memSpec.memarchitecturespec.nbrOfBanks * memSpec.memarchitecturespec.nbrOfRanks, + memSpec.memarchitecturespec.nbrOfBankGroups * memSpec.memarchitecturespec.nbrOfRanks, + memSpec.memarchitecturespec.nbrOfDevices), + memSpec(memSpec), + tREFI(tCK * memSpec.memtimingspec.REFI), + tREFIpb(tCK * memSpec.memtimingspec.REFIpb), + tRFCab(tCK * memSpec.memtimingspec.RFCab), + tRFCpb(tCK * memSpec.memtimingspec.RFCpb), + tRAS(tCK * memSpec.memtimingspec.RAS), + tRPab(tCK * memSpec.memtimingspec.RPab), + tRPpb(tCK * memSpec.memtimingspec.RPpb), + tRCpb(tCK * memSpec.memtimingspec.RCpb), + tRCab(tCK * memSpec.memtimingspec.RCab), + tPPD(tCK * memSpec.memtimingspec.PPD), + tRCD_L(tCK * memSpec.memtimingspec.RCD_L), + tRCD_S(tCK * memSpec.memtimingspec.RCD_S), + tFAW(tCK * memSpec.memtimingspec.FAW), + tRRD(tCK * memSpec.memtimingspec.RRD), + tRL(tCK * memSpec.memtimingspec.RL), // tCCD (tCK * parseUint(memspec["memtimingspec"], "CCD")), - tRBTP(tCK * memSpec.memtimingspec.entries.at("RBTP")), + tRBTP(tCK * memSpec.memtimingspec.RBTP), // tRPST (tCK * parseUint(memspec["memtimingspec"], "RPST")), // tDQSCK (tCK * parseUint(memspec["memtimingspec"], "DQSCK")), - tWL(tCK * memSpec.memtimingspec.entries.at("WL")), - tWR(tCK * memSpec.memtimingspec.entries.at("WR")), + tWL(tCK * memSpec.memtimingspec.WL), + tWR(tCK * memSpec.memtimingspec.WR), // tDQSS (tCK * parseUint(memspec["memtimingspec"], "DQSS")), // tDQS2DQ (tCK * parseUint(memspec["memtimingspec"], "DQS2DQ")), - tRTRS(tCK * memSpec.memtimingspec.entries.at("RTRS")), + tRTRS(tCK * memSpec.memtimingspec.RTRS), // tWPRE (tCK * parseUint(memspec["memtimingspec"], "WPRE")), // tWTR (tCK * parseUint(memspec["memtimingspec"], "WTR")), // tXP (tCK * parseUint(memspec["memtimingspec"] "XP")), @@ -90,24 +88,24 @@ MemSpecLPDDR5::MemSpecLPDDR5(const Config::MemSpec& memSpec) : // tESCKE (tCK * parseUint(memspec["memtimingspec"], "ESCKE")), // tCKE (tCK * parseUint(memspec["memtimingspec"], "CKE")), // tCMDCKE (tCK * parseUint(memspec["memtimingspec"], "CMDCKE")), - BL_n_min_16(tCK * memSpec.memtimingspec.entries.at("BL_n_min_16")), - BL_n_max_16(tCK * memSpec.memtimingspec.entries.at("BL_n_max_16")), - BL_n_L_16(tCK * memSpec.memtimingspec.entries.at("BL_n_L_16")), - BL_n_S_16(tCK * memSpec.memtimingspec.entries.at("BL_n_S_16")), - BL_n_min_32(tCK * memSpec.memtimingspec.entries.at("BL_n_min_32")), - BL_n_max_32(tCK * memSpec.memtimingspec.entries.at("BL_n_max_32")), - BL_n_L_32(tCK * memSpec.memtimingspec.entries.at("BL_n_L_32")), - BL_n_S_32(tCK * memSpec.memtimingspec.entries.at("BL_n_S_32")), - tWTR_L(tCK * memSpec.memtimingspec.entries.at("WTR_L")), - tWTR_S(tCK * memSpec.memtimingspec.entries.at("WTR_S")), - tWCK2DQO(tCK * memSpec.memtimingspec.entries.at("WCK2DQO")), - tpbR2act(tCK * memSpec.memtimingspec.entries.at("pbR2act")), - tpbR2pbR(tCK * memSpec.memtimingspec.entries.at("pbR2pbR")), + BL_n_min_16(tCK * memSpec.memtimingspec.BL_n_min_16), + BL_n_max_16(tCK * memSpec.memtimingspec.BL_n_max_16), + BL_n_L_16(tCK * memSpec.memtimingspec.BL_n_L_16), + BL_n_S_16(tCK * memSpec.memtimingspec.BL_n_S_16), + BL_n_min_32(tCK * memSpec.memtimingspec.BL_n_min_32), + BL_n_max_32(tCK * memSpec.memtimingspec.BL_n_max_32), + BL_n_L_32(tCK * memSpec.memtimingspec.BL_n_L_32), + BL_n_S_32(tCK * memSpec.memtimingspec.BL_n_S_32), + tWTR_L(tCK * memSpec.memtimingspec.WTR_L), + tWTR_S(tCK * memSpec.memtimingspec.WTR_S), + tWCK2DQO(tCK * memSpec.memtimingspec.WCK2DQO), + tpbR2act(tCK * memSpec.memtimingspec.pbR2act), + tpbR2pbR(tCK * memSpec.memtimingspec.pbR2pbR), tBURST16(tCK * 16 / dataRate), tBURST32(tCK * 32 / dataRate), bankMode(groupsPerRank != 1 ? BankMode::MBG : (banksPerRank == 16 ? BankMode::M16B : BankMode::M8B)), - per2BankOffset(memSpec.memarchitecturespec.entries.at("per2BankOffset")) + per2BankOffset(memSpec.memarchitecturespec.per2BankOffset) { commandLengthInCycles[Command::ACT] = 2; @@ -257,4 +255,11 @@ bool MemSpecLPDDR5::requiresMaskedWrite(const tlm::tlm_generic_payload& payload) return !allBytesEnabled(payload); } +#ifdef DRAMPOWER +std::unique_ptr> MemSpecLPDDR5::toDramPowerObject() const +{ + return std::make_unique(std::move(DRAMPower::MemSpecLPDDR5(memSpec))); +} +#endif + } // namespace DRAMSys diff --git a/extensions/standards/LPDDR5/DRAMSys/configuration/memspec/MemSpecLPDDR5.h b/extensions/standards/LPDDR5/DRAMSys/configuration/memspec/MemSpecLPDDR5.h index a896ea85..0773fe29 100644 --- a/extensions/standards/LPDDR5/DRAMSys/configuration/memspec/MemSpecLPDDR5.h +++ b/extensions/standards/LPDDR5/DRAMSys/configuration/memspec/MemSpecLPDDR5.h @@ -31,12 +31,23 @@ * * Authors: * Lukas Steiner + * Derek Christ + * Marco Mörz */ #ifndef MEMSPECLPDDR5_H #define MEMSPECLPDDR5_H #include + +#include + + +#ifdef DRAMPOWER +#include +#include +#endif + #include namespace DRAMSys @@ -45,9 +56,10 @@ namespace DRAMSys class MemSpecLPDDR5 final : public MemSpec { public: - explicit MemSpecLPDDR5(const Config::MemSpec& memSpec); + explicit MemSpecLPDDR5(const DRAMUtils::MemSpec::MemSpecLPDDR5& memSpec); // Memspec Variables: + const DRAMUtils::MemSpec::MemSpecLPDDR5& memSpec; const sc_core::sc_time tREFI; const sc_core::sc_time tREFIpb; const sc_core::sc_time tRFCab; @@ -122,6 +134,11 @@ public: [[nodiscard]] bool requiresMaskedWrite(const tlm::tlm_generic_payload& payload) const override; +#ifdef DRAMPOWER + [[nodiscard]] std::unique_ptr> + toDramPowerObject() const override; +#endif + private: unsigned per2BankOffset; }; diff --git a/src/configuration/CMakeLists.txt b/src/configuration/CMakeLists.txt index 0f8135a8..5ea094a7 100644 --- a/src/configuration/CMakeLists.txt +++ b/src/configuration/CMakeLists.txt @@ -31,6 +31,7 @@ # Authors: # Derek Christ # Thomas Psota +# Marco Mörz ######################################## ### DRAMSys::config ### @@ -38,16 +39,13 @@ add_library(configuration DRAMSys/config/DRAMSysConfiguration.cpp - DRAMSys/config/memspec/MemArchitectureSpec.cpp - DRAMSys/config/memspec/MemPowerSpec.cpp - DRAMSys/config/memspec/MemTimingSpec.cpp ) target_include_directories(configuration PUBLIC ${CMAKE_CURRENT_SOURCE_DIR}) target_link_libraries(configuration PUBLIC - nlohmann_json::nlohmann_json + DRAMUtils::DRAMUtils ) target_compile_features(configuration PUBLIC cxx_std_17) diff --git a/src/configuration/DRAMSys/config/AddressMapping.h b/src/configuration/DRAMSys/config/AddressMapping.h index a2382088..95d27334 100644 --- a/src/configuration/DRAMSys/config/AddressMapping.h +++ b/src/configuration/DRAMSys/config/AddressMapping.h @@ -36,7 +36,7 @@ #ifndef DRAMSYSCONFIGURATION_ADDRESSMAPPING_H #define DRAMSYSCONFIGURATION_ADDRESSMAPPING_H -#include "DRAMSys/util/json.h" +#include #include diff --git a/src/configuration/DRAMSys/config/DRAMSysConfiguration.cpp b/src/configuration/DRAMSys/config/DRAMSysConfiguration.cpp index 542ac11b..d2658f7b 100644 --- a/src/configuration/DRAMSys/config/DRAMSysConfiguration.cpp +++ b/src/configuration/DRAMSys/config/DRAMSysConfiguration.cpp @@ -35,6 +35,8 @@ #include "DRAMSysConfiguration.h" +#include "DRAMSys/config/MemSpec.h" + #include namespace DRAMSys::Config @@ -71,7 +73,7 @@ Configuration from_path(std::filesystem::path baseConfig) { assert(parsed.is_string()); - if (parsed == MemSpec::KEY) + if (parsed == MemSpecConstants::KEY) current_sub_config = SubConfig::MemSpec; else if (parsed == AddressMapping::KEY) current_sub_config = SubConfig::AddressMapping; @@ -107,7 +109,7 @@ Configuration from_path(std::filesystem::path baseConfig) }; if (current_sub_config == SubConfig::MemSpec) - parsed = parse_json(MemSpec::KEY, parsed); + parsed = parse_json(MemSpecConstants::KEY, parsed); else if (current_sub_config == SubConfig::AddressMapping) parsed = parse_json(AddressMapping::KEY, parsed); else if (current_sub_config == SubConfig::McConfig) diff --git a/src/configuration/DRAMSys/config/DRAMSysConfiguration.h b/src/configuration/DRAMSys/config/DRAMSysConfiguration.h index c66311fb..80b2d489 100644 --- a/src/configuration/DRAMSys/config/DRAMSysConfiguration.h +++ b/src/configuration/DRAMSys/config/DRAMSysConfiguration.h @@ -40,7 +40,9 @@ #include "DRAMSys/config/McConfig.h" #include "DRAMSys/config/SimConfig.h" #include "DRAMSys/config/TraceSetup.h" -#include "DRAMSys/config/memspec/MemSpec.h" + +#include +#include #include #include @@ -66,7 +68,7 @@ struct Configuration AddressMapping addressmapping; McConfig mcconfig; - MemSpec memspec; + DRAMUtils::MemSpec::MemSpecVariant memspec; SimConfig simconfig; std::string simulationid; std::optional> tracesetup; diff --git a/src/configuration/DRAMSys/config/McConfig.h b/src/configuration/DRAMSys/config/McConfig.h index bcd64363..729e9cf1 100644 --- a/src/configuration/DRAMSys/config/McConfig.h +++ b/src/configuration/DRAMSys/config/McConfig.h @@ -36,7 +36,7 @@ #ifndef DRAMSYSCONFIGURATION_MCCONFIG_H #define DRAMSYSCONFIGURATION_MCCONFIG_H -#include "DRAMSys/util/json.h" +#include #include diff --git a/src/configuration/DRAMSys/config/memspec/MemPowerSpec.cpp b/src/configuration/DRAMSys/config/MemSpec.h similarity index 83% rename from src/configuration/DRAMSys/config/memspec/MemPowerSpec.cpp rename to src/configuration/DRAMSys/config/MemSpec.h index 3d4049a5..c882bc06 100644 --- a/src/configuration/DRAMSys/config/memspec/MemPowerSpec.cpp +++ b/src/configuration/DRAMSys/config/MemSpec.h @@ -33,27 +33,20 @@ * Derek Christ */ -#include "MemPowerSpec.h" +#ifndef DRAMSYSCONFIGURATION_MEMSPEC_H +#define DRAMSYSCONFIGURATION_MEMSPEC_H + +#include namespace DRAMSys::Config { -void to_json(json_t& j, const MemPowerSpec& c) +struct MemSpecConstants { - j = json_t{}; - - for (const auto& entry : c.entries) - { - j[entry.first] = entry.second; - } -} - -void from_json(const json_t& j, MemPowerSpec& c) -{ - for (const auto& entry : j.items()) - { - c.entries[entry.key()] = entry.value(); - } -} + static constexpr std::string_view KEY = "memspec"; + static constexpr std::string_view SUB_DIR = "memspec"; +}; } // namespace DRAMSys::Config + +#endif // DRAMSYSCONFIGURATION_MEMSPEC_H diff --git a/src/configuration/DRAMSys/config/SimConfig.h b/src/configuration/DRAMSys/config/SimConfig.h index a83d1b8d..e37fbb4e 100644 --- a/src/configuration/DRAMSys/config/SimConfig.h +++ b/src/configuration/DRAMSys/config/SimConfig.h @@ -36,7 +36,8 @@ #ifndef DRAMSYSCONFIGURATION_SIMCONFIG_H #define DRAMSYSCONFIGURATION_SIMCONFIG_H -#include "DRAMSys/util/json.h" +#include +#include #include @@ -72,6 +73,7 @@ struct SimConfig std::optional UseMalloc; std::optional WindowSize; std::optional SimulationTime; + std::optional TogglingRate; }; NLOHMANN_JSONIFY_ALL_THINGS(SimConfig, @@ -87,7 +89,8 @@ NLOHMANN_JSONIFY_ALL_THINGS(SimConfig, ThermalSimulation, UseMalloc, WindowSize, - SimulationTime) + SimulationTime, + TogglingRate) } // namespace DRAMSys::Config diff --git a/src/configuration/DRAMSys/config/TraceSetup.h b/src/configuration/DRAMSys/config/TraceSetup.h index c93f679a..1b7581c8 100644 --- a/src/configuration/DRAMSys/config/TraceSetup.h +++ b/src/configuration/DRAMSys/config/TraceSetup.h @@ -36,7 +36,7 @@ #ifndef DRAMSYSCONFIGURATION_TRACESETUP_H #define DRAMSYSCONFIGURATION_TRACESETUP_H -#include "DRAMSys/util/json.h" +#include #include #include diff --git a/src/configuration/DRAMSys/config/memspec/MemArchitectureSpec.cpp b/src/configuration/DRAMSys/config/memspec/MemArchitectureSpec.cpp deleted file mode 100644 index 72206564..00000000 --- a/src/configuration/DRAMSys/config/memspec/MemArchitectureSpec.cpp +++ /dev/null @@ -1,59 +0,0 @@ -/* - * Copyright (c) 2021, RPTU Kaiserslautern-Landau - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER - * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: - * Derek Christ - */ - -#include "MemArchitectureSpec.h" - -namespace DRAMSys::Config -{ - -void to_json(json_t& j, const MemArchitectureSpecType& c) -{ - j = json_t{}; - - for (const auto& entry : c.entries) - { - j[entry.first] = entry.second; - } -} - -void from_json(const json_t& j, MemArchitectureSpecType& c) -{ - for (const auto& entry : j.items()) - { - c.entries[entry.key()] = entry.value(); - } -} - -} // namespace DRAMSys::Config diff --git a/src/configuration/DRAMSys/config/memspec/MemArchitectureSpec.h b/src/configuration/DRAMSys/config/memspec/MemArchitectureSpec.h deleted file mode 100644 index cd83f48d..00000000 --- a/src/configuration/DRAMSys/config/memspec/MemArchitectureSpec.h +++ /dev/null @@ -1,56 +0,0 @@ -/* - * Copyright (c) 2021, RPTU Kaiserslautern-Landau - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER - * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: - * Derek Christ - */ - -#ifndef DRAMSYSCONFIGURATION_MEMARCHITECTURESPEC_H -#define DRAMSYSCONFIGURATION_MEMARCHITECTURESPEC_H - -#include "DRAMSys/util/json.h" - -#include - -namespace DRAMSys::Config -{ - -struct MemArchitectureSpecType -{ - std::unordered_map entries; -}; - -void to_json(json_t& j, const MemArchitectureSpecType& c); -void from_json(const json_t& j, MemArchitectureSpecType& c); - -} // namespace DRAMSys::Config - -#endif // DRAMSYSCONFIGURATION_MEMARCHITECTURESPEC_H diff --git a/src/configuration/DRAMSys/config/memspec/MemPowerSpec.h b/src/configuration/DRAMSys/config/memspec/MemPowerSpec.h deleted file mode 100644 index 3c7d9f6e..00000000 --- a/src/configuration/DRAMSys/config/memspec/MemPowerSpec.h +++ /dev/null @@ -1,56 +0,0 @@ -/* - * Copyright (c) 2021, RPTU Kaiserslautern-Landau - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER - * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: - * Derek Christ - */ - -#ifndef DRAMSYSCONFIGURATION_MEMPOWERSPEC_H -#define DRAMSYSCONFIGURATION_MEMPOWERSPEC_H - -#include "DRAMSys/util/json.h" - -#include - -namespace DRAMSys::Config -{ - -struct MemPowerSpec -{ - std::unordered_map entries; -}; - -void to_json(json_t& j, const MemPowerSpec& c); -void from_json(const json_t& j, MemPowerSpec& c); - -} // namespace DRAMSys::Config - -#endif // DRAMSYSCONFIGURATION_MEMPOWERSPEC_H diff --git a/src/configuration/DRAMSys/config/memspec/MemSpec.h b/src/configuration/DRAMSys/config/memspec/MemSpec.h deleted file mode 100644 index d24bb890..00000000 --- a/src/configuration/DRAMSys/config/memspec/MemSpec.h +++ /dev/null @@ -1,99 +0,0 @@ -/* - * Copyright (c) 2021, RPTU Kaiserslautern-Landau - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER - * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: - * Derek Christ - */ - -#ifndef DRAMSYSCONFIGURATION_MEMSPEC_H -#define DRAMSYSCONFIGURATION_MEMSPEC_H - -#include "DRAMSys/config/memspec/MemArchitectureSpec.h" -#include "DRAMSys/config/memspec/MemPowerSpec.h" -#include "DRAMSys/config/memspec/MemTimingSpec.h" -#include "DRAMSys/util/json.h" - -#include - -namespace DRAMSys::Config -{ - -enum class MemoryType -{ - DDR3, - DDR4, - DDR5, - LPDDR4, - LPDDR5, - WideIO, - WideIO2, - GDDR5, - GDDR5X, - GDDR6, - HBM2, - HBM3, - STTMRAM, - Invalid = -1 -}; - -NLOHMANN_JSON_SERIALIZE_ENUM(MemoryType, - {{MemoryType::Invalid, nullptr}, - {MemoryType::DDR3, "DDR3"}, - {MemoryType::DDR4, "DDR4"}, - {MemoryType::DDR5, "DDR5"}, - {MemoryType::LPDDR4, "LPDDR4"}, - {MemoryType::LPDDR5, "LPDDR5"}, - {MemoryType::WideIO, "WIDEIO_SDR"}, - {MemoryType::WideIO2, "WIDEIO2"}, - {MemoryType::GDDR5, "GDDR5"}, - {MemoryType::GDDR5X, "GDDR5X"}, - {MemoryType::GDDR6, "GDDR6"}, - {MemoryType::HBM2, "HBM2"}, - {MemoryType::HBM3, "HBM3"}, - {MemoryType::STTMRAM, "STT-MRAM"}}) - -struct MemSpec -{ - static constexpr std::string_view KEY = "memspec"; - - MemArchitectureSpecType memarchitecturespec; - std::string memoryId; - MemoryType memoryType; - MemTimingSpecType memtimingspec; - std::optional mempowerspec; -}; - -NLOHMANN_JSONIFY_ALL_THINGS( - MemSpec, memarchitecturespec, memoryId, memoryType, memtimingspec, mempowerspec) - -} // namespace DRAMSys::Config - -#endif // DRAMSYSCONFIGURATION_MEMSPEC_H diff --git a/src/configuration/DRAMSys/config/memspec/MemTimingSpec.cpp b/src/configuration/DRAMSys/config/memspec/MemTimingSpec.cpp deleted file mode 100644 index c44f7cb5..00000000 --- a/src/configuration/DRAMSys/config/memspec/MemTimingSpec.cpp +++ /dev/null @@ -1,59 +0,0 @@ -/* - * Copyright (c) 2021, RPTU Kaiserslautern-Landau - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER - * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: - * Derek Christ - */ - -#include "MemTimingSpec.h" - -namespace DRAMSys::Config -{ - -void to_json(json_t& j, const MemTimingSpecType& c) -{ - j = json_t{}; - - for (const auto& entry : c.entries) - { - j[entry.first] = entry.second; - } -} - -void from_json(const json_t& j, MemTimingSpecType& c) -{ - for (const auto& entry : j.items()) - { - c.entries[entry.key()] = entry.value(); - } -} - -} // namespace DRAMSys::Config diff --git a/src/configuration/DRAMSys/config/memspec/MemTimingSpec.h b/src/configuration/DRAMSys/config/memspec/MemTimingSpec.h deleted file mode 100644 index 096fbd29..00000000 --- a/src/configuration/DRAMSys/config/memspec/MemTimingSpec.h +++ /dev/null @@ -1,57 +0,0 @@ -/* - * Copyright (c) 2021, RPTU Kaiserslautern-Landau - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER - * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: - * Derek Christ - */ - -#ifndef DRAMSYSCONFIGURATION_MEMTIMINGSPEC_H -#define DRAMSYSCONFIGURATION_MEMTIMINGSPEC_H - -#include "DRAMSys/util/json.h" - -#include - -namespace DRAMSys::Config -{ -using json = nlohmann::json; - -struct MemTimingSpecType -{ - std::unordered_map entries; -}; - -void to_json(json& j, const MemTimingSpecType& c); -void from_json(const json& j, MemTimingSpecType& c); - -} // namespace DRAMSys::Config - -#endif // DRAMSYSCONFIGURATION_MEMTIMINGSPEC_H diff --git a/src/configuration/DRAMSys/util/json.h b/src/configuration/DRAMSys/util/json.h deleted file mode 100644 index c15b74cd..00000000 --- a/src/configuration/DRAMSys/util/json.h +++ /dev/null @@ -1,166 +0,0 @@ -/* - * Copyright (c) 2021, RPTU Kaiserslautern-Landau - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER - * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: - * Thomas Psota - * Derek Christ - */ - -#ifndef DRAMSYSCONFIGURATION_JSON_H -#define DRAMSYSCONFIGURATION_JSON_H - -#include - -#include -#include - -using json_t = nlohmann::json; - -namespace DRAMSys::Config -{ -// See https://www.kdab.com/jsonify-with-nlohmann-json/ -// Try to set the value of type T into the variant data if it fails, do nothing -template -void variant_from_json(const nlohmann::json& j, std::variant& data) -{ - try - { - data = j.get(); - } - catch (...) - { - } -} - -template -void optional_to_json(nlohmann::json& j, std::string_view name, const std::optional& value) -{ - if (value) - j[name] = *value; -} - -template -void optional_from_json(const nlohmann::json& j, std::string_view name, std::optional& value) -{ - const auto it = j.find(name); - - if (it != j.end()) - value = it->get(); - else - value = std::nullopt; -} - -template constexpr bool is_optional = false; -template constexpr bool is_optional> = true; - -template void extended_to_json(const char* key, nlohmann::json& j, const T& value) -{ - if constexpr (is_optional) - optional_to_json(j, key, value); - else - j[key] = value; -} - -template void extended_from_json(const char* key, const nlohmann::json& j, T& value) -{ - if constexpr (is_optional) - optional_from_json(j, key, value); - else - j.at(key).get_to(value); -} - -} // namespace DRAMSys::Config - -NLOHMANN_JSON_NAMESPACE_BEGIN - -template struct adl_serializer> -{ - static void to_json(nlohmann::json& j, const std::variant& data) - { - std::visit([&j](const auto& v) { j = v; }, data); - } - - static void from_json(const nlohmann::json& j, std::variant& data) - { - // Call variant_from_json for all types, only one will succeed - (DRAMSys::Config::variant_from_json(j, data), ...); - } -}; - -template struct adl_serializer> -{ - static void to_json(json_t& j, const std::optional& opt) - { - if (opt == std::nullopt) - { - j = nullptr; - } - else - { - j = *opt; - } - } - - static void from_json(const json_t& j, std::optional& opt) - { - if (j.is_null()) - { - opt = std::nullopt; - } - else - { - opt = j.get(); - } - } -}; - -NLOHMANN_JSON_NAMESPACE_END - -// NOLINTBEGIN(cppcoreguidelines-macro-usage) - -#define EXTEND_JSON_TO(v1) \ - DRAMSys::Config::extended_to_json(#v1, nlohmann_json_j, nlohmann_json_t.v1); -#define EXTEND_JSON_FROM(v1) \ - DRAMSys::Config::extended_from_json(#v1, nlohmann_json_j, nlohmann_json_t.v1); - -#define NLOHMANN_JSONIFY_ALL_THINGS(Type, ...) \ - inline void to_json(nlohmann::json& nlohmann_json_j, const Type& nlohmann_json_t) \ - { \ - NLOHMANN_JSON_EXPAND(NLOHMANN_JSON_PASTE(EXTEND_JSON_TO, __VA_ARGS__)) \ - } \ - inline void from_json(const nlohmann::json& nlohmann_json_j, Type& nlohmann_json_t) \ - { \ - NLOHMANN_JSON_EXPAND(NLOHMANN_JSON_PASTE(EXTEND_JSON_FROM, __VA_ARGS__)) \ - } - -// NOLINTEND(cppcoreguidelines-macro-usage) - -#endif // DRAMSYSCONFIGURATION_JSON_H diff --git a/src/libdramsys/CMakeLists.txt b/src/libdramsys/CMakeLists.txt index a32772e6..f74ea34b 100644 --- a/src/libdramsys/CMakeLists.txt +++ b/src/libdramsys/CMakeLists.txt @@ -108,6 +108,7 @@ target_link_libraries(libdramsys PUBLIC SystemC::systemc DRAMSys::config + DRAMUtils::DRAMUtils $<$:DRAMPower::DRAMPower> PRIVATE SQLite::SQLite3 diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpec.cpp b/src/libdramsys/DRAMSys/configuration/memspec/MemSpec.cpp index bae38dc9..4e437f55 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpec.cpp +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpec.cpp @@ -32,6 +32,7 @@ * Authors: * Lukas Steiner * Derek Christ + * Marco Mörz */ #include "MemSpec.h" @@ -42,43 +43,6 @@ using namespace tlm; namespace DRAMSys { -MemSpec::MemSpec(const Config::MemSpec& memSpec, - unsigned numberOfChannels, - unsigned ranksPerChannel, - unsigned banksPerRank, - unsigned groupsPerRank, - unsigned banksPerGroup, - unsigned banksPerChannel, - unsigned bankGroupsPerChannel, - unsigned devicesPerRank) : - numberOfChannels(numberOfChannels), - ranksPerChannel(ranksPerChannel), - banksPerRank(banksPerRank), - groupsPerRank(groupsPerRank), - banksPerGroup(banksPerGroup), - banksPerChannel(banksPerChannel), - bankGroupsPerChannel(bankGroupsPerChannel), - devicesPerRank(devicesPerRank), - rowsPerBank(memSpec.memarchitecturespec.entries.at("nbrOfRows")), - columnsPerRow(memSpec.memarchitecturespec.entries.at("nbrOfColumns")), - defaultBurstLength(memSpec.memarchitecturespec.entries.at("burstLength")), - maxBurstLength(memSpec.memarchitecturespec.entries.find("maxBurstLength") != - memSpec.memarchitecturespec.entries.end() - ? memSpec.memarchitecturespec.entries.at("maxBurstLength") - : defaultBurstLength), - dataRate(memSpec.memarchitecturespec.entries.at("dataRate")), - bitWidth(memSpec.memarchitecturespec.entries.at("width")), - dataBusWidth(bitWidth * devicesPerRank), - defaultBytesPerBurst((defaultBurstLength * dataBusWidth) / 8), - maxBytesPerBurst((maxBurstLength * dataBusWidth) / 8), - tCK(sc_time(memSpec.memtimingspec.entries.at("tCK"), SC_PS)), - memoryId(memSpec.memoryId), - memoryType(memSpec.memoryType), - burstDuration(tCK * (static_cast(defaultBurstLength) / dataRate)) -{ - commandLengthInCycles = std::vector(Command::numberOfCommands(), 1); -} - sc_time MemSpec::getCommandLength(Command command) const { return tCK * commandLengthInCycles[command]; @@ -160,28 +124,4 @@ bool MemSpec::requiresMaskedWrite(const tlm::tlm_generic_payload& payload) const throw; } -bool MemSpec::allBytesEnabled(const tlm::tlm_generic_payload& trans) -{ - if (trans.get_byte_enable_ptr() == nullptr) - return true; - - for (std::size_t i = 0; i < trans.get_byte_enable_length(); i++) - { - if (trans.get_byte_enable_ptr()[i] != TLM_BYTE_ENABLED) - { - return false; - } - } - - return true; -} - -#ifdef DRAMPOWER -DRAMPower::MemorySpecification MemSpec::toDramPowerMemSpec() const -{ - SC_REPORT_FATAL("MemSpec", "DRAMPower does not support this memory standard"); - return {}; -} -#endif - } // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpec.h b/src/libdramsys/DRAMSys/configuration/memspec/MemSpec.h index e7be3742..d307d0ef 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpec.h +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpec.h @@ -34,23 +34,24 @@ * Matthias Jung * Lukas Steiner * Derek Christ + * Marco Mörz */ #ifndef MEMSPEC_H #define MEMSPEC_H #include "DRAMSys/common/utils.h" -#include "DRAMSys/config/DRAMSysConfiguration.h" -#include "DRAMSys/config/memspec/MemSpec.h" #include "DRAMSys/controller/Command.h" #include #include #include #include +#include #ifdef DRAMPOWER -#include +#include +#include #endif namespace DRAMSys @@ -63,29 +64,32 @@ public: MemSpec& operator=(MemSpec&&) = delete; virtual ~MemSpec() = default; - const unsigned numberOfChannels; - const unsigned ranksPerChannel; - const unsigned banksPerRank; - const unsigned groupsPerRank; - const unsigned banksPerGroup; - const unsigned banksPerChannel; - const unsigned bankGroupsPerChannel; - const unsigned devicesPerRank; - const unsigned rowsPerBank; - const unsigned columnsPerRow; - const unsigned defaultBurstLength; - const unsigned maxBurstLength; - const unsigned dataRate; - const unsigned bitWidth; - const unsigned dataBusWidth; - const unsigned defaultBytesPerBurst; - const unsigned maxBytesPerBurst; + static constexpr enum sc_core::sc_time_unit TCK_UNIT + = sc_core::SC_SEC; + + const uint64_t numberOfChannels; + const uint64_t ranksPerChannel; + const uint64_t banksPerRank; + const uint64_t groupsPerRank; + const uint64_t banksPerGroup; + const uint64_t banksPerChannel; + const uint64_t bankGroupsPerChannel; + const uint64_t devicesPerRank; + const uint64_t rowsPerBank; + const uint64_t columnsPerRow; + const uint64_t defaultBurstLength; + const uint64_t maxBurstLength; + const uint64_t dataRate; + const uint64_t bitWidth; + const uint64_t dataBusWidth; + const uint64_t defaultBytesPerBurst; + const uint64_t maxBytesPerBurst; // Clock const sc_core::sc_time tCK; const std::string memoryId; - const Config::MemoryType memoryType; + const std::string memoryType; [[nodiscard]] virtual sc_core::sc_time getRefreshIntervalAB() const; [[nodiscard]] virtual sc_core::sc_time getRefreshIntervalPB() const; @@ -112,21 +116,74 @@ public: [[nodiscard]] uint64_t getSimMemSizeInBytes() const; #ifdef DRAMPOWER - [[nodiscard]] virtual DRAMPower::MemorySpecification toDramPowerMemSpec() const; + /** + * @brief Creates the DRAMPower object if the standard is supported by DRAMPower. + * If the standard is not supported, a fatal error is reported and the simulation is aborted. + * @return unique_ptr to the DRAMPower object. + */ + [[nodiscard]] virtual std::unique_ptr> toDramPowerObject() const + { + SC_REPORT_FATAL("MemSpec", "DRAMPower does not support this memory standard"); + sc_core::sc_abort(); + // This line is never reached, but it is needed to avoid a compiler warning + return nullptr; + } #endif protected: - MemSpec(const Config::MemSpec& memSpec, - unsigned numberOfChannels, - unsigned ranksPerChannel, - unsigned banksPerRank, - unsigned groupsPerRank, - unsigned banksPerGroup, - unsigned banksPerChannel, - unsigned bankGroupsPerChannel, - unsigned devicesPerRank); + [[nodiscard]] static bool allBytesEnabled(const tlm::tlm_generic_payload& trans) + { + if (trans.get_byte_enable_ptr() == nullptr) + return true; - [[nodiscard]] static bool allBytesEnabled(const tlm::tlm_generic_payload& trans); + for (std::size_t i = 0; i < trans.get_byte_enable_length(); i++) + { + if (trans.get_byte_enable_ptr()[i] != TLM_BYTE_ENABLED) + { + return false; + } + } + + return true; + } + + template + MemSpec(const MemSpecType& memSpec, + uint64_t numberOfChannels, + uint64_t ranksPerChannel, + uint64_t banksPerRank, + uint64_t groupsPerRank, + uint64_t banksPerGroup, + uint64_t banksPerChannel, + uint64_t bankGroupsPerChannel, + uint64_t devicesPerRank) : + numberOfChannels(numberOfChannels), + ranksPerChannel(ranksPerChannel), + banksPerRank(banksPerRank), + groupsPerRank(groupsPerRank), + banksPerGroup(banksPerGroup), + banksPerChannel(banksPerChannel), + bankGroupsPerChannel(bankGroupsPerChannel), + devicesPerRank(devicesPerRank), + rowsPerBank(memSpec.memarchitecturespec.nbrOfRows), + columnsPerRow(memSpec.memarchitecturespec.nbrOfColumns), + defaultBurstLength(memSpec.memarchitecturespec.burstLength), + maxBurstLength(memSpec.memarchitecturespec.maxBurstLength.has_value() + ? memSpec.memarchitecturespec.maxBurstLength.value() + : defaultBurstLength), + dataRate(memSpec.memarchitecturespec.dataRate), + bitWidth(memSpec.memarchitecturespec.width), + dataBusWidth(bitWidth * devicesPerRank), + defaultBytesPerBurst((defaultBurstLength * dataBusWidth) / 8), + maxBytesPerBurst((maxBurstLength * dataBusWidth) / 8), + tCK(sc_core::sc_time(memSpec.memtimingspec.tCK, TCK_UNIT)), + memoryId(memSpec.memoryId), + memoryType(memSpec.id), + burstDuration(tCK * (static_cast(defaultBurstLength) / dataRate)) + + { + commandLengthInCycles = std::vector(Command::numberOfCommands(), 1); + } MemSpec(const MemSpec&) = default; MemSpec(MemSpec&&) = default; diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR3.cpp b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR3.cpp index d7664baa..9268ae55 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR3.cpp +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR3.cpp @@ -32,6 +32,7 @@ * Authors: * Lukas Steiner * Derek Christ + * Marco Mörz */ #include "MemSpecDDR3.h" @@ -46,68 +47,50 @@ using namespace tlm; namespace DRAMSys { -MemSpecDDR3::MemSpecDDR3(const Config::MemSpec& memSpec) : +MemSpecDDR3::MemSpecDDR3(const DRAMUtils::MemSpec::MemSpecDDR3& memSpec) : MemSpec(memSpec, - memSpec.memarchitecturespec.entries.at("nbrOfChannels"), - memSpec.memarchitecturespec.entries.at("nbrOfRanks"), - memSpec.memarchitecturespec.entries.at("nbrOfBanks"), + memSpec.memarchitecturespec.nbrOfChannels, + memSpec.memarchitecturespec.nbrOfRanks, + memSpec.memarchitecturespec.nbrOfBanks, 1, - memSpec.memarchitecturespec.entries.at("nbrOfBanks"), - memSpec.memarchitecturespec.entries.at("nbrOfBanks") * - memSpec.memarchitecturespec.entries.at("nbrOfRanks"), - memSpec.memarchitecturespec.entries.at("nbrOfRanks"), - memSpec.memarchitecturespec.entries.at("nbrOfDevices")), - tCKE(tCK * memSpec.memtimingspec.entries.at("CKE")), + memSpec.memarchitecturespec.nbrOfBanks, + memSpec.memarchitecturespec.nbrOfBanks * + memSpec.memarchitecturespec.nbrOfRanks, + memSpec.memarchitecturespec.nbrOfRanks, + memSpec.memarchitecturespec.nbrOfDevices), + tCKE(tCK * memSpec.memtimingspec.CKE), tPD(tCKE), - tCKESR(tCK * memSpec.memtimingspec.entries.at("CKESR")), - tRAS(tCK * memSpec.memtimingspec.entries.at("RAS")), - tRC(tCK * memSpec.memtimingspec.entries.at("RC")), - tRCD(tCK * memSpec.memtimingspec.entries.at("RCD")), - tRL(tCK * memSpec.memtimingspec.entries.at("RL")), - tRTP(tCK * memSpec.memtimingspec.entries.at("RTP")), - tWL(tCK * memSpec.memtimingspec.entries.at("WL")), - tWR(tCK * memSpec.memtimingspec.entries.at("WR")), - tXP(tCK * memSpec.memtimingspec.entries.at("XP")), - tXS(tCK * memSpec.memtimingspec.entries.at("XS")), - tREFI(tCK * memSpec.memtimingspec.entries.at("REFI")), - tRFC(tCK * memSpec.memtimingspec.entries.at("RFC")), - tRP(tCK * memSpec.memtimingspec.entries.at("RP")), - tDQSCK(tCK * memSpec.memtimingspec.entries.at("DQSCK")), - tCCD(tCK * memSpec.memtimingspec.entries.at("CCD")), - tFAW(tCK * memSpec.memtimingspec.entries.at("FAW")), - tRRD(tCK * memSpec.memtimingspec.entries.at("RRD")), - tWTR(tCK * memSpec.memtimingspec.entries.at("WTR")), - tXPDLL(tCK * memSpec.memtimingspec.entries.at("XPDLL")), - tXSDLL(tCK * memSpec.memtimingspec.entries.at("XSDLL")), - tAL(tCK * memSpec.memtimingspec.entries.at("AL")), - tACTPDEN(tCK * memSpec.memtimingspec.entries.at("ACTPDEN")), - tPRPDEN(tCK * memSpec.memtimingspec.entries.at("PRPDEN")), - tREFPDEN(tCK * memSpec.memtimingspec.entries.at("REFPDEN")), - tRTRS(tCK * memSpec.memtimingspec.entries.at("RTRS")), - iDD0(memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd0") : 0), - iDD2N(memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd2n") : 0), - iDD3N(memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd3n") : 0), - iDD4R(memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd4r") : 0), - iDD4W(memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd4w") : 0), - iDD5(memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd5") : 0), - iDD6(memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd6") : 0), - vDD(memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("vdd") : 0), - iDD2P0(memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd2p0") - : 0), - iDD2P1(memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd2p1") - : 0), - iDD3P0(memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd3p0") - : 0), - iDD3P1(memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd3p1") : 0) + tCKESR(tCK * memSpec.memtimingspec.CKESR), + tRAS(tCK * memSpec.memtimingspec.RAS), + tRC(tCK * memSpec.memtimingspec.RC), + tRCD(tCK * memSpec.memtimingspec.RCD), + tRL(tCK * memSpec.memtimingspec.RL), + tRTP(tCK * memSpec.memtimingspec.RTP), + tWL(tCK * memSpec.memtimingspec.WL), + tWR(tCK * memSpec.memtimingspec.WR), + tXP(tCK * memSpec.memtimingspec.XP), + tXS(tCK * memSpec.memtimingspec.XS), + tREFI(tCK * memSpec.memtimingspec.REFI), + tRFC(tCK * memSpec.memtimingspec.RFC), + tRP(tCK * memSpec.memtimingspec.RP), + tDQSCK(tCK * memSpec.memtimingspec.DQSCK), + tCCD(tCK * memSpec.memtimingspec.CCD), + tFAW(tCK * memSpec.memtimingspec.FAW), + tRRD(tCK * memSpec.memtimingspec.RRD), + tWTR(tCK * memSpec.memtimingspec.WTR), + tXPDLL(tCK * memSpec.memtimingspec.XPDLL), + tXSDLL(tCK * memSpec.memtimingspec.XSDLL), + tAL(tCK * memSpec.memtimingspec.AL), + tACTPDEN(tCK * memSpec.memtimingspec.ACTPDEN), + tPRPDEN(tCK * memSpec.memtimingspec.PRPDEN), + tREFPDEN(tCK * memSpec.memtimingspec.REFPDEN), + tRTRS(tCK * memSpec.memtimingspec.RTRS) { uint64_t deviceSizeBits = static_cast(banksPerRank) * rowsPerBank * columnsPerRow * bitWidth; uint64_t deviceSizeBytes = deviceSizeBits / 8; memorySizeBytes = deviceSizeBytes * devicesPerRank * ranksPerChannel * numberOfChannels; - if (!memSpec.mempowerspec.has_value()) - SC_REPORT_FATAL("MemSpec", "No power spec defined!"); - std::cout << headline << std::endl; std::cout << "Memory Configuration:" << std::endl << std::endl; std::cout << " Memory type: " @@ -180,97 +163,4 @@ bool MemSpecDDR3::requiresMaskedWrite(const tlm::tlm_generic_payload& payload) c return !allBytesEnabled(payload); } -#ifdef DRAMPOWER -DRAMPower::MemorySpecification MemSpecDDR3::toDramPowerMemSpec() const -{ - DRAMPower::MemArchitectureSpec memArchSpec; - memArchSpec.burstLength = defaultBurstLength; - memArchSpec.dataRate = dataRate; - memArchSpec.nbrOfRows = rowsPerBank; - memArchSpec.nbrOfBanks = banksPerChannel; - memArchSpec.nbrOfColumns = columnsPerRow; - memArchSpec.nbrOfRanks = ranksPerChannel; - memArchSpec.width = bitWidth; - memArchSpec.nbrOfBankGroups = bankGroupsPerChannel; - memArchSpec.twoVoltageDomains = false; - memArchSpec.dll = true; - - DRAMPower::MemTimingSpec memTimingSpec; - // FIXME: memTimingSpec.FAWB = tFAW / tCK; - // FIXME: memTimingSpec.RASB = tRAS / tCK; - // FIXME: memTimingSpec.RCB = tRC / tCK; - // FIXME: memTimingSpec.RPB = tRP / tCK; - // FIXME: memTimingSpec.RRDB = tRRD / tCK; - // FIXME: memTimingSpec.RRDB_L = tRRD / tCK; - // FIXME: memTimingSpec.RRDB_S = tRRD / tCK; - memTimingSpec.AL = tAL / tCK; - memTimingSpec.CCD = tCCD / tCK; - memTimingSpec.CCD_L = tCCD / tCK; - memTimingSpec.CCD_S = tCCD / tCK; - memTimingSpec.CKE = tCKE / tCK; - memTimingSpec.CKESR = tCKESR / tCK; - // See also MemTimingSpec.cc in DRAMPower - memTimingSpec.clkMhz = 1 / (tCK.to_seconds() * 1'000'000); - memTimingSpec.clkPeriod = tCK.to_seconds() * 1'000'000'000; - memTimingSpec.DQSCK = tDQSCK / tCK; - memTimingSpec.FAW = tFAW / tCK; - memTimingSpec.RAS = tRAS / tCK; - memTimingSpec.RC = tRC / tCK; - memTimingSpec.RCD = tRCD / tCK; - memTimingSpec.REFI = tREFI / tCK; - memTimingSpec.RFC = tRFC / tCK; - memTimingSpec.RL = tRL / tCK; - memTimingSpec.RP = tRP / tCK; - memTimingSpec.RRD = tRRD / tCK; - memTimingSpec.RRD_L = tRRD / tCK; - memTimingSpec.RRD_S = tRRD / tCK; - memTimingSpec.RTP = tRTP / tCK; - memTimingSpec.TAW = tFAW / tCK; - memTimingSpec.WL = tWL / tCK; - memTimingSpec.WR = tWR / tCK; - memTimingSpec.WTR = tWTR / tCK; - memTimingSpec.WTR_L = tWTR / tCK; - memTimingSpec.WTR_S = tWTR / tCK; - memTimingSpec.XP = tXP / tCK; - memTimingSpec.XPDLL = tXPDLL / tCK; - memTimingSpec.XS = tXS / tCK; - memTimingSpec.XSDLL = tXSDLL / tCK; - - DRAMPower::MemPowerSpec memPowerSpec; - memPowerSpec.idd0 = iDD0; - memPowerSpec.idd02 = 0; - memPowerSpec.idd2p0 = iDD2P0; - memPowerSpec.idd2p02 = 0; - memPowerSpec.idd2p1 = iDD2P1; - memPowerSpec.idd2p12 = 0; - memPowerSpec.idd2n = iDD2N; - memPowerSpec.idd2n2 = 0; - memPowerSpec.idd3p0 = iDD3P0; - memPowerSpec.idd3p02 = 0; - memPowerSpec.idd3p1 = iDD3P1; - memPowerSpec.idd3p12 = 0; - memPowerSpec.idd3n = iDD3N; - memPowerSpec.idd3n2 = 0; - memPowerSpec.idd4r = iDD4R; - memPowerSpec.idd4r2 = 0; - memPowerSpec.idd4w = iDD4W; - memPowerSpec.idd4w2 = 0; - memPowerSpec.idd5 = iDD5; - memPowerSpec.idd52 = 0; - memPowerSpec.idd6 = iDD6; - memPowerSpec.idd62 = 0; - memPowerSpec.vdd = vDD; - memPowerSpec.vdd2 = 0; - - DRAMPower::MemorySpecification powerSpec; - powerSpec.id = memoryId; - powerSpec.memoryType = DRAMPower::MemoryType::DDR3; - powerSpec.memTimingSpec = memTimingSpec; - powerSpec.memPowerSpec = memPowerSpec; - powerSpec.memArchSpec = memArchSpec; - - return powerSpec; -} -#endif - } // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR3.h b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR3.h index b94abcfd..db94ce73 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR3.h +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR3.h @@ -32,14 +32,16 @@ * Authors: * Lukas Steiner * Derek Christ + * Marco Mörz */ #ifndef MEMSPECDDR3_H #define MEMSPECDDR3_H -#include "DRAMSys/config/DRAMSysConfiguration.h" #include "DRAMSys/configuration/memspec/MemSpec.h" +#include + #include namespace DRAMSys @@ -48,7 +50,7 @@ namespace DRAMSys class MemSpecDDR3 final : public MemSpec { public: - explicit MemSpecDDR3(const Config::MemSpec& memSpec); + explicit MemSpecDDR3(const DRAMUtils::MemSpec::MemSpecDDR3& memSpec); // Memspec Variables: const sc_core::sc_time tCKE; @@ -79,20 +81,6 @@ public: const sc_core::sc_time tREFPDEN; const sc_core::sc_time tRTRS; - // Currents and Voltages: - const double iDD0; - const double iDD2N; - const double iDD3N; - const double iDD4R; - const double iDD4W; - const double iDD5; - const double iDD6; - const double vDD; - const double iDD2P0; - const double iDD2P1; - const double iDD3P0; - const double iDD3P1; - [[nodiscard]] sc_core::sc_time getRefreshIntervalAB() const override; [[nodiscard]] sc_core::sc_time @@ -103,9 +91,6 @@ public: [[nodiscard]] bool requiresMaskedWrite(const tlm::tlm_generic_payload& payload) const override; -#ifdef DRAMPOWER - [[nodiscard]] DRAMPower::MemorySpecification toDramPowerMemSpec() const override; -#endif }; } // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR4.cpp b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR4.cpp index 65ebf380..85163fd5 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR4.cpp +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR4.cpp @@ -32,6 +32,7 @@ * Authors: * Lukas Steiner * Derek Christ + * Marco Mörz */ #include "MemSpecDDR4.h" @@ -46,87 +47,75 @@ using namespace tlm; namespace DRAMSys { -MemSpecDDR4::MemSpecDDR4(const Config::MemSpec& memSpec) : +using DRAMUtils::MemSpec::RefModeTypeDDR4; + +MemSpecDDR4::MemSpecDDR4(const DRAMUtils::MemSpec::MemSpecDDR4& memSpec) : MemSpec(memSpec, - memSpec.memarchitecturespec.entries.at("nbrOfChannels"), - memSpec.memarchitecturespec.entries.at("nbrOfRanks"), - memSpec.memarchitecturespec.entries.at("nbrOfBanks"), - memSpec.memarchitecturespec.entries.at("nbrOfBankGroups"), - memSpec.memarchitecturespec.entries.at("nbrOfBanks") / - memSpec.memarchitecturespec.entries.at("nbrOfBankGroups"), - memSpec.memarchitecturespec.entries.at("nbrOfBanks") * - memSpec.memarchitecturespec.entries.at("nbrOfRanks"), - memSpec.memarchitecturespec.entries.at("nbrOfBankGroups") * - memSpec.memarchitecturespec.entries.at("nbrOfRanks"), - memSpec.memarchitecturespec.entries.at("nbrOfDevices")), - tCKE(tCK * memSpec.memtimingspec.entries.at("CKE")), + memSpec.memarchitecturespec.nbrOfChannels, + memSpec.memarchitecturespec.nbrOfRanks, + memSpec.memarchitecturespec.nbrOfBanks, + memSpec.memarchitecturespec.nbrOfBankGroups, + memSpec.memarchitecturespec.nbrOfBanks / + memSpec.memarchitecturespec.nbrOfBankGroups, + memSpec.memarchitecturespec.nbrOfBanks * + memSpec.memarchitecturespec.nbrOfRanks, + memSpec.memarchitecturespec.nbrOfBankGroups * + memSpec.memarchitecturespec.nbrOfRanks, + memSpec.memarchitecturespec.nbrOfDevices), + memSpec(memSpec), + tCKE(tCK * memSpec.memtimingspec.CKE), tPD(tCKE), - tCKESR(tCK * memSpec.memtimingspec.entries.at("CKESR")), - tRAS(tCK * memSpec.memtimingspec.entries.at("RAS")), - tRC(tCK * memSpec.memtimingspec.entries.at("RC")), - tRCD(tCK * memSpec.memtimingspec.entries.at("RCD")), - tRL(tCK * memSpec.memtimingspec.entries.at("RL")), - tRPRE(tCK * memSpec.memtimingspec.entries.at("RPRE")), - tRTP(tCK * memSpec.memtimingspec.entries.at("RTP")), - tWL(tCK * memSpec.memtimingspec.entries.at("WL")), - tWPRE(tCK * memSpec.memtimingspec.entries.at("WPRE")), - tWR(tCK * memSpec.memtimingspec.entries.at("WR")), - tXP(tCK * memSpec.memtimingspec.entries.at("XP")), - tXS(tCK * memSpec.memtimingspec.entries.at("XS")), - tREFI((memSpec.memtimingspec.entries.at("REFM") == 4) - ? (tCK * (static_cast(memSpec.memtimingspec.entries.at("REFI")) / 4)) - : ((memSpec.memtimingspec.entries.at("REFM") == 2) - ? (tCK * (static_cast(memSpec.memtimingspec.entries.at("REFI")) / 2)) - : (tCK * memSpec.memtimingspec.entries.at("REFI")))), - tRFC((memSpec.memtimingspec.entries.at("REFM") == 4) - ? (tCK * memSpec.memtimingspec.entries.at("RFC4")) - : ((memSpec.memtimingspec.entries.at("REFM") == 2) - ? (tCK * memSpec.memtimingspec.entries.at("RFC2")) - : (tCK * memSpec.memtimingspec.entries.at("RFC")))), - tRP(tCK * memSpec.memtimingspec.entries.at("RP")), - tDQSCK(tCK * memSpec.memtimingspec.entries.at("DQSCK")), - tCCD_S(tCK * memSpec.memtimingspec.entries.at("CCD_S")), - tCCD_L(tCK * memSpec.memtimingspec.entries.at("CCD_L")), - tFAW(tCK * memSpec.memtimingspec.entries.at("FAW")), - tRRD_S(tCK * memSpec.memtimingspec.entries.at("RRD_S")), - tRRD_L(tCK * memSpec.memtimingspec.entries.at("RRD_L")), - tWTR_S(tCK * memSpec.memtimingspec.entries.at("WTR_S")), - tWTR_L(tCK * memSpec.memtimingspec.entries.at("WTR_L")), - tAL(tCK * memSpec.memtimingspec.entries.at("AL")), - tXPDLL(tCK * memSpec.memtimingspec.entries.at("XPDLL")), - tXSDLL(tCK * memSpec.memtimingspec.entries.at("XSDLL")), - tACTPDEN(tCK * memSpec.memtimingspec.entries.at("ACTPDEN")), - tPRPDEN(tCK * memSpec.memtimingspec.entries.at("PRPDEN")), - tREFPDEN(tCK * memSpec.memtimingspec.entries.at("REFPDEN")), - tRTRS(tCK * memSpec.memtimingspec.entries.at("RTRS")), - iDD0(memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd0") : 0), - iDD2N(memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd2n") : 0), - iDD3N(memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd3n") : 0), - iDD4R(memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd4r") : 0), - iDD4W(memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd4w") : 0), - iDD5(memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd5") : 0), - iDD6(memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd6") : 0), - vDD(memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("vdd") : 0), - iDD02(memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd02") : 0), - iDD2P0(memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd2p0") - : 0), - iDD2P1(memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd2p1") - : 0), - iDD3P0(memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd3p0") - : 0), - iDD3P1(memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd3p1") - : 0), - iDD62(memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd62") : 0), - vDD2(memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("vdd2") : 0) + tCKESR(tCK * memSpec.memtimingspec.CKESR), + tRAS(tCK * memSpec.memtimingspec.RAS), + tRC(tCK * memSpec.memtimingspec.RC), + tRCD(tCK * memSpec.memtimingspec.RCD), + tRL(tCK * memSpec.memtimingspec.RL), + tRPRE(tCK * memSpec.memtimingspec.RPRE), + tRTP(tCK * memSpec.memtimingspec.RTP), + tWL(tCK * memSpec.memtimingspec.WL), + tWPRE(tCK * memSpec.memtimingspec.WPRE), + tWR(tCK * memSpec.memtimingspec.WR), + tXP(tCK * memSpec.memtimingspec.XP), + tXS(tCK * memSpec.memtimingspec.XS), + tREFI((memSpec.memarchitecturespec.RefMode == RefModeTypeDDR4::REF_MODE_4) ? + (tCK * (static_cast(memSpec.memtimingspec.REFI) / 4)) + : ((memSpec.memarchitecturespec.RefMode == RefModeTypeDDR4::REF_MODE_2) ? + (tCK * (static_cast(memSpec.memtimingspec.REFI) / 2)) + // RefModeTypeDDR4::REF_MODE_1 || RefModeTypeDDR4::INVALID + : (tCK * memSpec.memtimingspec.REFI))), + tRFC((memSpec.memarchitecturespec.RefMode == RefModeTypeDDR4::REF_MODE_4) ? + (tCK * memSpec.memtimingspec.RFC4) + : ((memSpec.memarchitecturespec.RefMode == RefModeTypeDDR4::REF_MODE_2) ? + (tCK * memSpec.memtimingspec.RFC2) + // RefModeTypeDDR4::REF_MODE_1 || RefModeTypeDDR4::INVALID + : (tCK * memSpec.memtimingspec.RFC1))), + tRP(tCK * memSpec.memtimingspec.RP), + tDQSCK(tCK * memSpec.memtimingspec.DQSCK), + tCCD_S(tCK * memSpec.memtimingspec.CCD_S), + tCCD_L(tCK * memSpec.memtimingspec.CCD_L), + tFAW(tCK * memSpec.memtimingspec.FAW), + tRRD_S(tCK * memSpec.memtimingspec.RRD_S), + tRRD_L(tCK * memSpec.memtimingspec.RRD_L), + tWTR_S(tCK * memSpec.memtimingspec.WTR_S), + tWTR_L(tCK * memSpec.memtimingspec.WTR_L), + tAL(tCK * memSpec.memtimingspec.AL), + tXPDLL(tCK * memSpec.memtimingspec.XPDLL), + tXSDLL(tCK * memSpec.memtimingspec.XSDLL), + tACTPDEN(tCK * memSpec.memtimingspec.ACTPDEN), + tPRPDEN(tCK * memSpec.memtimingspec.PRPDEN), + tREFPDEN(tCK * memSpec.memtimingspec.REFPDEN), + tRTRS(tCK * memSpec.memtimingspec.RTRS) { + if (RefModeTypeDDR4::INVALID == memSpec.memarchitecturespec.RefMode) + SC_REPORT_FATAL("MemSpecDDR4", + "Invalid refresh mode! " + "Set 1 for normal (fixed 1x), 2 for fixed 2x or 4 for fixed 4x refresh mode."); + uint64_t deviceSizeBits = static_cast(banksPerRank) * rowsPerBank * columnsPerRow * bitWidth; uint64_t deviceSizeBytes = deviceSizeBits / 8; memorySizeBytes = deviceSizeBytes * devicesPerRank * ranksPerChannel * numberOfChannels; - if (!memSpec.mempowerspec.has_value()) - SC_REPORT_WARNING("MemSpec", "No power spec defined!"); - std::cout << headline << std::endl; std::cout << "Memory Configuration:" << std::endl << std::endl; std::cout << " Memory type: " @@ -201,95 +190,9 @@ bool MemSpecDDR4::requiresMaskedWrite(const tlm::tlm_generic_payload& payload) c } #ifdef DRAMPOWER -DRAMPower::MemorySpecification MemSpecDDR4::toDramPowerMemSpec() const +std::unique_ptr> MemSpecDDR4::toDramPowerObject() const { - DRAMPower::MemArchitectureSpec memArchSpec; - memArchSpec.burstLength = defaultBurstLength; - memArchSpec.dataRate = dataRate; - memArchSpec.nbrOfRows = rowsPerBank; - memArchSpec.nbrOfBanks = banksPerChannel; - memArchSpec.nbrOfColumns = columnsPerRow; - memArchSpec.nbrOfRanks = ranksPerChannel; - memArchSpec.width = bitWidth; - memArchSpec.nbrOfBankGroups = bankGroupsPerChannel; - memArchSpec.twoVoltageDomains = true; - memArchSpec.dll = true; - - DRAMPower::MemTimingSpec memTimingSpec; - // FIXME: memTimingSpec.FAWB = tFAW / tCK; - // FIXME: memTimingSpec.RASB = tRAS / tCK; - // FIXME: memTimingSpec.RCB = tRC / tCK; - // FIXME: memTimingSpec.RPB = tRP / tCK; - // FIXME: memTimingSpec.RRDB = tRRD_S / tCK; - // FIXME: memTimingSpec.RRDB_L = tRRD_L / tCK; - // FIXME: memTimingSpec.RRDB_S = tRRD_S / tCK; - memTimingSpec.AL = tAL / tCK; - memTimingSpec.CCD = tCCD_S / tCK; - memTimingSpec.CCD_L = tCCD_L / tCK; - memTimingSpec.CCD_S = tCCD_S / tCK; - memTimingSpec.CKE = tCKE / tCK; - memTimingSpec.CKESR = tCKESR / tCK; - // See also MemTimingSpec.cc in DRAMPower - memTimingSpec.clkMhz = 1 / (tCK.to_seconds() * 1'000'000); - memTimingSpec.clkPeriod = tCK.to_seconds() * 1'000'000'000; - memTimingSpec.DQSCK = tDQSCK / tCK; - memTimingSpec.FAW = tFAW / tCK; - memTimingSpec.RAS = tRAS / tCK; - memTimingSpec.RC = tRC / tCK; - memTimingSpec.RCD = tRCD / tCK; - memTimingSpec.REFI = tREFI / tCK; - memTimingSpec.RFC = tRFC / tCK; - memTimingSpec.RL = tRL / tCK; - memTimingSpec.RP = tRP / tCK; - memTimingSpec.RRD = tRRD_S / tCK; - memTimingSpec.RRD_L = tRRD_L / tCK; - memTimingSpec.RRD_S = tRRD_S / tCK; - memTimingSpec.RTP = tRTP / tCK; - memTimingSpec.TAW = tFAW / tCK; - memTimingSpec.WL = tWL / tCK; - memTimingSpec.WR = tWR / tCK; - memTimingSpec.WTR = tWTR_S / tCK; - memTimingSpec.WTR_L = tWTR_L / tCK; - memTimingSpec.WTR_S = tWTR_S / tCK; - memTimingSpec.XP = tXP / tCK; - memTimingSpec.XPDLL = tXPDLL / tCK; - memTimingSpec.XS = tXS / tCK; - memTimingSpec.XSDLL = tXSDLL / tCK; - - DRAMPower::MemPowerSpec memPowerSpec; - memPowerSpec.idd0 = iDD0; - memPowerSpec.idd02 = iDD02; - memPowerSpec.idd2p0 = iDD2P0; - memPowerSpec.idd2p02 = 0; - memPowerSpec.idd2p1 = iDD2P1; - memPowerSpec.idd2p12 = 0; - memPowerSpec.idd2n = iDD2N; - memPowerSpec.idd2n2 = 0; - memPowerSpec.idd3p0 = iDD3P0; - memPowerSpec.idd3p02 = 0; - memPowerSpec.idd3p1 = iDD3P1; - memPowerSpec.idd3p12 = 0; - memPowerSpec.idd3n = iDD3N; - memPowerSpec.idd3n2 = 0; - memPowerSpec.idd4r = iDD4R; - memPowerSpec.idd4r2 = 0; - memPowerSpec.idd4w = iDD4W; - memPowerSpec.idd4w2 = 0; - memPowerSpec.idd5 = iDD5; - memPowerSpec.idd52 = 0; - memPowerSpec.idd6 = iDD6; - memPowerSpec.idd62 = iDD62; - memPowerSpec.vdd = vDD; - memPowerSpec.vdd2 = vDD2; - - DRAMPower::MemorySpecification powerSpec; - powerSpec.id = memoryId; - powerSpec.memoryType = DRAMPower::MemoryType::DDR4; - powerSpec.memTimingSpec = memTimingSpec; - powerSpec.memPowerSpec = memPowerSpec; - powerSpec.memArchSpec = memArchSpec; - - return powerSpec; + return std::make_unique(std::move(DRAMPower::MemSpecDDR4(memSpec))); } #endif diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR4.h b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR4.h index 9e2949ad..2bf128d1 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR4.h +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR4.h @@ -32,6 +32,7 @@ * Authors: * Lukas Steiner * Derek Christ + * Marco Mörz */ #ifndef MEMSPECDDR4_H @@ -39,6 +40,13 @@ #include "DRAMSys/configuration/memspec/MemSpec.h" +#include + +#ifdef DRAMPOWER +#include "DRAMPower/standards/ddr4/DDR4.h" +#include "DRAMPower/memspec/MemSpecDDR4.h" +#endif + #include namespace DRAMSys @@ -47,9 +55,10 @@ namespace DRAMSys class MemSpecDDR4 final : public MemSpec { public: - explicit MemSpecDDR4(const Config::MemSpec& memSpec); + explicit MemSpecDDR4(const DRAMUtils::MemSpec::MemSpecDDR4& memSpec); // Memspec Variables: + const DRAMUtils::MemSpec::MemSpecDDR4& memSpec; const sc_core::sc_time tCKE; const sc_core::sc_time tPD; const sc_core::sc_time tCKESR; @@ -83,23 +92,6 @@ public: const sc_core::sc_time tREFPDEN; const sc_core::sc_time tRTRS; - // Currents and Voltages: - const double iDD0; - const double iDD2N; - const double iDD3N; - const double iDD4R; - const double iDD4W; - const double iDD5; - const double iDD6; - const double vDD; - const double iDD02; - const double iDD2P0; - const double iDD2P1; - const double iDD3P0; - const double iDD3P1; - const double iDD62; - const double vDD2; - [[nodiscard]] sc_core::sc_time getRefreshIntervalAB() const override; [[nodiscard]] sc_core::sc_time @@ -111,7 +103,7 @@ public: [[nodiscard]] bool requiresMaskedWrite(const tlm::tlm_generic_payload& payload) const override; #ifdef DRAMPOWER - [[nodiscard]] DRAMPower::MemorySpecification toDramPowerMemSpec() const override; + [[nodiscard]] std::unique_ptr> toDramPowerObject() const override; #endif }; diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5.cpp b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5.cpp index a0a095d1..1b9b8bba 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5.cpp +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5.cpp @@ -32,6 +32,7 @@ * Authors: * Lukas Steiner * Derek Christ + * Marco Mörz */ #include "MemSpecGDDR5.h" @@ -46,53 +47,53 @@ using namespace tlm; namespace DRAMSys { -MemSpecGDDR5::MemSpecGDDR5(const Config::MemSpec& memSpec) : +MemSpecGDDR5::MemSpecGDDR5(const DRAMUtils::MemSpec::MemSpecGDDR5& memSpec) : MemSpec(memSpec, - memSpec.memarchitecturespec.entries.at("nbrOfChannels"), - memSpec.memarchitecturespec.entries.at("nbrOfRanks"), - memSpec.memarchitecturespec.entries.at("nbrOfBanks"), - memSpec.memarchitecturespec.entries.at("nbrOfBankGroups"), - memSpec.memarchitecturespec.entries.at("nbrOfBanks") / - memSpec.memarchitecturespec.entries.at("nbrOfBankGroups"), - memSpec.memarchitecturespec.entries.at("nbrOfBanks") * - memSpec.memarchitecturespec.entries.at("nbrOfRanks"), - memSpec.memarchitecturespec.entries.at("nbrOfBankGroups") * - memSpec.memarchitecturespec.entries.at("nbrOfRanks"), - memSpec.memarchitecturespec.entries.at("nbrOfDevices")), - tRP(tCK * memSpec.memtimingspec.entries.at("RP")), - tRAS(tCK * memSpec.memtimingspec.entries.at("RAS")), - tRC(tCK * memSpec.memtimingspec.entries.at("RC")), - tRCDRD(tCK * memSpec.memtimingspec.entries.at("RCDRD")), - tRCDWR(tCK * memSpec.memtimingspec.entries.at("RCDWR")), - tRTP(tCK * memSpec.memtimingspec.entries.at("RTP")), - tRRDS(tCK * memSpec.memtimingspec.entries.at("RRDS")), - tRRDL(tCK * memSpec.memtimingspec.entries.at("RRDL")), - tCCDS(tCK * memSpec.memtimingspec.entries.at("CCDS")), - tCCDL(tCK * memSpec.memtimingspec.entries.at("CCDL")), - tCL(tCK * memSpec.memtimingspec.entries.at("CL")), - tWCK2CKPIN(tCK * memSpec.memtimingspec.entries.at("WCK2CKPIN")), - tWCK2CK(tCK * memSpec.memtimingspec.entries.at("WCK2CK")), - tWCK2DQO(tCK * memSpec.memtimingspec.entries.at("WCK2DQO")), - tRTW(tCK * memSpec.memtimingspec.entries.at("RTW")), - tWL(tCK * memSpec.memtimingspec.entries.at("WL")), - tWCK2DQI(tCK * memSpec.memtimingspec.entries.at("WCK2DQI")), - tWR(tCK * memSpec.memtimingspec.entries.at("WR")), - tWTRS(tCK * memSpec.memtimingspec.entries.at("WTRS")), - tWTRL(tCK * memSpec.memtimingspec.entries.at("WTRL")), - tCKE(tCK * memSpec.memtimingspec.entries.at("CKE")), - tPD(tCK * memSpec.memtimingspec.entries.at("PD")), - tXPN(tCK * memSpec.memtimingspec.entries.at("XPN")), - tREFI(tCK * memSpec.memtimingspec.entries.at("REFI")), - tREFIPB(tCK * memSpec.memtimingspec.entries.at("REFIPB")), - tRFC(tCK * memSpec.memtimingspec.entries.at("RFC")), - tRFCPB(tCK * memSpec.memtimingspec.entries.at("RFCPB")), - tRREFD(tCK * memSpec.memtimingspec.entries.at("RREFD")), - tXS(tCK * memSpec.memtimingspec.entries.at("XS")), - tFAW(tCK * memSpec.memtimingspec.entries.at("FAW")), - t32AW(tCK * memSpec.memtimingspec.entries.at("32AW")), - tPPD(tCK * memSpec.memtimingspec.entries.at("PPD")), - tLK(tCK * memSpec.memtimingspec.entries.at("LK")), - tRTRS(tCK * memSpec.memtimingspec.entries.at("RTRS")) + memSpec.memarchitecturespec.nbrOfChannels, + memSpec.memarchitecturespec.nbrOfRanks, + memSpec.memarchitecturespec.nbrOfBanks, + memSpec.memarchitecturespec.nbrOfBankGroups, + memSpec.memarchitecturespec.nbrOfBanks / + memSpec.memarchitecturespec.nbrOfBankGroups, + memSpec.memarchitecturespec.nbrOfBanks * + memSpec.memarchitecturespec.nbrOfRanks, + memSpec.memarchitecturespec.nbrOfBankGroups * + memSpec.memarchitecturespec.nbrOfRanks, + memSpec.memarchitecturespec.nbrOfDevices), + tRP(tCK * memSpec.memtimingspec.RP), + tRAS(tCK * memSpec.memtimingspec.RAS), + tRC(tCK * memSpec.memtimingspec.RC), + tRCDRD(tCK * memSpec.memtimingspec.RCDRD), + tRCDWR(tCK * memSpec.memtimingspec.RCDWR), + tRTP(tCK * memSpec.memtimingspec.RTP), + tRRDS(tCK * memSpec.memtimingspec.RRDS), + tRRDL(tCK * memSpec.memtimingspec.RRDL), + tCCDS(tCK * memSpec.memtimingspec.CCDS), + tCCDL(tCK * memSpec.memtimingspec.CCDL), + tCL(tCK * memSpec.memtimingspec.CL), + tWCK2CKPIN(tCK * memSpec.memtimingspec.WCK2CKPIN), + tWCK2CK(tCK * memSpec.memtimingspec.WCK2CK), + tWCK2DQO(tCK * memSpec.memtimingspec.WCK2DQO), + tRTW(tCK * memSpec.memtimingspec.RTW), + tWL(tCK * memSpec.memtimingspec.WL), + tWCK2DQI(tCK * memSpec.memtimingspec.WCK2DQI), + tWR(tCK * memSpec.memtimingspec.WR), + tWTRS(tCK * memSpec.memtimingspec.WTRS), + tWTRL(tCK * memSpec.memtimingspec.WTRL), + tCKE(tCK * memSpec.memtimingspec.CKE), + tPD(tCK * memSpec.memtimingspec.PD), + tXPN(tCK * memSpec.memtimingspec.XPN), + tREFI(tCK * memSpec.memtimingspec.REFI), + tREFIPB(tCK * memSpec.memtimingspec.REFIPB), + tRFC(tCK * memSpec.memtimingspec.RFC), + tRFCPB(tCK * memSpec.memtimingspec.RFCPB), + tRREFD(tCK * memSpec.memtimingspec.RREFD), + tXS(tCK * memSpec.memtimingspec.XS), + tFAW(tCK * memSpec.memtimingspec.FAW), + t32AW(tCK * memSpec.memtimingspec._32AW), // TODO breaking change + tPPD(tCK * memSpec.memtimingspec.PPD), + tLK(tCK * memSpec.memtimingspec.LK), + tRTRS(tCK * memSpec.memtimingspec.RTRS) { uint64_t deviceSizeBits = static_cast(banksPerRank) * rowsPerBank * columnsPerRow * bitWidth; diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5.h b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5.h index 0f8a8497..d0bc6ceb 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5.h +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5.h @@ -32,6 +32,7 @@ * Authors: * Lukas Steiner * Derek Christ + * Marco Mörz */ #ifndef MEMSPECGDDR5_H @@ -39,6 +40,8 @@ #include "DRAMSys/configuration/memspec/MemSpec.h" +#include + #include namespace DRAMSys @@ -47,7 +50,7 @@ namespace DRAMSys class MemSpecGDDR5 final : public MemSpec { public: - explicit MemSpecGDDR5(const Config::MemSpec& memSpec); + explicit MemSpecGDDR5(const DRAMUtils::MemSpec::MemSpecGDDR5& memSpec); // Memspec Variables: const sc_core::sc_time tRP; diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5X.cpp b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5X.cpp index 92d4fd2f..50ba3d45 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5X.cpp +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5X.cpp @@ -32,6 +32,7 @@ * Authors: * Lukas Steiner * Derek Christ + * Marco Mörz */ #include "MemSpecGDDR5X.h" @@ -46,53 +47,53 @@ using namespace tlm; namespace DRAMSys { -MemSpecGDDR5X::MemSpecGDDR5X(const Config::MemSpec& memSpec) : +MemSpecGDDR5X::MemSpecGDDR5X(const DRAMUtils::MemSpec::MemSpecGDDR5X& memSpec) : MemSpec(memSpec, - memSpec.memarchitecturespec.entries.at("nbrOfChannels"), - memSpec.memarchitecturespec.entries.at("nbrOfRanks"), - memSpec.memarchitecturespec.entries.at("nbrOfBanks"), - memSpec.memarchitecturespec.entries.at("nbrOfBankGroups"), - memSpec.memarchitecturespec.entries.at("nbrOfBanks") / - memSpec.memarchitecturespec.entries.at("nbrOfBankGroups"), - memSpec.memarchitecturespec.entries.at("nbrOfBanks") * - memSpec.memarchitecturespec.entries.at("nbrOfRanks"), - memSpec.memarchitecturespec.entries.at("nbrOfBankGroups") * - memSpec.memarchitecturespec.entries.at("nbrOfRanks"), - memSpec.memarchitecturespec.entries.at("nbrOfDevices")), - tRP(tCK * memSpec.memtimingspec.entries.at("RP")), - tRAS(tCK * memSpec.memtimingspec.entries.at("RAS")), - tRC(tCK * memSpec.memtimingspec.entries.at("RC")), - tRCDRD(tCK * memSpec.memtimingspec.entries.at("RCDRD")), - tRCDWR(tCK * memSpec.memtimingspec.entries.at("RCDWR")), - tRTP(tCK * memSpec.memtimingspec.entries.at("RTP")), - tRRDS(tCK * memSpec.memtimingspec.entries.at("RRDS")), - tRRDL(tCK * memSpec.memtimingspec.entries.at("RRDL")), - tCCDS(tCK * memSpec.memtimingspec.entries.at("CCDS")), - tCCDL(tCK * memSpec.memtimingspec.entries.at("CCDL")), - tRL(tCK * memSpec.memtimingspec.entries.at("CL")), - tWCK2CKPIN(tCK * memSpec.memtimingspec.entries.at("WCK2CKPIN")), - tWCK2CK(tCK * memSpec.memtimingspec.entries.at("WCK2CK")), - tWCK2DQO(tCK * memSpec.memtimingspec.entries.at("WCK2DQO")), - tRTW(tCK * memSpec.memtimingspec.entries.at("RTW")), - tWL(tCK * memSpec.memtimingspec.entries.at("WL")), - tWCK2DQI(tCK * memSpec.memtimingspec.entries.at("WCK2DQI")), - tWR(tCK * memSpec.memtimingspec.entries.at("WR")), - tWTRS(tCK * memSpec.memtimingspec.entries.at("WTRS")), - tWTRL(tCK * memSpec.memtimingspec.entries.at("WTRL")), - tCKE(tCK * memSpec.memtimingspec.entries.at("CKE")), - tPD(tCK * memSpec.memtimingspec.entries.at("PD")), - tXP(tCK * memSpec.memtimingspec.entries.at("XP")), - tREFI(tCK * memSpec.memtimingspec.entries.at("REFI")), - tREFIPB(tCK * memSpec.memtimingspec.entries.at("REFIPB")), - tRFC(tCK * memSpec.memtimingspec.entries.at("RFC")), - tRFCPB(tCK * memSpec.memtimingspec.entries.at("RFCPB")), - tRREFD(tCK * memSpec.memtimingspec.entries.at("RREFD")), - tXS(tCK * memSpec.memtimingspec.entries.at("XS")), - tFAW(tCK * memSpec.memtimingspec.entries.at("FAW")), - t32AW(tCK * memSpec.memtimingspec.entries.at("32AW")), - tPPD(tCK * memSpec.memtimingspec.entries.at("PPD")), - tLK(tCK * memSpec.memtimingspec.entries.at("LK")), - tRTRS(tCK * memSpec.memtimingspec.entries.at("TRS")) + memSpec.memarchitecturespec.nbrOfChannels, + memSpec.memarchitecturespec.nbrOfRanks, + memSpec.memarchitecturespec.nbrOfBanks, + memSpec.memarchitecturespec.nbrOfBankGroups, + memSpec.memarchitecturespec.nbrOfBanks / + memSpec.memarchitecturespec.nbrOfBankGroups, + memSpec.memarchitecturespec.nbrOfBanks * + memSpec.memarchitecturespec.nbrOfRanks, + memSpec.memarchitecturespec.nbrOfBankGroups * + memSpec.memarchitecturespec.nbrOfRanks, + memSpec.memarchitecturespec.nbrOfDevices), + tRP(tCK * memSpec.memtimingspec.RP), + tRAS(tCK * memSpec.memtimingspec.RAS), + tRC(tCK * memSpec.memtimingspec.RC), + tRCDRD(tCK * memSpec.memtimingspec.RCDRD), + tRCDWR(tCK * memSpec.memtimingspec.RCDWR), + tRTP(tCK * memSpec.memtimingspec.RTP), + tRRDS(tCK * memSpec.memtimingspec.RRDS), + tRRDL(tCK * memSpec.memtimingspec.RRDL), + tCCDS(tCK * memSpec.memtimingspec.CCDS), + tCCDL(tCK * memSpec.memtimingspec.CCDL), + tRL(tCK * memSpec.memtimingspec.CL), + tWCK2CKPIN(tCK * memSpec.memtimingspec.WCK2CKPIN), + tWCK2CK(tCK * memSpec.memtimingspec.WCK2CK), + tWCK2DQO(tCK * memSpec.memtimingspec.WCK2DQO), + tRTW(tCK * memSpec.memtimingspec.RTW), + tWL(tCK * memSpec.memtimingspec.WL), + tWCK2DQI(tCK * memSpec.memtimingspec.WCK2DQI), + tWR(tCK * memSpec.memtimingspec.WR), + tWTRS(tCK * memSpec.memtimingspec.WTRS), + tWTRL(tCK * memSpec.memtimingspec.WTRL), + tCKE(tCK * memSpec.memtimingspec.CKE), + tPD(tCK * memSpec.memtimingspec.PD), + tXP(tCK * memSpec.memtimingspec.XP), + tREFI(tCK * memSpec.memtimingspec.REFI), + tREFIPB(tCK * memSpec.memtimingspec.REFIPB), + tRFC(tCK * memSpec.memtimingspec.RFC), + tRFCPB(tCK * memSpec.memtimingspec.RFCPB), + tRREFD(tCK * memSpec.memtimingspec.RREFD), + tXS(tCK * memSpec.memtimingspec.XS), + tFAW(tCK * memSpec.memtimingspec.FAW), + t32AW(tCK * memSpec.memtimingspec._32AW), // TODO breaking change + tPPD(tCK * memSpec.memtimingspec.PPD), + tLK(tCK * memSpec.memtimingspec.LK), + tRTRS(tCK * memSpec.memtimingspec.TRS) { uint64_t deviceSizeBits = static_cast(banksPerRank) * rowsPerBank * columnsPerRow * bitWidth; diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5X.h b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5X.h index 1536ef93..29eb290c 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5X.h +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5X.h @@ -32,6 +32,7 @@ * Authors: * Lukas Steiner * Derek Christ + * Marco Mörz */ #ifndef MEMSPECGDDR5X_H @@ -39,6 +40,8 @@ #include "DRAMSys/configuration/memspec/MemSpec.h" +#include + #include namespace DRAMSys @@ -47,7 +50,7 @@ namespace DRAMSys class MemSpecGDDR5X final : public MemSpec { public: - explicit MemSpecGDDR5X(const Config::MemSpec& memSpec); + explicit MemSpecGDDR5X(const DRAMUtils::MemSpec::MemSpecGDDR5X& memSpec); // Memspec Variables: const sc_core::sc_time tRP; diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR6.cpp b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR6.cpp index d560177d..fb1ddb66 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR6.cpp +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR6.cpp @@ -32,6 +32,7 @@ * Authors: * Lukas Steiner * Derek Christ + * Marco Mörz */ #include "MemSpecGDDR6.h" @@ -46,56 +47,56 @@ using namespace tlm; namespace DRAMSys { -MemSpecGDDR6::MemSpecGDDR6(const Config::MemSpec& memSpec) : +MemSpecGDDR6::MemSpecGDDR6(const DRAMUtils::MemSpec::MemSpecGDDR6& memSpec) : MemSpec(memSpec, - memSpec.memarchitecturespec.entries.at("nbrOfChannels"), - memSpec.memarchitecturespec.entries.at("nbrOfRanks"), - memSpec.memarchitecturespec.entries.at("nbrOfBanks"), - memSpec.memarchitecturespec.entries.at("nbrOfBankGroups"), - memSpec.memarchitecturespec.entries.at("nbrOfBanks") / - memSpec.memarchitecturespec.entries.at("nbrOfBankGroups"), - memSpec.memarchitecturespec.entries.at("nbrOfBanks") * - memSpec.memarchitecturespec.entries.at("nbrOfRanks"), - memSpec.memarchitecturespec.entries.at("nbrOfBankGroups") * - memSpec.memarchitecturespec.entries.at("nbrOfRanks"), - memSpec.memarchitecturespec.entries.at("nbrOfDevices")), - tRP(tCK * memSpec.memtimingspec.entries.at("RP")), - tRAS(tCK * memSpec.memtimingspec.entries.at("RAS")), - tRC(tCK * memSpec.memtimingspec.entries.at("RC")), - tRCDRD(tCK * memSpec.memtimingspec.entries.at("RCDRD")), - tRCDWR(tCK * memSpec.memtimingspec.entries.at("RCDWR")), - tRTP(tCK * memSpec.memtimingspec.entries.at("RTP")), - tRRDS(tCK * memSpec.memtimingspec.entries.at("RRDS")), - tRRDL(tCK * memSpec.memtimingspec.entries.at("RRDL")), - tCCDS(tCK * memSpec.memtimingspec.entries.at("CCDS")), - tCCDL(tCK * memSpec.memtimingspec.entries.at("CCDL")), - tRL(tCK * memSpec.memtimingspec.entries.at("RL")), - tWCK2CKPIN(tCK * memSpec.memtimingspec.entries.at("WCK2CKPIN")), - tWCK2CK(tCK * memSpec.memtimingspec.entries.at("WCK2CK")), - tWCK2DQO(tCK * memSpec.memtimingspec.entries.at("WCK2DQO")), - tRTW(tCK * memSpec.memtimingspec.entries.at("RTW")), - tWL(tCK * memSpec.memtimingspec.entries.at("WL")), - tWCK2DQI(tCK * memSpec.memtimingspec.entries.at("WCK2DQI")), - tWR(tCK * memSpec.memtimingspec.entries.at("WR")), - tWTRS(tCK * memSpec.memtimingspec.entries.at("WTRS")), - tWTRL(tCK * memSpec.memtimingspec.entries.at("WTRL")), - tPD(tCK * memSpec.memtimingspec.entries.at("PD")), - tCKESR(tCK * memSpec.memtimingspec.entries.at("CKESR")), - tXP(tCK * memSpec.memtimingspec.entries.at("XP")), - tREFI(tCK * memSpec.memtimingspec.entries.at("REFI")), - tREFIpb(tCK * memSpec.memtimingspec.entries.at("REFIpb")), - tRFCab(tCK * memSpec.memtimingspec.entries.at("RFCab")), - tRFCpb(tCK * memSpec.memtimingspec.entries.at("RFCpb")), - tRREFD(tCK * memSpec.memtimingspec.entries.at("RREFD")), - tXS(tCK * memSpec.memtimingspec.entries.at("XS")), - tFAW(tCK * memSpec.memtimingspec.entries.at("FAW")), - tPPD(tCK * memSpec.memtimingspec.entries.at("PPD")), - tLK(tCK * memSpec.memtimingspec.entries.at("LK")), - tACTPDE(tCK * memSpec.memtimingspec.entries.at("ACTPDE")), - tPREPDE(tCK * memSpec.memtimingspec.entries.at("PREPDE")), - tREFPDE(tCK * memSpec.memtimingspec.entries.at("REFPDE")), - tRTRS(tCK * memSpec.memtimingspec.entries.at("RTRS")), - per2BankOffset(memSpec.memarchitecturespec.entries.at("per2BankOffset")) + memSpec.memarchitecturespec.nbrOfChannels, + memSpec.memarchitecturespec.nbrOfRanks, + memSpec.memarchitecturespec.nbrOfBanks, + memSpec.memarchitecturespec.nbrOfBankGroups, + memSpec.memarchitecturespec.nbrOfBanks / + memSpec.memarchitecturespec.nbrOfBankGroups, + memSpec.memarchitecturespec.nbrOfBanks * + memSpec.memarchitecturespec.nbrOfRanks, + memSpec.memarchitecturespec.nbrOfBankGroups * + memSpec.memarchitecturespec.nbrOfRanks, + memSpec.memarchitecturespec.nbrOfDevices), + tRP(tCK * memSpec.memtimingspec.RP), + tRAS(tCK * memSpec.memtimingspec.RAS), + tRC(tCK * memSpec.memtimingspec.RC), + tRCDRD(tCK * memSpec.memtimingspec.RCDRD), + tRCDWR(tCK * memSpec.memtimingspec.RCDWR), + tRTP(tCK * memSpec.memtimingspec.RTP), + tRRDS(tCK * memSpec.memtimingspec.RRDS), + tRRDL(tCK * memSpec.memtimingspec.RRDL), + tCCDS(tCK * memSpec.memtimingspec.CCDS), + tCCDL(tCK * memSpec.memtimingspec.CCDL), + tRL(tCK * memSpec.memtimingspec.RL), + tWCK2CKPIN(tCK * memSpec.memtimingspec.WCK2CKPIN), + tWCK2CK(tCK * memSpec.memtimingspec.WCK2CK), + tWCK2DQO(tCK * memSpec.memtimingspec.WCK2DQO), + tRTW(tCK * memSpec.memtimingspec.RTW), + tWL(tCK * memSpec.memtimingspec.WL), + tWCK2DQI(tCK * memSpec.memtimingspec.WCK2DQI), + tWR(tCK * memSpec.memtimingspec.WR), + tWTRS(tCK * memSpec.memtimingspec.WTRS), + tWTRL(tCK * memSpec.memtimingspec.WTRL), + tPD(tCK * memSpec.memtimingspec.PD), + tCKESR(tCK * memSpec.memtimingspec.CKESR), + tXP(tCK * memSpec.memtimingspec.XP), + tREFI(tCK * memSpec.memtimingspec.REFI), + tREFIpb(tCK * memSpec.memtimingspec.REFIpb), + tRFCab(tCK * memSpec.memtimingspec.RFCab), + tRFCpb(tCK * memSpec.memtimingspec.RFCpb), + tRREFD(tCK * memSpec.memtimingspec.RREFD), + tXS(tCK * memSpec.memtimingspec.XS), + tFAW(tCK * memSpec.memtimingspec.FAW), + tPPD(tCK * memSpec.memtimingspec.PPD), + tLK(tCK * memSpec.memtimingspec.LK), + tACTPDE(tCK * memSpec.memtimingspec.ACTPDE), + tPREPDE(tCK * memSpec.memtimingspec.PREPDE), + tREFPDE(tCK * memSpec.memtimingspec.REFPDE), + tRTRS(tCK * memSpec.memtimingspec.RTRS), + per2BankOffset(memSpec.memarchitecturespec.per2BankOffset) { uint64_t deviceSizeBits = static_cast(banksPerRank) * rowsPerBank * columnsPerRow * bitWidth; diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR6.h b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR6.h index 4cba78d4..f5394eae 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR6.h +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR6.h @@ -32,6 +32,7 @@ * Authors: * Lukas Steiner * Derek Christ + * Marco Mörz */ #ifndef MEMSPECGDDR6_H @@ -39,14 +40,17 @@ #include "DRAMSys/configuration/memspec/MemSpec.h" +#include + #include + namespace DRAMSys { struct MemSpecGDDR6 final : public MemSpec { public: - explicit MemSpecGDDR6(const Config::MemSpec& memSpec); + explicit MemSpecGDDR6(const DRAMUtils::MemSpec::MemSpecGDDR6& memSpec); // Memspec Variables: const sc_core::sc_time tRP; diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecHBM2.cpp b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecHBM2.cpp index 7ae285e7..b845667c 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecHBM2.cpp +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecHBM2.cpp @@ -32,6 +32,7 @@ * Authors: * Lukas Steiner * Derek Christ + * Marco Mörz */ #include "MemSpecHBM2.h" @@ -46,50 +47,50 @@ using namespace tlm; namespace DRAMSys { -MemSpecHBM2::MemSpecHBM2(const Config::MemSpec& memSpec) : +MemSpecHBM2::MemSpecHBM2(const DRAMUtils::MemSpec::MemSpecHBM2& memSpec) : MemSpec(memSpec, - memSpec.memarchitecturespec.entries.at("nbrOfChannels"), - memSpec.memarchitecturespec.entries.at("nbrOfPseudoChannels"), - memSpec.memarchitecturespec.entries.at("nbrOfBanks"), - memSpec.memarchitecturespec.entries.at("nbrOfBankGroups"), - memSpec.memarchitecturespec.entries.at("nbrOfBanks") / - memSpec.memarchitecturespec.entries.at("nbrOfBankGroups"), - memSpec.memarchitecturespec.entries.at("nbrOfBanks") * - memSpec.memarchitecturespec.entries.at("nbrOfPseudoChannels"), - memSpec.memarchitecturespec.entries.at("nbrOfBankGroups") * - memSpec.memarchitecturespec.entries.at("nbrOfPseudoChannels"), - memSpec.memarchitecturespec.entries.at("nbrOfDevices")), - stacksPerChannel(memSpec.memarchitecturespec.entries.at("nbrOfStacks")), - tDQSCK(tCK * memSpec.memtimingspec.entries.at("DQSCK")), - tRC(tCK * memSpec.memtimingspec.entries.at("RC")), - tRAS(tCK * memSpec.memtimingspec.entries.at("RAS")), - tRCDRD(tCK * memSpec.memtimingspec.entries.at("RCDRD")), - tRCDWR(tCK * memSpec.memtimingspec.entries.at("RCDWR")), - tRRDL(tCK * memSpec.memtimingspec.entries.at("RRDL")), - tRRDS(tCK * memSpec.memtimingspec.entries.at("RRDS")), - tFAW(tCK * memSpec.memtimingspec.entries.at("FAW")), - tRTP(tCK * memSpec.memtimingspec.entries.at("RTP")), - tRP(tCK * memSpec.memtimingspec.entries.at("RP")), - tRL(tCK * memSpec.memtimingspec.entries.at("RL")), - tWL(tCK * memSpec.memtimingspec.entries.at("WL")), - tPL(tCK * memSpec.memtimingspec.entries.at("PL")), - tWR(tCK * memSpec.memtimingspec.entries.at("WR")), - tCCDL(tCK * memSpec.memtimingspec.entries.at("CCDL")), - tCCDS(tCK * memSpec.memtimingspec.entries.at("CCDS")), - tCCDR(tCK * memSpec.memtimingspec.entries.at("CCDR")), - tWTRL(tCK * memSpec.memtimingspec.entries.at("WTRL")), - tWTRS(tCK * memSpec.memtimingspec.entries.at("WTRS")), - tRTW(tCK * memSpec.memtimingspec.entries.at("RTW")), - tXP(tCK * memSpec.memtimingspec.entries.at("XP")), - tCKE(tCK * memSpec.memtimingspec.entries.at("CKE")), + memSpec.memarchitecturespec.nbrOfChannels, + memSpec.memarchitecturespec.nbrOfPseudoChannels, + memSpec.memarchitecturespec.nbrOfBanks, + memSpec.memarchitecturespec.nbrOfBankGroups, + memSpec.memarchitecturespec.nbrOfBanks / + memSpec.memarchitecturespec.nbrOfBankGroups, + memSpec.memarchitecturespec.nbrOfBanks * + memSpec.memarchitecturespec.nbrOfPseudoChannels, + memSpec.memarchitecturespec.nbrOfBankGroups * + memSpec.memarchitecturespec.nbrOfPseudoChannels, + memSpec.memarchitecturespec.nbrOfDevices), + stacksPerChannel(memSpec.memarchitecturespec.nbrOfStacks), + tDQSCK(tCK * memSpec.memtimingspec.DQSCK), + tRC(tCK * memSpec.memtimingspec.RC), + tRAS(tCK * memSpec.memtimingspec.RAS), + tRCDRD(tCK * memSpec.memtimingspec.RCDRD), + tRCDWR(tCK * memSpec.memtimingspec.RCDWR), + tRRDL(tCK * memSpec.memtimingspec.RRDL), + tRRDS(tCK * memSpec.memtimingspec.RRDS), + tFAW(tCK * memSpec.memtimingspec.FAW), + tRTP(tCK * memSpec.memtimingspec.RTP), + tRP(tCK * memSpec.memtimingspec.RP), + tRL(tCK * memSpec.memtimingspec.RL), + tWL(tCK * memSpec.memtimingspec.WL), + tPL(tCK * memSpec.memtimingspec.PL), + tWR(tCK * memSpec.memtimingspec.WR), + tCCDL(tCK * memSpec.memtimingspec.CCDL), + tCCDS(tCK * memSpec.memtimingspec.CCDS), + tCCDR(tCK * memSpec.memtimingspec.CCDR), + tWTRL(tCK * memSpec.memtimingspec.WTRL), + tWTRS(tCK * memSpec.memtimingspec.WTRS), + tRTW(tCK * memSpec.memtimingspec.RTW), + tXP(tCK * memSpec.memtimingspec.XP), + tCKE(tCK * memSpec.memtimingspec.CKE), tPD(tCKE), tCKESR(tCKE + tCK), - tXS(tCK * memSpec.memtimingspec.entries.at("XS")), - tRFC(tCK * memSpec.memtimingspec.entries.at("RFC")), - tRFCSB(tCK * memSpec.memtimingspec.entries.at("RFCSB")), - tRREFD(tCK * memSpec.memtimingspec.entries.at("RREFD")), - tREFI(tCK * memSpec.memtimingspec.entries.at("REFI")), - tREFISB(tCK * memSpec.memtimingspec.entries.at("REFISB")) + tXS(tCK * memSpec.memtimingspec.XS), + tRFC(tCK * memSpec.memtimingspec.RFC), + tRFCSB(tCK * memSpec.memtimingspec.RFCSB), + tRREFD(tCK * memSpec.memtimingspec.RREFD), + tREFI(tCK * memSpec.memtimingspec.REFI), + tREFISB(tCK * memSpec.memtimingspec.REFISB) { commandLengthInCycles[Command::ACT] = 2; diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecHBM2.h b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecHBM2.h index 4ec04607..09a2dcdf 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecHBM2.h +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecHBM2.h @@ -32,6 +32,7 @@ * Authors: * Lukas Steiner * Derek Christ + * Marco Mörz */ #ifndef MEMSPECHBM2_H @@ -39,6 +40,8 @@ #include "DRAMSys/configuration/memspec/MemSpec.h" +#include + #include namespace DRAMSys @@ -47,7 +50,7 @@ namespace DRAMSys class MemSpecHBM2 final : public MemSpec { public: - explicit MemSpecHBM2(const Config::MemSpec& memSpec); + explicit MemSpecHBM2(const DRAMUtils::MemSpec::MemSpecHBM2& memSpec); // Memspec Variables: const unsigned stacksPerChannel; diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecLPDDR4.cpp b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecLPDDR4.cpp index c55bfa85..2a33dd47 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecLPDDR4.cpp +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecLPDDR4.cpp @@ -32,6 +32,7 @@ * Authors: * Lukas Steiner * Derek Christ + * Marco Mörz */ #include "MemSpecLPDDR4.h" @@ -46,49 +47,50 @@ using namespace tlm; namespace DRAMSys { -MemSpecLPDDR4::MemSpecLPDDR4(const Config::MemSpec& memSpec) : +MemSpecLPDDR4::MemSpecLPDDR4(const DRAMUtils::MemSpec::MemSpecLPDDR4& memSpec) : MemSpec(memSpec, - memSpec.memarchitecturespec.entries.at("nbrOfChannels"), - memSpec.memarchitecturespec.entries.at("nbrOfRanks"), - memSpec.memarchitecturespec.entries.at("nbrOfBanks"), + memSpec.memarchitecturespec.nbrOfChannels, + memSpec.memarchitecturespec.nbrOfRanks, + memSpec.memarchitecturespec.nbrOfBanks, 1, - memSpec.memarchitecturespec.entries.at("nbrOfBanks"), - memSpec.memarchitecturespec.entries.at("nbrOfBanks") * - memSpec.memarchitecturespec.entries.at("nbrOfRanks"), - memSpec.memarchitecturespec.entries.at("nbrOfRanks"), - memSpec.memarchitecturespec.entries.at("nbrOfDevices")), - tREFI(tCK * memSpec.memtimingspec.entries.at("REFI")), - tREFIpb(tCK * memSpec.memtimingspec.entries.at("REFIPB")), - tRFCab(tCK * memSpec.memtimingspec.entries.at("RFCAB")), - tRFCpb(tCK * memSpec.memtimingspec.entries.at("RFCPB")), - tRAS(tCK * memSpec.memtimingspec.entries.at("RAS")), - tRPab(tCK * memSpec.memtimingspec.entries.at("RPAB")), - tRPpb(tCK * memSpec.memtimingspec.entries.at("RPPB")), - tRCpb(tCK * memSpec.memtimingspec.entries.at("RCPB")), - tRCab(tCK * memSpec.memtimingspec.entries.at("RCAB")), - tPPD(tCK * memSpec.memtimingspec.entries.at("PPD")), - tRCD(tCK * memSpec.memtimingspec.entries.at("RCD")), - tFAW(tCK * memSpec.memtimingspec.entries.at("FAW")), - tRRD(tCK * memSpec.memtimingspec.entries.at("RRD")), - tCCD(tCK * memSpec.memtimingspec.entries.at("CCD")), - tCCDMW(tCK * memSpec.memtimingspec.entries.at("CCDMW")), - tRL(tCK * memSpec.memtimingspec.entries.at("RL")), - tRPST(tCK * memSpec.memtimingspec.entries.at("RPST")), - tDQSCK(tCK * memSpec.memtimingspec.entries.at("DQSCK")), - tRTP(tCK * memSpec.memtimingspec.entries.at("RTP")), - tWL(tCK * memSpec.memtimingspec.entries.at("WL")), - tDQSS(tCK * memSpec.memtimingspec.entries.at("DQSS")), - tDQS2DQ(tCK * memSpec.memtimingspec.entries.at("DQS2DQ")), - tWR(tCK * memSpec.memtimingspec.entries.at("WR")), - tWPRE(tCK * memSpec.memtimingspec.entries.at("WPRE")), - tWTR(tCK * memSpec.memtimingspec.entries.at("WTR")), - tXP(tCK * memSpec.memtimingspec.entries.at("XP")), - tSR(tCK * memSpec.memtimingspec.entries.at("SR")), - tXSR(tCK * memSpec.memtimingspec.entries.at("XSR")), - tESCKE(tCK * memSpec.memtimingspec.entries.at("ESCKE")), - tCKE(tCK * memSpec.memtimingspec.entries.at("CKE")), - tCMDCKE(tCK * memSpec.memtimingspec.entries.at("CMDCKE")), - tRTRS(tCK * memSpec.memtimingspec.entries.at("RTRS")) + memSpec.memarchitecturespec.nbrOfBanks, + memSpec.memarchitecturespec.nbrOfBanks * + memSpec.memarchitecturespec.nbrOfRanks, + memSpec.memarchitecturespec.nbrOfRanks, + memSpec.memarchitecturespec.nbrOfDevices), + memSpec(memSpec), + tREFI(tCK * memSpec.memtimingspec.REFI), + tREFIpb(tCK * memSpec.memtimingspec.REFIpb), + tRFCab(tCK * memSpec.memtimingspec.RFCab), + tRFCpb(tCK * memSpec.memtimingspec.RFCpb), + tRAS(tCK * memSpec.memtimingspec.RAS), + tRPab(tCK * memSpec.memtimingspec.RPab), + tRPpb(tCK * memSpec.memtimingspec.RPpb), + tRCpb(tCK * memSpec.memtimingspec.RCpb), + tRCab(tCK * memSpec.memtimingspec.RCab), + tPPD(tCK * memSpec.memtimingspec.PPD), + tRCD(tCK * memSpec.memtimingspec.RCD), + tFAW(tCK * memSpec.memtimingspec.FAW), + tRRD(tCK * memSpec.memtimingspec.RRD), + tCCD(tCK * memSpec.memtimingspec.CCD), + tCCDMW(tCK * memSpec.memtimingspec.CCDMW), + tRL(tCK * memSpec.memtimingspec.RL), + tRPST(tCK * memSpec.memtimingspec.RPST), + tDQSCK(tCK * memSpec.memtimingspec.DQSCK), + tRTP(tCK * memSpec.memtimingspec.RTP), + tWL(tCK * memSpec.memtimingspec.WL), + tDQSS(tCK * memSpec.memtimingspec.DQSS), + tDQS2DQ(tCK * memSpec.memtimingspec.DQS2DQ), + tWR(tCK * memSpec.memtimingspec.WR), + tWPRE(tCK * memSpec.memtimingspec.WPRE), + tWTR(tCK * memSpec.memtimingspec.WTR), + tXP(tCK * memSpec.memtimingspec.XP), + tSR(tCK * memSpec.memtimingspec.SR), + tXSR(tCK * memSpec.memtimingspec.XSR), + tESCKE(tCK * memSpec.memtimingspec.ESCKE), + tCKE(tCK * memSpec.memtimingspec.CKE), + tCMDCKE(tCK * memSpec.memtimingspec.CMDCKE), + tRTRS(tCK * memSpec.memtimingspec.RTRS) { commandLengthInCycles[Command::ACT] = 4; commandLengthInCycles[Command::PREPB] = 2; @@ -186,6 +188,13 @@ MemSpecLPDDR4::getIntervalOnDataStrobe(Command command, throw; } +#ifdef DRAMPOWER +std::unique_ptr> MemSpecLPDDR4::toDramPowerObject() const +{ + return std::make_unique(std::move(DRAMPower::MemSpecLPDDR4(memSpec))); +} +#endif + bool MemSpecLPDDR4::requiresMaskedWrite(const tlm::tlm_generic_payload& payload) const { return !allBytesEnabled(payload); diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecLPDDR4.h b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecLPDDR4.h index 82913340..55ce805f 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecLPDDR4.h +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecLPDDR4.h @@ -32,6 +32,7 @@ * Authors: * Lukas Steiner * Derek Christ + * Marco Mörz */ #ifndef MEMSPECLPDDR4_H @@ -39,6 +40,13 @@ #include "DRAMSys/configuration/memspec/MemSpec.h" +#include + +#ifdef DRAMPOWER +#include "DRAMPower/standards/lpddr4/LPDDR4.h" +#include "DRAMPower/memspec/MemSpecLPDDR4.h" +#endif + #include namespace DRAMSys @@ -47,9 +55,10 @@ namespace DRAMSys class MemSpecLPDDR4 final : public MemSpec { public: - explicit MemSpecLPDDR4(const Config::MemSpec& memSpec); + explicit MemSpecLPDDR4(const DRAMUtils::MemSpec::MemSpecLPDDR4& memSpec); // Memspec Variables: + const DRAMUtils::MemSpec::MemSpecLPDDR4& memSpec; const sc_core::sc_time tREFI; const sc_core::sc_time tREFIpb; const sc_core::sc_time tRFCab; @@ -96,6 +105,11 @@ public: const tlm::tlm_generic_payload& payload) const override; [[nodiscard]] bool requiresMaskedWrite(const tlm::tlm_generic_payload& payload) const override; + +#ifdef DRAMPOWER + [[nodiscard]] std::unique_ptr> toDramPowerObject() const override; +#endif + }; } // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecSTTMRAM.cpp b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecSTTMRAM.cpp index f56abcbb..9a34495b 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecSTTMRAM.cpp +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecSTTMRAM.cpp @@ -32,6 +32,7 @@ * Authors: * Lukas Steiner * Derek Christ + * Marco Mörz */ #include "MemSpecSTTMRAM.h" @@ -46,41 +47,41 @@ using namespace tlm; namespace DRAMSys { -MemSpecSTTMRAM::MemSpecSTTMRAM(const Config::MemSpec& memSpec) : +MemSpecSTTMRAM::MemSpecSTTMRAM(const DRAMUtils::MemSpec::MemSpecSTTMRAM& memSpec) : MemSpec(memSpec, - memSpec.memarchitecturespec.entries.at("nbrOfChannels"), - memSpec.memarchitecturespec.entries.at("nbrOfRanks"), - memSpec.memarchitecturespec.entries.at("nbrOfBanks"), + memSpec.memarchitecturespec.nbrOfChannels, + memSpec.memarchitecturespec.nbrOfRanks, + memSpec.memarchitecturespec.nbrOfBanks, 1, - memSpec.memarchitecturespec.entries.at("nbrOfBanks"), - memSpec.memarchitecturespec.entries.at("nbrOfBanks") * - memSpec.memarchitecturespec.entries.at("nbrOfRanks"), - memSpec.memarchitecturespec.entries.at("nbrOfRanks"), - memSpec.memarchitecturespec.entries.at("nbrOfDevices")), - tCKE(tCK * memSpec.memtimingspec.entries.at("CKE")), + memSpec.memarchitecturespec.nbrOfBanks, + memSpec.memarchitecturespec.nbrOfBanks * + memSpec.memarchitecturespec.nbrOfRanks, + memSpec.memarchitecturespec.nbrOfRanks, + memSpec.memarchitecturespec.nbrOfDevices), + tCKE(tCK * memSpec.memtimingspec.CKE), tPD(tCKE), - tCKESR(tCK * memSpec.memtimingspec.entries.at("CKESR")), - tRAS(tCK * memSpec.memtimingspec.entries.at("RAS")), - tRC(tCK * memSpec.memtimingspec.entries.at("RC")), - tRCD(tCK * memSpec.memtimingspec.entries.at("RCD")), - tRL(tCK * memSpec.memtimingspec.entries.at("RL")), - tRTP(tCK * memSpec.memtimingspec.entries.at("RTP")), - tWL(tCK * memSpec.memtimingspec.entries.at("WL")), - tWR(tCK * memSpec.memtimingspec.entries.at("WR")), - tXP(tCK * memSpec.memtimingspec.entries.at("XP")), - tXS(tCK * memSpec.memtimingspec.entries.at("XS")), - tRP(tCK * memSpec.memtimingspec.entries.at("RP")), - tDQSCK(tCK * memSpec.memtimingspec.entries.at("DQSCK")), - tCCD(tCK * memSpec.memtimingspec.entries.at("CCD")), - tFAW(tCK * memSpec.memtimingspec.entries.at("FAW")), - tRRD(tCK * memSpec.memtimingspec.entries.at("RRD")), - tWTR(tCK * memSpec.memtimingspec.entries.at("WTR")), - tXPDLL(tCK * memSpec.memtimingspec.entries.at("XPDLL")), - tXSDLL(tCK * memSpec.memtimingspec.entries.at("XSDLL")), - tAL(tCK * memSpec.memtimingspec.entries.at("AL")), - tACTPDEN(tCK * memSpec.memtimingspec.entries.at("ACTPDEN")), - tPRPDEN(tCK * memSpec.memtimingspec.entries.at("PRPDEN")), - tRTRS(tCK * memSpec.memtimingspec.entries.at("RTRS")) + tCKESR(tCK * memSpec.memtimingspec.CKESR), + tRAS(tCK * memSpec.memtimingspec.RAS), + tRC(tCK * memSpec.memtimingspec.RC), + tRCD(tCK * memSpec.memtimingspec.RCD), + tRL(tCK * memSpec.memtimingspec.RL), + tRTP(tCK * memSpec.memtimingspec.RTP), + tWL(tCK * memSpec.memtimingspec.WL), + tWR(tCK * memSpec.memtimingspec.WR), + tXP(tCK * memSpec.memtimingspec.XP), + tXS(tCK * memSpec.memtimingspec.XS), + tRP(tCK * memSpec.memtimingspec.RP), + tDQSCK(tCK * memSpec.memtimingspec.DQSCK), + tCCD(tCK * memSpec.memtimingspec.CCD), + tFAW(tCK * memSpec.memtimingspec.FAW), + tRRD(tCK * memSpec.memtimingspec.RRD), + tWTR(tCK * memSpec.memtimingspec.WTR), + tXPDLL(tCK * memSpec.memtimingspec.XPDLL), + tXSDLL(tCK * memSpec.memtimingspec.XSDLL), + tAL(tCK * memSpec.memtimingspec.AL), + tACTPDEN(tCK * memSpec.memtimingspec.ACTPDEN), + tPRPDEN(tCK * memSpec.memtimingspec.PRPDEN), + tRTRS(tCK * memSpec.memtimingspec.RTRS) { uint64_t deviceSizeBits = static_cast(banksPerRank) * rowsPerBank * columnsPerRow * bitWidth; diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecSTTMRAM.h b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecSTTMRAM.h index ba5064a5..4e039f88 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecSTTMRAM.h +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecSTTMRAM.h @@ -39,6 +39,8 @@ #include "DRAMSys/configuration/memspec/MemSpec.h" +#include + #include namespace DRAMSys @@ -47,7 +49,7 @@ namespace DRAMSys class MemSpecSTTMRAM final : public MemSpec { public: - explicit MemSpecSTTMRAM(const Config::MemSpec& memSpec); + explicit MemSpecSTTMRAM(const DRAMUtils::MemSpec::MemSpecSTTMRAM& memSpec); // Memspec Variables: const sc_core::sc_time tCKE; diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO.cpp b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO.cpp index b89b9162..fa59d879 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO.cpp +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO.cpp @@ -32,6 +32,7 @@ * Authors: * Lukas Steiner * Derek Christ + * Marco Mörz */ #include "MemSpecWideIO.h" @@ -46,83 +47,44 @@ using namespace tlm; namespace DRAMSys { -MemSpecWideIO::MemSpecWideIO(const Config::MemSpec& memSpec) : +MemSpecWideIO::MemSpecWideIO(const DRAMUtils::MemSpec::MemSpecWideIO& memSpec) : MemSpec(memSpec, - memSpec.memarchitecturespec.entries.at("nbrOfChannels"), - memSpec.memarchitecturespec.entries.at("nbrOfRanks"), - memSpec.memarchitecturespec.entries.at("nbrOfBanks"), + memSpec.memarchitecturespec.nbrOfChannels, + memSpec.memarchitecturespec.nbrOfRanks, + memSpec.memarchitecturespec.nbrOfBanks, 1, - memSpec.memarchitecturespec.entries.at("nbrOfBanks"), - memSpec.memarchitecturespec.entries.at("nbrOfBanks") * - memSpec.memarchitecturespec.entries.at("nbrOfRanks"), - memSpec.memarchitecturespec.entries.at("nbrOfRanks"), - memSpec.memarchitecturespec.entries.at("nbrOfDevices")), - tCKE(tCK * memSpec.memtimingspec.entries.at("CKE")), - tCKESR(tCK * memSpec.memtimingspec.entries.at("CKESR")), - tRAS(tCK * memSpec.memtimingspec.entries.at("RAS")), - tRC(tCK * memSpec.memtimingspec.entries.at("RC")), - tRCD(tCK * memSpec.memtimingspec.entries.at("RCD")), - tRL(tCK * memSpec.memtimingspec.entries.at("RL")), - tWL(tCK * memSpec.memtimingspec.entries.at("WL")), - tWR(tCK * memSpec.memtimingspec.entries.at("WR")), - tXP(tCK * memSpec.memtimingspec.entries.at("XP")), - tXSR(tCK * memSpec.memtimingspec.entries.at("XSR")), - tREFI(tCK * memSpec.memtimingspec.entries.at("REFI")), - tRFC(tCK * memSpec.memtimingspec.entries.at("RFC")), - tRP(tCK * memSpec.memtimingspec.entries.at("RP")), - tDQSCK(tCK * memSpec.memtimingspec.entries.at("DQSCK")), - tAC(tCK * memSpec.memtimingspec.entries.at("AC")), - tCCD_R(tCK * memSpec.memtimingspec.entries.at("CCD_R")), - tCCD_W(tCK * memSpec.memtimingspec.entries.at("CCD_W")), - tRRD(tCK * memSpec.memtimingspec.entries.at("RRD")), - tTAW(tCK * memSpec.memtimingspec.entries.at("TAW")), - tWTR(tCK * memSpec.memtimingspec.entries.at("WTR")), - tRTRS(tCK * memSpec.memtimingspec.entries.at("RTRS")), - iDD0(memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd0") : 0), - iDD2N(memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd2n") : 0), - iDD3N(memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd3n") : 0), - iDD4R(memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd4r") : 0), - iDD4W(memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd4w") : 0), - iDD5(memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd5") : 0), - iDD6(memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd6") : 0), - vDD(memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("vdd") : 0), - iDD02(memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd02") : 0), - iDD2P0(memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd2p0") - : 0), - iDD2P02(memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd2p02") - : 0), - iDD2P1(memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd2p1") - : 0), - iDD2P12(memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd2p12") - : 0), - iDD2N2(memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd2n2") - : 0), - iDD3P0(memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd3p0") - : 0), - iDD3P02(memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd3p02") - : 0), - iDD3P1(memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd3p1") - : 0), - iDD3P12(memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd3p12") - : 0), - iDD3N2(memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd3n2") - : 0), - iDD4R2(memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd4r2") - : 0), - iDD4W2(memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd4w2") - : 0), - iDD52(memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd52") : 0), - iDD62(memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd62") : 0), - vDD2(memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("vdd2") : 0) + memSpec.memarchitecturespec.nbrOfBanks, + memSpec.memarchitecturespec.nbrOfBanks * + memSpec.memarchitecturespec.nbrOfRanks, + memSpec.memarchitecturespec.nbrOfRanks, + memSpec.memarchitecturespec.nbrOfDevices), + tCKE(tCK * memSpec.memtimingspec.CKE), + tCKESR(tCK * memSpec.memtimingspec.CKESR), + tRAS(tCK * memSpec.memtimingspec.RAS), + tRC(tCK * memSpec.memtimingspec.RC), + tRCD(tCK * memSpec.memtimingspec.RCD), + tRL(tCK * memSpec.memtimingspec.RL), + tWL(tCK * memSpec.memtimingspec.WL), + tWR(tCK * memSpec.memtimingspec.WR), + tXP(tCK * memSpec.memtimingspec.XP), + tXSR(tCK * memSpec.memtimingspec.XSR), + tREFI(tCK * memSpec.memtimingspec.REFI), + tRFC(tCK * memSpec.memtimingspec.RFC), + tRP(tCK * memSpec.memtimingspec.RP), + tDQSCK(tCK * memSpec.memtimingspec.DQSCK), + tAC(tCK * memSpec.memtimingspec.AC), + tCCD_R(tCK * memSpec.memtimingspec.CCD_R), + tCCD_W(tCK * memSpec.memtimingspec.CCD_W), + tRRD(tCK * memSpec.memtimingspec.RRD), + tTAW(tCK * memSpec.memtimingspec.TAW), + tWTR(tCK * memSpec.memtimingspec.WTR), + tRTRS(tCK * memSpec.memtimingspec.RTRS) { uint64_t deviceSizeBits = static_cast(banksPerRank) * rowsPerBank * columnsPerRow * bitWidth; uint64_t deviceSizeBytes = deviceSizeBits / 8; memorySizeBytes = deviceSizeBytes * ranksPerChannel * numberOfChannels; - if (!memSpec.mempowerspec.has_value()) - SC_REPORT_FATAL("MemSpec", "No power spec defined!"); - std::cout << headline << std::endl; std::cout << "Memory Configuration:" << std::endl << std::endl; std::cout << " Memory type: " @@ -195,97 +157,4 @@ bool MemSpecWideIO::requiresMaskedWrite(const tlm::tlm_generic_payload& payload) return !allBytesEnabled(payload); } -#ifdef DRAMPOWER -DRAMPower::MemorySpecification MemSpecWideIO::toDramPowerMemSpec() const -{ - DRAMPower::MemArchitectureSpec memArchSpec; - memArchSpec.burstLength = defaultBurstLength; - memArchSpec.dataRate = dataRate; - memArchSpec.nbrOfRows = rowsPerBank; - memArchSpec.nbrOfBanks = banksPerChannel; - memArchSpec.nbrOfColumns = columnsPerRow; - memArchSpec.nbrOfRanks = ranksPerChannel; - memArchSpec.width = bitWidth; - memArchSpec.nbrOfBankGroups = bankGroupsPerChannel; - memArchSpec.twoVoltageDomains = true; - memArchSpec.dll = false; - - DRAMPower::MemTimingSpec memTimingSpec; - // FIXME: memTimingSpec.FAWB = tTAW / tCK; - // FIXME: memTimingSpec.RASB = tRAS / tCK; - // FIXME: memTimingSpec.RCB = tRC / tCK; - // FIXME: memTimingSpec.RPB = tRP / tCK; - // FIXME: memTimingSpec.RRDB = tRRD / tCK; - // FIXME: memTimingSpec.RRDB_L = tRRD / tCK; - // FIXME: memTimingSpec.RRDB_S = tRRD / tCK; - memTimingSpec.AL = 0; - memTimingSpec.CCD = defaultBurstLength; - memTimingSpec.CCD_L = defaultBurstLength; - memTimingSpec.CCD_S = defaultBurstLength; - memTimingSpec.CKE = tCKE / tCK; - memTimingSpec.CKESR = tCKESR / tCK; - // See also MemTimingSpec.cc in DRAMPower - memTimingSpec.clkMhz = 1 / (tCK.to_seconds() * 1'000'000); - memTimingSpec.clkPeriod = tCK.to_seconds() * 1'000'000'000; - memTimingSpec.DQSCK = tDQSCK / tCK; - memTimingSpec.FAW = tTAW / tCK; - memTimingSpec.RAS = tRAS / tCK; - memTimingSpec.RC = tRC / tCK; - memTimingSpec.RCD = tRCD / tCK; - memTimingSpec.REFI = tREFI / tCK; - memTimingSpec.RFC = tRFC / tCK; - memTimingSpec.RL = tRL / tCK; - memTimingSpec.RP = tRP / tCK; - memTimingSpec.RRD = tRRD / tCK; - memTimingSpec.RRD_L = tRRD / tCK; - memTimingSpec.RRD_S = tRRD / tCK; - memTimingSpec.RTP = defaultBurstLength; - memTimingSpec.TAW = tTAW / tCK; - memTimingSpec.WL = tWL / tCK; - memTimingSpec.WR = tWR / tCK; - memTimingSpec.WTR = tWTR / tCK; - memTimingSpec.WTR_L = tWTR / tCK; - memTimingSpec.WTR_S = tWTR / tCK; - memTimingSpec.XP = tXP / tCK; - memTimingSpec.XPDLL = tXP / tCK; - memTimingSpec.XS = tXSR / tCK; - memTimingSpec.XSDLL = tXSR / tCK; - - DRAMPower::MemPowerSpec memPowerSpec; - memPowerSpec.idd0 = iDD0; - memPowerSpec.idd02 = iDD02; - memPowerSpec.idd2p0 = iDD2P0; - memPowerSpec.idd2p02 = iDD2P02; - memPowerSpec.idd2p1 = iDD2P1; - memPowerSpec.idd2p12 = iDD2P12; - memPowerSpec.idd2n = iDD2N; - memPowerSpec.idd2n2 = iDD2N2; - memPowerSpec.idd3p0 = iDD3P0; - memPowerSpec.idd3p02 = iDD3P02; - memPowerSpec.idd3p1 = iDD3P1; - memPowerSpec.idd3p12 = iDD3P12; - memPowerSpec.idd3n = iDD3N; - memPowerSpec.idd3n2 = iDD3N2; - memPowerSpec.idd4r = iDD4R; - memPowerSpec.idd4r2 = iDD4R2; - memPowerSpec.idd4w = iDD4W; - memPowerSpec.idd4w2 = iDD4W2; - memPowerSpec.idd5 = iDD5; - memPowerSpec.idd52 = iDD52; - memPowerSpec.idd6 = iDD6; - memPowerSpec.idd62 = iDD62; - memPowerSpec.vdd = vDD; - memPowerSpec.vdd2 = vDD2; - - DRAMPower::MemorySpecification powerSpec; - powerSpec.id = memoryId; - powerSpec.memoryType = DRAMPower::MemoryType::WIDEIO_SDR; - powerSpec.memTimingSpec = memTimingSpec; - powerSpec.memPowerSpec = memPowerSpec; - powerSpec.memArchSpec = memArchSpec; - - return powerSpec; -} -#endif - } // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO.h b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO.h index ed80398f..a67e6ef9 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO.h +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO.h @@ -32,6 +32,7 @@ * Authors: * Lukas Steiner * Derek Christ + * Marco Mörz */ #ifndef MEMSPECWIDEIO_H @@ -39,6 +40,8 @@ #include "DRAMSys/configuration/memspec/MemSpec.h" +#include + #include namespace DRAMSys @@ -47,7 +50,7 @@ namespace DRAMSys class MemSpecWideIO final : public MemSpec { public: - explicit MemSpecWideIO(const Config::MemSpec& memSpec); + explicit MemSpecWideIO(const DRAMUtils::MemSpec::MemSpecWideIO& memSpec); // Memspec Variables: const sc_core::sc_time tCKE; @@ -72,32 +75,6 @@ public: const sc_core::sc_time tWTR; const sc_core::sc_time tRTRS; - // Currents and Voltages: - const double iDD0; - const double iDD2N; - const double iDD3N; - const double iDD4R; - const double iDD4W; - const double iDD5; - const double iDD6; - const double vDD; - const double iDD02; - const double iDD2P0; - const double iDD2P02; - const double iDD2P1; - const double iDD2P12; - const double iDD2N2; - const double iDD3P0; - const double iDD3P02; - const double iDD3P1; - const double iDD3P12; - const double iDD3N2; - const double iDD4R2; - const double iDD4W2; - const double iDD52; - const double iDD62; - const double vDD2; - [[nodiscard]] sc_core::sc_time getRefreshIntervalAB() const override; [[nodiscard]] sc_core::sc_time @@ -107,10 +84,6 @@ public: const tlm::tlm_generic_payload& payload) const override; [[nodiscard]] bool requiresMaskedWrite(const tlm::tlm_generic_payload& payload) const override; - -#ifdef DRAMPOWER - [[nodiscard]] DRAMPower::MemorySpecification toDramPowerMemSpec() const override; -#endif }; } // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO2.cpp b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO2.cpp index c7f89431..586c6951 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO2.cpp +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO2.cpp @@ -32,6 +32,7 @@ * Authors: * Lukas Steiner * Derek Christ + * Marco Mörz */ #include "MemSpecWideIO2.h" @@ -46,44 +47,44 @@ using namespace tlm; namespace DRAMSys { -MemSpecWideIO2::MemSpecWideIO2(const Config::MemSpec& memSpec) : +MemSpecWideIO2::MemSpecWideIO2(const DRAMUtils::MemSpec::MemSpecWideIO2& memSpec) : MemSpec(memSpec, - memSpec.memarchitecturespec.entries.at("nbrOfChannels"), - memSpec.memarchitecturespec.entries.at("nbrOfRanks"), - memSpec.memarchitecturespec.entries.at("nbrOfBanks"), + memSpec.memarchitecturespec.nbrOfChannels, + memSpec.memarchitecturespec.nbrOfRanks, + memSpec.memarchitecturespec.nbrOfBanks, 1, - memSpec.memarchitecturespec.entries.at("nbrOfBanks"), - memSpec.memarchitecturespec.entries.at("nbrOfBanks") * - memSpec.memarchitecturespec.entries.at("nbrOfRanks"), - memSpec.memarchitecturespec.entries.at("nbrOfRanks"), - memSpec.memarchitecturespec.entries.at("nbrOfDevices")), - tDQSCK(tCK * memSpec.memtimingspec.entries.at("DQSCK")), - tDQSS(tCK * memSpec.memtimingspec.entries.at("DQSS")), - tCKE(tCK * memSpec.memtimingspec.entries.at("CKE")), - tRL(tCK * memSpec.memtimingspec.entries.at("RL")), - tWL(tCK * memSpec.memtimingspec.entries.at("WL")), - tRCpb(tCK * memSpec.memtimingspec.entries.at("RCPB")), - tRCab(tCK * memSpec.memtimingspec.entries.at("RCAB")), - tCKESR(tCK * memSpec.memtimingspec.entries.at("CKESR")), - tXSR(tCK * memSpec.memtimingspec.entries.at("XSR")), - tXP(tCK * memSpec.memtimingspec.entries.at("XP")), - tCCD(tCK * memSpec.memtimingspec.entries.at("CCD")), - tRTP(tCK * memSpec.memtimingspec.entries.at("RTP")), - tRCD(tCK * memSpec.memtimingspec.entries.at("RCD")), - tRPpb(tCK * memSpec.memtimingspec.entries.at("RPPB")), - tRPab(tCK * memSpec.memtimingspec.entries.at("RPAB")), - tRAS(tCK * memSpec.memtimingspec.entries.at("RAS")), - tWR(tCK * memSpec.memtimingspec.entries.at("WR")), - tWTR(tCK * memSpec.memtimingspec.entries.at("WTR")), - tRRD(tCK * memSpec.memtimingspec.entries.at("RRD")), - tFAW(tCK * memSpec.memtimingspec.entries.at("FAW")), - tREFI(tCK * static_cast(memSpec.memtimingspec.entries.at("REFI") * - memSpec.memtimingspec.entries.at("REFM"))), - tREFIpb(tCK * static_cast(memSpec.memtimingspec.entries.at("REFIPB") * - memSpec.memtimingspec.entries.at("REFM"))), - tRFCab(tCK * memSpec.memtimingspec.entries.at("RFCAB")), - tRFCpb(tCK * memSpec.memtimingspec.entries.at("RFCPB")), - tRTRS(tCK * memSpec.memtimingspec.entries.at("RTRS")) + memSpec.memarchitecturespec.nbrOfBanks, + memSpec.memarchitecturespec.nbrOfBanks * + memSpec.memarchitecturespec.nbrOfRanks, + memSpec.memarchitecturespec.nbrOfRanks, + memSpec.memarchitecturespec.nbrOfDevices), + tDQSCK(tCK * memSpec.memtimingspec.DQSCK), + tDQSS(tCK * memSpec.memtimingspec.DQSS), + tCKE(tCK * memSpec.memtimingspec.CKE), + tRL(tCK * memSpec.memtimingspec.RL), + tWL(tCK * memSpec.memtimingspec.WL), + tRCpb(tCK * memSpec.memtimingspec.RCPB), + tRCab(tCK * memSpec.memtimingspec.RCAB), + tCKESR(tCK * memSpec.memtimingspec.CKESR), + tXSR(tCK * memSpec.memtimingspec.XSR), + tXP(tCK * memSpec.memtimingspec.XP), + tCCD(tCK * memSpec.memtimingspec.CCD), + tRTP(tCK * memSpec.memtimingspec.RTP), + tRCD(tCK * memSpec.memtimingspec.RCD), + tRPpb(tCK * memSpec.memtimingspec.RPPB), + tRPab(tCK * memSpec.memtimingspec.RPAB), + tRAS(tCK * memSpec.memtimingspec.RAS), + tWR(tCK * memSpec.memtimingspec.WR), + tWTR(tCK * memSpec.memtimingspec.WTR), + tRRD(tCK * memSpec.memtimingspec.RRD), + tFAW(tCK * memSpec.memtimingspec.FAW), + tREFI(tCK * static_cast(memSpec.memtimingspec.REFI * + memSpec.memtimingspec.REFM)), + tREFIpb(tCK * static_cast(memSpec.memtimingspec.REFIPB * + memSpec.memtimingspec.REFM)), + tRFCab(tCK * memSpec.memtimingspec.RFCAB), + tRFCpb(tCK * memSpec.memtimingspec.RFCPB), + tRTRS(tCK * memSpec.memtimingspec.RTRS) { uint64_t deviceSizeBits = static_cast(banksPerRank) * rowsPerBank * columnsPerRow * bitWidth; diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO2.h b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO2.h index cf171492..67e683d6 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO2.h +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO2.h @@ -32,6 +32,7 @@ * Authors: * Lukas Steiner * Derek Christ + * Marco Mörz */ #ifndef MEMSPECWIDEIO2_H @@ -39,6 +40,8 @@ #include "DRAMSys/configuration/memspec/MemSpec.h" +#include + #include namespace DRAMSys @@ -47,7 +50,7 @@ namespace DRAMSys class MemSpecWideIO2 final : public MemSpec { public: - explicit MemSpecWideIO2(const Config::MemSpec& memSpec); + explicit MemSpecWideIO2(const DRAMUtils::MemSpec::MemSpecWideIO2& memSpec); // Memspec Variables: const sc_core::sc_time tDQSCK; diff --git a/src/libdramsys/DRAMSys/controller/Command.cpp b/src/libdramsys/DRAMSys/controller/Command.cpp index d66b332c..3752c4d4 100644 --- a/src/libdramsys/DRAMSys/controller/Command.cpp +++ b/src/libdramsys/DRAMSys/controller/Command.cpp @@ -34,6 +34,7 @@ * Robert Gernhardt * Matthias Jung * Lukas Steiner + * Marco Mörz */ #include "Command.h" @@ -82,7 +83,7 @@ Command::Command(Command::Type type) : type(type) Command::Command(tlm_phase phase) { - assert(phase >= BEGIN_NOP && phase <= END_SREF); + assert(phase >= BEGIN_NOP && phase <= END_SREF); // TODO < END_ENUM && type >= 0 static constexpr std::array commandOfPhase = { Command::NOP, // 0 Command::RD, // 1 @@ -115,7 +116,7 @@ Command::Command(tlm_phase phase) std::string Command::toString() const { - assert(type >= Command::NOP && type <= Command::SREFEX); + assert(type >= 0 && type < Command::END_ENUM); // TODO < END_ENUM && type >= 0 static std::array stringOfCommand = { "NOP", // 0 "RD", // 1 @@ -153,7 +154,7 @@ unsigned Command::numberOfCommands() tlm_phase Command::toPhase() const { - assert(type >= Command::NOP && type <= Command::SREFEX); + assert(type >= 0 && type < Command::END_ENUM); static std::array phaseOfCommand = { BEGIN_NOP, // 0 BEGIN_RD, // 1 @@ -185,36 +186,36 @@ tlm_phase Command::toPhase() const } #ifdef DRAMPOWER -MemCommand::cmds phaseToDRAMPowerCommand(tlm_phase phase) +CmdType phaseToDRAMPowerCommand(tlm_phase phase) { - // TODO: add correct phases when DRAMPower supports DDR5 same bank refresh + // TODO missing DSMEN, DSMEX assert(phase >= BEGIN_NOP && phase <= END_SREF); - static std::array phaseOfCommand = { - MemCommand::NOP, // 0 - MemCommand::RD, // 1 - MemCommand::WR, // 2 - MemCommand::NOP, // 3 - MemCommand::RDA, // 4 - MemCommand::WRA, // 5 - MemCommand::NOP, // 6 - MemCommand::ACT, // 7 - MemCommand::PRE, // 8, PREPB - MemCommand::REFB, // 9, REFPB - MemCommand::NOP, // 10, RFMPB - MemCommand::NOP, // 11, REFP2B - MemCommand::NOP, // 12, RFMP2B - MemCommand::NOP, // 13, PRESB - MemCommand::NOP, // 14, REFSB - MemCommand::NOP, // 15, RFMSB - MemCommand::PREA, // 16, PREAB - MemCommand::REF, // 17, REFAB - MemCommand::NOP, // 18, RFMAB - MemCommand::PDN_S_ACT, // 19 - MemCommand::PDN_S_PRE, // 20 - MemCommand::SREN, // 21 - MemCommand::PUP_ACT, // 22 - MemCommand::PUP_PRE, // 23 - MemCommand::SREX // 24 + static std::array phaseOfCommand = { + CmdType::NOP, // 0 + CmdType::RD, // 1 + CmdType::WR, // 2 + CmdType::NOP, // 3 + CmdType::RDA, // 4 + CmdType::WRA, // 5 + CmdType::NOP, // 6 + CmdType::ACT, // 7 + CmdType::PRE, // 8, PREPB + CmdType::REFB, // 9, REFPB + CmdType::NOP, // 10, RFMPB + CmdType::REFP2B, // 11, REFP2B + CmdType::NOP, // 12, RFMP2B + CmdType::PRESB, // 13, PRESB + CmdType::REFSB, // 14, REFSB + CmdType::NOP, // 15, RFMSB + CmdType::PREA, // 16, PREAB + CmdType::REFA, // 17, REFAB + CmdType::NOP, // 18, RFMAB + CmdType::PDEA, // 19 + CmdType::PDEP, // 20 + CmdType::SREFEN, // 21 + CmdType::PDXA, // 22 + CmdType::PDXP, // 23 + CmdType::SREFEX // 24 }; return phaseOfCommand[phase - BEGIN_NOP]; } diff --git a/src/libdramsys/DRAMSys/controller/Command.h b/src/libdramsys/DRAMSys/controller/Command.h index 952be4be..7faa0053 100644 --- a/src/libdramsys/DRAMSys/controller/Command.h +++ b/src/libdramsys/DRAMSys/controller/Command.h @@ -33,12 +33,13 @@ * Janik Schlemminger * Matthias Jung * Lukas Steiner + * Marco Mörz */ #ifndef COMMAND_H #define COMMAND_H #ifdef DRAMPOWER -#include "MemCommand.h" +#include #endif #include @@ -86,7 +87,7 @@ DECLARE_EXTENDED_PHASE(END_PDNP); // 28 DECLARE_EXTENDED_PHASE(END_SREF); // 29 #ifdef DRAMPOWER -DRAMPower::MemCommand::cmds phaseToDRAMPowerCommand(tlm::tlm_phase phase); +DRAMPower::CmdType phaseToDRAMPowerCommand(tlm::tlm_phase phase); #endif bool phaseHasDataStrobe(tlm::tlm_phase phase); diff --git a/src/libdramsys/DRAMSys/controller/Controller.cpp b/src/libdramsys/DRAMSys/controller/Controller.cpp index 89bf5bc3..f1cd0599 100644 --- a/src/libdramsys/DRAMSys/controller/Controller.cpp +++ b/src/libdramsys/DRAMSys/controller/Controller.cpp @@ -32,6 +32,7 @@ * Authors: * Lukas Steiner * Derek Christ + * Marco Mörz */ #include "Controller.h" @@ -64,6 +65,7 @@ #include "DRAMSys/controller/scheduler/SchedulerFrFcfsGrp.h" #include "DRAMSys/controller/scheduler/SchedulerGrpFrFcfs.h" #include "DRAMSys/controller/scheduler/SchedulerGrpFrFcfsWm.h" + #include #include #include @@ -128,62 +130,62 @@ Controller::Controller(const sc_module_name& name, // instantiate timing checker try { - if (memSpec.memoryType == Config::MemoryType::DDR3) + if (memSpec.memoryType == DRAMUtils::MemSpec::MemSpecDDR3::id) { checker = std::make_unique(dynamic_cast(memSpec)); } - else if (memSpec.memoryType == Config::MemoryType::DDR4) + else if (memSpec.memoryType == DRAMUtils::MemSpec::MemSpecDDR4::id) { checker = std::make_unique(dynamic_cast(memSpec)); } - else if (memSpec.memoryType == Config::MemoryType::WideIO) + else if (memSpec.memoryType == DRAMUtils::MemSpec::MemSpecWideIO::id) { checker = std::make_unique(dynamic_cast(memSpec)); } - else if (memSpec.memoryType == Config::MemoryType::LPDDR4) + else if (memSpec.memoryType == DRAMUtils::MemSpec::MemSpecLPDDR4::id) { checker = std::make_unique(dynamic_cast(memSpec)); } - else if (memSpec.memoryType == Config::MemoryType::WideIO2) + else if (memSpec.memoryType == DRAMUtils::MemSpec::MemSpecWideIO2::id) { checker = std::make_unique(dynamic_cast(memSpec)); } - else if (memSpec.memoryType == Config::MemoryType::HBM2) + else if (memSpec.memoryType == DRAMUtils::MemSpec::MemSpecHBM2::id) { checker = std::make_unique(dynamic_cast(memSpec)); } - else if (memSpec.memoryType == Config::MemoryType::GDDR5) + else if (memSpec.memoryType == DRAMUtils::MemSpec::MemSpecGDDR5::id) { checker = std::make_unique(dynamic_cast(memSpec)); } - else if (memSpec.memoryType == Config::MemoryType::GDDR5X) + else if (memSpec.memoryType == DRAMUtils::MemSpec::MemSpecGDDR5X::id) { checker = std::make_unique(dynamic_cast(memSpec)); } - else if (memSpec.memoryType == Config::MemoryType::GDDR6) + else if (memSpec.memoryType == DRAMUtils::MemSpec::MemSpecGDDR6::id) { checker = std::make_unique(dynamic_cast(memSpec)); } - else if (memSpec.memoryType == Config::MemoryType::STTMRAM) + else if (memSpec.memoryType == DRAMUtils::MemSpec::MemSpecSTTMRAM::id) { checker = std::make_unique(dynamic_cast(memSpec)); } #ifdef DDR5_SIM - else if (memSpec.memoryType == Config::MemoryType::DDR5) + else if (memSpec.memoryType == DRAMUtils::MemSpec::MemSpecDDR5::id) { checker = std::make_unique(dynamic_cast(memSpec)); } #endif #ifdef LPDDR5_SIM - else if (memSpec.memoryType == Config::MemoryType::LPDDR5) + else if (memSpec.memoryType == DRAMUtils::MemSpec::MemSpecLPDDR5::id) { checker = std::make_unique(dynamic_cast(memSpec)); } #endif #ifdef HBM3_SIM - else if (memSpec.memoryType == Config::MemoryType::HBM3) + else if (memSpec.memoryType == DRAMUtils::MemSpec::MemSpecHBM3::id) { checker = std::make_unique(dynamic_cast(memSpec)); } diff --git a/src/libdramsys/DRAMSys/simulation/DRAMSys.cpp b/src/libdramsys/DRAMSys/simulation/DRAMSys.cpp index c0a92821..4264ac34 100644 --- a/src/libdramsys/DRAMSys/simulation/DRAMSys.cpp +++ b/src/libdramsys/DRAMSys/simulation/DRAMSys.cpp @@ -36,6 +36,7 @@ * Felipe S. Prado * Lukas Steiner * Derek Christ + * Marco Mörz */ #include "DRAMSys.h" @@ -45,6 +46,8 @@ #include "DRAMSys/simulation/Dram.h" +#include "DRAMSys/config/MemSpec.h" + #include "DRAMSys/configuration/memspec/MemSpecDDR3.h" #include "DRAMSys/configuration/memspec/MemSpecDDR4.h" #include "DRAMSys/configuration/memspec/MemSpecGDDR5.h" @@ -69,8 +72,9 @@ #include #include #include -#include #include +#include +#include namespace DRAMSys { @@ -223,7 +227,7 @@ void DRAMSys::setupTlmRecorders(const std::string& traceName, const Config::Conf nlohmann::json mcconfig; nlohmann::json memspec; mcconfig[Config::McConfig::KEY] = config.mcconfig; - memspec[Config::MemSpec::KEY] = config.memspec; + memspec[Config::MemSpecConstants::KEY] = config.memspec; tlmRecorders.emplace_back(recorderName, simConfig, @@ -306,57 +310,49 @@ void DRAMSys::report() std::cout << headline << std::endl; } -std::unique_ptr DRAMSys::createMemSpec(const Config::MemSpec& memSpec) +std::unique_ptr DRAMSys::createMemSpec(const DRAMUtils::MemSpec::MemSpecVariant& memSpec) { - auto memoryType = memSpec.memoryType; - - if (memoryType == Config::MemoryType::DDR3) - return std::make_unique(memSpec); - - if (memoryType == Config::MemoryType::DDR4) - return std::make_unique(memSpec); - - if (memoryType == Config::MemoryType::LPDDR4) - return std::make_unique(memSpec); - - if (memoryType == Config::MemoryType::WideIO) - return std::make_unique(memSpec); - - if (memoryType == Config::MemoryType::WideIO2) - return std::make_unique(memSpec); - - if (memoryType == Config::MemoryType::HBM2) - return std::make_unique(memSpec); - - if (memoryType == Config::MemoryType::GDDR5) - return std::make_unique(memSpec); - - if (memoryType == Config::MemoryType::GDDR5X) - return std::make_unique(memSpec); - - if (memoryType == Config::MemoryType::GDDR6) - return std::make_unique(memSpec); - - if (memoryType == Config::MemoryType::STTMRAM) - return std::make_unique(memSpec); - + return std::visit([](const auto& v) -> std::unique_ptr { + using T = std::decay_t; + + if constexpr (std::is_same_v) + return std::make_unique(v); + else if constexpr (std::is_same_v) + return std::make_unique(v); + else if constexpr (std::is_same_v) + return std::make_unique(v); + else if constexpr (std::is_same_v) + return std::make_unique(v); + else if constexpr (std::is_same_v) + return std::make_unique(v); + else if constexpr (std::is_same_v) + return std::make_unique(v); + else if constexpr (std::is_same_v) + return std::make_unique(v); + else if constexpr (std::is_same_v) + return std::make_unique(v); + else if constexpr (std::is_same_v) + return std::make_unique(v); + else if constexpr (std::is_same_v) + return std::make_unique(v); #ifdef DDR5_SIM - if (memoryType == Config::MemoryType::DDR5) - return std::make_unique(memSpec); + else if constexpr ((std::is_same_v)) + return std::make_unique(v); #endif - #ifdef LPDDR5_SIM - if (memoryType == Config::MemoryType::LPDDR5) - return std::make_unique(memSpec); + else if constexpr ((std::is_same_v)) + return std::make_unique(v); #endif - #ifdef HBM3_SIM - if (memoryType == Config::MemoryType::HBM3) - return std::make_unique(memSpec); + else if constexpr ((std::is_same_v)) + return std::make_unique(v); #endif - - SC_REPORT_FATAL("Configuration", "Unsupported DRAM type"); - return {}; + else + { + SC_REPORT_FATAL("Configuration", "Unsupported DRAM type"); + return nullptr; + } + }, memSpec.getVariant()); } std::unique_ptr DRAMSys::createArbiter(const SimConfig& simConfig, diff --git a/src/libdramsys/DRAMSys/simulation/DRAMSys.h b/src/libdramsys/DRAMSys/simulation/DRAMSys.h index 158df249..272ad6d1 100644 --- a/src/libdramsys/DRAMSys/simulation/DRAMSys.h +++ b/src/libdramsys/DRAMSys/simulation/DRAMSys.h @@ -36,6 +36,7 @@ * Felipe S. Prado * Lukas Steiner * Derek Christ + * Marco Mörz */ #ifndef DRAMSYS_H @@ -53,7 +54,8 @@ #include "DRAMSys/simulation/Dram.h" #include "DRAMSys/simulation/SimConfig.h" -#include +#include + #include #include #include @@ -93,7 +95,7 @@ public: private: static void logo(); - static std::unique_ptr createMemSpec(const Config::MemSpec& memSpec); + static std::unique_ptr createMemSpec(const DRAMUtils::MemSpec::MemSpecVariant& memSpec); static std::unique_ptr createArbiter(const SimConfig& simConfig, const McConfig& mcConfig, const MemSpec& memSpec, diff --git a/src/libdramsys/DRAMSys/simulation/Dram.cpp b/src/libdramsys/DRAMSys/simulation/Dram.cpp index 22e8e756..38094167 100644 --- a/src/libdramsys/DRAMSys/simulation/Dram.cpp +++ b/src/libdramsys/DRAMSys/simulation/Dram.cpp @@ -36,6 +36,7 @@ * Eder F. Zulian * Felipe S. Prado * Derek Christ + * Marco Mörz */ #include "Dram.h" @@ -45,12 +46,7 @@ #include "DRAMSys/config/SimConfig.h" #include -#ifdef DRAMPOWER -#include "LibDRAMPower.h" -#endif - #include -#include #include #ifdef _WIN32 @@ -59,6 +55,11 @@ #include #endif +#ifdef DRAMPOWER +#include "DRAMPower/data/energy.h" +#include "DRAMPower/command/Command.h" +#endif + using namespace sc_core; using namespace tlm; @@ -114,7 +115,14 @@ Dram::Dram(const sc_module_name& name, #ifdef DRAMPOWER if (powerAnalysis) { - DRAMPower = std::make_unique(memSpec.toDramPowerMemSpec(), false); + DRAMPower = memSpec.toDramPowerObject(); + if (DRAMPower && storeMode == Config::StoreModeType::NoStorage) { + if (simConfig.togglingRate) { + DRAMPower->setToggleRate(0, simConfig.togglingRate); + } else { + SC_REPORT_FATAL("DRAM", "Toggling rates for power estimation must be provided for storeMode NoStorage"); + } + } } if (simConfig.powerAnalysis && simConfig.enableWindowing) @@ -131,23 +139,25 @@ Dram::~Dram() void Dram::reportPower() { #ifdef DRAMPOWER - DRAMPower->calcEnergy(); + if (!DRAMPower) + return; + double energy = DRAMPower->getTotalEnergy(DRAMPower->getLastCommandTime()); + double time = DRAMPower->getLastCommandTime() * memSpec.tCK.to_seconds(); // Print the final total energy and the average power for // the simulation: - std::cout << name() << std::string(" Total Energy: ") << std::fixed << std::setprecision(2) - << DRAMPower->getEnergy().total_energy * memSpec.devicesPerRank << std::string(" pJ") + std::cout << name() << std::string(" Total Energy: ") << std::defaultfloat << std::setprecision(3) + << energy << std::string(" J") << std::endl; - std::cout << name() << std::string(" Average Power: ") << std::fixed << std::setprecision(2) - << DRAMPower->getPower().average_power * memSpec.devicesPerRank << std::string(" mW") + std::cout << name() << std::string(" Average Power: ") << std::defaultfloat << std::setprecision(3) + << energy / time << std::string(" W") << std::endl; if (tlmRecorder != nullptr) { tlmRecorder->recordPower(sc_time_stamp().to_seconds(), - this->DRAMPower->getPower().window_average_power * - this->memSpec.devicesPerRank); + energy / time); } #endif } @@ -157,11 +167,29 @@ tlm_sync_enum Dram::nb_transport_fw(tlm_generic_payload& trans, tlm_phase& phase assert(phase >= BEGIN_RD && phase <= END_SREF); #ifdef DRAMPOWER - if (powerAnalysis) + if (powerAnalysis && DRAMPower) { - int bank = static_cast(ControllerExtension::getBank(trans)); - int64_t cycle = std::lround((sc_time_stamp() + delay) / memSpec.tCK); - DRAMPower->doCommand(phaseToDRAMPowerCommand(phase), bank, cycle); + std::size_t rank = static_cast(ControllerExtension::getRank(trans)); // relaitve to the channel + std::size_t bank_group_abs = static_cast(ControllerExtension::getBankGroup(trans)); // relative to the channel + std::size_t bank_group = bank_group_abs - rank * memSpec.groupsPerRank; // relative to the rank + std::size_t bank = static_cast(ControllerExtension::getBank(trans)) - bank_group_abs * memSpec.banksPerGroup; // relative to the bank_group + std::size_t row = static_cast(ControllerExtension::getRow(trans)); + std::size_t column = static_cast(ControllerExtension::getColumn(trans)); + uint64_t cycle = std::lround((sc_time_stamp() + delay) / memSpec.tCK); + + // DRAMPower: + // banks are relative to the rank + // bankgroups are relative to the rank + bank = bank + (bank_group * memSpec.banksPerGroup); + + DRAMPower::TargetCoordinate target(bank, bank_group, rank, row, column); + + // TODO read, write data for interface calculation + uint8_t * data = trans.get_data_ptr(); // Can be nullptr if no data + std::size_t datasize = trans.get_data_length() * 8; // Is always set + + DRAMPower::Command command(cycle, phaseToDRAMPowerCommand(phase), target, data, datasize); + DRAMPower->doCoreInterfaceCommand(command); } #endif @@ -291,6 +319,10 @@ void Dram::deserialize(std::istream& stream) void Dram::powerWindow() { int64_t clkCycles = 0; + double previousEnergy = 0; + double currentEnergy = 0; + double windowEnergy = 0; + double powerWindowSizeSeconds = powerWindowSize.to_seconds(); while (true) { @@ -299,30 +331,28 @@ void Dram::powerWindow() clkCycles = std::lround(sc_time_stamp() / this->memSpec.tCK); - this->DRAMPower->calcWindowEnergy(clkCycles); + currentEnergy = this->DRAMPower->getTotalEnergy(clkCycles); + windowEnergy = currentEnergy - previousEnergy; // During operation the energy should never be zero since the device is always consuming - assert(!this->DRAMPower->getEnergy().window_energy < 1e-05); + assert(!(windowEnergy < 1e-15)); if (tlmRecorder) { // Store the time (in seconds) and the current average power (in mW) into the database tlmRecorder->recordPower(sc_time_stamp().to_seconds(), - this->DRAMPower->getPower().window_average_power * - this->memSpec.devicesPerRank); + windowEnergy / powerWindowSizeSeconds); } - // Here considering that DRAMPower provides the energy in pJ and the power in mW + // Here considering that DRAMPower provides the energy in J and the power in W PRINTDEBUGMESSAGE(this->name(), std::string("\tWindow Energy: \t") + - std::to_string(this->DRAMPower->getEnergy().window_energy * - this->memSpec.devicesPerRank) + - std::string("\t[pJ]")); + std::to_string(windowEnergy) + + std::string("\t[J]")); PRINTDEBUGMESSAGE(this->name(), std::string("\tWindow Average Power: \t") + - std::to_string(this->DRAMPower->getPower().window_average_power * - this->memSpec.devicesPerRank) + - std::string("\t[mW]")); + std::to_string(windowEnergy / powerWindowSizeSeconds) + + std::string("\t[W]")); } } #endif diff --git a/src/libdramsys/DRAMSys/simulation/Dram.h b/src/libdramsys/DRAMSys/simulation/Dram.h index 05742a91..6fc8d1c9 100644 --- a/src/libdramsys/DRAMSys/simulation/Dram.h +++ b/src/libdramsys/DRAMSys/simulation/Dram.h @@ -36,6 +36,7 @@ * Eder F. Zulian * Felipe S. Prado * Derek Christ + * Marco Mörz */ #ifndef DRAM_H @@ -47,13 +48,15 @@ #include "DRAMSys/configuration/memspec/MemSpec.h" #include "DRAMSys/simulation/SimConfig.h" -#include +#ifdef DRAMPOWER +#include "DRAMPower/command/CmdType.h" +#include "DRAMPower/dram/dram_base.h" +#endif + #include #include #include -class libDRAMPower; - namespace DRAMSys { @@ -73,7 +76,7 @@ protected: sc_core::sc_time powerWindowSize; #ifdef DRAMPOWER - std::unique_ptr DRAMPower; + std::unique_ptr> DRAMPower; // This Thread is only triggered when Power Simulation is enabled. // It estimates the current average power which will be stored in the trace database for // visualization purposes. diff --git a/src/libdramsys/DRAMSys/simulation/SimConfig.cpp b/src/libdramsys/DRAMSys/simulation/SimConfig.cpp index f2958faf..b5d343d3 100644 --- a/src/libdramsys/DRAMSys/simulation/SimConfig.cpp +++ b/src/libdramsys/DRAMSys/simulation/SimConfig.cpp @@ -31,6 +31,7 @@ * * Authors: * Derek Christ + * Marco Mörz */ #include "SimConfig.h" @@ -53,7 +54,8 @@ SimConfig::SimConfig(const Config::SimConfig& simConfig) : checkTLM2Protocol(simConfig.CheckTLM2Protocol.value_or(DEFAULT_CHECK_TLM2_PROTOCOL)), useMalloc(simConfig.UseMalloc.value_or(DEFAULT_USE_MALLOC)), addressOffset(simConfig.AddressOffset.value_or(DEFAULT_ADDRESS_OFFSET)), - storeMode(simConfig.StoreMode.value_or(DEFAULT_STORE_MODE)) + storeMode(simConfig.StoreMode.value_or(DEFAULT_STORE_MODE)), + togglingRate(simConfig.TogglingRate) { if (storeMode == Config::StoreModeType::Invalid) SC_REPORT_FATAL("SimConfig", "Invalid StoreMode"); diff --git a/src/libdramsys/DRAMSys/simulation/SimConfig.h b/src/libdramsys/DRAMSys/simulation/SimConfig.h index d02454d8..c9cfd33e 100644 --- a/src/libdramsys/DRAMSys/simulation/SimConfig.h +++ b/src/libdramsys/DRAMSys/simulation/SimConfig.h @@ -31,14 +31,17 @@ * * Authors: * Derek Christ + * Marco Mörz */ #ifndef SIM_CONFIG_H #define SIM_CONFIG_H #include +#include #include +#include namespace DRAMSys { @@ -58,6 +61,7 @@ struct SimConfig bool useMalloc; unsigned long long int addressOffset; Config::StoreModeType storeMode; + std::optional togglingRate; static constexpr std::string_view DEFAULT_SIMULATION_NAME = "default"; static constexpr bool DEFAULT_DATABASE_RECORDING = false; diff --git a/tests/tests_configuration/CMakeLists.txt b/tests/tests_configuration/CMakeLists.txt index 0eccb7f4..74cdae8b 100644 --- a/tests/tests_configuration/CMakeLists.txt +++ b/tests/tests_configuration/CMakeLists.txt @@ -11,6 +11,7 @@ set_target_properties(tests_configuration PROPERTIES FOLDER tests/configuration) target_link_libraries(tests_configuration PRIVATE DRAMSys::config + DRAMUtils::DRAMUtils GTest::gtest GTest::gtest_main ) diff --git a/tests/tests_configuration/reference.json b/tests/tests_configuration/reference.json index 60d918c8..eebfa58c 100644 --- a/tests/tests_configuration/reference.json +++ b/tests/tests_configuration/reference.json @@ -72,6 +72,7 @@ "burstLength": 16, "cmdMode": 1, "dataRate": 2, + "maxBurstLength": 16, "nbrOfBankGroups": 8, "nbrOfBanks": 16, "nbrOfChannels": 2, @@ -82,60 +83,115 @@ "nbrOfPhysicalRanks": 1, "nbrOfRanks": 1, "nbrOfRows": 65536, - "refMode": 1, + "RefMode": 1, "width": 4 }, + "memimpedancespec": { + "ck_termination": true, + "ck_R_eq": 1e6, + "ck_dyn_E": 1e-12, + + "ca_termination": true, + "ca_R_eq": 1e6, + "ca_dyn_E": 1e-12, + + "rdq_termination": true, + "rdq_R_eq": 1e6, + "rdq_dyn_E": 1e-12, + "wdq_termination": true, + "wdq_R_eq": 1e6, + "wdq_dyn_E": 1e-12, + + "wdqs_termination": true, + "wdqs_R_eq": 1e6, + "wdqs_dyn_E": 1e-12, + "rdqs_termination": true, + "rdqs_R_eq": 1e6, + "rdqs_dyn_E": 1e-12 + }, "memoryId": "JEDEC_2x8x2Gbx4_DDR5-3200A", "memoryType": "DDR5", + "mempowerspec": { + "vdd": 0.0, + "idd0": 0.0, + "idd2n": 0.0, + "idd3n": 0.0, + "idd4r": 0.0, + "idd4w": 0.0, + "idd5c": 0.0, + "idd6n": 0.0, + "idd2p": 0.0, + "idd3p": 0.0, + "vpp": 0.0, + "ipp0": 0.0, + "ipp2n": 0.0, + "ipp3n": 0.0, + "ipp4r": 0.0, + "ipp4w": 0.0, + "ipp5c": 0.0, + "ipp6n": 0.0, + "ipp2p": 0.0, + "ipp3p": 0.0, + "idd5b": 0.0, + "idd5f": 0.0, + "ipp5b": 0.0, + "ipp5f": 0.0, + "vddq": 0.0, + "iBeta_vdd": 0.0, + "iBeta_vpp": 0.0 + }, "memtimingspec": { - "ACTPDEN": 2, - "CCD_L_WR2_slr": 16, - "CCD_L_WR_slr": 32, - "CCD_L_slr": 8, - "CCD_S_WR_slr": 8, - "CCD_S_slr": 8, - "CCD_WR_dlr": 0, - "CCD_WR_dpr": 0, - "CCD_dlr": 0, - "CPDED": 8, - "FAW_dlr": 0, - "FAW_slr": 32, - "PD": 12, - "PPD": 2, - "PRPDEN": 2, - "RAS": 52, "RCD": 22, - "RDDQS": 0, - "REFI1": 6240, - "REFI2": 3120, - "REFISB": 1560, - "REFPDEN": 2, - "REFSBRD_dlr": 0, - "REFSBRD_slr": 48, - "RFC1_dlr": 0, - "RFC1_dpr": 0, - "RFC1_slr": 312, - "RFC2_dlr": 0, - "RFC2_dpr": 0, - "RFC2_slr": 208, - "RFCsb_dlr": 0, - "RFCsb_slr": 184, - "RL": 22, + "PPD": 2, "RP": 22, + "RAS": 52, + "RL": 22, + "RTP": 12, "RPRE": 1, "RPST": 0, - "RRD_L_slr": 8, - "RRD_S_slr": 8, - "RRD_dlr": 0, - "RTP": 12, - "RTRS": 2, + "RDDQS": 0, "WL": 20, "WPRE": 2, "WPST": 0, "WR": 48, + "CCD_L_slr": 8, + "CCD_L_WR_slr": 32, + "CCD_L_WR2_slr": 16, + "CCD_M_slr": 8, + "CCD_M_WR_slr": 32, + "CCD_S_slr": 8, + "CCD_S_WR_slr": 8, + "CCD_dlr": 0, + "CCD_WR_dlr": 0, + "CCD_WR_dpr": 0, + "RRD_L_slr": 8, + "RRD_S_slr": 8, + "RRD_dlr": 0, + "FAW_slr": 32, + "FAW_dlr": 0, "WTR_L": 16, + "WTR_M": 16, "WTR_S": 4, + "RFC1_slr": 312, + "RFC2_slr": 208, + "RFC1_dlr": 0, + "RFC2_dlr": 0, + "RFC1_dpr": 0, + "RFC2_dpr": 0, + "RFCsb_slr": 184, + "RFCsb_dlr": 0, + "REFI1": 6240, + "REFI2": 3120, + "REFISB": 1560, + "REFSBRD_slr": 48, + "REFSBRD_dlr": 0, + "RTRS": 2, + "CPDED": 8, + "PD": 12, "XP": 12, + "ACTPDEN": 2, + "PRPDEN": 2, + "REFPDEN": 2, "tCK": 625 } }, diff --git a/tests/tests_configuration/resources/memspec/JEDEC_2x8x2Gbx4_DDR5-3200A.json b/tests/tests_configuration/resources/memspec/JEDEC_2x8x2Gbx4_DDR5-3200A.json index 0c725533..7057f806 100644 --- a/tests/tests_configuration/resources/memspec/JEDEC_2x8x2Gbx4_DDR5-3200A.json +++ b/tests/tests_configuration/resources/memspec/JEDEC_2x8x2Gbx4_DDR5-3200A.json @@ -1,27 +1,80 @@ { "memspec": { "memarchitecturespec": { + "RAADEC": 1, + "RAAIMT": 32, + "RAAMMT": 96, "burstLength": 16, + "cmdMode": 1, "dataRate": 2, + "maxBurstLength": 16, "nbrOfBankGroups": 8, "nbrOfBanks": 16, - "nbrOfColumns": 2048, - "nbrOfRanks": 1, - "nbrOfDIMMRanks": 1, - "nbrOfPhysicalRanks": 1, - "nbrOfLogicalRanks": 1, - "nbrOfRows": 65536, - "width": 4, - "nbrOfDevices": 8, "nbrOfChannels": 2, - "cmdMode": 1, - "refMode": 1, - "RAAIMT" : 32, - "RAAMMT" : 96, - "RAADEC" : 16 + "nbrOfColumns": 2048, + "nbrOfDIMMRanks": 1, + "nbrOfDevices": 8, + "nbrOfLogicalRanks": 1, + "nbrOfPhysicalRanks": 1, + "nbrOfRanks": 1, + "nbrOfRows": 65536, + "RefMode": 1, + "width": 4 + }, + "memimpedancespec": { + "ck_termination": true, + "ck_R_eq": 1e6, + "ck_dyn_E": 1e-12, + + "ca_termination": true, + "ca_R_eq": 1e6, + "ca_dyn_E": 1e-12, + + "rdq_termination": true, + "rdq_R_eq": 1e6, + "rdq_dyn_E": 1e-12, + "wdq_termination": true, + "wdq_R_eq": 1e6, + "wdq_dyn_E": 1e-12, + + "wdqs_termination": true, + "wdqs_R_eq": 1e6, + "wdqs_dyn_E": 1e-12, + "rdqs_termination": true, + "rdqs_R_eq": 1e6, + "rdqs_dyn_E": 1e-12 }, "memoryId": "JEDEC_2x8x2Gbx4_DDR5-3200A", "memoryType": "DDR5", + "mempowerspec": { + "vdd": 0.0, + "idd0": 0.0, + "idd2n": 0.0, + "idd3n": 0.0, + "idd4r": 0.0, + "idd4w": 0.0, + "idd5c": 0.0, + "idd6n": 0.0, + "idd2p": 0.0, + "idd3p": 0.0, + "vpp": 0.0, + "ipp0": 0.0, + "ipp2n": 0.0, + "ipp3n": 0.0, + "ipp4r": 0.0, + "ipp4w": 0.0, + "ipp5c": 0.0, + "ipp6n": 0.0, + "ipp2p": 0.0, + "ipp3p": 0.0, + "idd5b": 0.0, + "idd5f": 0.0, + "ipp5b": 0.0, + "ipp5f": 0.0, + "vddq": 0.0, + "iBeta_vdd": 0.0, + "iBeta_vpp": 0.0 + }, "memtimingspec": { "RCD": 22, "PPD": 2, @@ -39,6 +92,8 @@ "CCD_L_slr": 8, "CCD_L_WR_slr": 32, "CCD_L_WR2_slr": 16, + "CCD_M_slr": 8, + "CCD_M_WR_slr": 32, "CCD_S_slr": 8, "CCD_S_WR_slr": 8, "CCD_dlr": 0, @@ -50,6 +105,7 @@ "FAW_slr": 32, "FAW_dlr": 0, "WTR_L": 16, + "WTR_M": 16, "WTR_S": 4, "RFC1_slr": 312, "RFC2_slr": 208, @@ -71,7 +127,11 @@ "ACTPDEN": 2, "PRPDEN": 2, "REFPDEN": 2, - "tCK": 625 + "tCK": 625, + + "RFCsb": 0, + "RFC1": 0, + "RFC2": 0 } } } diff --git a/tests/tests_configuration/test_configuration.cpp b/tests/tests_configuration/test_configuration.cpp index 5c0047b1..59a2aa21 100644 --- a/tests/tests_configuration/test_configuration.cpp +++ b/tests/tests_configuration/test_configuration.cpp @@ -31,14 +31,20 @@ * * Authors: * Derek Christ + * Marco Mörz */ #include -#include +#include + +#include +#include +#include #include #include #include +#include using namespace DRAMSys::Config; @@ -54,7 +60,7 @@ protected: { } - static DRAMSys::Config::MemSpec createMemSpec(); + static DRAMUtils::MemSpec::MemSpecVariant createMemSpec(); static DRAMSys::Config::TracePlayer createTracePlayer(); static DRAMSys::Config::TrafficGenerator createTraceGeneratorOneState(); @@ -116,63 +122,185 @@ protected: false, false, 1000, - 1e-3}; + 1e-3, + std::nullopt}; - DRAMSys::Config::MemSpec memSpec; + DRAMUtils::MemSpec::MemSpecVariant memSpec; DRAMSys::Config::TracePlayer tracePlayer; DRAMSys::Config::TrafficGenerator traceGeneratorOneState; DRAMSys::Config::TrafficGeneratorStateMachine traceGeneratorMultipleStates; DRAMSys::Config::RowHammer traceHammer; std::vector traceSetup{ - {tracePlayer, traceGeneratorOneState, traceGeneratorMultipleStates, traceHammer}}; + { + DRAMSys::Config::Initiator{tracePlayer}, + DRAMSys::Config::Initiator{traceGeneratorOneState}, + DRAMSys::Config::Initiator{traceGeneratorMultipleStates}, + DRAMSys::Config::Initiator{traceHammer} + } + }; DRAMSys::Config::Configuration configuration{ addressMapping, mcConfig, memSpec, simConfig, "std::string_simulationId", traceSetup}; }; -DRAMSys::Config::MemSpec ConfigurationTest::createMemSpec() +DRAMUtils::MemSpec::MemSpecVariant ConfigurationTest::createMemSpec() { - MemArchitectureSpecType memArchitectureSpec{{{"burstLength", 16}, - {"dataRate", 2}, - {"nbrOfBankGroups", 8}, - {"nbrOfBanks", 16}, - {"nbrOfColumns", 2048}, - {"nbrOfRanks", 1}, - {"nbrOfDIMMRanks", 1}, - {"nbrOfPhysicalRanks", 1}, - {"nbrOfLogicalRanks", 1}, - {"nbrOfRows", 65536}, - {"width", 4}, - {"nbrOfDevices", 8}, - {"nbrOfChannels", 2}, - {"cmdMode", 1}, - {"refMode", 1}, - {"RAAIMT", 32}, - {"RAAMMT", 96}, - {"RAADEC", 1}}}; + DRAMUtils::MemSpec::MemArchitectureSpecTypeDDR5 memArchitectureSpec + { + 2, // nbrOfChannels + 8, // nbrOfDevices + 1, // nbrOfRanks + 1, // nbrOfDIMMRanks + 1, // nbrOfPhysicalRanks + 1, // nbrOfLogicalRanks + 16, // nbrOfBanks + 8, // nbrOfBankGroups + 65536, // nbrOfRows + 2048, // nbrOfColumns + 16, // burstLength + 2, // dataRate + 4, // width + DRAMUtils::MemSpec::RefModeTypeDDR5::REF_MODE_1, // RefMode + 16, // maxBurstLength + 1, // cmdMode + 32, // RAAIMT + 96, // RAAMMT + 1 // RAADEC + }; - MemTimingSpecType memTimingSpec{{{ - {"RCD", 22}, {"PPD", 2}, {"RP", 22}, {"RAS", 52}, - {"RL", 22}, {"RTP", 12}, {"RPRE", 1}, {"RPST", 0}, - {"RDDQS", 0}, {"WL", 20}, {"WPRE", 2}, {"WPST", 0}, - {"WR", 48}, {"CCD_L_slr", 8}, {"CCD_L_WR_slr", 32}, {"CCD_L_WR2_slr", 16}, - {"CCD_S_slr", 8}, {"CCD_S_WR_slr", 8}, {"CCD_dlr", 0}, {"CCD_WR_dlr", 0}, - {"CCD_WR_dpr", 0}, {"RRD_L_slr", 8}, {"RRD_S_slr", 8}, {"RRD_dlr", 0}, - {"FAW_slr", 32}, {"FAW_dlr", 0}, {"WTR_L", 16}, {"WTR_S", 4}, - {"RFC1_slr", 312}, {"RFC2_slr", 208}, {"RFC1_dlr", 0}, {"RFC2_dlr", 0}, - {"RFC1_dpr", 0}, {"RFC2_dpr", 0}, {"RFCsb_slr", 184}, {"RFCsb_dlr", 0}, - {"REFI1", 6240}, {"REFI2", 3120}, {"REFISB", 1560}, {"REFSBRD_slr", 48}, - {"REFSBRD_dlr", 0}, {"RTRS", 2}, {"CPDED", 8}, {"PD", 12}, - {"XP", 12}, {"ACTPDEN", 2}, {"PRPDEN", 2}, {"REFPDEN", 2}, - {"tCK", 625}, - }}}; + DRAMUtils::MemSpec::MemTimingSpecTypeDDR5 memTimingSpec + { + 625, // tCK + 52, // RAS + 22, // RCD + 12, // RTP + 20, // WL + 48, // WR + 22, // RP - return {memArchitectureSpec, - "JEDEC_2x8x2Gbx4_DDR5-3200A", - DRAMSys::Config::MemoryType::DDR5, - memTimingSpec, - {}}; + 2, // PPD + 22, // RL + 1, // RPRE + 0, // RPST + 0, // RDDQS + 2, // WPRE + 0, // WPST + + 8, // CCD_L_slr + 32, // CCD_L_WR_slr + 16, // CCD_L_WR2_slr + 8, // CCD_M_slr + 32, // CCD_M_WR_slr + 8, // CCD_S_slr + 8, // CCD_S_WR_slr + 0, // CCD_dlr + 0, // CCD_WR_dlr + 0, // CCD_WR_dpr + 8, // RRD_L_slr + 8, // RRD_S_slr + 0, // RRD_dlr + 32, // FAW_slr + 0, // FAW_dlr + 16, // WTR_L + 16, // WTR_M + 4, // WTR_S + 312, // RFC1_slr + 208, // RFC2_slr + 0, // RFC1_dlr + 0, // RFC2_dlr + 0, // RFC1_dpr + 0, // RFC2_dpr + 184, // RFCsb_slr + 0, // RFCsb_dlr + 6240, // REFI1 + 3120, // REFI2 + 1560, // REFISB + 48, // REFSBRD_slr + 0, // REFSBRD_dlr + 2, // RTRS + 8, // CPDED + 12, // PD + 12, // XP + 2, // ACTPDEN + 2, // PRPDEN + 2 // REFPDEN + }; + + DRAMUtils::MemSpec::MemImpedanceSpecTypeDDR5 memImpedanceSpec { + true, // ck_termination + 1e6, // ck_R_eq + 1e-12, // ck_dyn_E + + true, // ca_termination + 1e6, // ca_R_eq + 1e-12, // ca_dyn_E + + true, // rdq_termination + 1e6, // rdq_R_eq + 1e-12, // rdq_dyn_E + true, // wdq_termination + 1e6, // wdq_R_eq + 1e-12, // wdq_dyn_E + + true, // rdqs_termination + 1e6, // rdqs_R_eq + 1e-12, // rdqs_dyn_E + true, // wdqs_termination + 1e6, // wdqs_R_eq + 1e-12 // wdqs_dyn_E + }; + + DRAMUtils::MemSpec::MemPowerSpecTypeDDR5 memPowerSpec { + 0, // vdd + 0, // idd0 + 0, // idd2n + 0, // idd3n + 0, // idd4r + 0, // idd4w + 0, // idd5c + 0, // idd6n + 0, // idd2p + 0, // idd3p + + 0, // vpp + 0, // ipp0 + 0, // ipp2n + 0, // ipp3n + 0, // ipp4r + 0, // ipp4w + 0, // ipp5c + 0, // ipp6n + 0, // ipp2p + 0, // ipp3p + + 0, // idd5b // RefModeTypeDDR5::REF_MODE_1 + 0, // idd5f // RefModeTypeDDR5::REF_MODE_2 + + 0, // ipp5b // RefModeTypeDDR5::REF_MODE_1 + 0, // ipp5f // RefModeTypeDDR5::REF_MODE_2 + + 0, // vddq + + 0, // iBeta_vdd + 0 // iBeta_vpp + }; + + + DRAMUtils::MemSpec::MemSpecVariant variant; + DRAMUtils::MemSpec::MemSpecDDR5 memspec + { + DRAMUtils::MemSpec::BaseMemSpec{}, // base + "JEDEC_2x8x2Gbx4_DDR5-3200A", // memoryId + memArchitectureSpec, // memarchitecturespec + memPowerSpec, // mempowerspec + memTimingSpec, // memtimingspec + std::nullopt, // bankwisespec + memImpedanceSpec, // memimpedancespec + std::nullopt // dataratespec + }; + variant.setVariant(memspec); + return variant; } DRAMSys::Config::TracePlayer ConfigurationTest::createTracePlayer() @@ -378,6 +506,7 @@ TEST_F(ConfigurationTest, MemSpec) "burstLength": 16, "cmdMode": 1, "dataRate": 2, + "maxBurstLength": 16, "nbrOfBankGroups": 8, "nbrOfBanks": 16, "nbrOfChannels": 2, @@ -388,60 +517,115 @@ TEST_F(ConfigurationTest, MemSpec) "nbrOfPhysicalRanks": 1, "nbrOfRanks": 1, "nbrOfRows": 65536, - "refMode": 1, + "RefMode": 1, "width": 4 }, + "memimpedancespec": { + "ck_termination": true, + "ck_R_eq": 1e6, + "ck_dyn_E": 1e-12, + + "ca_termination": true, + "ca_R_eq": 1e6, + "ca_dyn_E": 1e-12, + + "rdq_termination": true, + "rdq_R_eq": 1e6, + "rdq_dyn_E": 1e-12, + "wdq_termination": true, + "wdq_R_eq": 1e6, + "wdq_dyn_E": 1e-12, + + "wdqs_termination": true, + "wdqs_R_eq": 1e6, + "wdqs_dyn_E": 1e-12, + "rdqs_termination": true, + "rdqs_R_eq": 1e6, + "rdqs_dyn_E": 1e-12 + }, "memoryId": "JEDEC_2x8x2Gbx4_DDR5-3200A", "memoryType": "DDR5", + "mempowerspec": { + "vdd": 0.0, + "idd0": 0.0, + "idd2n": 0.0, + "idd3n": 0.0, + "idd4r": 0.0, + "idd4w": 0.0, + "idd5c": 0.0, + "idd6n": 0.0, + "idd2p": 0.0, + "idd3p": 0.0, + "vpp": 0.0, + "ipp0": 0.0, + "ipp2n": 0.0, + "ipp3n": 0.0, + "ipp4r": 0.0, + "ipp4w": 0.0, + "ipp5c": 0.0, + "ipp6n": 0.0, + "ipp2p": 0.0, + "ipp3p": 0.0, + "idd5b": 0.0, + "idd5f": 0.0, + "ipp5b": 0.0, + "ipp5f": 0.0, + "vddq": 0.0, + "iBeta_vdd": 0.0, + "iBeta_vpp": 0.0 + }, "memtimingspec": { - "ACTPDEN": 2, - "CCD_L_WR2_slr": 16, - "CCD_L_WR_slr": 32, - "CCD_L_slr": 8, - "CCD_S_WR_slr": 8, - "CCD_S_slr": 8, - "CCD_WR_dlr": 0, - "CCD_WR_dpr": 0, - "CCD_dlr": 0, - "CPDED": 8, - "FAW_dlr": 0, - "FAW_slr": 32, - "PD": 12, - "PPD": 2, - "PRPDEN": 2, - "RAS": 52, "RCD": 22, - "RDDQS": 0, - "REFI1": 6240, - "REFI2": 3120, - "REFISB": 1560, - "REFPDEN": 2, - "REFSBRD_dlr": 0, - "REFSBRD_slr": 48, - "RFC1_dlr": 0, - "RFC1_dpr": 0, - "RFC1_slr": 312, - "RFC2_dlr": 0, - "RFC2_dpr": 0, - "RFC2_slr": 208, - "RFCsb_dlr": 0, - "RFCsb_slr": 184, - "RL": 22, + "PPD": 2, "RP": 22, + "RAS": 52, + "RL": 22, + "RTP": 12, "RPRE": 1, "RPST": 0, - "RRD_L_slr": 8, - "RRD_S_slr": 8, - "RRD_dlr": 0, - "RTP": 12, - "RTRS": 2, + "RDDQS": 0, "WL": 20, "WPRE": 2, "WPST": 0, "WR": 48, + "CCD_L_slr": 8, + "CCD_L_WR_slr": 32, + "CCD_L_WR2_slr": 16, + "CCD_M_slr": 8, + "CCD_M_WR_slr": 32, + "CCD_S_slr": 8, + "CCD_S_WR_slr": 8, + "CCD_dlr": 0, + "CCD_WR_dlr": 0, + "CCD_WR_dpr": 0, + "RRD_L_slr": 8, + "RRD_S_slr": 8, + "RRD_dlr": 0, + "FAW_slr": 32, + "FAW_dlr": 0, "WTR_L": 16, + "WTR_M": 16, "WTR_S": 4, + "RFC1_slr": 312, + "RFC2_slr": 208, + "RFC1_dlr": 0, + "RFC2_dlr": 0, + "RFC1_dpr": 0, + "RFC2_dpr": 0, + "RFCsb_slr": 184, + "RFCsb_dlr": 0, + "REFI1": 6240, + "REFI2": 3120, + "REFISB": 1560, + "REFSBRD_slr": 48, + "REFSBRD_dlr": 0, + "RTRS": 2, + "CPDED": 8, + "PD": 12, "XP": 12, + "ACTPDEN": 2, + "PRPDEN": 2, + "REFPDEN": 2, "tCK": 625 } } @@ -450,7 +634,7 @@ TEST_F(ConfigurationTest, MemSpec) json_t memspec_reference = json_t::parse(memspec_string); json_t memspec_test; - memspec_test[MemSpec::KEY] = memSpec; + memspec_test[MemSpecConstants::KEY] = memSpec; EXPECT_EQ(memspec_test, memspec_reference); } diff --git a/tests/tests_configuration/test_json.cpp b/tests/tests_configuration/test_json.cpp index 8ac26e33..ac1bede1 100644 --- a/tests/tests_configuration/test_json.cpp +++ b/tests/tests_configuration/test_json.cpp @@ -1,6 +1,6 @@ #include -#include +#include class JsonTest : public ::testing::Test { diff --git a/tests/tests_dramsys/b_transport/configs/no_storage.json b/tests/tests_dramsys/b_transport/configs/no_storage.json index e45a7b78..fb5d4c3f 100644 --- a/tests/tests_dramsys/b_transport/configs/no_storage.json +++ b/tests/tests_dramsys/b_transport/configs/no_storage.json @@ -72,26 +72,39 @@ "nbrOfDevices": 8, "nbrOfRanks": 1, "nbrOfRows": 32768, + "RefMode": 1, "width": 8 }, "memoryId": "MICRON_4Gb_DDR4-1866_8bit_A", "memoryType": "DDR4", "mempowerspec": { + "vdd": 1.2, "idd0": 56.25, - "idd02": 4.05, "idd2n": 33.75, - "idd2p0": 17.0, - "idd2p1": 17.0, "idd3n": 39.5, - "idd3p0": 22.5, - "idd3p1": 22.5, "idd4r": 157.5, "idd4w": 135.0, - "idd5": 118.0, - "idd6": 20.25, - "idd62": 2.6, - "vdd": 1.2, - "vdd2": 2.5 + "idd6n": 22.5, + "idd2p": 17.0, + "idd3p": 22.5, + "idd5B": 0.0, + "idd5F2": 0.0, + "idd5F4": 0.0, + + "vpp": 0.0, + "ipp0": 0.0, + "ipp2n": 0.0, + "ipp3n": 0.0, + "ipp4r": 0.0, + "ipp4w": 0.0, + "ipp6n": 0.0, + "ipp2p": 0.0, + "ipp3p": 0.0, + "ipp5B": 0.0, + "ipp5F2": 0.0, + "ipp5F4": 0.0, + + "vddq": 1.2 }, "memtimingspec": { "ACTPDEN": 1, @@ -110,7 +123,7 @@ "REFI": 7280, "REFM": 1, "REFPDEN": 1, - "RFC": 243, + "RFC1": 243, "RFC2": 150, "RFC4": 103, "RL": 13, @@ -130,6 +143,41 @@ "XS": 252, "XSDLL": 512, "tCK": 1072 + }, + "memimpedancespec": { + "ck_termination": true, + "ck_R_eq": 1e6, + "ck_dyn_E": 1e-12, + + "ca_termination": true, + "ca_R_eq": 1e6, + "ca_dyn_E": 1e-12, + + "rdq_termination": true, + "rdq_R_eq": 1e6, + "rdq_dyn_E": 1e-12, + "wdq_termination": true, + "wdq_R_eq": 1e6, + "wdq_dyn_E": 1e-12, + + "wdqs_termination": true, + "wdqs_R_eq": 1e6, + "wdqs_dyn_E": 1e-12, + "rdqs_termination": true, + "rdqs_R_eq": 1e6, + "rdqs_dyn_E": 1e-12 + }, + "prepostamble": { + "read_zeroes": 0.0, + "write_zeroes": 0.0, + "read_ones": 0.0, + "write_ones": 0.0, + "read_zeroes_to_ones": 0, + "write_zeroes_to_ones": 0, + "write_ones_to_zeroes": 0, + "read_ones_to_zeroes": 0, + "readMinTccd": 0, + "writeMinTccd": 0 } }, "simconfig": { diff --git a/tests/tests_dramsys/b_transport/configs/storage.json b/tests/tests_dramsys/b_transport/configs/storage.json index 9f060231..307f8c5c 100644 --- a/tests/tests_dramsys/b_transport/configs/storage.json +++ b/tests/tests_dramsys/b_transport/configs/storage.json @@ -70,26 +70,39 @@ "nbrOfDevices": 8, "nbrOfRanks": 1, "nbrOfRows": 32768, + "RefMode": 1, "width": 8 }, "memoryId": "MICRON_4Gb_DDR4-1866_8bit_A", "memoryType": "DDR4", "mempowerspec": { + "vdd": 1.2, "idd0": 56.25, - "idd02": 4.05, "idd2n": 33.75, - "idd2p0": 17.0, - "idd2p1": 17.0, "idd3n": 39.5, - "idd3p0": 22.5, - "idd3p1": 22.5, "idd4r": 157.5, "idd4w": 135.0, - "idd5": 118.0, - "idd6": 20.25, - "idd62": 2.6, - "vdd": 1.2, - "vdd2": 2.5 + "idd6n": 22.5, + "idd2p": 17.0, + "idd3p": 22.5, + "idd5B": 0.0, + "idd5F2": 0.0, + "idd5F4": 0.0, + + "vpp": 0.0, + "ipp0": 0.0, + "ipp2n": 0.0, + "ipp3n": 0.0, + "ipp4r": 0.0, + "ipp4w": 0.0, + "ipp6n": 0.0, + "ipp2p": 0.0, + "ipp3p": 0.0, + "ipp5B": 0.0, + "ipp5F2": 0.0, + "ipp5F4": 0.0, + + "vddq": 1.2 }, "memtimingspec": { "ACTPDEN": 1, @@ -108,7 +121,7 @@ "REFI": 7280, "REFM": 1, "REFPDEN": 1, - "RFC": 243, + "RFC1": 243, "RFC2": 150, "RFC4": 103, "RL": 13, @@ -128,6 +141,41 @@ "XS": 252, "XSDLL": 512, "tCK": 1072 + }, + "memimpedancespec": { + "ck_termination": true, + "ck_R_eq": 1e6, + "ck_dyn_E": 1e-12, + + "ca_termination": true, + "ca_R_eq": 1e6, + "ca_dyn_E": 1e-12, + + "rdq_termination": true, + "rdq_R_eq": 1e6, + "rdq_dyn_E": 1e-12, + "wdq_termination": true, + "wdq_R_eq": 1e6, + "wdq_dyn_E": 1e-12, + + "wdqs_termination": true, + "wdqs_R_eq": 1e6, + "wdqs_dyn_E": 1e-12, + "rdqs_termination": true, + "rdqs_R_eq": 1e6, + "rdqs_dyn_E": 1e-12 + }, + "prepostamble": { + "read_zeroes": 0.0, + "write_zeroes": 0.0, + "read_ones": 0.0, + "write_ones": 0.0, + "read_zeroes_to_ones": 0, + "write_zeroes_to_ones": 0, + "write_ones_to_zeroes": 0, + "read_ones_to_zeroes": 0, + "readMinTccd": 0, + "writeMinTccd": 0 } }, "simconfig": { diff --git a/tests/tests_regression/DDR3/ddr3-example.json b/tests/tests_regression/DDR3/ddr3-example.json index 0e49e60b..34af9561 100644 --- a/tests/tests_regression/DDR3/ddr3-example.json +++ b/tests/tests_regression/DDR3/ddr3-example.json @@ -65,22 +65,23 @@ "nbrOfChannels": 1, "nbrOfRows": 16384, "width": 64, - "nbrOfDevices": 1 + "nbrOfDevices": 1, + "maxBurstLength": 8 }, "memoryId": "MICRON_2GB_DDR3-1066_64bit_D_SODIMM", "memoryType": "DDR3", "mempowerspec": { - "idd0": 720.0, - "idd2n": 400.0, - "idd2p0": 80.0, - "idd2p1": 200.0, - "idd3n": 440.0, - "idd3p0": 240.0, - "idd3p1": 240.0, - "idd4r": 1200.0, - "idd4w": 1200.0, - "idd5": 1760.0, - "idd6": 48.0, + "idd0": 720.0e-3, + "idd2n": 400.0e-3, + "idd2p0": 80.0e-3, + "idd2p1": 200.0e-3, + "idd3n": 440.0e-3, + "idd3p0": 240.0e-3, + "idd3p1": 240.0e-3, + "idd4r": 1200.0e-3, + "idd4w": 1200.0e-3, + "idd5": 1760.0e-3, + "idd6": 48.0e-3, "vdd": 1.5 }, "memtimingspec": { @@ -111,7 +112,7 @@ "PRPDEN": 1, "REFPDEN": 1, "RTRS": 1, - "tCK": 1876 + "tCK": 1876e-12 } }, "simconfig": { @@ -123,7 +124,7 @@ "EnableWindowing": false, "ErrorCSVFile": "", "ErrorChipSeed": 42, - "PowerAnalysis": true, + "PowerAnalysis": false, "SimulationName": "ddr3", "SimulationProgressBar": true, "StoreMode": "NoStorage", diff --git a/tests/tests_regression/DDR3/expected/DRAMSys_ddr3-dual-rank_ddr3_ch0.tdb b/tests/tests_regression/DDR3/expected/DRAMSys_ddr3-dual-rank_ddr3_ch0.tdb index 88d7a543..2002c1c2 100644 --- a/tests/tests_regression/DDR3/expected/DRAMSys_ddr3-dual-rank_ddr3_ch0.tdb +++ b/tests/tests_regression/DDR3/expected/DRAMSys_ddr3-dual-rank_ddr3_ch0.tdb @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:ce0fe36061b63a23c0323a2748f1da657bedda18bbf27e2a34edb0fad4c0fdb8 +oid sha256:42e35a7b37068126ad611610231d0ed8b665bc8a442b20b6a94d93fd2dec94e4 size 139264 diff --git a/tests/tests_regression/DDR4/ddr4-example.json b/tests/tests_regression/DDR4/ddr4-example.json index 326cd060..aaad9378 100644 --- a/tests/tests_regression/DDR4/ddr4-example.json +++ b/tests/tests_regression/DDR4/ddr4-example.json @@ -67,26 +67,44 @@ "nbrOfChannels": 1, "nbrOfRows": 32768, "width": 8, - "nbrOfDevices": 8 + "RefMode": 1, + "nbrOfDevices": 8, + "maxBurstLength": 8 }, "memoryId": "MICRON_4Gb_DDR4-1866_8bit_A", "memoryType": "DDR4", "mempowerspec": { - "idd0": 56.25, - "idd02": 4.05, - "idd2n": 33.75, - "idd2p0": 17.0, - "idd2p1": 17.0, - "idd3n": 39.5, - "idd3p0": 22.5, - "idd3p1": 22.5, - "idd4r": 157.5, - "idd4w": 135.0, - "idd5": 118.0, - "idd6": 20.25, - "idd62": 2.6, "vdd": 1.2, - "vdd2": 2.5 + "idd0": 56.25e-3, + "idd2n": 33.75e-3, + "idd3n": 39.5e-3, + "idd4r": 157.5e-3, + "idd4w": 135.0e-3, + "idd6n": 20.25e-3, + "idd2p": 17.0e-3, + "idd3p": 22.5e-3, + + "vpp": 2.5, + "ipp0": 4.05e-3, + "ipp2n": 0.0, + "ipp3n": 0.0, + "ipp4r": 0.0, + "ipp4w": 0.0, + "ipp6n": 2.6e-3, + "ipp2p": 17.0e-3, + "ipp3p": 22.5e-3, + + "idd5B": 118.0e-3, + "ipp5B": 0.0, + "idd5F2": 0.0, + "ipp5F2": 0.0, + "idd5F4": 0.0, + "ipp5F4": 0.0, + + "vddq": 0.0, + + "iBeta_vdd": 56.25e-3, + "iBeta_vpp": 4.05e-3 }, "memtimingspec": { "AL": 0, @@ -102,7 +120,9 @@ "RCD": 13, "REFM": 1, "REFI": 3644, - "RFC": 243, + "RFC1": 243, + "RFC2": 0, + "RFC4": 0, "RL": 13, "RPRE": 1, "RP": 13, @@ -122,7 +142,45 @@ "PRPDEN": 1, "REFPDEN": 1, "RTRS": 1, - "tCK": 1072 + "tCK": 1072e-12 + }, + "bankwisespec": { + "factRho": 1.0 + }, + "memimpedancespec": { + "ck_termination": true, + "ck_R_eq": 1e6, + "ck_dyn_E": 1e-12, + + "ca_termination": true, + "ca_R_eq": 1e6, + "ca_dyn_E": 1e-12, + + "rdq_termination": true, + "rdq_R_eq": 1e6, + "rdq_dyn_E": 1e-12, + "wdq_termination": true, + "wdq_R_eq": 1e6, + "wdq_dyn_E": 1e-12, + + "wdqs_termination": true, + "wdqs_R_eq": 1e6, + "wdqs_dyn_E": 1e-12, + "rdqs_termination": true, + "rdqs_R_eq": 1e6, + "rdqs_dyn_E": 1e-12 + }, + "prepostamble": { + "read_zeroes": 0.0, + "write_zeroes": 0.0, + "read_ones": 0.0, + "write_ones": 0.0, + "read_zeroes_to_ones": 0, + "write_zeroes_to_ones": 0, + "write_ones_to_zeroes": 0, + "read_ones_to_zeroes": 0, + "readMinTccd": 0, + "writeMinTccd": 0 } }, "simconfig": { @@ -140,7 +198,15 @@ "StoreMode": "NoStorage", "ThermalSimulation": false, "UseMalloc": false, - "WindowSize": 1000 + "WindowSize": 1000, + "TogglingRate": { + "togglingRateRead": 0.5, + "togglingRateWrite": 0.5, + "dutyCycleRead": 0.5, + "dutyCycleWrite": 0.5, + "idlePatternRead": "H", + "idlePatternWrite": "H" + } }, "simulationid": "ddr4-bankgrp", "tracesetup": [ diff --git a/tests/tests_regression/DDR4/expected/DRAMSys_ddr4-bankgrp_ddr4_ch0.tdb b/tests/tests_regression/DDR4/expected/DRAMSys_ddr4-bankgrp_ddr4_ch0.tdb index f78440a3..2c1b1a98 100644 --- a/tests/tests_regression/DDR4/expected/DRAMSys_ddr4-bankgrp_ddr4_ch0.tdb +++ b/tests/tests_regression/DDR4/expected/DRAMSys_ddr4-bankgrp_ddr4_ch0.tdb @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:df2c6750bfad509dc4746a876ebc090eae5a4006df05b9d8ccb5aeac673830ac -size 5050368 +oid sha256:b581129f7e4242d78470a7945deab9486fe8740ee11f374d9dc55e9f65702061 +size 5079040 diff --git a/tests/tests_regression/DDR5/ddr5-example.json b/tests/tests_regression/DDR5/ddr5-example.json index 31bb498a..8b3d3725 100644 --- a/tests/tests_regression/DDR5/ddr5-example.json +++ b/tests/tests_regression/DDR5/ddr5-example.json @@ -81,8 +81,9 @@ "nbrOfPhysicalRanks": 1, "nbrOfRanks": 1, "nbrOfRows": 65536, - "refMode": 1, - "width": 4 + "RefMode": 1, + "width": 4, + "maxBurstLength": 16 }, "memoryId": "JEDEC_2x8x2Gbx4_DDR5-3200A", "memoryType": "DDR5", @@ -138,7 +139,67 @@ "WTR_M": 16, "WTR_S": 4, "XP": 12, - "tCK": 625 + "tCK": 625e-12 + }, + "mempowerspec": { + "vdd": 0.0, + "idd0": 0.0, + "idd2n": 0.0, + "idd3n": 0.0, + "idd4r": 0.0, + "idd4w": 0.0, + "idd5c": 0.0, + "idd6n": 0.0, + "idd2p": 0.0, + "idd3p": 0.0, + "vpp": 0.0, + "ipp0": 0.0, + "ipp2n": 0.0, + "ipp3n": 0.0, + "ipp4r": 0.0, + "ipp4w": 0.0, + "ipp5c": 0.0, + "ipp6n": 0.0, + "ipp2p": 0.0, + "ipp3p": 0.0, + "idd5b": 0.0, + "idd5f": 0.0, + "ipp5b": 0.0, + "ipp5f": 0.0, + "vddq": 0.0, + "iBeta_vdd": 0.0, + "iBeta_vpp": 0.0 + }, + "bankwisespec": { + "factRho": 1.0 + }, + "memimpedancespec": { + "ck_termination": true, + "ck_R_eq": 1e6, + "ck_dyn_E": 1e-12, + + "ca_termination": true, + "ca_R_eq": 1e6, + "ca_dyn_E": 1e-12, + + "rdq_termination": true, + "rdq_R_eq": 1e6, + "rdq_dyn_E": 1e-12, + "wdq_termination": true, + "wdq_R_eq": 1e6, + "wdq_dyn_E": 1e-12, + + "wdqs_termination": true, + "wdqs_R_eq": 1e6, + "wdqs_dyn_E": 1e-12, + "rdqs_termination": true, + "rdqs_R_eq": 1e6, + "rdqs_dyn_E": 1e-12 + }, + "dataratespec": { + "ca_bus_rate": 2, + "dq_bus_rate": 2, + "dqs_bus_rate": 2 } }, "simconfig": { diff --git a/tests/tests_regression/HBM2/hbm2-example.json b/tests/tests_regression/HBM2/hbm2-example.json index 25d0589f..8d4f3433 100644 --- a/tests/tests_regression/HBM2/hbm2-example.json +++ b/tests/tests_regression/HBM2/hbm2-example.json @@ -69,7 +69,8 @@ "nbrOfChannels": 2, "nbrOfDevices": 1, "nbrOfRows": 32768, - "width": 128 + "width": 128, + "maxBurstLength": 4 }, "memoryId": "https://www.computerbase.de/2019-05/amd-memory-tweak-vram-oc/#bilder", "memoryType": "HBM2", @@ -102,7 +103,7 @@ "WTRS": 4, "XP": 8, "XS": 216, - "tCK": 1000 + "tCK": 1000e-12 } }, "simconfig": { diff --git a/tests/tests_regression/HBM3/hbm3-example.json b/tests/tests_regression/HBM3/hbm3-example.json index c20d579e..11f5f5e0 100644 --- a/tests/tests_regression/HBM3/hbm3-example.json +++ b/tests/tests_regression/HBM3/hbm3-example.json @@ -71,7 +71,8 @@ "nbrOfChannels": 1, "RAAIMT" : 16, "RAAMMT" : 96, - "RAADEC" : 16 + "RAADEC" : 16, + "maxBurstLength": 8 }, "memoryId": "", "memoryType": "HBM3", @@ -105,7 +106,7 @@ "WTRS": 4, "XP": 8, "XS": 260, - "tCK": 625 + "tCK": 625e-12 } }, "simconfig": { diff --git a/tests/tests_regression/LPDDR4/lpddr4-example.json b/tests/tests_regression/LPDDR4/lpddr4-example.json index a0c9aa08..f856a3f6 100644 --- a/tests/tests_regression/LPDDR4/lpddr4-example.json +++ b/tests/tests_regression/LPDDR4/lpddr4-example.json @@ -54,6 +54,7 @@ }, "memspec": { "memarchitecturespec": { + "nbrOfBankGroups": 1, "burstLength": 16, "dataRate": 2, "nbrOfBanks": 8, @@ -62,7 +63,8 @@ "nbrOfChannels": 1, "nbrOfDevices": 1, "nbrOfRows": 65536, - "width": 16 + "width": 16, + "maxBurstLength": 16 }, "memoryId": "JEDEC_8Gb_LPDDR4-3200_16bit", "memoryType": "LPDDR4", @@ -80,14 +82,14 @@ "RAS": 68, "RCD": 29, "REFI": 6246, - "REFIPB": 780, - "RFCAB": 448, - "RFCPB": 224, + "REFIpb": 780, + "RFCab": 448, + "RFCpb": 224, "RL": 28, - "RPAB": 34, - "RPPB": 29, - "RCAB": 102, - "RCPB": 97, + "RPab": 34, + "RPpb": 29, + "RCab": 102, + "RCpb": 97, "RPST": 0, "RRD": 16, "RTP": 12, @@ -99,7 +101,64 @@ "XP": 12, "XSR": 460, "RTRS": 1, - "tCK": 625 + "REFM": 0, + "tCK": 625e-12 + }, + "mempowerspec": { + "vdd1": 0.0, + "idd01": 0.0, + "idd2n1": 0.0, + "idd3n1": 0.0, + "idd4r1": 0.0, + "idd4w1": 0.0, + "idd51": 0.0, + "idd5pb1": 0.0, + "idd61": 0.0, + "idd2p1": 0.0, + "idd3p1": 0.0, + "vdd2": 0.0, + "idd02": 0.0, + "idd2n2": 0.0, + "idd3n2": 0.0, + "idd4r2": 0.0, + "idd4w2": 0.0, + "idd52": 0.0, + "idd5pb2": 0.0, + "idd62": 0.0, + "idd2p2": 0.0, + "idd3p2": 0.0, + "vddq": 0.0, + "iBeta_vdd1": 0.0, + "iBeta_vdd2": 0.0 + }, + "memimpedancespec": { + "ck_termination": true, + "ck_R_eq": 1e6, + "ck_dyn_E": 1e-12, + + "ca_termination": true, + "ca_R_eq": 1e6, + "ca_dyn_E": 1e-12, + + "rdq_termination": true, + "rdq_R_eq": 1e6, + "rdq_dyn_E": 1e-12, + "wdq_termination": true, + "wdq_R_eq": 1e6, + "wdq_dyn_E": 1e-12, + + "wdqs_termination": true, + "wdqs_R_eq": 1e6, + "wdqs_dyn_E": 1e-12, + "rdqs_termination": true, + "rdqs_R_eq": 1e6, + "rdqs_dyn_E": 1e-12 + }, + "bankwisespec": { + "factRho": 1.0, + "factSigma": 1.0, + "pasrMode": 0, + "hasPASR": false } }, "simconfig": { diff --git a/tests/tests_regression/LPDDR5/lpddr5-example.json b/tests/tests_regression/LPDDR5/lpddr5-example.json index ba4c208e..69e84359 100644 --- a/tests/tests_regression/LPDDR5/lpddr5-example.json +++ b/tests/tests_regression/LPDDR5/lpddr5-example.json @@ -70,7 +70,9 @@ "nbrOfRanks": 1, "nbrOfRows": 65536, "per2BankOffset": 8, - "width": 16 + "width": 16, + "WCKalwaysOn": false, + "maxBurstLength": 16 }, "memoryId": "JEDEC_1Gbx16_BG_LPDDR5-6400", "memoryType": "LPDDR5", @@ -114,7 +116,75 @@ "WTR_S": 5, "pbR2act": 6, "pbR2pbR": 72, - "tCK": 800 + "tCK": 800e-12 + }, + "mempowerspec": { + "vdd1": 0.0, + "idd01": 0.0, + "idd2n1": 0.0, + "idd3n1": 0.0, + "idd4r1": 0.0, + "idd4w1": 0.0, + "idd51": 0.0, + "idd5pb1": 0.0, + "idd61": 0.0, + "idd6ds1": 0.0, + "idd2p1": 0.0, + "idd3p1": 0.0, + "vdd2h": 0.0, + "idd02h": 0.0, + "idd2n2h": 0.0, + "idd3n2h": 0.0, + "idd4r2h": 0.0, + "idd4w2h": 0.0, + "idd52h": 0.0, + "idd5pb2h": 0.0, + "idd62h": 0.0, + "idd6ds2h": 0.0, + "idd2p2h": 0.0, + "idd3p2h": 0.0, + "vdd2l": 0.0, + "idd02l": 0.0, + "idd2n2l": 0.0, + "idd3n2l": 0.0, + "idd4r2l": 0.0, + "idd4w2l": 0.0, + "idd52l": 0.0, + "idd5pb2l": 0.0, + "idd62l": 0.0, + "idd6ds2l": 0.0, + "idd2p2l": 0.0, + "idd3p2l": 0.0, + "vddq": 0.0, + "iBeta_vdd1": 0.0, + "iBeta_vdd2h": 0.0, + "iBeta_vdd2l": 0.0 + }, + "bankwisespec": { + "factRho": 1.0 + }, + "memimpedancespec": { + "ck_termination": true, + "ck_R_eq": 1e6, + "ck_dyn_E": 1e-12, + + "ca_termination": true, + "ca_R_eq": 1e6, + "ca_dyn_E": 1e-12, + + "rdq_termination": true, + "rdq_R_eq": 1e6, + "rdq_dyn_E": 1e-12, + "wdq_termination": true, + "wdq_R_eq": 1e6, + "wdq_dyn_E": 1e-12, + + "wck_termination": true, + "wck_R_eq": 1e6, + "wck_dyn_E": 1e-12, + "rdqs_termination": true, + "rdqs_R_eq": 1e6, + "rdqs_dyn_E": 1e-12 } }, "simconfig": { diff --git a/tools/CMakeLists.txt b/tools/CMakeLists.txt index 4ffb4a2d..3ee22c69 100644 --- a/tools/CMakeLists.txt +++ b/tools/CMakeLists.txt @@ -1,2 +1,8 @@ +find_package(nlohmann_json REQUIRED) + add_executable(json_converter json_converter.cpp) -target_link_libraries(json_converter PRIVATE DRAMSys::config) + +target_link_libraries(json_converter PRIVATE + DRAMSys::config + nlohmann_json::nlohmann_json +)