Integrate DRAMUtils and new DRAMPower

tests/tests_regression/DDR4/ddr4-example.json

@@ -67,26 +67,44 @@
                 "nbrOfChannels": 1,
                 "nbrOfRows": 32768,
                 "width": 8,
-                "nbrOfDevices": 8
+                "RefMode": 1,
+                "nbrOfDevices": 8,
+                "maxBurstLength": 8
             },
             "memoryId": "MICRON_4Gb_DDR4-1866_8bit_A",
             "memoryType": "DDR4",
             "mempowerspec": {
-                "idd0": 56.25,
-                "idd02": 4.05,
-                "idd2n": 33.75,
-                "idd2p0": 17.0,
-                "idd2p1": 17.0,
-                "idd3n": 39.5,
-                "idd3p0": 22.5,
-                "idd3p1": 22.5,
-                "idd4r": 157.5,
-                "idd4w": 135.0,
-                "idd5": 118.0,
-                "idd6": 20.25,
-                "idd62": 2.6,
                 "vdd": 1.2,
-                "vdd2": 2.5
+                "idd0": 56.25e-3,
+                "idd2n": 33.75e-3,
+                "idd3n": 39.5e-3,
+                "idd4r": 157.5e-3,
+                "idd4w": 135.0e-3,
+                "idd6n": 20.25e-3,
+                "idd2p": 17.0e-3,
+                "idd3p": 22.5e-3,
+
+                "vpp": 2.5,
+                "ipp0": 4.05e-3,
+                "ipp2n": 0.0,
+                "ipp3n": 0.0,
+                "ipp4r": 0.0,
+                "ipp4w": 0.0,
+                "ipp6n": 2.6e-3,
+                "ipp2p": 17.0e-3,
+                "ipp3p": 22.5e-3,
+
+                "idd5B": 118.0e-3,
+                "ipp5B": 0.0,
+                "idd5F2": 0.0,
+                "ipp5F2": 0.0,
+                "idd5F4": 0.0,
+                "ipp5F4": 0.0,
+
+                "vddq": 0.0,
+                
+                "iBeta_vdd": 56.25e-3,
+                "iBeta_vpp": 4.05e-3
             },
             "memtimingspec": {
                 "AL": 0,
@@ -102,7 +120,9 @@
                 "RCD": 13,
                 "REFM": 1,
                 "REFI": 3644,
-                "RFC": 243,
+                "RFC1": 243,
+                "RFC2": 0,
+                "RFC4": 0,
                 "RL": 13,
                 "RPRE": 1,
                 "RP": 13,
@@ -122,7 +142,45 @@
                 "PRPDEN": 1,
                 "REFPDEN": 1,
                 "RTRS": 1,
-                "tCK": 1072
+                "tCK": 1072e-12
+            },
+            "bankwisespec": {
+                "factRho": 1.0
+            },
+            "memimpedancespec": {
+                "ck_termination": true,
+                "ck_R_eq": 1e6,
+                "ck_dyn_E": 1e-12,
+          
+                "ca_termination": true,
+                "ca_R_eq": 1e6,
+                "ca_dyn_E": 1e-12,
+          
+                "rdq_termination": true,
+                "rdq_R_eq": 1e6,
+                "rdq_dyn_E": 1e-12,
+                "wdq_termination": true,
+                "wdq_R_eq": 1e6,
+                "wdq_dyn_E": 1e-12,
+          
+                "wdqs_termination": true,
+                "wdqs_R_eq": 1e6,
+                "wdqs_dyn_E": 1e-12,
+                "rdqs_termination": true,
+                "rdqs_R_eq": 1e6,
+                "rdqs_dyn_E": 1e-12
+            },
+            "prepostamble": {
+                "read_zeroes": 0.0,
+                "write_zeroes": 0.0,
+                "read_ones": 0.0,
+                "write_ones": 0.0,
+                "read_zeroes_to_ones": 0,
+                "write_zeroes_to_ones": 0,
+                "write_ones_to_zeroes": 0,
+                "read_ones_to_zeroes": 0,
+                "readMinTccd": 0,
+                "writeMinTccd": 0
             }
         },
         "simconfig": {
@@ -140,7 +198,15 @@
             "StoreMode": "NoStorage",
             "ThermalSimulation": false,
             "UseMalloc": false,
-            "WindowSize": 1000
+            "WindowSize": 1000,
+            "TogglingRate": {
+                "togglingRateRead": 0.5,
+                "togglingRateWrite": 0.5,
+                "dutyCycleRead": 0.5,
+                "dutyCycleWrite": 0.5,
+                "idlePatternRead": "H",
+                "idlePatternWrite": "H"
+            }
         },
         "simulationid": "ddr4-bankgrp",
         "tracesetup": [