Integrate DRAMUtils and new DRAMPower
This commit is contained in:
marcomoerz
@@ -31,6 +31,7 @@
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# Authors:
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# Derek Christ
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# Thomas Psota
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# Marco Mörz
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########################################
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### DRAMSys::config ###
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@@ -38,16 +39,13 @@
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add_library(configuration
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DRAMSys/config/DRAMSysConfiguration.cpp
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DRAMSys/config/memspec/MemArchitectureSpec.cpp
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DRAMSys/config/memspec/MemPowerSpec.cpp
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DRAMSys/config/memspec/MemTimingSpec.cpp
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)
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target_include_directories(configuration PUBLIC ${CMAKE_CURRENT_SOURCE_DIR})
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target_link_libraries(configuration
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PUBLIC
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nlohmann_json::nlohmann_json
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DRAMUtils::DRAMUtils
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)
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target_compile_features(configuration PUBLIC cxx_std_17)
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@@ -36,7 +36,7 @@
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#ifndef DRAMSYSCONFIGURATION_ADDRESSMAPPING_H
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#define DRAMSYSCONFIGURATION_ADDRESSMAPPING_H
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#include "DRAMSys/util/json.h"
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#include <DRAMUtils/util/json_utils.h>
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#include <optional>
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@@ -35,6 +35,8 @@
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#include "DRAMSysConfiguration.h"
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#include "DRAMSys/config/MemSpec.h"
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#include <fstream>
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namespace DRAMSys::Config
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@@ -71,7 +73,7 @@ Configuration from_path(std::filesystem::path baseConfig)
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{
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assert(parsed.is_string());
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if (parsed == MemSpec::KEY)
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if (parsed == MemSpecConstants::KEY)
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current_sub_config = SubConfig::MemSpec;
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else if (parsed == AddressMapping::KEY)
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current_sub_config = SubConfig::AddressMapping;
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@@ -107,7 +109,7 @@ Configuration from_path(std::filesystem::path baseConfig)
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};
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if (current_sub_config == SubConfig::MemSpec)
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parsed = parse_json(MemSpec::KEY, parsed);
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parsed = parse_json(MemSpecConstants::KEY, parsed);
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else if (current_sub_config == SubConfig::AddressMapping)
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parsed = parse_json(AddressMapping::KEY, parsed);
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else if (current_sub_config == SubConfig::McConfig)
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@@ -40,7 +40,9 @@
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#include "DRAMSys/config/McConfig.h"
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#include "DRAMSys/config/SimConfig.h"
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#include "DRAMSys/config/TraceSetup.h"
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#include "DRAMSys/config/memspec/MemSpec.h"
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#include <DRAMUtils/memspec/MemSpec.h>
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#include <DRAMUtils/util/json_utils.h>
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#include <optional>
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#include <string>
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@@ -66,7 +68,7 @@ struct Configuration
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AddressMapping addressmapping;
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McConfig mcconfig;
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MemSpec memspec;
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DRAMUtils::MemSpec::MemSpecVariant memspec;
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SimConfig simconfig;
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std::string simulationid;
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std::optional<std::vector<Initiator>> tracesetup;
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@@ -36,7 +36,7 @@
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#ifndef DRAMSYSCONFIGURATION_MCCONFIG_H
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#define DRAMSYSCONFIGURATION_MCCONFIG_H
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#include "DRAMSys/util/json.h"
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#include <DRAMUtils/util/json_utils.h>
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#include <optional>
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@@ -33,27 +33,20 @@
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* Derek Christ
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*/
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#include "MemPowerSpec.h"
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#ifndef DRAMSYSCONFIGURATION_MEMSPEC_H
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#define DRAMSYSCONFIGURATION_MEMSPEC_H
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#include <string_view>
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namespace DRAMSys::Config
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{
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void to_json(json_t& j, const MemPowerSpec& c)
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struct MemSpecConstants
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{
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j = json_t{};
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for (const auto& entry : c.entries)
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{
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j[entry.first] = entry.second;
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}
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}
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void from_json(const json_t& j, MemPowerSpec& c)
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{
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for (const auto& entry : j.items())
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{
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c.entries[entry.key()] = entry.value();
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}
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}
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static constexpr std::string_view KEY = "memspec";
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static constexpr std::string_view SUB_DIR = "memspec";
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};
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} // namespace DRAMSys::Config
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#endif // DRAMSYSCONFIGURATION_MEMSPEC_H
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@@ -36,7 +36,8 @@
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#ifndef DRAMSYSCONFIGURATION_SIMCONFIG_H
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#define DRAMSYSCONFIGURATION_SIMCONFIG_H
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#include "DRAMSys/util/json.h"
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#include <DRAMUtils/util/json_utils.h>
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#include <DRAMUtils/config/toggling_rate.h>
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#include <optional>
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@@ -72,6 +73,7 @@ struct SimConfig
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std::optional<bool> UseMalloc;
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std::optional<unsigned int> WindowSize;
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std::optional<double> SimulationTime;
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std::optional<DRAMUtils::Config::ToggleRateDefinition> TogglingRate;
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};
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NLOHMANN_JSONIFY_ALL_THINGS(SimConfig,
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@@ -87,7 +89,8 @@ NLOHMANN_JSONIFY_ALL_THINGS(SimConfig,
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ThermalSimulation,
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UseMalloc,
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WindowSize,
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SimulationTime)
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SimulationTime,
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TogglingRate)
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} // namespace DRAMSys::Config
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@@ -36,7 +36,7 @@
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#ifndef DRAMSYSCONFIGURATION_TRACESETUP_H
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#define DRAMSYSCONFIGURATION_TRACESETUP_H
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#include "DRAMSys/util/json.h"
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#include <DRAMUtils/util/json_utils.h>
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#include <optional>
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#include <variant>
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@@ -1,59 +0,0 @@
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/*
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* Copyright (c) 2021, RPTU Kaiserslautern-Landau
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
*
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||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
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||||
* 3. Neither the name of the copyright holder nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
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||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
|
||||
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
|
||||
* OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
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* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
|
||||
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
|
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* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors:
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* Derek Christ
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*/
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#include "MemArchitectureSpec.h"
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namespace DRAMSys::Config
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{
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void to_json(json_t& j, const MemArchitectureSpecType& c)
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{
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j = json_t{};
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for (const auto& entry : c.entries)
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{
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j[entry.first] = entry.second;
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}
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}
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void from_json(const json_t& j, MemArchitectureSpecType& c)
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{
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for (const auto& entry : j.items())
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{
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c.entries[entry.key()] = entry.value();
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}
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}
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} // namespace DRAMSys::Config
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@@ -1,56 +0,0 @@
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/*
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* Copyright (c) 2021, RPTU Kaiserslautern-Landau
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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||||
*
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* 1. Redistributions of source code must retain the above copyright notice,
|
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* this list of conditions and the following disclaimer.
|
||||
*
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* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
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* 3. Neither the name of the copyright holder nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
|
||||
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
|
||||
* OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
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* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
|
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* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
|
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* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors:
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* Derek Christ
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*/
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#ifndef DRAMSYSCONFIGURATION_MEMARCHITECTURESPEC_H
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#define DRAMSYSCONFIGURATION_MEMARCHITECTURESPEC_H
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#include "DRAMSys/util/json.h"
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#include <unordered_map>
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namespace DRAMSys::Config
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{
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struct MemArchitectureSpecType
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{
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std::unordered_map<std::string, unsigned int> entries;
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};
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void to_json(json_t& j, const MemArchitectureSpecType& c);
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void from_json(const json_t& j, MemArchitectureSpecType& c);
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} // namespace DRAMSys::Config
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#endif // DRAMSYSCONFIGURATION_MEMARCHITECTURESPEC_H
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@@ -1,56 +0,0 @@
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/*
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* Copyright (c) 2021, RPTU Kaiserslautern-Landau
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
|
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* modification, are permitted provided that the following conditions are
|
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* met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of the copyright holder nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
|
||||
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
|
||||
* OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
|
||||
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
|
||||
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
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*
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* Authors:
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* Derek Christ
|
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*/
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#ifndef DRAMSYSCONFIGURATION_MEMPOWERSPEC_H
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#define DRAMSYSCONFIGURATION_MEMPOWERSPEC_H
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#include "DRAMSys/util/json.h"
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#include <unordered_map>
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namespace DRAMSys::Config
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{
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struct MemPowerSpec
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{
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std::unordered_map<std::string, double> entries;
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};
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void to_json(json_t& j, const MemPowerSpec& c);
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void from_json(const json_t& j, MemPowerSpec& c);
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} // namespace DRAMSys::Config
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#endif // DRAMSYSCONFIGURATION_MEMPOWERSPEC_H
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@@ -1,99 +0,0 @@
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/*
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* Copyright (c) 2021, RPTU Kaiserslautern-Landau
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are
|
||||
* met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of the copyright holder nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
|
||||
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
|
||||
* OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
|
||||
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
|
||||
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* Authors:
|
||||
* Derek Christ
|
||||
*/
|
||||
|
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#ifndef DRAMSYSCONFIGURATION_MEMSPEC_H
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#define DRAMSYSCONFIGURATION_MEMSPEC_H
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#include "DRAMSys/config/memspec/MemArchitectureSpec.h"
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#include "DRAMSys/config/memspec/MemPowerSpec.h"
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#include "DRAMSys/config/memspec/MemTimingSpec.h"
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#include "DRAMSys/util/json.h"
|
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|
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#include <optional>
|
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namespace DRAMSys::Config
|
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{
|
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enum class MemoryType
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{
|
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DDR3,
|
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DDR4,
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DDR5,
|
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LPDDR4,
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LPDDR5,
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WideIO,
|
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WideIO2,
|
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GDDR5,
|
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GDDR5X,
|
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GDDR6,
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HBM2,
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HBM3,
|
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STTMRAM,
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Invalid = -1
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};
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NLOHMANN_JSON_SERIALIZE_ENUM(MemoryType,
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{{MemoryType::Invalid, nullptr},
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{MemoryType::DDR3, "DDR3"},
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{MemoryType::DDR4, "DDR4"},
|
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{MemoryType::DDR5, "DDR5"},
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{MemoryType::LPDDR4, "LPDDR4"},
|
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{MemoryType::LPDDR5, "LPDDR5"},
|
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{MemoryType::WideIO, "WIDEIO_SDR"},
|
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{MemoryType::WideIO2, "WIDEIO2"},
|
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{MemoryType::GDDR5, "GDDR5"},
|
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{MemoryType::GDDR5X, "GDDR5X"},
|
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{MemoryType::GDDR6, "GDDR6"},
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{MemoryType::HBM2, "HBM2"},
|
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{MemoryType::HBM3, "HBM3"},
|
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{MemoryType::STTMRAM, "STT-MRAM"}})
|
||||
|
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struct MemSpec
|
||||
{
|
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static constexpr std::string_view KEY = "memspec";
|
||||
|
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MemArchitectureSpecType memarchitecturespec;
|
||||
std::string memoryId;
|
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MemoryType memoryType;
|
||||
MemTimingSpecType memtimingspec;
|
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std::optional<MemPowerSpec> mempowerspec;
|
||||
};
|
||||
|
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NLOHMANN_JSONIFY_ALL_THINGS(
|
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MemSpec, memarchitecturespec, memoryId, memoryType, memtimingspec, mempowerspec)
|
||||
|
||||
} // namespace DRAMSys::Config
|
||||
|
||||
#endif // DRAMSYSCONFIGURATION_MEMSPEC_H
|
||||
@@ -1,59 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) 2021, RPTU Kaiserslautern-Landau
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are
|
||||
* met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of the copyright holder nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
|
||||
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
|
||||
* OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
|
||||
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
|
||||
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* Authors:
|
||||
* Derek Christ
|
||||
*/
|
||||
|
||||
#include "MemTimingSpec.h"
|
||||
|
||||
namespace DRAMSys::Config
|
||||
{
|
||||
|
||||
void to_json(json_t& j, const MemTimingSpecType& c)
|
||||
{
|
||||
j = json_t{};
|
||||
|
||||
for (const auto& entry : c.entries)
|
||||
{
|
||||
j[entry.first] = entry.second;
|
||||
}
|
||||
}
|
||||
|
||||
void from_json(const json_t& j, MemTimingSpecType& c)
|
||||
{
|
||||
for (const auto& entry : j.items())
|
||||
{
|
||||
c.entries[entry.key()] = entry.value();
|
||||
}
|
||||
}
|
||||
|
||||
} // namespace DRAMSys::Config
|
||||
@@ -1,57 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) 2021, RPTU Kaiserslautern-Landau
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are
|
||||
* met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of the copyright holder nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
|
||||
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
|
||||
* OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
|
||||
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
|
||||
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* Authors:
|
||||
* Derek Christ
|
||||
*/
|
||||
|
||||
#ifndef DRAMSYSCONFIGURATION_MEMTIMINGSPEC_H
|
||||
#define DRAMSYSCONFIGURATION_MEMTIMINGSPEC_H
|
||||
|
||||
#include "DRAMSys/util/json.h"
|
||||
|
||||
#include <unordered_map>
|
||||
|
||||
namespace DRAMSys::Config
|
||||
{
|
||||
using json = nlohmann::json;
|
||||
|
||||
struct MemTimingSpecType
|
||||
{
|
||||
std::unordered_map<std::string, unsigned int> entries;
|
||||
};
|
||||
|
||||
void to_json(json& j, const MemTimingSpecType& c);
|
||||
void from_json(const json& j, MemTimingSpecType& c);
|
||||
|
||||
} // namespace DRAMSys::Config
|
||||
|
||||
#endif // DRAMSYSCONFIGURATION_MEMTIMINGSPEC_H
|
||||
@@ -1,166 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) 2021, RPTU Kaiserslautern-Landau
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are
|
||||
* met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of the copyright holder nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
|
||||
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
|
||||
* OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
|
||||
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
|
||||
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* Authors:
|
||||
* Thomas Psota
|
||||
* Derek Christ
|
||||
*/
|
||||
|
||||
#ifndef DRAMSYSCONFIGURATION_JSON_H
|
||||
#define DRAMSYSCONFIGURATION_JSON_H
|
||||
|
||||
#include <nlohmann/json.hpp>
|
||||
|
||||
#include <optional>
|
||||
#include <variant>
|
||||
|
||||
using json_t = nlohmann::json;
|
||||
|
||||
namespace DRAMSys::Config
|
||||
{
|
||||
// See https://www.kdab.com/jsonify-with-nlohmann-json/
|
||||
// Try to set the value of type T into the variant data if it fails, do nothing
|
||||
template <typename T, typename... Ts>
|
||||
void variant_from_json(const nlohmann::json& j, std::variant<Ts...>& data)
|
||||
{
|
||||
try
|
||||
{
|
||||
data = j.get<T>();
|
||||
}
|
||||
catch (...)
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
template <typename T>
|
||||
void optional_to_json(nlohmann::json& j, std::string_view name, const std::optional<T>& value)
|
||||
{
|
||||
if (value)
|
||||
j[name] = *value;
|
||||
}
|
||||
|
||||
template <class T>
|
||||
void optional_from_json(const nlohmann::json& j, std::string_view name, std::optional<T>& value)
|
||||
{
|
||||
const auto it = j.find(name);
|
||||
|
||||
if (it != j.end())
|
||||
value = it->get<T>();
|
||||
else
|
||||
value = std::nullopt;
|
||||
}
|
||||
|
||||
template <typename> constexpr bool is_optional = false;
|
||||
template <typename T> constexpr bool is_optional<std::optional<T>> = true;
|
||||
|
||||
template <typename T> void extended_to_json(const char* key, nlohmann::json& j, const T& value)
|
||||
{
|
||||
if constexpr (is_optional<T>)
|
||||
optional_to_json(j, key, value);
|
||||
else
|
||||
j[key] = value;
|
||||
}
|
||||
|
||||
template <typename T> void extended_from_json(const char* key, const nlohmann::json& j, T& value)
|
||||
{
|
||||
if constexpr (is_optional<T>)
|
||||
optional_from_json(j, key, value);
|
||||
else
|
||||
j.at(key).get_to(value);
|
||||
}
|
||||
|
||||
} // namespace DRAMSys::Config
|
||||
|
||||
NLOHMANN_JSON_NAMESPACE_BEGIN
|
||||
|
||||
template <typename... Ts> struct adl_serializer<std::variant<Ts...>>
|
||||
{
|
||||
static void to_json(nlohmann::json& j, const std::variant<Ts...>& data)
|
||||
{
|
||||
std::visit([&j](const auto& v) { j = v; }, data);
|
||||
}
|
||||
|
||||
static void from_json(const nlohmann::json& j, std::variant<Ts...>& data)
|
||||
{
|
||||
// Call variant_from_json for all types, only one will succeed
|
||||
(DRAMSys::Config::variant_from_json<Ts>(j, data), ...);
|
||||
}
|
||||
};
|
||||
|
||||
template <typename T> struct adl_serializer<std::optional<T>>
|
||||
{
|
||||
static void to_json(json_t& j, const std::optional<T>& opt)
|
||||
{
|
||||
if (opt == std::nullopt)
|
||||
{
|
||||
j = nullptr;
|
||||
}
|
||||
else
|
||||
{
|
||||
j = *opt;
|
||||
}
|
||||
}
|
||||
|
||||
static void from_json(const json_t& j, std::optional<T>& opt)
|
||||
{
|
||||
if (j.is_null())
|
||||
{
|
||||
opt = std::nullopt;
|
||||
}
|
||||
else
|
||||
{
|
||||
opt = j.get<T>();
|
||||
}
|
||||
}
|
||||
};
|
||||
|
||||
NLOHMANN_JSON_NAMESPACE_END
|
||||
|
||||
// NOLINTBEGIN(cppcoreguidelines-macro-usage)
|
||||
|
||||
#define EXTEND_JSON_TO(v1) \
|
||||
DRAMSys::Config::extended_to_json(#v1, nlohmann_json_j, nlohmann_json_t.v1);
|
||||
#define EXTEND_JSON_FROM(v1) \
|
||||
DRAMSys::Config::extended_from_json(#v1, nlohmann_json_j, nlohmann_json_t.v1);
|
||||
|
||||
#define NLOHMANN_JSONIFY_ALL_THINGS(Type, ...) \
|
||||
inline void to_json(nlohmann::json& nlohmann_json_j, const Type& nlohmann_json_t) \
|
||||
{ \
|
||||
NLOHMANN_JSON_EXPAND(NLOHMANN_JSON_PASTE(EXTEND_JSON_TO, __VA_ARGS__)) \
|
||||
} \
|
||||
inline void from_json(const nlohmann::json& nlohmann_json_j, Type& nlohmann_json_t) \
|
||||
{ \
|
||||
NLOHMANN_JSON_EXPAND(NLOHMANN_JSON_PASTE(EXTEND_JSON_FROM, __VA_ARGS__)) \
|
||||
}
|
||||
|
||||
// NOLINTEND(cppcoreguidelines-macro-usage)
|
||||
|
||||
#endif // DRAMSYSCONFIGURATION_JSON_H
|
||||
@@ -108,6 +108,7 @@ target_link_libraries(libdramsys
|
||||
PUBLIC
|
||||
SystemC::systemc
|
||||
DRAMSys::config
|
||||
DRAMUtils::DRAMUtils
|
||||
$<$<TARGET_EXISTS:DRAMPower::DRAMPower>:DRAMPower::DRAMPower>
|
||||
PRIVATE
|
||||
SQLite::SQLite3
|
||||
|
||||
@@ -32,6 +32,7 @@
|
||||
* Authors:
|
||||
* Lukas Steiner
|
||||
* Derek Christ
|
||||
* Marco Mörz
|
||||
*/
|
||||
|
||||
#include "MemSpec.h"
|
||||
@@ -42,43 +43,6 @@ using namespace tlm;
|
||||
namespace DRAMSys
|
||||
{
|
||||
|
||||
MemSpec::MemSpec(const Config::MemSpec& memSpec,
|
||||
unsigned numberOfChannels,
|
||||
unsigned ranksPerChannel,
|
||||
unsigned banksPerRank,
|
||||
unsigned groupsPerRank,
|
||||
unsigned banksPerGroup,
|
||||
unsigned banksPerChannel,
|
||||
unsigned bankGroupsPerChannel,
|
||||
unsigned devicesPerRank) :
|
||||
numberOfChannels(numberOfChannels),
|
||||
ranksPerChannel(ranksPerChannel),
|
||||
banksPerRank(banksPerRank),
|
||||
groupsPerRank(groupsPerRank),
|
||||
banksPerGroup(banksPerGroup),
|
||||
banksPerChannel(banksPerChannel),
|
||||
bankGroupsPerChannel(bankGroupsPerChannel),
|
||||
devicesPerRank(devicesPerRank),
|
||||
rowsPerBank(memSpec.memarchitecturespec.entries.at("nbrOfRows")),
|
||||
columnsPerRow(memSpec.memarchitecturespec.entries.at("nbrOfColumns")),
|
||||
defaultBurstLength(memSpec.memarchitecturespec.entries.at("burstLength")),
|
||||
maxBurstLength(memSpec.memarchitecturespec.entries.find("maxBurstLength") !=
|
||||
memSpec.memarchitecturespec.entries.end()
|
||||
? memSpec.memarchitecturespec.entries.at("maxBurstLength")
|
||||
: defaultBurstLength),
|
||||
dataRate(memSpec.memarchitecturespec.entries.at("dataRate")),
|
||||
bitWidth(memSpec.memarchitecturespec.entries.at("width")),
|
||||
dataBusWidth(bitWidth * devicesPerRank),
|
||||
defaultBytesPerBurst((defaultBurstLength * dataBusWidth) / 8),
|
||||
maxBytesPerBurst((maxBurstLength * dataBusWidth) / 8),
|
||||
tCK(sc_time(memSpec.memtimingspec.entries.at("tCK"), SC_PS)),
|
||||
memoryId(memSpec.memoryId),
|
||||
memoryType(memSpec.memoryType),
|
||||
burstDuration(tCK * (static_cast<double>(defaultBurstLength) / dataRate))
|
||||
{
|
||||
commandLengthInCycles = std::vector<double>(Command::numberOfCommands(), 1);
|
||||
}
|
||||
|
||||
sc_time MemSpec::getCommandLength(Command command) const
|
||||
{
|
||||
return tCK * commandLengthInCycles[command];
|
||||
@@ -160,28 +124,4 @@ bool MemSpec::requiresMaskedWrite(const tlm::tlm_generic_payload& payload) const
|
||||
throw;
|
||||
}
|
||||
|
||||
bool MemSpec::allBytesEnabled(const tlm::tlm_generic_payload& trans)
|
||||
{
|
||||
if (trans.get_byte_enable_ptr() == nullptr)
|
||||
return true;
|
||||
|
||||
for (std::size_t i = 0; i < trans.get_byte_enable_length(); i++)
|
||||
{
|
||||
if (trans.get_byte_enable_ptr()[i] != TLM_BYTE_ENABLED)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
#ifdef DRAMPOWER
|
||||
DRAMPower::MemorySpecification MemSpec::toDramPowerMemSpec() const
|
||||
{
|
||||
SC_REPORT_FATAL("MemSpec", "DRAMPower does not support this memory standard");
|
||||
return {};
|
||||
}
|
||||
#endif
|
||||
|
||||
} // namespace DRAMSys
|
||||
|
||||
@@ -34,23 +34,24 @@
|
||||
* Matthias Jung
|
||||
* Lukas Steiner
|
||||
* Derek Christ
|
||||
* Marco Mörz
|
||||
*/
|
||||
|
||||
#ifndef MEMSPEC_H
|
||||
#define MEMSPEC_H
|
||||
|
||||
#include "DRAMSys/common/utils.h"
|
||||
#include "DRAMSys/config/DRAMSysConfiguration.h"
|
||||
#include "DRAMSys/config/memspec/MemSpec.h"
|
||||
#include "DRAMSys/controller/Command.h"
|
||||
|
||||
#include <string>
|
||||
#include <systemc>
|
||||
#include <tlm>
|
||||
#include <vector>
|
||||
#include <memory>
|
||||
|
||||
#ifdef DRAMPOWER
|
||||
#include <LibDRAMPower.h>
|
||||
#include <DRAMPower/dram/dram_base.h>
|
||||
#include <DRAMPower/command/CmdType.h>
|
||||
#endif
|
||||
|
||||
namespace DRAMSys
|
||||
@@ -63,29 +64,32 @@ public:
|
||||
MemSpec& operator=(MemSpec&&) = delete;
|
||||
virtual ~MemSpec() = default;
|
||||
|
||||
const unsigned numberOfChannels;
|
||||
const unsigned ranksPerChannel;
|
||||
const unsigned banksPerRank;
|
||||
const unsigned groupsPerRank;
|
||||
const unsigned banksPerGroup;
|
||||
const unsigned banksPerChannel;
|
||||
const unsigned bankGroupsPerChannel;
|
||||
const unsigned devicesPerRank;
|
||||
const unsigned rowsPerBank;
|
||||
const unsigned columnsPerRow;
|
||||
const unsigned defaultBurstLength;
|
||||
const unsigned maxBurstLength;
|
||||
const unsigned dataRate;
|
||||
const unsigned bitWidth;
|
||||
const unsigned dataBusWidth;
|
||||
const unsigned defaultBytesPerBurst;
|
||||
const unsigned maxBytesPerBurst;
|
||||
static constexpr enum sc_core::sc_time_unit TCK_UNIT
|
||||
= sc_core::SC_SEC;
|
||||
|
||||
const uint64_t numberOfChannels;
|
||||
const uint64_t ranksPerChannel;
|
||||
const uint64_t banksPerRank;
|
||||
const uint64_t groupsPerRank;
|
||||
const uint64_t banksPerGroup;
|
||||
const uint64_t banksPerChannel;
|
||||
const uint64_t bankGroupsPerChannel;
|
||||
const uint64_t devicesPerRank;
|
||||
const uint64_t rowsPerBank;
|
||||
const uint64_t columnsPerRow;
|
||||
const uint64_t defaultBurstLength;
|
||||
const uint64_t maxBurstLength;
|
||||
const uint64_t dataRate;
|
||||
const uint64_t bitWidth;
|
||||
const uint64_t dataBusWidth;
|
||||
const uint64_t defaultBytesPerBurst;
|
||||
const uint64_t maxBytesPerBurst;
|
||||
|
||||
// Clock
|
||||
const sc_core::sc_time tCK;
|
||||
|
||||
const std::string memoryId;
|
||||
const Config::MemoryType memoryType;
|
||||
const std::string memoryType;
|
||||
|
||||
[[nodiscard]] virtual sc_core::sc_time getRefreshIntervalAB() const;
|
||||
[[nodiscard]] virtual sc_core::sc_time getRefreshIntervalPB() const;
|
||||
@@ -112,21 +116,74 @@ public:
|
||||
[[nodiscard]] uint64_t getSimMemSizeInBytes() const;
|
||||
|
||||
#ifdef DRAMPOWER
|
||||
[[nodiscard]] virtual DRAMPower::MemorySpecification toDramPowerMemSpec() const;
|
||||
/**
|
||||
* @brief Creates the DRAMPower object if the standard is supported by DRAMPower.
|
||||
* If the standard is not supported, a fatal error is reported and the simulation is aborted.
|
||||
* @return unique_ptr to the DRAMPower object.
|
||||
*/
|
||||
[[nodiscard]] virtual std::unique_ptr<DRAMPower::dram_base<DRAMPower::CmdType>> toDramPowerObject() const
|
||||
{
|
||||
SC_REPORT_FATAL("MemSpec", "DRAMPower does not support this memory standard");
|
||||
sc_core::sc_abort();
|
||||
// This line is never reached, but it is needed to avoid a compiler warning
|
||||
return nullptr;
|
||||
}
|
||||
#endif
|
||||
|
||||
protected:
|
||||
MemSpec(const Config::MemSpec& memSpec,
|
||||
unsigned numberOfChannels,
|
||||
unsigned ranksPerChannel,
|
||||
unsigned banksPerRank,
|
||||
unsigned groupsPerRank,
|
||||
unsigned banksPerGroup,
|
||||
unsigned banksPerChannel,
|
||||
unsigned bankGroupsPerChannel,
|
||||
unsigned devicesPerRank);
|
||||
[[nodiscard]] static bool allBytesEnabled(const tlm::tlm_generic_payload& trans)
|
||||
{
|
||||
if (trans.get_byte_enable_ptr() == nullptr)
|
||||
return true;
|
||||
|
||||
[[nodiscard]] static bool allBytesEnabled(const tlm::tlm_generic_payload& trans);
|
||||
for (std::size_t i = 0; i < trans.get_byte_enable_length(); i++)
|
||||
{
|
||||
if (trans.get_byte_enable_ptr()[i] != TLM_BYTE_ENABLED)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
template<typename MemSpecType>
|
||||
MemSpec(const MemSpecType& memSpec,
|
||||
uint64_t numberOfChannels,
|
||||
uint64_t ranksPerChannel,
|
||||
uint64_t banksPerRank,
|
||||
uint64_t groupsPerRank,
|
||||
uint64_t banksPerGroup,
|
||||
uint64_t banksPerChannel,
|
||||
uint64_t bankGroupsPerChannel,
|
||||
uint64_t devicesPerRank) :
|
||||
numberOfChannels(numberOfChannels),
|
||||
ranksPerChannel(ranksPerChannel),
|
||||
banksPerRank(banksPerRank),
|
||||
groupsPerRank(groupsPerRank),
|
||||
banksPerGroup(banksPerGroup),
|
||||
banksPerChannel(banksPerChannel),
|
||||
bankGroupsPerChannel(bankGroupsPerChannel),
|
||||
devicesPerRank(devicesPerRank),
|
||||
rowsPerBank(memSpec.memarchitecturespec.nbrOfRows),
|
||||
columnsPerRow(memSpec.memarchitecturespec.nbrOfColumns),
|
||||
defaultBurstLength(memSpec.memarchitecturespec.burstLength),
|
||||
maxBurstLength(memSpec.memarchitecturespec.maxBurstLength.has_value()
|
||||
? memSpec.memarchitecturespec.maxBurstLength.value()
|
||||
: defaultBurstLength),
|
||||
dataRate(memSpec.memarchitecturespec.dataRate),
|
||||
bitWidth(memSpec.memarchitecturespec.width),
|
||||
dataBusWidth(bitWidth * devicesPerRank),
|
||||
defaultBytesPerBurst((defaultBurstLength * dataBusWidth) / 8),
|
||||
maxBytesPerBurst((maxBurstLength * dataBusWidth) / 8),
|
||||
tCK(sc_core::sc_time(memSpec.memtimingspec.tCK, TCK_UNIT)),
|
||||
memoryId(memSpec.memoryId),
|
||||
memoryType(memSpec.id),
|
||||
burstDuration(tCK * (static_cast<double>(defaultBurstLength) / dataRate))
|
||||
|
||||
{
|
||||
commandLengthInCycles = std::vector<double>(Command::numberOfCommands(), 1);
|
||||
}
|
||||
|
||||
MemSpec(const MemSpec&) = default;
|
||||
MemSpec(MemSpec&&) = default;
|
||||
|
||||
@@ -32,6 +32,7 @@
|
||||
* Authors:
|
||||
* Lukas Steiner
|
||||
* Derek Christ
|
||||
* Marco Mörz
|
||||
*/
|
||||
|
||||
#include "MemSpecDDR3.h"
|
||||
@@ -46,68 +47,50 @@ using namespace tlm;
|
||||
namespace DRAMSys
|
||||
{
|
||||
|
||||
MemSpecDDR3::MemSpecDDR3(const Config::MemSpec& memSpec) :
|
||||
MemSpecDDR3::MemSpecDDR3(const DRAMUtils::MemSpec::MemSpecDDR3& memSpec) :
|
||||
MemSpec(memSpec,
|
||||
memSpec.memarchitecturespec.entries.at("nbrOfChannels"),
|
||||
memSpec.memarchitecturespec.entries.at("nbrOfRanks"),
|
||||
memSpec.memarchitecturespec.entries.at("nbrOfBanks"),
|
||||
memSpec.memarchitecturespec.nbrOfChannels,
|
||||
memSpec.memarchitecturespec.nbrOfRanks,
|
||||
memSpec.memarchitecturespec.nbrOfBanks,
|
||||
1,
|
||||
memSpec.memarchitecturespec.entries.at("nbrOfBanks"),
|
||||
memSpec.memarchitecturespec.entries.at("nbrOfBanks") *
|
||||
memSpec.memarchitecturespec.entries.at("nbrOfRanks"),
|
||||
memSpec.memarchitecturespec.entries.at("nbrOfRanks"),
|
||||
memSpec.memarchitecturespec.entries.at("nbrOfDevices")),
|
||||
tCKE(tCK * memSpec.memtimingspec.entries.at("CKE")),
|
||||
memSpec.memarchitecturespec.nbrOfBanks,
|
||||
memSpec.memarchitecturespec.nbrOfBanks *
|
||||
memSpec.memarchitecturespec.nbrOfRanks,
|
||||
memSpec.memarchitecturespec.nbrOfRanks,
|
||||
memSpec.memarchitecturespec.nbrOfDevices),
|
||||
tCKE(tCK * memSpec.memtimingspec.CKE),
|
||||
tPD(tCKE),
|
||||
tCKESR(tCK * memSpec.memtimingspec.entries.at("CKESR")),
|
||||
tRAS(tCK * memSpec.memtimingspec.entries.at("RAS")),
|
||||
tRC(tCK * memSpec.memtimingspec.entries.at("RC")),
|
||||
tRCD(tCK * memSpec.memtimingspec.entries.at("RCD")),
|
||||
tRL(tCK * memSpec.memtimingspec.entries.at("RL")),
|
||||
tRTP(tCK * memSpec.memtimingspec.entries.at("RTP")),
|
||||
tWL(tCK * memSpec.memtimingspec.entries.at("WL")),
|
||||
tWR(tCK * memSpec.memtimingspec.entries.at("WR")),
|
||||
tXP(tCK * memSpec.memtimingspec.entries.at("XP")),
|
||||
tXS(tCK * memSpec.memtimingspec.entries.at("XS")),
|
||||
tREFI(tCK * memSpec.memtimingspec.entries.at("REFI")),
|
||||
tRFC(tCK * memSpec.memtimingspec.entries.at("RFC")),
|
||||
tRP(tCK * memSpec.memtimingspec.entries.at("RP")),
|
||||
tDQSCK(tCK * memSpec.memtimingspec.entries.at("DQSCK")),
|
||||
tCCD(tCK * memSpec.memtimingspec.entries.at("CCD")),
|
||||
tFAW(tCK * memSpec.memtimingspec.entries.at("FAW")),
|
||||
tRRD(tCK * memSpec.memtimingspec.entries.at("RRD")),
|
||||
tWTR(tCK * memSpec.memtimingspec.entries.at("WTR")),
|
||||
tXPDLL(tCK * memSpec.memtimingspec.entries.at("XPDLL")),
|
||||
tXSDLL(tCK * memSpec.memtimingspec.entries.at("XSDLL")),
|
||||
tAL(tCK * memSpec.memtimingspec.entries.at("AL")),
|
||||
tACTPDEN(tCK * memSpec.memtimingspec.entries.at("ACTPDEN")),
|
||||
tPRPDEN(tCK * memSpec.memtimingspec.entries.at("PRPDEN")),
|
||||
tREFPDEN(tCK * memSpec.memtimingspec.entries.at("REFPDEN")),
|
||||
tRTRS(tCK * memSpec.memtimingspec.entries.at("RTRS")),
|
||||
iDD0(memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd0") : 0),
|
||||
iDD2N(memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd2n") : 0),
|
||||
iDD3N(memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd3n") : 0),
|
||||
iDD4R(memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd4r") : 0),
|
||||
iDD4W(memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd4w") : 0),
|
||||
iDD5(memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd5") : 0),
|
||||
iDD6(memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd6") : 0),
|
||||
vDD(memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("vdd") : 0),
|
||||
iDD2P0(memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd2p0")
|
||||
: 0),
|
||||
iDD2P1(memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd2p1")
|
||||
: 0),
|
||||
iDD3P0(memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd3p0")
|
||||
: 0),
|
||||
iDD3P1(memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd3p1") : 0)
|
||||
tCKESR(tCK * memSpec.memtimingspec.CKESR),
|
||||
tRAS(tCK * memSpec.memtimingspec.RAS),
|
||||
tRC(tCK * memSpec.memtimingspec.RC),
|
||||
tRCD(tCK * memSpec.memtimingspec.RCD),
|
||||
tRL(tCK * memSpec.memtimingspec.RL),
|
||||
tRTP(tCK * memSpec.memtimingspec.RTP),
|
||||
tWL(tCK * memSpec.memtimingspec.WL),
|
||||
tWR(tCK * memSpec.memtimingspec.WR),
|
||||
tXP(tCK * memSpec.memtimingspec.XP),
|
||||
tXS(tCK * memSpec.memtimingspec.XS),
|
||||
tREFI(tCK * memSpec.memtimingspec.REFI),
|
||||
tRFC(tCK * memSpec.memtimingspec.RFC),
|
||||
tRP(tCK * memSpec.memtimingspec.RP),
|
||||
tDQSCK(tCK * memSpec.memtimingspec.DQSCK),
|
||||
tCCD(tCK * memSpec.memtimingspec.CCD),
|
||||
tFAW(tCK * memSpec.memtimingspec.FAW),
|
||||
tRRD(tCK * memSpec.memtimingspec.RRD),
|
||||
tWTR(tCK * memSpec.memtimingspec.WTR),
|
||||
tXPDLL(tCK * memSpec.memtimingspec.XPDLL),
|
||||
tXSDLL(tCK * memSpec.memtimingspec.XSDLL),
|
||||
tAL(tCK * memSpec.memtimingspec.AL),
|
||||
tACTPDEN(tCK * memSpec.memtimingspec.ACTPDEN),
|
||||
tPRPDEN(tCK * memSpec.memtimingspec.PRPDEN),
|
||||
tREFPDEN(tCK * memSpec.memtimingspec.REFPDEN),
|
||||
tRTRS(tCK * memSpec.memtimingspec.RTRS)
|
||||
{
|
||||
uint64_t deviceSizeBits =
|
||||
static_cast<uint64_t>(banksPerRank) * rowsPerBank * columnsPerRow * bitWidth;
|
||||
uint64_t deviceSizeBytes = deviceSizeBits / 8;
|
||||
memorySizeBytes = deviceSizeBytes * devicesPerRank * ranksPerChannel * numberOfChannels;
|
||||
|
||||
if (!memSpec.mempowerspec.has_value())
|
||||
SC_REPORT_FATAL("MemSpec", "No power spec defined!");
|
||||
|
||||
std::cout << headline << std::endl;
|
||||
std::cout << "Memory Configuration:" << std::endl << std::endl;
|
||||
std::cout << " Memory type: "
|
||||
@@ -180,97 +163,4 @@ bool MemSpecDDR3::requiresMaskedWrite(const tlm::tlm_generic_payload& payload) c
|
||||
return !allBytesEnabled(payload);
|
||||
}
|
||||
|
||||
#ifdef DRAMPOWER
|
||||
DRAMPower::MemorySpecification MemSpecDDR3::toDramPowerMemSpec() const
|
||||
{
|
||||
DRAMPower::MemArchitectureSpec memArchSpec;
|
||||
memArchSpec.burstLength = defaultBurstLength;
|
||||
memArchSpec.dataRate = dataRate;
|
||||
memArchSpec.nbrOfRows = rowsPerBank;
|
||||
memArchSpec.nbrOfBanks = banksPerChannel;
|
||||
memArchSpec.nbrOfColumns = columnsPerRow;
|
||||
memArchSpec.nbrOfRanks = ranksPerChannel;
|
||||
memArchSpec.width = bitWidth;
|
||||
memArchSpec.nbrOfBankGroups = bankGroupsPerChannel;
|
||||
memArchSpec.twoVoltageDomains = false;
|
||||
memArchSpec.dll = true;
|
||||
|
||||
DRAMPower::MemTimingSpec memTimingSpec;
|
||||
// FIXME: memTimingSpec.FAWB = tFAW / tCK;
|
||||
// FIXME: memTimingSpec.RASB = tRAS / tCK;
|
||||
// FIXME: memTimingSpec.RCB = tRC / tCK;
|
||||
// FIXME: memTimingSpec.RPB = tRP / tCK;
|
||||
// FIXME: memTimingSpec.RRDB = tRRD / tCK;
|
||||
// FIXME: memTimingSpec.RRDB_L = tRRD / tCK;
|
||||
// FIXME: memTimingSpec.RRDB_S = tRRD / tCK;
|
||||
memTimingSpec.AL = tAL / tCK;
|
||||
memTimingSpec.CCD = tCCD / tCK;
|
||||
memTimingSpec.CCD_L = tCCD / tCK;
|
||||
memTimingSpec.CCD_S = tCCD / tCK;
|
||||
memTimingSpec.CKE = tCKE / tCK;
|
||||
memTimingSpec.CKESR = tCKESR / tCK;
|
||||
// See also MemTimingSpec.cc in DRAMPower
|
||||
memTimingSpec.clkMhz = 1 / (tCK.to_seconds() * 1'000'000);
|
||||
memTimingSpec.clkPeriod = tCK.to_seconds() * 1'000'000'000;
|
||||
memTimingSpec.DQSCK = tDQSCK / tCK;
|
||||
memTimingSpec.FAW = tFAW / tCK;
|
||||
memTimingSpec.RAS = tRAS / tCK;
|
||||
memTimingSpec.RC = tRC / tCK;
|
||||
memTimingSpec.RCD = tRCD / tCK;
|
||||
memTimingSpec.REFI = tREFI / tCK;
|
||||
memTimingSpec.RFC = tRFC / tCK;
|
||||
memTimingSpec.RL = tRL / tCK;
|
||||
memTimingSpec.RP = tRP / tCK;
|
||||
memTimingSpec.RRD = tRRD / tCK;
|
||||
memTimingSpec.RRD_L = tRRD / tCK;
|
||||
memTimingSpec.RRD_S = tRRD / tCK;
|
||||
memTimingSpec.RTP = tRTP / tCK;
|
||||
memTimingSpec.TAW = tFAW / tCK;
|
||||
memTimingSpec.WL = tWL / tCK;
|
||||
memTimingSpec.WR = tWR / tCK;
|
||||
memTimingSpec.WTR = tWTR / tCK;
|
||||
memTimingSpec.WTR_L = tWTR / tCK;
|
||||
memTimingSpec.WTR_S = tWTR / tCK;
|
||||
memTimingSpec.XP = tXP / tCK;
|
||||
memTimingSpec.XPDLL = tXPDLL / tCK;
|
||||
memTimingSpec.XS = tXS / tCK;
|
||||
memTimingSpec.XSDLL = tXSDLL / tCK;
|
||||
|
||||
DRAMPower::MemPowerSpec memPowerSpec;
|
||||
memPowerSpec.idd0 = iDD0;
|
||||
memPowerSpec.idd02 = 0;
|
||||
memPowerSpec.idd2p0 = iDD2P0;
|
||||
memPowerSpec.idd2p02 = 0;
|
||||
memPowerSpec.idd2p1 = iDD2P1;
|
||||
memPowerSpec.idd2p12 = 0;
|
||||
memPowerSpec.idd2n = iDD2N;
|
||||
memPowerSpec.idd2n2 = 0;
|
||||
memPowerSpec.idd3p0 = iDD3P0;
|
||||
memPowerSpec.idd3p02 = 0;
|
||||
memPowerSpec.idd3p1 = iDD3P1;
|
||||
memPowerSpec.idd3p12 = 0;
|
||||
memPowerSpec.idd3n = iDD3N;
|
||||
memPowerSpec.idd3n2 = 0;
|
||||
memPowerSpec.idd4r = iDD4R;
|
||||
memPowerSpec.idd4r2 = 0;
|
||||
memPowerSpec.idd4w = iDD4W;
|
||||
memPowerSpec.idd4w2 = 0;
|
||||
memPowerSpec.idd5 = iDD5;
|
||||
memPowerSpec.idd52 = 0;
|
||||
memPowerSpec.idd6 = iDD6;
|
||||
memPowerSpec.idd62 = 0;
|
||||
memPowerSpec.vdd = vDD;
|
||||
memPowerSpec.vdd2 = 0;
|
||||
|
||||
DRAMPower::MemorySpecification powerSpec;
|
||||
powerSpec.id = memoryId;
|
||||
powerSpec.memoryType = DRAMPower::MemoryType::DDR3;
|
||||
powerSpec.memTimingSpec = memTimingSpec;
|
||||
powerSpec.memPowerSpec = memPowerSpec;
|
||||
powerSpec.memArchSpec = memArchSpec;
|
||||
|
||||
return powerSpec;
|
||||
}
|
||||
#endif
|
||||
|
||||
} // namespace DRAMSys
|
||||
|
||||
@@ -32,14 +32,16 @@
|
||||
* Authors:
|
||||
* Lukas Steiner
|
||||
* Derek Christ
|
||||
* Marco Mörz
|
||||
*/
|
||||
|
||||
#ifndef MEMSPECDDR3_H
|
||||
#define MEMSPECDDR3_H
|
||||
|
||||
#include "DRAMSys/config/DRAMSysConfiguration.h"
|
||||
#include "DRAMSys/configuration/memspec/MemSpec.h"
|
||||
|
||||
#include <DRAMUtils/memspec/standards/MemSpecDDR3.h>
|
||||
|
||||
#include <systemc>
|
||||
|
||||
namespace DRAMSys
|
||||
@@ -48,7 +50,7 @@ namespace DRAMSys
|
||||
class MemSpecDDR3 final : public MemSpec
|
||||
{
|
||||
public:
|
||||
explicit MemSpecDDR3(const Config::MemSpec& memSpec);
|
||||
explicit MemSpecDDR3(const DRAMUtils::MemSpec::MemSpecDDR3& memSpec);
|
||||
|
||||
// Memspec Variables:
|
||||
const sc_core::sc_time tCKE;
|
||||
@@ -79,20 +81,6 @@ public:
|
||||
const sc_core::sc_time tREFPDEN;
|
||||
const sc_core::sc_time tRTRS;
|
||||
|
||||
// Currents and Voltages:
|
||||
const double iDD0;
|
||||
const double iDD2N;
|
||||
const double iDD3N;
|
||||
const double iDD4R;
|
||||
const double iDD4W;
|
||||
const double iDD5;
|
||||
const double iDD6;
|
||||
const double vDD;
|
||||
const double iDD2P0;
|
||||
const double iDD2P1;
|
||||
const double iDD3P0;
|
||||
const double iDD3P1;
|
||||
|
||||
[[nodiscard]] sc_core::sc_time getRefreshIntervalAB() const override;
|
||||
|
||||
[[nodiscard]] sc_core::sc_time
|
||||
@@ -103,9 +91,6 @@ public:
|
||||
|
||||
[[nodiscard]] bool requiresMaskedWrite(const tlm::tlm_generic_payload& payload) const override;
|
||||
|
||||
#ifdef DRAMPOWER
|
||||
[[nodiscard]] DRAMPower::MemorySpecification toDramPowerMemSpec() const override;
|
||||
#endif
|
||||
};
|
||||
|
||||
} // namespace DRAMSys
|
||||
|
||||
@@ -32,6 +32,7 @@
|
||||
* Authors:
|
||||
* Lukas Steiner
|
||||
* Derek Christ
|
||||
* Marco Mörz
|
||||
*/
|
||||
|
||||
#include "MemSpecDDR4.h"
|
||||
@@ -46,87 +47,75 @@ using namespace tlm;
|
||||
namespace DRAMSys
|
||||
{
|
||||
|
||||
MemSpecDDR4::MemSpecDDR4(const Config::MemSpec& memSpec) :
|
||||
using DRAMUtils::MemSpec::RefModeTypeDDR4;
|
||||
|
||||
MemSpecDDR4::MemSpecDDR4(const DRAMUtils::MemSpec::MemSpecDDR4& memSpec) :
|
||||
MemSpec(memSpec,
|
||||
memSpec.memarchitecturespec.entries.at("nbrOfChannels"),
|
||||
memSpec.memarchitecturespec.entries.at("nbrOfRanks"),
|
||||
memSpec.memarchitecturespec.entries.at("nbrOfBanks"),
|
||||
memSpec.memarchitecturespec.entries.at("nbrOfBankGroups"),
|
||||
memSpec.memarchitecturespec.entries.at("nbrOfBanks") /
|
||||
memSpec.memarchitecturespec.entries.at("nbrOfBankGroups"),
|
||||
memSpec.memarchitecturespec.entries.at("nbrOfBanks") *
|
||||
memSpec.memarchitecturespec.entries.at("nbrOfRanks"),
|
||||
memSpec.memarchitecturespec.entries.at("nbrOfBankGroups") *
|
||||
memSpec.memarchitecturespec.entries.at("nbrOfRanks"),
|
||||
memSpec.memarchitecturespec.entries.at("nbrOfDevices")),
|
||||
tCKE(tCK * memSpec.memtimingspec.entries.at("CKE")),
|
||||
memSpec.memarchitecturespec.nbrOfChannels,
|
||||
memSpec.memarchitecturespec.nbrOfRanks,
|
||||
memSpec.memarchitecturespec.nbrOfBanks,
|
||||
memSpec.memarchitecturespec.nbrOfBankGroups,
|
||||
memSpec.memarchitecturespec.nbrOfBanks /
|
||||
memSpec.memarchitecturespec.nbrOfBankGroups,
|
||||
memSpec.memarchitecturespec.nbrOfBanks *
|
||||
memSpec.memarchitecturespec.nbrOfRanks,
|
||||
memSpec.memarchitecturespec.nbrOfBankGroups *
|
||||
memSpec.memarchitecturespec.nbrOfRanks,
|
||||
memSpec.memarchitecturespec.nbrOfDevices),
|
||||
memSpec(memSpec),
|
||||
tCKE(tCK * memSpec.memtimingspec.CKE),
|
||||
tPD(tCKE),
|
||||
tCKESR(tCK * memSpec.memtimingspec.entries.at("CKESR")),
|
||||
tRAS(tCK * memSpec.memtimingspec.entries.at("RAS")),
|
||||
tRC(tCK * memSpec.memtimingspec.entries.at("RC")),
|
||||
tRCD(tCK * memSpec.memtimingspec.entries.at("RCD")),
|
||||
tRL(tCK * memSpec.memtimingspec.entries.at("RL")),
|
||||
tRPRE(tCK * memSpec.memtimingspec.entries.at("RPRE")),
|
||||
tRTP(tCK * memSpec.memtimingspec.entries.at("RTP")),
|
||||
tWL(tCK * memSpec.memtimingspec.entries.at("WL")),
|
||||
tWPRE(tCK * memSpec.memtimingspec.entries.at("WPRE")),
|
||||
tWR(tCK * memSpec.memtimingspec.entries.at("WR")),
|
||||
tXP(tCK * memSpec.memtimingspec.entries.at("XP")),
|
||||
tXS(tCK * memSpec.memtimingspec.entries.at("XS")),
|
||||
tREFI((memSpec.memtimingspec.entries.at("REFM") == 4)
|
||||
? (tCK * (static_cast<double>(memSpec.memtimingspec.entries.at("REFI")) / 4))
|
||||
: ((memSpec.memtimingspec.entries.at("REFM") == 2)
|
||||
? (tCK * (static_cast<double>(memSpec.memtimingspec.entries.at("REFI")) / 2))
|
||||
: (tCK * memSpec.memtimingspec.entries.at("REFI")))),
|
||||
tRFC((memSpec.memtimingspec.entries.at("REFM") == 4)
|
||||
? (tCK * memSpec.memtimingspec.entries.at("RFC4"))
|
||||
: ((memSpec.memtimingspec.entries.at("REFM") == 2)
|
||||
? (tCK * memSpec.memtimingspec.entries.at("RFC2"))
|
||||
: (tCK * memSpec.memtimingspec.entries.at("RFC")))),
|
||||
tRP(tCK * memSpec.memtimingspec.entries.at("RP")),
|
||||
tDQSCK(tCK * memSpec.memtimingspec.entries.at("DQSCK")),
|
||||
tCCD_S(tCK * memSpec.memtimingspec.entries.at("CCD_S")),
|
||||
tCCD_L(tCK * memSpec.memtimingspec.entries.at("CCD_L")),
|
||||
tFAW(tCK * memSpec.memtimingspec.entries.at("FAW")),
|
||||
tRRD_S(tCK * memSpec.memtimingspec.entries.at("RRD_S")),
|
||||
tRRD_L(tCK * memSpec.memtimingspec.entries.at("RRD_L")),
|
||||
tWTR_S(tCK * memSpec.memtimingspec.entries.at("WTR_S")),
|
||||
tWTR_L(tCK * memSpec.memtimingspec.entries.at("WTR_L")),
|
||||
tAL(tCK * memSpec.memtimingspec.entries.at("AL")),
|
||||
tXPDLL(tCK * memSpec.memtimingspec.entries.at("XPDLL")),
|
||||
tXSDLL(tCK * memSpec.memtimingspec.entries.at("XSDLL")),
|
||||
tACTPDEN(tCK * memSpec.memtimingspec.entries.at("ACTPDEN")),
|
||||
tPRPDEN(tCK * memSpec.memtimingspec.entries.at("PRPDEN")),
|
||||
tREFPDEN(tCK * memSpec.memtimingspec.entries.at("REFPDEN")),
|
||||
tRTRS(tCK * memSpec.memtimingspec.entries.at("RTRS")),
|
||||
iDD0(memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd0") : 0),
|
||||
iDD2N(memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd2n") : 0),
|
||||
iDD3N(memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd3n") : 0),
|
||||
iDD4R(memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd4r") : 0),
|
||||
iDD4W(memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd4w") : 0),
|
||||
iDD5(memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd5") : 0),
|
||||
iDD6(memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd6") : 0),
|
||||
vDD(memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("vdd") : 0),
|
||||
iDD02(memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd02") : 0),
|
||||
iDD2P0(memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd2p0")
|
||||
: 0),
|
||||
iDD2P1(memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd2p1")
|
||||
: 0),
|
||||
iDD3P0(memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd3p0")
|
||||
: 0),
|
||||
iDD3P1(memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd3p1")
|
||||
: 0),
|
||||
iDD62(memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd62") : 0),
|
||||
vDD2(memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("vdd2") : 0)
|
||||
tCKESR(tCK * memSpec.memtimingspec.CKESR),
|
||||
tRAS(tCK * memSpec.memtimingspec.RAS),
|
||||
tRC(tCK * memSpec.memtimingspec.RC),
|
||||
tRCD(tCK * memSpec.memtimingspec.RCD),
|
||||
tRL(tCK * memSpec.memtimingspec.RL),
|
||||
tRPRE(tCK * memSpec.memtimingspec.RPRE),
|
||||
tRTP(tCK * memSpec.memtimingspec.RTP),
|
||||
tWL(tCK * memSpec.memtimingspec.WL),
|
||||
tWPRE(tCK * memSpec.memtimingspec.WPRE),
|
||||
tWR(tCK * memSpec.memtimingspec.WR),
|
||||
tXP(tCK * memSpec.memtimingspec.XP),
|
||||
tXS(tCK * memSpec.memtimingspec.XS),
|
||||
tREFI((memSpec.memarchitecturespec.RefMode == RefModeTypeDDR4::REF_MODE_4) ?
|
||||
(tCK * (static_cast<double>(memSpec.memtimingspec.REFI) / 4))
|
||||
: ((memSpec.memarchitecturespec.RefMode == RefModeTypeDDR4::REF_MODE_2) ?
|
||||
(tCK * (static_cast<double>(memSpec.memtimingspec.REFI) / 2))
|
||||
// RefModeTypeDDR4::REF_MODE_1 || RefModeTypeDDR4::INVALID
|
||||
: (tCK * memSpec.memtimingspec.REFI))),
|
||||
tRFC((memSpec.memarchitecturespec.RefMode == RefModeTypeDDR4::REF_MODE_4) ?
|
||||
(tCK * memSpec.memtimingspec.RFC4)
|
||||
: ((memSpec.memarchitecturespec.RefMode == RefModeTypeDDR4::REF_MODE_2) ?
|
||||
(tCK * memSpec.memtimingspec.RFC2)
|
||||
// RefModeTypeDDR4::REF_MODE_1 || RefModeTypeDDR4::INVALID
|
||||
: (tCK * memSpec.memtimingspec.RFC1))),
|
||||
tRP(tCK * memSpec.memtimingspec.RP),
|
||||
tDQSCK(tCK * memSpec.memtimingspec.DQSCK),
|
||||
tCCD_S(tCK * memSpec.memtimingspec.CCD_S),
|
||||
tCCD_L(tCK * memSpec.memtimingspec.CCD_L),
|
||||
tFAW(tCK * memSpec.memtimingspec.FAW),
|
||||
tRRD_S(tCK * memSpec.memtimingspec.RRD_S),
|
||||
tRRD_L(tCK * memSpec.memtimingspec.RRD_L),
|
||||
tWTR_S(tCK * memSpec.memtimingspec.WTR_S),
|
||||
tWTR_L(tCK * memSpec.memtimingspec.WTR_L),
|
||||
tAL(tCK * memSpec.memtimingspec.AL),
|
||||
tXPDLL(tCK * memSpec.memtimingspec.XPDLL),
|
||||
tXSDLL(tCK * memSpec.memtimingspec.XSDLL),
|
||||
tACTPDEN(tCK * memSpec.memtimingspec.ACTPDEN),
|
||||
tPRPDEN(tCK * memSpec.memtimingspec.PRPDEN),
|
||||
tREFPDEN(tCK * memSpec.memtimingspec.REFPDEN),
|
||||
tRTRS(tCK * memSpec.memtimingspec.RTRS)
|
||||
{
|
||||
if (RefModeTypeDDR4::INVALID == memSpec.memarchitecturespec.RefMode)
|
||||
SC_REPORT_FATAL("MemSpecDDR4",
|
||||
"Invalid refresh mode! "
|
||||
"Set 1 for normal (fixed 1x), 2 for fixed 2x or 4 for fixed 4x refresh mode.");
|
||||
|
||||
uint64_t deviceSizeBits =
|
||||
static_cast<uint64_t>(banksPerRank) * rowsPerBank * columnsPerRow * bitWidth;
|
||||
uint64_t deviceSizeBytes = deviceSizeBits / 8;
|
||||
memorySizeBytes = deviceSizeBytes * devicesPerRank * ranksPerChannel * numberOfChannels;
|
||||
|
||||
if (!memSpec.mempowerspec.has_value())
|
||||
SC_REPORT_WARNING("MemSpec", "No power spec defined!");
|
||||
|
||||
std::cout << headline << std::endl;
|
||||
std::cout << "Memory Configuration:" << std::endl << std::endl;
|
||||
std::cout << " Memory type: "
|
||||
@@ -201,95 +190,9 @@ bool MemSpecDDR4::requiresMaskedWrite(const tlm::tlm_generic_payload& payload) c
|
||||
}
|
||||
|
||||
#ifdef DRAMPOWER
|
||||
DRAMPower::MemorySpecification MemSpecDDR4::toDramPowerMemSpec() const
|
||||
std::unique_ptr<DRAMPower::dram_base<DRAMPower::CmdType>> MemSpecDDR4::toDramPowerObject() const
|
||||
{
|
||||
DRAMPower::MemArchitectureSpec memArchSpec;
|
||||
memArchSpec.burstLength = defaultBurstLength;
|
||||
memArchSpec.dataRate = dataRate;
|
||||
memArchSpec.nbrOfRows = rowsPerBank;
|
||||
memArchSpec.nbrOfBanks = banksPerChannel;
|
||||
memArchSpec.nbrOfColumns = columnsPerRow;
|
||||
memArchSpec.nbrOfRanks = ranksPerChannel;
|
||||
memArchSpec.width = bitWidth;
|
||||
memArchSpec.nbrOfBankGroups = bankGroupsPerChannel;
|
||||
memArchSpec.twoVoltageDomains = true;
|
||||
memArchSpec.dll = true;
|
||||
|
||||
DRAMPower::MemTimingSpec memTimingSpec;
|
||||
// FIXME: memTimingSpec.FAWB = tFAW / tCK;
|
||||
// FIXME: memTimingSpec.RASB = tRAS / tCK;
|
||||
// FIXME: memTimingSpec.RCB = tRC / tCK;
|
||||
// FIXME: memTimingSpec.RPB = tRP / tCK;
|
||||
// FIXME: memTimingSpec.RRDB = tRRD_S / tCK;
|
||||
// FIXME: memTimingSpec.RRDB_L = tRRD_L / tCK;
|
||||
// FIXME: memTimingSpec.RRDB_S = tRRD_S / tCK;
|
||||
memTimingSpec.AL = tAL / tCK;
|
||||
memTimingSpec.CCD = tCCD_S / tCK;
|
||||
memTimingSpec.CCD_L = tCCD_L / tCK;
|
||||
memTimingSpec.CCD_S = tCCD_S / tCK;
|
||||
memTimingSpec.CKE = tCKE / tCK;
|
||||
memTimingSpec.CKESR = tCKESR / tCK;
|
||||
// See also MemTimingSpec.cc in DRAMPower
|
||||
memTimingSpec.clkMhz = 1 / (tCK.to_seconds() * 1'000'000);
|
||||
memTimingSpec.clkPeriod = tCK.to_seconds() * 1'000'000'000;
|
||||
memTimingSpec.DQSCK = tDQSCK / tCK;
|
||||
memTimingSpec.FAW = tFAW / tCK;
|
||||
memTimingSpec.RAS = tRAS / tCK;
|
||||
memTimingSpec.RC = tRC / tCK;
|
||||
memTimingSpec.RCD = tRCD / tCK;
|
||||
memTimingSpec.REFI = tREFI / tCK;
|
||||
memTimingSpec.RFC = tRFC / tCK;
|
||||
memTimingSpec.RL = tRL / tCK;
|
||||
memTimingSpec.RP = tRP / tCK;
|
||||
memTimingSpec.RRD = tRRD_S / tCK;
|
||||
memTimingSpec.RRD_L = tRRD_L / tCK;
|
||||
memTimingSpec.RRD_S = tRRD_S / tCK;
|
||||
memTimingSpec.RTP = tRTP / tCK;
|
||||
memTimingSpec.TAW = tFAW / tCK;
|
||||
memTimingSpec.WL = tWL / tCK;
|
||||
memTimingSpec.WR = tWR / tCK;
|
||||
memTimingSpec.WTR = tWTR_S / tCK;
|
||||
memTimingSpec.WTR_L = tWTR_L / tCK;
|
||||
memTimingSpec.WTR_S = tWTR_S / tCK;
|
||||
memTimingSpec.XP = tXP / tCK;
|
||||
memTimingSpec.XPDLL = tXPDLL / tCK;
|
||||
memTimingSpec.XS = tXS / tCK;
|
||||
memTimingSpec.XSDLL = tXSDLL / tCK;
|
||||
|
||||
DRAMPower::MemPowerSpec memPowerSpec;
|
||||
memPowerSpec.idd0 = iDD0;
|
||||
memPowerSpec.idd02 = iDD02;
|
||||
memPowerSpec.idd2p0 = iDD2P0;
|
||||
memPowerSpec.idd2p02 = 0;
|
||||
memPowerSpec.idd2p1 = iDD2P1;
|
||||
memPowerSpec.idd2p12 = 0;
|
||||
memPowerSpec.idd2n = iDD2N;
|
||||
memPowerSpec.idd2n2 = 0;
|
||||
memPowerSpec.idd3p0 = iDD3P0;
|
||||
memPowerSpec.idd3p02 = 0;
|
||||
memPowerSpec.idd3p1 = iDD3P1;
|
||||
memPowerSpec.idd3p12 = 0;
|
||||
memPowerSpec.idd3n = iDD3N;
|
||||
memPowerSpec.idd3n2 = 0;
|
||||
memPowerSpec.idd4r = iDD4R;
|
||||
memPowerSpec.idd4r2 = 0;
|
||||
memPowerSpec.idd4w = iDD4W;
|
||||
memPowerSpec.idd4w2 = 0;
|
||||
memPowerSpec.idd5 = iDD5;
|
||||
memPowerSpec.idd52 = 0;
|
||||
memPowerSpec.idd6 = iDD6;
|
||||
memPowerSpec.idd62 = iDD62;
|
||||
memPowerSpec.vdd = vDD;
|
||||
memPowerSpec.vdd2 = vDD2;
|
||||
|
||||
DRAMPower::MemorySpecification powerSpec;
|
||||
powerSpec.id = memoryId;
|
||||
powerSpec.memoryType = DRAMPower::MemoryType::DDR4;
|
||||
powerSpec.memTimingSpec = memTimingSpec;
|
||||
powerSpec.memPowerSpec = memPowerSpec;
|
||||
powerSpec.memArchSpec = memArchSpec;
|
||||
|
||||
return powerSpec;
|
||||
return std::make_unique<DRAMPower::DDR4>(std::move(DRAMPower::MemSpecDDR4(memSpec)));
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
@@ -32,6 +32,7 @@
|
||||
* Authors:
|
||||
* Lukas Steiner
|
||||
* Derek Christ
|
||||
* Marco Mörz
|
||||
*/
|
||||
|
||||
#ifndef MEMSPECDDR4_H
|
||||
@@ -39,6 +40,13 @@
|
||||
|
||||
#include "DRAMSys/configuration/memspec/MemSpec.h"
|
||||
|
||||
#include <DRAMUtils/memspec/standards/MemSpecDDR4.h>
|
||||
|
||||
#ifdef DRAMPOWER
|
||||
#include "DRAMPower/standards/ddr4/DDR4.h"
|
||||
#include "DRAMPower/memspec/MemSpecDDR4.h"
|
||||
#endif
|
||||
|
||||
#include <systemc>
|
||||
|
||||
namespace DRAMSys
|
||||
@@ -47,9 +55,10 @@ namespace DRAMSys
|
||||
class MemSpecDDR4 final : public MemSpec
|
||||
{
|
||||
public:
|
||||
explicit MemSpecDDR4(const Config::MemSpec& memSpec);
|
||||
explicit MemSpecDDR4(const DRAMUtils::MemSpec::MemSpecDDR4& memSpec);
|
||||
|
||||
// Memspec Variables:
|
||||
const DRAMUtils::MemSpec::MemSpecDDR4& memSpec;
|
||||
const sc_core::sc_time tCKE;
|
||||
const sc_core::sc_time tPD;
|
||||
const sc_core::sc_time tCKESR;
|
||||
@@ -83,23 +92,6 @@ public:
|
||||
const sc_core::sc_time tREFPDEN;
|
||||
const sc_core::sc_time tRTRS;
|
||||
|
||||
// Currents and Voltages:
|
||||
const double iDD0;
|
||||
const double iDD2N;
|
||||
const double iDD3N;
|
||||
const double iDD4R;
|
||||
const double iDD4W;
|
||||
const double iDD5;
|
||||
const double iDD6;
|
||||
const double vDD;
|
||||
const double iDD02;
|
||||
const double iDD2P0;
|
||||
const double iDD2P1;
|
||||
const double iDD3P0;
|
||||
const double iDD3P1;
|
||||
const double iDD62;
|
||||
const double vDD2;
|
||||
|
||||
[[nodiscard]] sc_core::sc_time getRefreshIntervalAB() const override;
|
||||
|
||||
[[nodiscard]] sc_core::sc_time
|
||||
@@ -111,7 +103,7 @@ public:
|
||||
[[nodiscard]] bool requiresMaskedWrite(const tlm::tlm_generic_payload& payload) const override;
|
||||
|
||||
#ifdef DRAMPOWER
|
||||
[[nodiscard]] DRAMPower::MemorySpecification toDramPowerMemSpec() const override;
|
||||
[[nodiscard]] std::unique_ptr<DRAMPower::dram_base<DRAMPower::CmdType>> toDramPowerObject() const override;
|
||||
#endif
|
||||
};
|
||||
|
||||
|
||||
@@ -32,6 +32,7 @@
|
||||
* Authors:
|
||||
* Lukas Steiner
|
||||
* Derek Christ
|
||||
* Marco Mörz
|
||||
*/
|
||||
|
||||
#include "MemSpecGDDR5.h"
|
||||
@@ -46,53 +47,53 @@ using namespace tlm;
|
||||
namespace DRAMSys
|
||||
{
|
||||
|
||||
MemSpecGDDR5::MemSpecGDDR5(const Config::MemSpec& memSpec) :
|
||||
MemSpecGDDR5::MemSpecGDDR5(const DRAMUtils::MemSpec::MemSpecGDDR5& memSpec) :
|
||||
MemSpec(memSpec,
|
||||
memSpec.memarchitecturespec.entries.at("nbrOfChannels"),
|
||||
memSpec.memarchitecturespec.entries.at("nbrOfRanks"),
|
||||
memSpec.memarchitecturespec.entries.at("nbrOfBanks"),
|
||||
memSpec.memarchitecturespec.entries.at("nbrOfBankGroups"),
|
||||
memSpec.memarchitecturespec.entries.at("nbrOfBanks") /
|
||||
memSpec.memarchitecturespec.entries.at("nbrOfBankGroups"),
|
||||
memSpec.memarchitecturespec.entries.at("nbrOfBanks") *
|
||||
memSpec.memarchitecturespec.entries.at("nbrOfRanks"),
|
||||
memSpec.memarchitecturespec.entries.at("nbrOfBankGroups") *
|
||||
memSpec.memarchitecturespec.entries.at("nbrOfRanks"),
|
||||
memSpec.memarchitecturespec.entries.at("nbrOfDevices")),
|
||||
tRP(tCK * memSpec.memtimingspec.entries.at("RP")),
|
||||
tRAS(tCK * memSpec.memtimingspec.entries.at("RAS")),
|
||||
tRC(tCK * memSpec.memtimingspec.entries.at("RC")),
|
||||
tRCDRD(tCK * memSpec.memtimingspec.entries.at("RCDRD")),
|
||||
tRCDWR(tCK * memSpec.memtimingspec.entries.at("RCDWR")),
|
||||
tRTP(tCK * memSpec.memtimingspec.entries.at("RTP")),
|
||||
tRRDS(tCK * memSpec.memtimingspec.entries.at("RRDS")),
|
||||
tRRDL(tCK * memSpec.memtimingspec.entries.at("RRDL")),
|
||||
tCCDS(tCK * memSpec.memtimingspec.entries.at("CCDS")),
|
||||
tCCDL(tCK * memSpec.memtimingspec.entries.at("CCDL")),
|
||||
tCL(tCK * memSpec.memtimingspec.entries.at("CL")),
|
||||
tWCK2CKPIN(tCK * memSpec.memtimingspec.entries.at("WCK2CKPIN")),
|
||||
tWCK2CK(tCK * memSpec.memtimingspec.entries.at("WCK2CK")),
|
||||
tWCK2DQO(tCK * memSpec.memtimingspec.entries.at("WCK2DQO")),
|
||||
tRTW(tCK * memSpec.memtimingspec.entries.at("RTW")),
|
||||
tWL(tCK * memSpec.memtimingspec.entries.at("WL")),
|
||||
tWCK2DQI(tCK * memSpec.memtimingspec.entries.at("WCK2DQI")),
|
||||
tWR(tCK * memSpec.memtimingspec.entries.at("WR")),
|
||||
tWTRS(tCK * memSpec.memtimingspec.entries.at("WTRS")),
|
||||
tWTRL(tCK * memSpec.memtimingspec.entries.at("WTRL")),
|
||||
tCKE(tCK * memSpec.memtimingspec.entries.at("CKE")),
|
||||
tPD(tCK * memSpec.memtimingspec.entries.at("PD")),
|
||||
tXPN(tCK * memSpec.memtimingspec.entries.at("XPN")),
|
||||
tREFI(tCK * memSpec.memtimingspec.entries.at("REFI")),
|
||||
tREFIPB(tCK * memSpec.memtimingspec.entries.at("REFIPB")),
|
||||
tRFC(tCK * memSpec.memtimingspec.entries.at("RFC")),
|
||||
tRFCPB(tCK * memSpec.memtimingspec.entries.at("RFCPB")),
|
||||
tRREFD(tCK * memSpec.memtimingspec.entries.at("RREFD")),
|
||||
tXS(tCK * memSpec.memtimingspec.entries.at("XS")),
|
||||
tFAW(tCK * memSpec.memtimingspec.entries.at("FAW")),
|
||||
t32AW(tCK * memSpec.memtimingspec.entries.at("32AW")),
|
||||
tPPD(tCK * memSpec.memtimingspec.entries.at("PPD")),
|
||||
tLK(tCK * memSpec.memtimingspec.entries.at("LK")),
|
||||
tRTRS(tCK * memSpec.memtimingspec.entries.at("RTRS"))
|
||||
memSpec.memarchitecturespec.nbrOfChannels,
|
||||
memSpec.memarchitecturespec.nbrOfRanks,
|
||||
memSpec.memarchitecturespec.nbrOfBanks,
|
||||
memSpec.memarchitecturespec.nbrOfBankGroups,
|
||||
memSpec.memarchitecturespec.nbrOfBanks /
|
||||
memSpec.memarchitecturespec.nbrOfBankGroups,
|
||||
memSpec.memarchitecturespec.nbrOfBanks *
|
||||
memSpec.memarchitecturespec.nbrOfRanks,
|
||||
memSpec.memarchitecturespec.nbrOfBankGroups *
|
||||
memSpec.memarchitecturespec.nbrOfRanks,
|
||||
memSpec.memarchitecturespec.nbrOfDevices),
|
||||
tRP(tCK * memSpec.memtimingspec.RP),
|
||||
tRAS(tCK * memSpec.memtimingspec.RAS),
|
||||
tRC(tCK * memSpec.memtimingspec.RC),
|
||||
tRCDRD(tCK * memSpec.memtimingspec.RCDRD),
|
||||
tRCDWR(tCK * memSpec.memtimingspec.RCDWR),
|
||||
tRTP(tCK * memSpec.memtimingspec.RTP),
|
||||
tRRDS(tCK * memSpec.memtimingspec.RRDS),
|
||||
tRRDL(tCK * memSpec.memtimingspec.RRDL),
|
||||
tCCDS(tCK * memSpec.memtimingspec.CCDS),
|
||||
tCCDL(tCK * memSpec.memtimingspec.CCDL),
|
||||
tCL(tCK * memSpec.memtimingspec.CL),
|
||||
tWCK2CKPIN(tCK * memSpec.memtimingspec.WCK2CKPIN),
|
||||
tWCK2CK(tCK * memSpec.memtimingspec.WCK2CK),
|
||||
tWCK2DQO(tCK * memSpec.memtimingspec.WCK2DQO),
|
||||
tRTW(tCK * memSpec.memtimingspec.RTW),
|
||||
tWL(tCK * memSpec.memtimingspec.WL),
|
||||
tWCK2DQI(tCK * memSpec.memtimingspec.WCK2DQI),
|
||||
tWR(tCK * memSpec.memtimingspec.WR),
|
||||
tWTRS(tCK * memSpec.memtimingspec.WTRS),
|
||||
tWTRL(tCK * memSpec.memtimingspec.WTRL),
|
||||
tCKE(tCK * memSpec.memtimingspec.CKE),
|
||||
tPD(tCK * memSpec.memtimingspec.PD),
|
||||
tXPN(tCK * memSpec.memtimingspec.XPN),
|
||||
tREFI(tCK * memSpec.memtimingspec.REFI),
|
||||
tREFIPB(tCK * memSpec.memtimingspec.REFIPB),
|
||||
tRFC(tCK * memSpec.memtimingspec.RFC),
|
||||
tRFCPB(tCK * memSpec.memtimingspec.RFCPB),
|
||||
tRREFD(tCK * memSpec.memtimingspec.RREFD),
|
||||
tXS(tCK * memSpec.memtimingspec.XS),
|
||||
tFAW(tCK * memSpec.memtimingspec.FAW),
|
||||
t32AW(tCK * memSpec.memtimingspec._32AW), // TODO breaking change
|
||||
tPPD(tCK * memSpec.memtimingspec.PPD),
|
||||
tLK(tCK * memSpec.memtimingspec.LK),
|
||||
tRTRS(tCK * memSpec.memtimingspec.RTRS)
|
||||
{
|
||||
uint64_t deviceSizeBits =
|
||||
static_cast<uint64_t>(banksPerRank) * rowsPerBank * columnsPerRow * bitWidth;
|
||||
|
||||
@@ -32,6 +32,7 @@
|
||||
* Authors:
|
||||
* Lukas Steiner
|
||||
* Derek Christ
|
||||
* Marco Mörz
|
||||
*/
|
||||
|
||||
#ifndef MEMSPECGDDR5_H
|
||||
@@ -39,6 +40,8 @@
|
||||
|
||||
#include "DRAMSys/configuration/memspec/MemSpec.h"
|
||||
|
||||
#include <DRAMUtils/memspec/standards/MemSpecGDDR5.h>
|
||||
|
||||
#include <systemc>
|
||||
|
||||
namespace DRAMSys
|
||||
@@ -47,7 +50,7 @@ namespace DRAMSys
|
||||
class MemSpecGDDR5 final : public MemSpec
|
||||
{
|
||||
public:
|
||||
explicit MemSpecGDDR5(const Config::MemSpec& memSpec);
|
||||
explicit MemSpecGDDR5(const DRAMUtils::MemSpec::MemSpecGDDR5& memSpec);
|
||||
|
||||
// Memspec Variables:
|
||||
const sc_core::sc_time tRP;
|
||||
|
||||
@@ -32,6 +32,7 @@
|
||||
* Authors:
|
||||
* Lukas Steiner
|
||||
* Derek Christ
|
||||
* Marco Mörz
|
||||
*/
|
||||
|
||||
#include "MemSpecGDDR5X.h"
|
||||
@@ -46,53 +47,53 @@ using namespace tlm;
|
||||
namespace DRAMSys
|
||||
{
|
||||
|
||||
MemSpecGDDR5X::MemSpecGDDR5X(const Config::MemSpec& memSpec) :
|
||||
MemSpecGDDR5X::MemSpecGDDR5X(const DRAMUtils::MemSpec::MemSpecGDDR5X& memSpec) :
|
||||
MemSpec(memSpec,
|
||||
memSpec.memarchitecturespec.entries.at("nbrOfChannels"),
|
||||
memSpec.memarchitecturespec.entries.at("nbrOfRanks"),
|
||||
memSpec.memarchitecturespec.entries.at("nbrOfBanks"),
|
||||
memSpec.memarchitecturespec.entries.at("nbrOfBankGroups"),
|
||||
memSpec.memarchitecturespec.entries.at("nbrOfBanks") /
|
||||
memSpec.memarchitecturespec.entries.at("nbrOfBankGroups"),
|
||||
memSpec.memarchitecturespec.entries.at("nbrOfBanks") *
|
||||
memSpec.memarchitecturespec.entries.at("nbrOfRanks"),
|
||||
memSpec.memarchitecturespec.entries.at("nbrOfBankGroups") *
|
||||
memSpec.memarchitecturespec.entries.at("nbrOfRanks"),
|
||||
memSpec.memarchitecturespec.entries.at("nbrOfDevices")),
|
||||
tRP(tCK * memSpec.memtimingspec.entries.at("RP")),
|
||||
tRAS(tCK * memSpec.memtimingspec.entries.at("RAS")),
|
||||
tRC(tCK * memSpec.memtimingspec.entries.at("RC")),
|
||||
tRCDRD(tCK * memSpec.memtimingspec.entries.at("RCDRD")),
|
||||
tRCDWR(tCK * memSpec.memtimingspec.entries.at("RCDWR")),
|
||||
tRTP(tCK * memSpec.memtimingspec.entries.at("RTP")),
|
||||
tRRDS(tCK * memSpec.memtimingspec.entries.at("RRDS")),
|
||||
tRRDL(tCK * memSpec.memtimingspec.entries.at("RRDL")),
|
||||
tCCDS(tCK * memSpec.memtimingspec.entries.at("CCDS")),
|
||||
tCCDL(tCK * memSpec.memtimingspec.entries.at("CCDL")),
|
||||
tRL(tCK * memSpec.memtimingspec.entries.at("CL")),
|
||||
tWCK2CKPIN(tCK * memSpec.memtimingspec.entries.at("WCK2CKPIN")),
|
||||
tWCK2CK(tCK * memSpec.memtimingspec.entries.at("WCK2CK")),
|
||||
tWCK2DQO(tCK * memSpec.memtimingspec.entries.at("WCK2DQO")),
|
||||
tRTW(tCK * memSpec.memtimingspec.entries.at("RTW")),
|
||||
tWL(tCK * memSpec.memtimingspec.entries.at("WL")),
|
||||
tWCK2DQI(tCK * memSpec.memtimingspec.entries.at("WCK2DQI")),
|
||||
tWR(tCK * memSpec.memtimingspec.entries.at("WR")),
|
||||
tWTRS(tCK * memSpec.memtimingspec.entries.at("WTRS")),
|
||||
tWTRL(tCK * memSpec.memtimingspec.entries.at("WTRL")),
|
||||
tCKE(tCK * memSpec.memtimingspec.entries.at("CKE")),
|
||||
tPD(tCK * memSpec.memtimingspec.entries.at("PD")),
|
||||
tXP(tCK * memSpec.memtimingspec.entries.at("XP")),
|
||||
tREFI(tCK * memSpec.memtimingspec.entries.at("REFI")),
|
||||
tREFIPB(tCK * memSpec.memtimingspec.entries.at("REFIPB")),
|
||||
tRFC(tCK * memSpec.memtimingspec.entries.at("RFC")),
|
||||
tRFCPB(tCK * memSpec.memtimingspec.entries.at("RFCPB")),
|
||||
tRREFD(tCK * memSpec.memtimingspec.entries.at("RREFD")),
|
||||
tXS(tCK * memSpec.memtimingspec.entries.at("XS")),
|
||||
tFAW(tCK * memSpec.memtimingspec.entries.at("FAW")),
|
||||
t32AW(tCK * memSpec.memtimingspec.entries.at("32AW")),
|
||||
tPPD(tCK * memSpec.memtimingspec.entries.at("PPD")),
|
||||
tLK(tCK * memSpec.memtimingspec.entries.at("LK")),
|
||||
tRTRS(tCK * memSpec.memtimingspec.entries.at("TRS"))
|
||||
memSpec.memarchitecturespec.nbrOfChannels,
|
||||
memSpec.memarchitecturespec.nbrOfRanks,
|
||||
memSpec.memarchitecturespec.nbrOfBanks,
|
||||
memSpec.memarchitecturespec.nbrOfBankGroups,
|
||||
memSpec.memarchitecturespec.nbrOfBanks /
|
||||
memSpec.memarchitecturespec.nbrOfBankGroups,
|
||||
memSpec.memarchitecturespec.nbrOfBanks *
|
||||
memSpec.memarchitecturespec.nbrOfRanks,
|
||||
memSpec.memarchitecturespec.nbrOfBankGroups *
|
||||
memSpec.memarchitecturespec.nbrOfRanks,
|
||||
memSpec.memarchitecturespec.nbrOfDevices),
|
||||
tRP(tCK * memSpec.memtimingspec.RP),
|
||||
tRAS(tCK * memSpec.memtimingspec.RAS),
|
||||
tRC(tCK * memSpec.memtimingspec.RC),
|
||||
tRCDRD(tCK * memSpec.memtimingspec.RCDRD),
|
||||
tRCDWR(tCK * memSpec.memtimingspec.RCDWR),
|
||||
tRTP(tCK * memSpec.memtimingspec.RTP),
|
||||
tRRDS(tCK * memSpec.memtimingspec.RRDS),
|
||||
tRRDL(tCK * memSpec.memtimingspec.RRDL),
|
||||
tCCDS(tCK * memSpec.memtimingspec.CCDS),
|
||||
tCCDL(tCK * memSpec.memtimingspec.CCDL),
|
||||
tRL(tCK * memSpec.memtimingspec.CL),
|
||||
tWCK2CKPIN(tCK * memSpec.memtimingspec.WCK2CKPIN),
|
||||
tWCK2CK(tCK * memSpec.memtimingspec.WCK2CK),
|
||||
tWCK2DQO(tCK * memSpec.memtimingspec.WCK2DQO),
|
||||
tRTW(tCK * memSpec.memtimingspec.RTW),
|
||||
tWL(tCK * memSpec.memtimingspec.WL),
|
||||
tWCK2DQI(tCK * memSpec.memtimingspec.WCK2DQI),
|
||||
tWR(tCK * memSpec.memtimingspec.WR),
|
||||
tWTRS(tCK * memSpec.memtimingspec.WTRS),
|
||||
tWTRL(tCK * memSpec.memtimingspec.WTRL),
|
||||
tCKE(tCK * memSpec.memtimingspec.CKE),
|
||||
tPD(tCK * memSpec.memtimingspec.PD),
|
||||
tXP(tCK * memSpec.memtimingspec.XP),
|
||||
tREFI(tCK * memSpec.memtimingspec.REFI),
|
||||
tREFIPB(tCK * memSpec.memtimingspec.REFIPB),
|
||||
tRFC(tCK * memSpec.memtimingspec.RFC),
|
||||
tRFCPB(tCK * memSpec.memtimingspec.RFCPB),
|
||||
tRREFD(tCK * memSpec.memtimingspec.RREFD),
|
||||
tXS(tCK * memSpec.memtimingspec.XS),
|
||||
tFAW(tCK * memSpec.memtimingspec.FAW),
|
||||
t32AW(tCK * memSpec.memtimingspec._32AW), // TODO breaking change
|
||||
tPPD(tCK * memSpec.memtimingspec.PPD),
|
||||
tLK(tCK * memSpec.memtimingspec.LK),
|
||||
tRTRS(tCK * memSpec.memtimingspec.TRS)
|
||||
{
|
||||
uint64_t deviceSizeBits =
|
||||
static_cast<uint64_t>(banksPerRank) * rowsPerBank * columnsPerRow * bitWidth;
|
||||
|
||||
@@ -32,6 +32,7 @@
|
||||
* Authors:
|
||||
* Lukas Steiner
|
||||
* Derek Christ
|
||||
* Marco Mörz
|
||||
*/
|
||||
|
||||
#ifndef MEMSPECGDDR5X_H
|
||||
@@ -39,6 +40,8 @@
|
||||
|
||||
#include "DRAMSys/configuration/memspec/MemSpec.h"
|
||||
|
||||
#include <DRAMUtils/memspec/standards/MemSpecGDDR5X.h>
|
||||
|
||||
#include <systemc>
|
||||
|
||||
namespace DRAMSys
|
||||
@@ -47,7 +50,7 @@ namespace DRAMSys
|
||||
class MemSpecGDDR5X final : public MemSpec
|
||||
{
|
||||
public:
|
||||
explicit MemSpecGDDR5X(const Config::MemSpec& memSpec);
|
||||
explicit MemSpecGDDR5X(const DRAMUtils::MemSpec::MemSpecGDDR5X& memSpec);
|
||||
|
||||
// Memspec Variables:
|
||||
const sc_core::sc_time tRP;
|
||||
|
||||
@@ -32,6 +32,7 @@
|
||||
* Authors:
|
||||
* Lukas Steiner
|
||||
* Derek Christ
|
||||
* Marco Mörz
|
||||
*/
|
||||
|
||||
#include "MemSpecGDDR6.h"
|
||||
@@ -46,56 +47,56 @@ using namespace tlm;
|
||||
namespace DRAMSys
|
||||
{
|
||||
|
||||
MemSpecGDDR6::MemSpecGDDR6(const Config::MemSpec& memSpec) :
|
||||
MemSpecGDDR6::MemSpecGDDR6(const DRAMUtils::MemSpec::MemSpecGDDR6& memSpec) :
|
||||
MemSpec(memSpec,
|
||||
memSpec.memarchitecturespec.entries.at("nbrOfChannels"),
|
||||
memSpec.memarchitecturespec.entries.at("nbrOfRanks"),
|
||||
memSpec.memarchitecturespec.entries.at("nbrOfBanks"),
|
||||
memSpec.memarchitecturespec.entries.at("nbrOfBankGroups"),
|
||||
memSpec.memarchitecturespec.entries.at("nbrOfBanks") /
|
||||
memSpec.memarchitecturespec.entries.at("nbrOfBankGroups"),
|
||||
memSpec.memarchitecturespec.entries.at("nbrOfBanks") *
|
||||
memSpec.memarchitecturespec.entries.at("nbrOfRanks"),
|
||||
memSpec.memarchitecturespec.entries.at("nbrOfBankGroups") *
|
||||
memSpec.memarchitecturespec.entries.at("nbrOfRanks"),
|
||||
memSpec.memarchitecturespec.entries.at("nbrOfDevices")),
|
||||
tRP(tCK * memSpec.memtimingspec.entries.at("RP")),
|
||||
tRAS(tCK * memSpec.memtimingspec.entries.at("RAS")),
|
||||
tRC(tCK * memSpec.memtimingspec.entries.at("RC")),
|
||||
tRCDRD(tCK * memSpec.memtimingspec.entries.at("RCDRD")),
|
||||
tRCDWR(tCK * memSpec.memtimingspec.entries.at("RCDWR")),
|
||||
tRTP(tCK * memSpec.memtimingspec.entries.at("RTP")),
|
||||
tRRDS(tCK * memSpec.memtimingspec.entries.at("RRDS")),
|
||||
tRRDL(tCK * memSpec.memtimingspec.entries.at("RRDL")),
|
||||
tCCDS(tCK * memSpec.memtimingspec.entries.at("CCDS")),
|
||||
tCCDL(tCK * memSpec.memtimingspec.entries.at("CCDL")),
|
||||
tRL(tCK * memSpec.memtimingspec.entries.at("RL")),
|
||||
tWCK2CKPIN(tCK * memSpec.memtimingspec.entries.at("WCK2CKPIN")),
|
||||
tWCK2CK(tCK * memSpec.memtimingspec.entries.at("WCK2CK")),
|
||||
tWCK2DQO(tCK * memSpec.memtimingspec.entries.at("WCK2DQO")),
|
||||
tRTW(tCK * memSpec.memtimingspec.entries.at("RTW")),
|
||||
tWL(tCK * memSpec.memtimingspec.entries.at("WL")),
|
||||
tWCK2DQI(tCK * memSpec.memtimingspec.entries.at("WCK2DQI")),
|
||||
tWR(tCK * memSpec.memtimingspec.entries.at("WR")),
|
||||
tWTRS(tCK * memSpec.memtimingspec.entries.at("WTRS")),
|
||||
tWTRL(tCK * memSpec.memtimingspec.entries.at("WTRL")),
|
||||
tPD(tCK * memSpec.memtimingspec.entries.at("PD")),
|
||||
tCKESR(tCK * memSpec.memtimingspec.entries.at("CKESR")),
|
||||
tXP(tCK * memSpec.memtimingspec.entries.at("XP")),
|
||||
tREFI(tCK * memSpec.memtimingspec.entries.at("REFI")),
|
||||
tREFIpb(tCK * memSpec.memtimingspec.entries.at("REFIpb")),
|
||||
tRFCab(tCK * memSpec.memtimingspec.entries.at("RFCab")),
|
||||
tRFCpb(tCK * memSpec.memtimingspec.entries.at("RFCpb")),
|
||||
tRREFD(tCK * memSpec.memtimingspec.entries.at("RREFD")),
|
||||
tXS(tCK * memSpec.memtimingspec.entries.at("XS")),
|
||||
tFAW(tCK * memSpec.memtimingspec.entries.at("FAW")),
|
||||
tPPD(tCK * memSpec.memtimingspec.entries.at("PPD")),
|
||||
tLK(tCK * memSpec.memtimingspec.entries.at("LK")),
|
||||
tACTPDE(tCK * memSpec.memtimingspec.entries.at("ACTPDE")),
|
||||
tPREPDE(tCK * memSpec.memtimingspec.entries.at("PREPDE")),
|
||||
tREFPDE(tCK * memSpec.memtimingspec.entries.at("REFPDE")),
|
||||
tRTRS(tCK * memSpec.memtimingspec.entries.at("RTRS")),
|
||||
per2BankOffset(memSpec.memarchitecturespec.entries.at("per2BankOffset"))
|
||||
memSpec.memarchitecturespec.nbrOfChannels,
|
||||
memSpec.memarchitecturespec.nbrOfRanks,
|
||||
memSpec.memarchitecturespec.nbrOfBanks,
|
||||
memSpec.memarchitecturespec.nbrOfBankGroups,
|
||||
memSpec.memarchitecturespec.nbrOfBanks /
|
||||
memSpec.memarchitecturespec.nbrOfBankGroups,
|
||||
memSpec.memarchitecturespec.nbrOfBanks *
|
||||
memSpec.memarchitecturespec.nbrOfRanks,
|
||||
memSpec.memarchitecturespec.nbrOfBankGroups *
|
||||
memSpec.memarchitecturespec.nbrOfRanks,
|
||||
memSpec.memarchitecturespec.nbrOfDevices),
|
||||
tRP(tCK * memSpec.memtimingspec.RP),
|
||||
tRAS(tCK * memSpec.memtimingspec.RAS),
|
||||
tRC(tCK * memSpec.memtimingspec.RC),
|
||||
tRCDRD(tCK * memSpec.memtimingspec.RCDRD),
|
||||
tRCDWR(tCK * memSpec.memtimingspec.RCDWR),
|
||||
tRTP(tCK * memSpec.memtimingspec.RTP),
|
||||
tRRDS(tCK * memSpec.memtimingspec.RRDS),
|
||||
tRRDL(tCK * memSpec.memtimingspec.RRDL),
|
||||
tCCDS(tCK * memSpec.memtimingspec.CCDS),
|
||||
tCCDL(tCK * memSpec.memtimingspec.CCDL),
|
||||
tRL(tCK * memSpec.memtimingspec.RL),
|
||||
tWCK2CKPIN(tCK * memSpec.memtimingspec.WCK2CKPIN),
|
||||
tWCK2CK(tCK * memSpec.memtimingspec.WCK2CK),
|
||||
tWCK2DQO(tCK * memSpec.memtimingspec.WCK2DQO),
|
||||
tRTW(tCK * memSpec.memtimingspec.RTW),
|
||||
tWL(tCK * memSpec.memtimingspec.WL),
|
||||
tWCK2DQI(tCK * memSpec.memtimingspec.WCK2DQI),
|
||||
tWR(tCK * memSpec.memtimingspec.WR),
|
||||
tWTRS(tCK * memSpec.memtimingspec.WTRS),
|
||||
tWTRL(tCK * memSpec.memtimingspec.WTRL),
|
||||
tPD(tCK * memSpec.memtimingspec.PD),
|
||||
tCKESR(tCK * memSpec.memtimingspec.CKESR),
|
||||
tXP(tCK * memSpec.memtimingspec.XP),
|
||||
tREFI(tCK * memSpec.memtimingspec.REFI),
|
||||
tREFIpb(tCK * memSpec.memtimingspec.REFIpb),
|
||||
tRFCab(tCK * memSpec.memtimingspec.RFCab),
|
||||
tRFCpb(tCK * memSpec.memtimingspec.RFCpb),
|
||||
tRREFD(tCK * memSpec.memtimingspec.RREFD),
|
||||
tXS(tCK * memSpec.memtimingspec.XS),
|
||||
tFAW(tCK * memSpec.memtimingspec.FAW),
|
||||
tPPD(tCK * memSpec.memtimingspec.PPD),
|
||||
tLK(tCK * memSpec.memtimingspec.LK),
|
||||
tACTPDE(tCK * memSpec.memtimingspec.ACTPDE),
|
||||
tPREPDE(tCK * memSpec.memtimingspec.PREPDE),
|
||||
tREFPDE(tCK * memSpec.memtimingspec.REFPDE),
|
||||
tRTRS(tCK * memSpec.memtimingspec.RTRS),
|
||||
per2BankOffset(memSpec.memarchitecturespec.per2BankOffset)
|
||||
{
|
||||
uint64_t deviceSizeBits =
|
||||
static_cast<uint64_t>(banksPerRank) * rowsPerBank * columnsPerRow * bitWidth;
|
||||
|
||||
@@ -32,6 +32,7 @@
|
||||
* Authors:
|
||||
* Lukas Steiner
|
||||
* Derek Christ
|
||||
* Marco Mörz
|
||||
*/
|
||||
|
||||
#ifndef MEMSPECGDDR6_H
|
||||
@@ -39,14 +40,17 @@
|
||||
|
||||
#include "DRAMSys/configuration/memspec/MemSpec.h"
|
||||
|
||||
#include <DRAMUtils/memspec/standards/MemSpecGDDR6.h>
|
||||
|
||||
#include <systemc>
|
||||
|
||||
namespace DRAMSys
|
||||
{
|
||||
|
||||
struct MemSpecGDDR6 final : public MemSpec
|
||||
{
|
||||
public:
|
||||
explicit MemSpecGDDR6(const Config::MemSpec& memSpec);
|
||||
explicit MemSpecGDDR6(const DRAMUtils::MemSpec::MemSpecGDDR6& memSpec);
|
||||
|
||||
// Memspec Variables:
|
||||
const sc_core::sc_time tRP;
|
||||
|
||||
@@ -32,6 +32,7 @@
|
||||
* Authors:
|
||||
* Lukas Steiner
|
||||
* Derek Christ
|
||||
* Marco Mörz
|
||||
*/
|
||||
|
||||
#include "MemSpecHBM2.h"
|
||||
@@ -46,50 +47,50 @@ using namespace tlm;
|
||||
namespace DRAMSys
|
||||
{
|
||||
|
||||
MemSpecHBM2::MemSpecHBM2(const Config::MemSpec& memSpec) :
|
||||
MemSpecHBM2::MemSpecHBM2(const DRAMUtils::MemSpec::MemSpecHBM2& memSpec) :
|
||||
MemSpec(memSpec,
|
||||
memSpec.memarchitecturespec.entries.at("nbrOfChannels"),
|
||||
memSpec.memarchitecturespec.entries.at("nbrOfPseudoChannels"),
|
||||
memSpec.memarchitecturespec.entries.at("nbrOfBanks"),
|
||||
memSpec.memarchitecturespec.entries.at("nbrOfBankGroups"),
|
||||
memSpec.memarchitecturespec.entries.at("nbrOfBanks") /
|
||||
memSpec.memarchitecturespec.entries.at("nbrOfBankGroups"),
|
||||
memSpec.memarchitecturespec.entries.at("nbrOfBanks") *
|
||||
memSpec.memarchitecturespec.entries.at("nbrOfPseudoChannels"),
|
||||
memSpec.memarchitecturespec.entries.at("nbrOfBankGroups") *
|
||||
memSpec.memarchitecturespec.entries.at("nbrOfPseudoChannels"),
|
||||
memSpec.memarchitecturespec.entries.at("nbrOfDevices")),
|
||||
stacksPerChannel(memSpec.memarchitecturespec.entries.at("nbrOfStacks")),
|
||||
tDQSCK(tCK * memSpec.memtimingspec.entries.at("DQSCK")),
|
||||
tRC(tCK * memSpec.memtimingspec.entries.at("RC")),
|
||||
tRAS(tCK * memSpec.memtimingspec.entries.at("RAS")),
|
||||
tRCDRD(tCK * memSpec.memtimingspec.entries.at("RCDRD")),
|
||||
tRCDWR(tCK * memSpec.memtimingspec.entries.at("RCDWR")),
|
||||
tRRDL(tCK * memSpec.memtimingspec.entries.at("RRDL")),
|
||||
tRRDS(tCK * memSpec.memtimingspec.entries.at("RRDS")),
|
||||
tFAW(tCK * memSpec.memtimingspec.entries.at("FAW")),
|
||||
tRTP(tCK * memSpec.memtimingspec.entries.at("RTP")),
|
||||
tRP(tCK * memSpec.memtimingspec.entries.at("RP")),
|
||||
tRL(tCK * memSpec.memtimingspec.entries.at("RL")),
|
||||
tWL(tCK * memSpec.memtimingspec.entries.at("WL")),
|
||||
tPL(tCK * memSpec.memtimingspec.entries.at("PL")),
|
||||
tWR(tCK * memSpec.memtimingspec.entries.at("WR")),
|
||||
tCCDL(tCK * memSpec.memtimingspec.entries.at("CCDL")),
|
||||
tCCDS(tCK * memSpec.memtimingspec.entries.at("CCDS")),
|
||||
tCCDR(tCK * memSpec.memtimingspec.entries.at("CCDR")),
|
||||
tWTRL(tCK * memSpec.memtimingspec.entries.at("WTRL")),
|
||||
tWTRS(tCK * memSpec.memtimingspec.entries.at("WTRS")),
|
||||
tRTW(tCK * memSpec.memtimingspec.entries.at("RTW")),
|
||||
tXP(tCK * memSpec.memtimingspec.entries.at("XP")),
|
||||
tCKE(tCK * memSpec.memtimingspec.entries.at("CKE")),
|
||||
memSpec.memarchitecturespec.nbrOfChannels,
|
||||
memSpec.memarchitecturespec.nbrOfPseudoChannels,
|
||||
memSpec.memarchitecturespec.nbrOfBanks,
|
||||
memSpec.memarchitecturespec.nbrOfBankGroups,
|
||||
memSpec.memarchitecturespec.nbrOfBanks /
|
||||
memSpec.memarchitecturespec.nbrOfBankGroups,
|
||||
memSpec.memarchitecturespec.nbrOfBanks *
|
||||
memSpec.memarchitecturespec.nbrOfPseudoChannels,
|
||||
memSpec.memarchitecturespec.nbrOfBankGroups *
|
||||
memSpec.memarchitecturespec.nbrOfPseudoChannels,
|
||||
memSpec.memarchitecturespec.nbrOfDevices),
|
||||
stacksPerChannel(memSpec.memarchitecturespec.nbrOfStacks),
|
||||
tDQSCK(tCK * memSpec.memtimingspec.DQSCK),
|
||||
tRC(tCK * memSpec.memtimingspec.RC),
|
||||
tRAS(tCK * memSpec.memtimingspec.RAS),
|
||||
tRCDRD(tCK * memSpec.memtimingspec.RCDRD),
|
||||
tRCDWR(tCK * memSpec.memtimingspec.RCDWR),
|
||||
tRRDL(tCK * memSpec.memtimingspec.RRDL),
|
||||
tRRDS(tCK * memSpec.memtimingspec.RRDS),
|
||||
tFAW(tCK * memSpec.memtimingspec.FAW),
|
||||
tRTP(tCK * memSpec.memtimingspec.RTP),
|
||||
tRP(tCK * memSpec.memtimingspec.RP),
|
||||
tRL(tCK * memSpec.memtimingspec.RL),
|
||||
tWL(tCK * memSpec.memtimingspec.WL),
|
||||
tPL(tCK * memSpec.memtimingspec.PL),
|
||||
tWR(tCK * memSpec.memtimingspec.WR),
|
||||
tCCDL(tCK * memSpec.memtimingspec.CCDL),
|
||||
tCCDS(tCK * memSpec.memtimingspec.CCDS),
|
||||
tCCDR(tCK * memSpec.memtimingspec.CCDR),
|
||||
tWTRL(tCK * memSpec.memtimingspec.WTRL),
|
||||
tWTRS(tCK * memSpec.memtimingspec.WTRS),
|
||||
tRTW(tCK * memSpec.memtimingspec.RTW),
|
||||
tXP(tCK * memSpec.memtimingspec.XP),
|
||||
tCKE(tCK * memSpec.memtimingspec.CKE),
|
||||
tPD(tCKE),
|
||||
tCKESR(tCKE + tCK),
|
||||
tXS(tCK * memSpec.memtimingspec.entries.at("XS")),
|
||||
tRFC(tCK * memSpec.memtimingspec.entries.at("RFC")),
|
||||
tRFCSB(tCK * memSpec.memtimingspec.entries.at("RFCSB")),
|
||||
tRREFD(tCK * memSpec.memtimingspec.entries.at("RREFD")),
|
||||
tREFI(tCK * memSpec.memtimingspec.entries.at("REFI")),
|
||||
tREFISB(tCK * memSpec.memtimingspec.entries.at("REFISB"))
|
||||
tXS(tCK * memSpec.memtimingspec.XS),
|
||||
tRFC(tCK * memSpec.memtimingspec.RFC),
|
||||
tRFCSB(tCK * memSpec.memtimingspec.RFCSB),
|
||||
tRREFD(tCK * memSpec.memtimingspec.RREFD),
|
||||
tREFI(tCK * memSpec.memtimingspec.REFI),
|
||||
tREFISB(tCK * memSpec.memtimingspec.REFISB)
|
||||
{
|
||||
commandLengthInCycles[Command::ACT] = 2;
|
||||
|
||||
|
||||
@@ -32,6 +32,7 @@
|
||||
* Authors:
|
||||
* Lukas Steiner
|
||||
* Derek Christ
|
||||
* Marco Mörz
|
||||
*/
|
||||
|
||||
#ifndef MEMSPECHBM2_H
|
||||
@@ -39,6 +40,8 @@
|
||||
|
||||
#include "DRAMSys/configuration/memspec/MemSpec.h"
|
||||
|
||||
#include <DRAMUtils/memspec/standards/MemSpecHBM2.h>
|
||||
|
||||
#include <systemc>
|
||||
|
||||
namespace DRAMSys
|
||||
@@ -47,7 +50,7 @@ namespace DRAMSys
|
||||
class MemSpecHBM2 final : public MemSpec
|
||||
{
|
||||
public:
|
||||
explicit MemSpecHBM2(const Config::MemSpec& memSpec);
|
||||
explicit MemSpecHBM2(const DRAMUtils::MemSpec::MemSpecHBM2& memSpec);
|
||||
|
||||
// Memspec Variables:
|
||||
const unsigned stacksPerChannel;
|
||||
|
||||
@@ -32,6 +32,7 @@
|
||||
* Authors:
|
||||
* Lukas Steiner
|
||||
* Derek Christ
|
||||
* Marco Mörz
|
||||
*/
|
||||
|
||||
#include "MemSpecLPDDR4.h"
|
||||
@@ -46,49 +47,50 @@ using namespace tlm;
|
||||
namespace DRAMSys
|
||||
{
|
||||
|
||||
MemSpecLPDDR4::MemSpecLPDDR4(const Config::MemSpec& memSpec) :
|
||||
MemSpecLPDDR4::MemSpecLPDDR4(const DRAMUtils::MemSpec::MemSpecLPDDR4& memSpec) :
|
||||
MemSpec(memSpec,
|
||||
memSpec.memarchitecturespec.entries.at("nbrOfChannels"),
|
||||
memSpec.memarchitecturespec.entries.at("nbrOfRanks"),
|
||||
memSpec.memarchitecturespec.entries.at("nbrOfBanks"),
|
||||
memSpec.memarchitecturespec.nbrOfChannels,
|
||||
memSpec.memarchitecturespec.nbrOfRanks,
|
||||
memSpec.memarchitecturespec.nbrOfBanks,
|
||||
1,
|
||||
memSpec.memarchitecturespec.entries.at("nbrOfBanks"),
|
||||
memSpec.memarchitecturespec.entries.at("nbrOfBanks") *
|
||||
memSpec.memarchitecturespec.entries.at("nbrOfRanks"),
|
||||
memSpec.memarchitecturespec.entries.at("nbrOfRanks"),
|
||||
memSpec.memarchitecturespec.entries.at("nbrOfDevices")),
|
||||
tREFI(tCK * memSpec.memtimingspec.entries.at("REFI")),
|
||||
tREFIpb(tCK * memSpec.memtimingspec.entries.at("REFIPB")),
|
||||
tRFCab(tCK * memSpec.memtimingspec.entries.at("RFCAB")),
|
||||
tRFCpb(tCK * memSpec.memtimingspec.entries.at("RFCPB")),
|
||||
tRAS(tCK * memSpec.memtimingspec.entries.at("RAS")),
|
||||
tRPab(tCK * memSpec.memtimingspec.entries.at("RPAB")),
|
||||
tRPpb(tCK * memSpec.memtimingspec.entries.at("RPPB")),
|
||||
tRCpb(tCK * memSpec.memtimingspec.entries.at("RCPB")),
|
||||
tRCab(tCK * memSpec.memtimingspec.entries.at("RCAB")),
|
||||
tPPD(tCK * memSpec.memtimingspec.entries.at("PPD")),
|
||||
tRCD(tCK * memSpec.memtimingspec.entries.at("RCD")),
|
||||
tFAW(tCK * memSpec.memtimingspec.entries.at("FAW")),
|
||||
tRRD(tCK * memSpec.memtimingspec.entries.at("RRD")),
|
||||
tCCD(tCK * memSpec.memtimingspec.entries.at("CCD")),
|
||||
tCCDMW(tCK * memSpec.memtimingspec.entries.at("CCDMW")),
|
||||
tRL(tCK * memSpec.memtimingspec.entries.at("RL")),
|
||||
tRPST(tCK * memSpec.memtimingspec.entries.at("RPST")),
|
||||
tDQSCK(tCK * memSpec.memtimingspec.entries.at("DQSCK")),
|
||||
tRTP(tCK * memSpec.memtimingspec.entries.at("RTP")),
|
||||
tWL(tCK * memSpec.memtimingspec.entries.at("WL")),
|
||||
tDQSS(tCK * memSpec.memtimingspec.entries.at("DQSS")),
|
||||
tDQS2DQ(tCK * memSpec.memtimingspec.entries.at("DQS2DQ")),
|
||||
tWR(tCK * memSpec.memtimingspec.entries.at("WR")),
|
||||
tWPRE(tCK * memSpec.memtimingspec.entries.at("WPRE")),
|
||||
tWTR(tCK * memSpec.memtimingspec.entries.at("WTR")),
|
||||
tXP(tCK * memSpec.memtimingspec.entries.at("XP")),
|
||||
tSR(tCK * memSpec.memtimingspec.entries.at("SR")),
|
||||
tXSR(tCK * memSpec.memtimingspec.entries.at("XSR")),
|
||||
tESCKE(tCK * memSpec.memtimingspec.entries.at("ESCKE")),
|
||||
tCKE(tCK * memSpec.memtimingspec.entries.at("CKE")),
|
||||
tCMDCKE(tCK * memSpec.memtimingspec.entries.at("CMDCKE")),
|
||||
tRTRS(tCK * memSpec.memtimingspec.entries.at("RTRS"))
|
||||
memSpec.memarchitecturespec.nbrOfBanks,
|
||||
memSpec.memarchitecturespec.nbrOfBanks *
|
||||
memSpec.memarchitecturespec.nbrOfRanks,
|
||||
memSpec.memarchitecturespec.nbrOfRanks,
|
||||
memSpec.memarchitecturespec.nbrOfDevices),
|
||||
memSpec(memSpec),
|
||||
tREFI(tCK * memSpec.memtimingspec.REFI),
|
||||
tREFIpb(tCK * memSpec.memtimingspec.REFIpb),
|
||||
tRFCab(tCK * memSpec.memtimingspec.RFCab),
|
||||
tRFCpb(tCK * memSpec.memtimingspec.RFCpb),
|
||||
tRAS(tCK * memSpec.memtimingspec.RAS),
|
||||
tRPab(tCK * memSpec.memtimingspec.RPab),
|
||||
tRPpb(tCK * memSpec.memtimingspec.RPpb),
|
||||
tRCpb(tCK * memSpec.memtimingspec.RCpb),
|
||||
tRCab(tCK * memSpec.memtimingspec.RCab),
|
||||
tPPD(tCK * memSpec.memtimingspec.PPD),
|
||||
tRCD(tCK * memSpec.memtimingspec.RCD),
|
||||
tFAW(tCK * memSpec.memtimingspec.FAW),
|
||||
tRRD(tCK * memSpec.memtimingspec.RRD),
|
||||
tCCD(tCK * memSpec.memtimingspec.CCD),
|
||||
tCCDMW(tCK * memSpec.memtimingspec.CCDMW),
|
||||
tRL(tCK * memSpec.memtimingspec.RL),
|
||||
tRPST(tCK * memSpec.memtimingspec.RPST),
|
||||
tDQSCK(tCK * memSpec.memtimingspec.DQSCK),
|
||||
tRTP(tCK * memSpec.memtimingspec.RTP),
|
||||
tWL(tCK * memSpec.memtimingspec.WL),
|
||||
tDQSS(tCK * memSpec.memtimingspec.DQSS),
|
||||
tDQS2DQ(tCK * memSpec.memtimingspec.DQS2DQ),
|
||||
tWR(tCK * memSpec.memtimingspec.WR),
|
||||
tWPRE(tCK * memSpec.memtimingspec.WPRE),
|
||||
tWTR(tCK * memSpec.memtimingspec.WTR),
|
||||
tXP(tCK * memSpec.memtimingspec.XP),
|
||||
tSR(tCK * memSpec.memtimingspec.SR),
|
||||
tXSR(tCK * memSpec.memtimingspec.XSR),
|
||||
tESCKE(tCK * memSpec.memtimingspec.ESCKE),
|
||||
tCKE(tCK * memSpec.memtimingspec.CKE),
|
||||
tCMDCKE(tCK * memSpec.memtimingspec.CMDCKE),
|
||||
tRTRS(tCK * memSpec.memtimingspec.RTRS)
|
||||
{
|
||||
commandLengthInCycles[Command::ACT] = 4;
|
||||
commandLengthInCycles[Command::PREPB] = 2;
|
||||
@@ -186,6 +188,13 @@ MemSpecLPDDR4::getIntervalOnDataStrobe(Command command,
|
||||
throw;
|
||||
}
|
||||
|
||||
#ifdef DRAMPOWER
|
||||
std::unique_ptr<DRAMPower::dram_base<DRAMPower::CmdType>> MemSpecLPDDR4::toDramPowerObject() const
|
||||
{
|
||||
return std::make_unique<DRAMPower::LPDDR4>(std::move(DRAMPower::MemSpecLPDDR4(memSpec)));
|
||||
}
|
||||
#endif
|
||||
|
||||
bool MemSpecLPDDR4::requiresMaskedWrite(const tlm::tlm_generic_payload& payload) const
|
||||
{
|
||||
return !allBytesEnabled(payload);
|
||||
|
||||
@@ -32,6 +32,7 @@
|
||||
* Authors:
|
||||
* Lukas Steiner
|
||||
* Derek Christ
|
||||
* Marco Mörz
|
||||
*/
|
||||
|
||||
#ifndef MEMSPECLPDDR4_H
|
||||
@@ -39,6 +40,13 @@
|
||||
|
||||
#include "DRAMSys/configuration/memspec/MemSpec.h"
|
||||
|
||||
#include <DRAMUtils/memspec/standards/MemSpecLPDDR4.h>
|
||||
|
||||
#ifdef DRAMPOWER
|
||||
#include "DRAMPower/standards/lpddr4/LPDDR4.h"
|
||||
#include "DRAMPower/memspec/MemSpecLPDDR4.h"
|
||||
#endif
|
||||
|
||||
#include <systemc>
|
||||
|
||||
namespace DRAMSys
|
||||
@@ -47,9 +55,10 @@ namespace DRAMSys
|
||||
class MemSpecLPDDR4 final : public MemSpec
|
||||
{
|
||||
public:
|
||||
explicit MemSpecLPDDR4(const Config::MemSpec& memSpec);
|
||||
explicit MemSpecLPDDR4(const DRAMUtils::MemSpec::MemSpecLPDDR4& memSpec);
|
||||
|
||||
// Memspec Variables:
|
||||
const DRAMUtils::MemSpec::MemSpecLPDDR4& memSpec;
|
||||
const sc_core::sc_time tREFI;
|
||||
const sc_core::sc_time tREFIpb;
|
||||
const sc_core::sc_time tRFCab;
|
||||
@@ -96,6 +105,11 @@ public:
|
||||
const tlm::tlm_generic_payload& payload) const override;
|
||||
|
||||
[[nodiscard]] bool requiresMaskedWrite(const tlm::tlm_generic_payload& payload) const override;
|
||||
|
||||
#ifdef DRAMPOWER
|
||||
[[nodiscard]] std::unique_ptr<DRAMPower::dram_base<DRAMPower::CmdType>> toDramPowerObject() const override;
|
||||
#endif
|
||||
|
||||
};
|
||||
|
||||
} // namespace DRAMSys
|
||||
|
||||
@@ -32,6 +32,7 @@
|
||||
* Authors:
|
||||
* Lukas Steiner
|
||||
* Derek Christ
|
||||
* Marco Mörz
|
||||
*/
|
||||
|
||||
#include "MemSpecSTTMRAM.h"
|
||||
@@ -46,41 +47,41 @@ using namespace tlm;
|
||||
namespace DRAMSys
|
||||
{
|
||||
|
||||
MemSpecSTTMRAM::MemSpecSTTMRAM(const Config::MemSpec& memSpec) :
|
||||
MemSpecSTTMRAM::MemSpecSTTMRAM(const DRAMUtils::MemSpec::MemSpecSTTMRAM& memSpec) :
|
||||
MemSpec(memSpec,
|
||||
memSpec.memarchitecturespec.entries.at("nbrOfChannels"),
|
||||
memSpec.memarchitecturespec.entries.at("nbrOfRanks"),
|
||||
memSpec.memarchitecturespec.entries.at("nbrOfBanks"),
|
||||
memSpec.memarchitecturespec.nbrOfChannels,
|
||||
memSpec.memarchitecturespec.nbrOfRanks,
|
||||
memSpec.memarchitecturespec.nbrOfBanks,
|
||||
1,
|
||||
memSpec.memarchitecturespec.entries.at("nbrOfBanks"),
|
||||
memSpec.memarchitecturespec.entries.at("nbrOfBanks") *
|
||||
memSpec.memarchitecturespec.entries.at("nbrOfRanks"),
|
||||
memSpec.memarchitecturespec.entries.at("nbrOfRanks"),
|
||||
memSpec.memarchitecturespec.entries.at("nbrOfDevices")),
|
||||
tCKE(tCK * memSpec.memtimingspec.entries.at("CKE")),
|
||||
memSpec.memarchitecturespec.nbrOfBanks,
|
||||
memSpec.memarchitecturespec.nbrOfBanks *
|
||||
memSpec.memarchitecturespec.nbrOfRanks,
|
||||
memSpec.memarchitecturespec.nbrOfRanks,
|
||||
memSpec.memarchitecturespec.nbrOfDevices),
|
||||
tCKE(tCK * memSpec.memtimingspec.CKE),
|
||||
tPD(tCKE),
|
||||
tCKESR(tCK * memSpec.memtimingspec.entries.at("CKESR")),
|
||||
tRAS(tCK * memSpec.memtimingspec.entries.at("RAS")),
|
||||
tRC(tCK * memSpec.memtimingspec.entries.at("RC")),
|
||||
tRCD(tCK * memSpec.memtimingspec.entries.at("RCD")),
|
||||
tRL(tCK * memSpec.memtimingspec.entries.at("RL")),
|
||||
tRTP(tCK * memSpec.memtimingspec.entries.at("RTP")),
|
||||
tWL(tCK * memSpec.memtimingspec.entries.at("WL")),
|
||||
tWR(tCK * memSpec.memtimingspec.entries.at("WR")),
|
||||
tXP(tCK * memSpec.memtimingspec.entries.at("XP")),
|
||||
tXS(tCK * memSpec.memtimingspec.entries.at("XS")),
|
||||
tRP(tCK * memSpec.memtimingspec.entries.at("RP")),
|
||||
tDQSCK(tCK * memSpec.memtimingspec.entries.at("DQSCK")),
|
||||
tCCD(tCK * memSpec.memtimingspec.entries.at("CCD")),
|
||||
tFAW(tCK * memSpec.memtimingspec.entries.at("FAW")),
|
||||
tRRD(tCK * memSpec.memtimingspec.entries.at("RRD")),
|
||||
tWTR(tCK * memSpec.memtimingspec.entries.at("WTR")),
|
||||
tXPDLL(tCK * memSpec.memtimingspec.entries.at("XPDLL")),
|
||||
tXSDLL(tCK * memSpec.memtimingspec.entries.at("XSDLL")),
|
||||
tAL(tCK * memSpec.memtimingspec.entries.at("AL")),
|
||||
tACTPDEN(tCK * memSpec.memtimingspec.entries.at("ACTPDEN")),
|
||||
tPRPDEN(tCK * memSpec.memtimingspec.entries.at("PRPDEN")),
|
||||
tRTRS(tCK * memSpec.memtimingspec.entries.at("RTRS"))
|
||||
tCKESR(tCK * memSpec.memtimingspec.CKESR),
|
||||
tRAS(tCK * memSpec.memtimingspec.RAS),
|
||||
tRC(tCK * memSpec.memtimingspec.RC),
|
||||
tRCD(tCK * memSpec.memtimingspec.RCD),
|
||||
tRL(tCK * memSpec.memtimingspec.RL),
|
||||
tRTP(tCK * memSpec.memtimingspec.RTP),
|
||||
tWL(tCK * memSpec.memtimingspec.WL),
|
||||
tWR(tCK * memSpec.memtimingspec.WR),
|
||||
tXP(tCK * memSpec.memtimingspec.XP),
|
||||
tXS(tCK * memSpec.memtimingspec.XS),
|
||||
tRP(tCK * memSpec.memtimingspec.RP),
|
||||
tDQSCK(tCK * memSpec.memtimingspec.DQSCK),
|
||||
tCCD(tCK * memSpec.memtimingspec.CCD),
|
||||
tFAW(tCK * memSpec.memtimingspec.FAW),
|
||||
tRRD(tCK * memSpec.memtimingspec.RRD),
|
||||
tWTR(tCK * memSpec.memtimingspec.WTR),
|
||||
tXPDLL(tCK * memSpec.memtimingspec.XPDLL),
|
||||
tXSDLL(tCK * memSpec.memtimingspec.XSDLL),
|
||||
tAL(tCK * memSpec.memtimingspec.AL),
|
||||
tACTPDEN(tCK * memSpec.memtimingspec.ACTPDEN),
|
||||
tPRPDEN(tCK * memSpec.memtimingspec.PRPDEN),
|
||||
tRTRS(tCK * memSpec.memtimingspec.RTRS)
|
||||
{
|
||||
uint64_t deviceSizeBits =
|
||||
static_cast<uint64_t>(banksPerRank) * rowsPerBank * columnsPerRow * bitWidth;
|
||||
|
||||
@@ -39,6 +39,8 @@
|
||||
|
||||
#include "DRAMSys/configuration/memspec/MemSpec.h"
|
||||
|
||||
#include <DRAMUtils/memspec/standards/MemSpecSTTMRAM.h>
|
||||
|
||||
#include <systemc>
|
||||
|
||||
namespace DRAMSys
|
||||
@@ -47,7 +49,7 @@ namespace DRAMSys
|
||||
class MemSpecSTTMRAM final : public MemSpec
|
||||
{
|
||||
public:
|
||||
explicit MemSpecSTTMRAM(const Config::MemSpec& memSpec);
|
||||
explicit MemSpecSTTMRAM(const DRAMUtils::MemSpec::MemSpecSTTMRAM& memSpec);
|
||||
|
||||
// Memspec Variables:
|
||||
const sc_core::sc_time tCKE;
|
||||
|
||||
@@ -32,6 +32,7 @@
|
||||
* Authors:
|
||||
* Lukas Steiner
|
||||
* Derek Christ
|
||||
* Marco Mörz
|
||||
*/
|
||||
|
||||
#include "MemSpecWideIO.h"
|
||||
@@ -46,83 +47,44 @@ using namespace tlm;
|
||||
namespace DRAMSys
|
||||
{
|
||||
|
||||
MemSpecWideIO::MemSpecWideIO(const Config::MemSpec& memSpec) :
|
||||
MemSpecWideIO::MemSpecWideIO(const DRAMUtils::MemSpec::MemSpecWideIO& memSpec) :
|
||||
MemSpec(memSpec,
|
||||
memSpec.memarchitecturespec.entries.at("nbrOfChannels"),
|
||||
memSpec.memarchitecturespec.entries.at("nbrOfRanks"),
|
||||
memSpec.memarchitecturespec.entries.at("nbrOfBanks"),
|
||||
memSpec.memarchitecturespec.nbrOfChannels,
|
||||
memSpec.memarchitecturespec.nbrOfRanks,
|
||||
memSpec.memarchitecturespec.nbrOfBanks,
|
||||
1,
|
||||
memSpec.memarchitecturespec.entries.at("nbrOfBanks"),
|
||||
memSpec.memarchitecturespec.entries.at("nbrOfBanks") *
|
||||
memSpec.memarchitecturespec.entries.at("nbrOfRanks"),
|
||||
memSpec.memarchitecturespec.entries.at("nbrOfRanks"),
|
||||
memSpec.memarchitecturespec.entries.at("nbrOfDevices")),
|
||||
tCKE(tCK * memSpec.memtimingspec.entries.at("CKE")),
|
||||
tCKESR(tCK * memSpec.memtimingspec.entries.at("CKESR")),
|
||||
tRAS(tCK * memSpec.memtimingspec.entries.at("RAS")),
|
||||
tRC(tCK * memSpec.memtimingspec.entries.at("RC")),
|
||||
tRCD(tCK * memSpec.memtimingspec.entries.at("RCD")),
|
||||
tRL(tCK * memSpec.memtimingspec.entries.at("RL")),
|
||||
tWL(tCK * memSpec.memtimingspec.entries.at("WL")),
|
||||
tWR(tCK * memSpec.memtimingspec.entries.at("WR")),
|
||||
tXP(tCK * memSpec.memtimingspec.entries.at("XP")),
|
||||
tXSR(tCK * memSpec.memtimingspec.entries.at("XSR")),
|
||||
tREFI(tCK * memSpec.memtimingspec.entries.at("REFI")),
|
||||
tRFC(tCK * memSpec.memtimingspec.entries.at("RFC")),
|
||||
tRP(tCK * memSpec.memtimingspec.entries.at("RP")),
|
||||
tDQSCK(tCK * memSpec.memtimingspec.entries.at("DQSCK")),
|
||||
tAC(tCK * memSpec.memtimingspec.entries.at("AC")),
|
||||
tCCD_R(tCK * memSpec.memtimingspec.entries.at("CCD_R")),
|
||||
tCCD_W(tCK * memSpec.memtimingspec.entries.at("CCD_W")),
|
||||
tRRD(tCK * memSpec.memtimingspec.entries.at("RRD")),
|
||||
tTAW(tCK * memSpec.memtimingspec.entries.at("TAW")),
|
||||
tWTR(tCK * memSpec.memtimingspec.entries.at("WTR")),
|
||||
tRTRS(tCK * memSpec.memtimingspec.entries.at("RTRS")),
|
||||
iDD0(memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd0") : 0),
|
||||
iDD2N(memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd2n") : 0),
|
||||
iDD3N(memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd3n") : 0),
|
||||
iDD4R(memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd4r") : 0),
|
||||
iDD4W(memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd4w") : 0),
|
||||
iDD5(memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd5") : 0),
|
||||
iDD6(memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd6") : 0),
|
||||
vDD(memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("vdd") : 0),
|
||||
iDD02(memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd02") : 0),
|
||||
iDD2P0(memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd2p0")
|
||||
: 0),
|
||||
iDD2P02(memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd2p02")
|
||||
: 0),
|
||||
iDD2P1(memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd2p1")
|
||||
: 0),
|
||||
iDD2P12(memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd2p12")
|
||||
: 0),
|
||||
iDD2N2(memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd2n2")
|
||||
: 0),
|
||||
iDD3P0(memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd3p0")
|
||||
: 0),
|
||||
iDD3P02(memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd3p02")
|
||||
: 0),
|
||||
iDD3P1(memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd3p1")
|
||||
: 0),
|
||||
iDD3P12(memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd3p12")
|
||||
: 0),
|
||||
iDD3N2(memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd3n2")
|
||||
: 0),
|
||||
iDD4R2(memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd4r2")
|
||||
: 0),
|
||||
iDD4W2(memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd4w2")
|
||||
: 0),
|
||||
iDD52(memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd52") : 0),
|
||||
iDD62(memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("idd62") : 0),
|
||||
vDD2(memSpec.mempowerspec.has_value() ? memSpec.mempowerspec.value().entries.at("vdd2") : 0)
|
||||
memSpec.memarchitecturespec.nbrOfBanks,
|
||||
memSpec.memarchitecturespec.nbrOfBanks *
|
||||
memSpec.memarchitecturespec.nbrOfRanks,
|
||||
memSpec.memarchitecturespec.nbrOfRanks,
|
||||
memSpec.memarchitecturespec.nbrOfDevices),
|
||||
tCKE(tCK * memSpec.memtimingspec.CKE),
|
||||
tCKESR(tCK * memSpec.memtimingspec.CKESR),
|
||||
tRAS(tCK * memSpec.memtimingspec.RAS),
|
||||
tRC(tCK * memSpec.memtimingspec.RC),
|
||||
tRCD(tCK * memSpec.memtimingspec.RCD),
|
||||
tRL(tCK * memSpec.memtimingspec.RL),
|
||||
tWL(tCK * memSpec.memtimingspec.WL),
|
||||
tWR(tCK * memSpec.memtimingspec.WR),
|
||||
tXP(tCK * memSpec.memtimingspec.XP),
|
||||
tXSR(tCK * memSpec.memtimingspec.XSR),
|
||||
tREFI(tCK * memSpec.memtimingspec.REFI),
|
||||
tRFC(tCK * memSpec.memtimingspec.RFC),
|
||||
tRP(tCK * memSpec.memtimingspec.RP),
|
||||
tDQSCK(tCK * memSpec.memtimingspec.DQSCK),
|
||||
tAC(tCK * memSpec.memtimingspec.AC),
|
||||
tCCD_R(tCK * memSpec.memtimingspec.CCD_R),
|
||||
tCCD_W(tCK * memSpec.memtimingspec.CCD_W),
|
||||
tRRD(tCK * memSpec.memtimingspec.RRD),
|
||||
tTAW(tCK * memSpec.memtimingspec.TAW),
|
||||
tWTR(tCK * memSpec.memtimingspec.WTR),
|
||||
tRTRS(tCK * memSpec.memtimingspec.RTRS)
|
||||
{
|
||||
uint64_t deviceSizeBits =
|
||||
static_cast<uint64_t>(banksPerRank) * rowsPerBank * columnsPerRow * bitWidth;
|
||||
uint64_t deviceSizeBytes = deviceSizeBits / 8;
|
||||
memorySizeBytes = deviceSizeBytes * ranksPerChannel * numberOfChannels;
|
||||
|
||||
if (!memSpec.mempowerspec.has_value())
|
||||
SC_REPORT_FATAL("MemSpec", "No power spec defined!");
|
||||
|
||||
std::cout << headline << std::endl;
|
||||
std::cout << "Memory Configuration:" << std::endl << std::endl;
|
||||
std::cout << " Memory type: "
|
||||
@@ -195,97 +157,4 @@ bool MemSpecWideIO::requiresMaskedWrite(const tlm::tlm_generic_payload& payload)
|
||||
return !allBytesEnabled(payload);
|
||||
}
|
||||
|
||||
#ifdef DRAMPOWER
|
||||
DRAMPower::MemorySpecification MemSpecWideIO::toDramPowerMemSpec() const
|
||||
{
|
||||
DRAMPower::MemArchitectureSpec memArchSpec;
|
||||
memArchSpec.burstLength = defaultBurstLength;
|
||||
memArchSpec.dataRate = dataRate;
|
||||
memArchSpec.nbrOfRows = rowsPerBank;
|
||||
memArchSpec.nbrOfBanks = banksPerChannel;
|
||||
memArchSpec.nbrOfColumns = columnsPerRow;
|
||||
memArchSpec.nbrOfRanks = ranksPerChannel;
|
||||
memArchSpec.width = bitWidth;
|
||||
memArchSpec.nbrOfBankGroups = bankGroupsPerChannel;
|
||||
memArchSpec.twoVoltageDomains = true;
|
||||
memArchSpec.dll = false;
|
||||
|
||||
DRAMPower::MemTimingSpec memTimingSpec;
|
||||
// FIXME: memTimingSpec.FAWB = tTAW / tCK;
|
||||
// FIXME: memTimingSpec.RASB = tRAS / tCK;
|
||||
// FIXME: memTimingSpec.RCB = tRC / tCK;
|
||||
// FIXME: memTimingSpec.RPB = tRP / tCK;
|
||||
// FIXME: memTimingSpec.RRDB = tRRD / tCK;
|
||||
// FIXME: memTimingSpec.RRDB_L = tRRD / tCK;
|
||||
// FIXME: memTimingSpec.RRDB_S = tRRD / tCK;
|
||||
memTimingSpec.AL = 0;
|
||||
memTimingSpec.CCD = defaultBurstLength;
|
||||
memTimingSpec.CCD_L = defaultBurstLength;
|
||||
memTimingSpec.CCD_S = defaultBurstLength;
|
||||
memTimingSpec.CKE = tCKE / tCK;
|
||||
memTimingSpec.CKESR = tCKESR / tCK;
|
||||
// See also MemTimingSpec.cc in DRAMPower
|
||||
memTimingSpec.clkMhz = 1 / (tCK.to_seconds() * 1'000'000);
|
||||
memTimingSpec.clkPeriod = tCK.to_seconds() * 1'000'000'000;
|
||||
memTimingSpec.DQSCK = tDQSCK / tCK;
|
||||
memTimingSpec.FAW = tTAW / tCK;
|
||||
memTimingSpec.RAS = tRAS / tCK;
|
||||
memTimingSpec.RC = tRC / tCK;
|
||||
memTimingSpec.RCD = tRCD / tCK;
|
||||
memTimingSpec.REFI = tREFI / tCK;
|
||||
memTimingSpec.RFC = tRFC / tCK;
|
||||
memTimingSpec.RL = tRL / tCK;
|
||||
memTimingSpec.RP = tRP / tCK;
|
||||
memTimingSpec.RRD = tRRD / tCK;
|
||||
memTimingSpec.RRD_L = tRRD / tCK;
|
||||
memTimingSpec.RRD_S = tRRD / tCK;
|
||||
memTimingSpec.RTP = defaultBurstLength;
|
||||
memTimingSpec.TAW = tTAW / tCK;
|
||||
memTimingSpec.WL = tWL / tCK;
|
||||
memTimingSpec.WR = tWR / tCK;
|
||||
memTimingSpec.WTR = tWTR / tCK;
|
||||
memTimingSpec.WTR_L = tWTR / tCK;
|
||||
memTimingSpec.WTR_S = tWTR / tCK;
|
||||
memTimingSpec.XP = tXP / tCK;
|
||||
memTimingSpec.XPDLL = tXP / tCK;
|
||||
memTimingSpec.XS = tXSR / tCK;
|
||||
memTimingSpec.XSDLL = tXSR / tCK;
|
||||
|
||||
DRAMPower::MemPowerSpec memPowerSpec;
|
||||
memPowerSpec.idd0 = iDD0;
|
||||
memPowerSpec.idd02 = iDD02;
|
||||
memPowerSpec.idd2p0 = iDD2P0;
|
||||
memPowerSpec.idd2p02 = iDD2P02;
|
||||
memPowerSpec.idd2p1 = iDD2P1;
|
||||
memPowerSpec.idd2p12 = iDD2P12;
|
||||
memPowerSpec.idd2n = iDD2N;
|
||||
memPowerSpec.idd2n2 = iDD2N2;
|
||||
memPowerSpec.idd3p0 = iDD3P0;
|
||||
memPowerSpec.idd3p02 = iDD3P02;
|
||||
memPowerSpec.idd3p1 = iDD3P1;
|
||||
memPowerSpec.idd3p12 = iDD3P12;
|
||||
memPowerSpec.idd3n = iDD3N;
|
||||
memPowerSpec.idd3n2 = iDD3N2;
|
||||
memPowerSpec.idd4r = iDD4R;
|
||||
memPowerSpec.idd4r2 = iDD4R2;
|
||||
memPowerSpec.idd4w = iDD4W;
|
||||
memPowerSpec.idd4w2 = iDD4W2;
|
||||
memPowerSpec.idd5 = iDD5;
|
||||
memPowerSpec.idd52 = iDD52;
|
||||
memPowerSpec.idd6 = iDD6;
|
||||
memPowerSpec.idd62 = iDD62;
|
||||
memPowerSpec.vdd = vDD;
|
||||
memPowerSpec.vdd2 = vDD2;
|
||||
|
||||
DRAMPower::MemorySpecification powerSpec;
|
||||
powerSpec.id = memoryId;
|
||||
powerSpec.memoryType = DRAMPower::MemoryType::WIDEIO_SDR;
|
||||
powerSpec.memTimingSpec = memTimingSpec;
|
||||
powerSpec.memPowerSpec = memPowerSpec;
|
||||
powerSpec.memArchSpec = memArchSpec;
|
||||
|
||||
return powerSpec;
|
||||
}
|
||||
#endif
|
||||
|
||||
} // namespace DRAMSys
|
||||
|
||||
@@ -32,6 +32,7 @@
|
||||
* Authors:
|
||||
* Lukas Steiner
|
||||
* Derek Christ
|
||||
* Marco Mörz
|
||||
*/
|
||||
|
||||
#ifndef MEMSPECWIDEIO_H
|
||||
@@ -39,6 +40,8 @@
|
||||
|
||||
#include "DRAMSys/configuration/memspec/MemSpec.h"
|
||||
|
||||
#include <DRAMUtils/memspec/standards/MemSpecWideIO.h>
|
||||
|
||||
#include <systemc>
|
||||
|
||||
namespace DRAMSys
|
||||
@@ -47,7 +50,7 @@ namespace DRAMSys
|
||||
class MemSpecWideIO final : public MemSpec
|
||||
{
|
||||
public:
|
||||
explicit MemSpecWideIO(const Config::MemSpec& memSpec);
|
||||
explicit MemSpecWideIO(const DRAMUtils::MemSpec::MemSpecWideIO& memSpec);
|
||||
|
||||
// Memspec Variables:
|
||||
const sc_core::sc_time tCKE;
|
||||
@@ -72,32 +75,6 @@ public:
|
||||
const sc_core::sc_time tWTR;
|
||||
const sc_core::sc_time tRTRS;
|
||||
|
||||
// Currents and Voltages:
|
||||
const double iDD0;
|
||||
const double iDD2N;
|
||||
const double iDD3N;
|
||||
const double iDD4R;
|
||||
const double iDD4W;
|
||||
const double iDD5;
|
||||
const double iDD6;
|
||||
const double vDD;
|
||||
const double iDD02;
|
||||
const double iDD2P0;
|
||||
const double iDD2P02;
|
||||
const double iDD2P1;
|
||||
const double iDD2P12;
|
||||
const double iDD2N2;
|
||||
const double iDD3P0;
|
||||
const double iDD3P02;
|
||||
const double iDD3P1;
|
||||
const double iDD3P12;
|
||||
const double iDD3N2;
|
||||
const double iDD4R2;
|
||||
const double iDD4W2;
|
||||
const double iDD52;
|
||||
const double iDD62;
|
||||
const double vDD2;
|
||||
|
||||
[[nodiscard]] sc_core::sc_time getRefreshIntervalAB() const override;
|
||||
|
||||
[[nodiscard]] sc_core::sc_time
|
||||
@@ -107,10 +84,6 @@ public:
|
||||
const tlm::tlm_generic_payload& payload) const override;
|
||||
|
||||
[[nodiscard]] bool requiresMaskedWrite(const tlm::tlm_generic_payload& payload) const override;
|
||||
|
||||
#ifdef DRAMPOWER
|
||||
[[nodiscard]] DRAMPower::MemorySpecification toDramPowerMemSpec() const override;
|
||||
#endif
|
||||
};
|
||||
|
||||
} // namespace DRAMSys
|
||||
|
||||
@@ -32,6 +32,7 @@
|
||||
* Authors:
|
||||
* Lukas Steiner
|
||||
* Derek Christ
|
||||
* Marco Mörz
|
||||
*/
|
||||
|
||||
#include "MemSpecWideIO2.h"
|
||||
@@ -46,44 +47,44 @@ using namespace tlm;
|
||||
namespace DRAMSys
|
||||
{
|
||||
|
||||
MemSpecWideIO2::MemSpecWideIO2(const Config::MemSpec& memSpec) :
|
||||
MemSpecWideIO2::MemSpecWideIO2(const DRAMUtils::MemSpec::MemSpecWideIO2& memSpec) :
|
||||
MemSpec(memSpec,
|
||||
memSpec.memarchitecturespec.entries.at("nbrOfChannels"),
|
||||
memSpec.memarchitecturespec.entries.at("nbrOfRanks"),
|
||||
memSpec.memarchitecturespec.entries.at("nbrOfBanks"),
|
||||
memSpec.memarchitecturespec.nbrOfChannels,
|
||||
memSpec.memarchitecturespec.nbrOfRanks,
|
||||
memSpec.memarchitecturespec.nbrOfBanks,
|
||||
1,
|
||||
memSpec.memarchitecturespec.entries.at("nbrOfBanks"),
|
||||
memSpec.memarchitecturespec.entries.at("nbrOfBanks") *
|
||||
memSpec.memarchitecturespec.entries.at("nbrOfRanks"),
|
||||
memSpec.memarchitecturespec.entries.at("nbrOfRanks"),
|
||||
memSpec.memarchitecturespec.entries.at("nbrOfDevices")),
|
||||
tDQSCK(tCK * memSpec.memtimingspec.entries.at("DQSCK")),
|
||||
tDQSS(tCK * memSpec.memtimingspec.entries.at("DQSS")),
|
||||
tCKE(tCK * memSpec.memtimingspec.entries.at("CKE")),
|
||||
tRL(tCK * memSpec.memtimingspec.entries.at("RL")),
|
||||
tWL(tCK * memSpec.memtimingspec.entries.at("WL")),
|
||||
tRCpb(tCK * memSpec.memtimingspec.entries.at("RCPB")),
|
||||
tRCab(tCK * memSpec.memtimingspec.entries.at("RCAB")),
|
||||
tCKESR(tCK * memSpec.memtimingspec.entries.at("CKESR")),
|
||||
tXSR(tCK * memSpec.memtimingspec.entries.at("XSR")),
|
||||
tXP(tCK * memSpec.memtimingspec.entries.at("XP")),
|
||||
tCCD(tCK * memSpec.memtimingspec.entries.at("CCD")),
|
||||
tRTP(tCK * memSpec.memtimingspec.entries.at("RTP")),
|
||||
tRCD(tCK * memSpec.memtimingspec.entries.at("RCD")),
|
||||
tRPpb(tCK * memSpec.memtimingspec.entries.at("RPPB")),
|
||||
tRPab(tCK * memSpec.memtimingspec.entries.at("RPAB")),
|
||||
tRAS(tCK * memSpec.memtimingspec.entries.at("RAS")),
|
||||
tWR(tCK * memSpec.memtimingspec.entries.at("WR")),
|
||||
tWTR(tCK * memSpec.memtimingspec.entries.at("WTR")),
|
||||
tRRD(tCK * memSpec.memtimingspec.entries.at("RRD")),
|
||||
tFAW(tCK * memSpec.memtimingspec.entries.at("FAW")),
|
||||
tREFI(tCK * static_cast<unsigned>(memSpec.memtimingspec.entries.at("REFI") *
|
||||
memSpec.memtimingspec.entries.at("REFM"))),
|
||||
tREFIpb(tCK * static_cast<unsigned>(memSpec.memtimingspec.entries.at("REFIPB") *
|
||||
memSpec.memtimingspec.entries.at("REFM"))),
|
||||
tRFCab(tCK * memSpec.memtimingspec.entries.at("RFCAB")),
|
||||
tRFCpb(tCK * memSpec.memtimingspec.entries.at("RFCPB")),
|
||||
tRTRS(tCK * memSpec.memtimingspec.entries.at("RTRS"))
|
||||
memSpec.memarchitecturespec.nbrOfBanks,
|
||||
memSpec.memarchitecturespec.nbrOfBanks *
|
||||
memSpec.memarchitecturespec.nbrOfRanks,
|
||||
memSpec.memarchitecturespec.nbrOfRanks,
|
||||
memSpec.memarchitecturespec.nbrOfDevices),
|
||||
tDQSCK(tCK * memSpec.memtimingspec.DQSCK),
|
||||
tDQSS(tCK * memSpec.memtimingspec.DQSS),
|
||||
tCKE(tCK * memSpec.memtimingspec.CKE),
|
||||
tRL(tCK * memSpec.memtimingspec.RL),
|
||||
tWL(tCK * memSpec.memtimingspec.WL),
|
||||
tRCpb(tCK * memSpec.memtimingspec.RCPB),
|
||||
tRCab(tCK * memSpec.memtimingspec.RCAB),
|
||||
tCKESR(tCK * memSpec.memtimingspec.CKESR),
|
||||
tXSR(tCK * memSpec.memtimingspec.XSR),
|
||||
tXP(tCK * memSpec.memtimingspec.XP),
|
||||
tCCD(tCK * memSpec.memtimingspec.CCD),
|
||||
tRTP(tCK * memSpec.memtimingspec.RTP),
|
||||
tRCD(tCK * memSpec.memtimingspec.RCD),
|
||||
tRPpb(tCK * memSpec.memtimingspec.RPPB),
|
||||
tRPab(tCK * memSpec.memtimingspec.RPAB),
|
||||
tRAS(tCK * memSpec.memtimingspec.RAS),
|
||||
tWR(tCK * memSpec.memtimingspec.WR),
|
||||
tWTR(tCK * memSpec.memtimingspec.WTR),
|
||||
tRRD(tCK * memSpec.memtimingspec.RRD),
|
||||
tFAW(tCK * memSpec.memtimingspec.FAW),
|
||||
tREFI(tCK * static_cast<unsigned>(memSpec.memtimingspec.REFI *
|
||||
memSpec.memtimingspec.REFM)),
|
||||
tREFIpb(tCK * static_cast<unsigned>(memSpec.memtimingspec.REFIPB *
|
||||
memSpec.memtimingspec.REFM)),
|
||||
tRFCab(tCK * memSpec.memtimingspec.RFCAB),
|
||||
tRFCpb(tCK * memSpec.memtimingspec.RFCPB),
|
||||
tRTRS(tCK * memSpec.memtimingspec.RTRS)
|
||||
{
|
||||
uint64_t deviceSizeBits =
|
||||
static_cast<uint64_t>(banksPerRank) * rowsPerBank * columnsPerRow * bitWidth;
|
||||
|
||||
@@ -32,6 +32,7 @@
|
||||
* Authors:
|
||||
* Lukas Steiner
|
||||
* Derek Christ
|
||||
* Marco Mörz
|
||||
*/
|
||||
|
||||
#ifndef MEMSPECWIDEIO2_H
|
||||
@@ -39,6 +40,8 @@
|
||||
|
||||
#include "DRAMSys/configuration/memspec/MemSpec.h"
|
||||
|
||||
#include <DRAMUtils/memspec/standards/MemSpecWideIO2.h>
|
||||
|
||||
#include <systemc>
|
||||
|
||||
namespace DRAMSys
|
||||
@@ -47,7 +50,7 @@ namespace DRAMSys
|
||||
class MemSpecWideIO2 final : public MemSpec
|
||||
{
|
||||
public:
|
||||
explicit MemSpecWideIO2(const Config::MemSpec& memSpec);
|
||||
explicit MemSpecWideIO2(const DRAMUtils::MemSpec::MemSpecWideIO2& memSpec);
|
||||
|
||||
// Memspec Variables:
|
||||
const sc_core::sc_time tDQSCK;
|
||||
|
||||
@@ -34,6 +34,7 @@
|
||||
* Robert Gernhardt
|
||||
* Matthias Jung
|
||||
* Lukas Steiner
|
||||
* Marco Mörz
|
||||
*/
|
||||
|
||||
#include "Command.h"
|
||||
@@ -82,7 +83,7 @@ Command::Command(Command::Type type) : type(type)
|
||||
|
||||
Command::Command(tlm_phase phase)
|
||||
{
|
||||
assert(phase >= BEGIN_NOP && phase <= END_SREF);
|
||||
assert(phase >= BEGIN_NOP && phase <= END_SREF); // TODO < END_ENUM && type >= 0
|
||||
static constexpr std::array<Command::Type, Command::Type::END_ENUM> commandOfPhase = {
|
||||
Command::NOP, // 0
|
||||
Command::RD, // 1
|
||||
@@ -115,7 +116,7 @@ Command::Command(tlm_phase phase)
|
||||
|
||||
std::string Command::toString() const
|
||||
{
|
||||
assert(type >= Command::NOP && type <= Command::SREFEX);
|
||||
assert(type >= 0 && type < Command::END_ENUM); // TODO < END_ENUM && type >= 0
|
||||
static std::array<std::string, Command::Type::END_ENUM> stringOfCommand = {
|
||||
"NOP", // 0
|
||||
"RD", // 1
|
||||
@@ -153,7 +154,7 @@ unsigned Command::numberOfCommands()
|
||||
|
||||
tlm_phase Command::toPhase() const
|
||||
{
|
||||
assert(type >= Command::NOP && type <= Command::SREFEX);
|
||||
assert(type >= 0 && type < Command::END_ENUM);
|
||||
static std::array<tlm_phase, Command::Type::END_ENUM> phaseOfCommand = {
|
||||
BEGIN_NOP, // 0
|
||||
BEGIN_RD, // 1
|
||||
@@ -185,36 +186,36 @@ tlm_phase Command::toPhase() const
|
||||
}
|
||||
|
||||
#ifdef DRAMPOWER
|
||||
MemCommand::cmds phaseToDRAMPowerCommand(tlm_phase phase)
|
||||
CmdType phaseToDRAMPowerCommand(tlm_phase phase)
|
||||
{
|
||||
// TODO: add correct phases when DRAMPower supports DDR5 same bank refresh
|
||||
// TODO missing DSMEN, DSMEX
|
||||
assert(phase >= BEGIN_NOP && phase <= END_SREF);
|
||||
static std::array<MemCommand::cmds, Command::Type::END_ENUM> phaseOfCommand = {
|
||||
MemCommand::NOP, // 0
|
||||
MemCommand::RD, // 1
|
||||
MemCommand::WR, // 2
|
||||
MemCommand::NOP, // 3
|
||||
MemCommand::RDA, // 4
|
||||
MemCommand::WRA, // 5
|
||||
MemCommand::NOP, // 6
|
||||
MemCommand::ACT, // 7
|
||||
MemCommand::PRE, // 8, PREPB
|
||||
MemCommand::REFB, // 9, REFPB
|
||||
MemCommand::NOP, // 10, RFMPB
|
||||
MemCommand::NOP, // 11, REFP2B
|
||||
MemCommand::NOP, // 12, RFMP2B
|
||||
MemCommand::NOP, // 13, PRESB
|
||||
MemCommand::NOP, // 14, REFSB
|
||||
MemCommand::NOP, // 15, RFMSB
|
||||
MemCommand::PREA, // 16, PREAB
|
||||
MemCommand::REF, // 17, REFAB
|
||||
MemCommand::NOP, // 18, RFMAB
|
||||
MemCommand::PDN_S_ACT, // 19
|
||||
MemCommand::PDN_S_PRE, // 20
|
||||
MemCommand::SREN, // 21
|
||||
MemCommand::PUP_ACT, // 22
|
||||
MemCommand::PUP_PRE, // 23
|
||||
MemCommand::SREX // 24
|
||||
static std::array<CmdType, Command::Type::END_ENUM> phaseOfCommand = {
|
||||
CmdType::NOP, // 0
|
||||
CmdType::RD, // 1
|
||||
CmdType::WR, // 2
|
||||
CmdType::NOP, // 3
|
||||
CmdType::RDA, // 4
|
||||
CmdType::WRA, // 5
|
||||
CmdType::NOP, // 6
|
||||
CmdType::ACT, // 7
|
||||
CmdType::PRE, // 8, PREPB
|
||||
CmdType::REFB, // 9, REFPB
|
||||
CmdType::NOP, // 10, RFMPB
|
||||
CmdType::REFP2B, // 11, REFP2B
|
||||
CmdType::NOP, // 12, RFMP2B
|
||||
CmdType::PRESB, // 13, PRESB
|
||||
CmdType::REFSB, // 14, REFSB
|
||||
CmdType::NOP, // 15, RFMSB
|
||||
CmdType::PREA, // 16, PREAB
|
||||
CmdType::REFA, // 17, REFAB
|
||||
CmdType::NOP, // 18, RFMAB
|
||||
CmdType::PDEA, // 19
|
||||
CmdType::PDEP, // 20
|
||||
CmdType::SREFEN, // 21
|
||||
CmdType::PDXA, // 22
|
||||
CmdType::PDXP, // 23
|
||||
CmdType::SREFEX // 24
|
||||
};
|
||||
return phaseOfCommand[phase - BEGIN_NOP];
|
||||
}
|
||||
|
||||
@@ -33,12 +33,13 @@
|
||||
* Janik Schlemminger
|
||||
* Matthias Jung
|
||||
* Lukas Steiner
|
||||
* Marco Mörz
|
||||
*/
|
||||
#ifndef COMMAND_H
|
||||
#define COMMAND_H
|
||||
|
||||
#ifdef DRAMPOWER
|
||||
#include "MemCommand.h"
|
||||
#include <DRAMPower/command/CmdType.h>
|
||||
#endif
|
||||
|
||||
#include <string>
|
||||
@@ -86,7 +87,7 @@ DECLARE_EXTENDED_PHASE(END_PDNP); // 28
|
||||
DECLARE_EXTENDED_PHASE(END_SREF); // 29
|
||||
|
||||
#ifdef DRAMPOWER
|
||||
DRAMPower::MemCommand::cmds phaseToDRAMPowerCommand(tlm::tlm_phase phase);
|
||||
DRAMPower::CmdType phaseToDRAMPowerCommand(tlm::tlm_phase phase);
|
||||
#endif
|
||||
|
||||
bool phaseHasDataStrobe(tlm::tlm_phase phase);
|
||||
|
||||
@@ -32,6 +32,7 @@
|
||||
* Authors:
|
||||
* Lukas Steiner
|
||||
* Derek Christ
|
||||
* Marco Mörz
|
||||
*/
|
||||
|
||||
#include "Controller.h"
|
||||
@@ -64,6 +65,7 @@
|
||||
#include "DRAMSys/controller/scheduler/SchedulerFrFcfsGrp.h"
|
||||
#include "DRAMSys/controller/scheduler/SchedulerGrpFrFcfs.h"
|
||||
#include "DRAMSys/controller/scheduler/SchedulerGrpFrFcfsWm.h"
|
||||
|
||||
#include <cstdint>
|
||||
#include <numeric>
|
||||
#include <string>
|
||||
@@ -128,62 +130,62 @@ Controller::Controller(const sc_module_name& name,
|
||||
// instantiate timing checker
|
||||
try
|
||||
{
|
||||
if (memSpec.memoryType == Config::MemoryType::DDR3)
|
||||
if (memSpec.memoryType == DRAMUtils::MemSpec::MemSpecDDR3::id)
|
||||
{
|
||||
checker = std::make_unique<CheckerDDR3>(dynamic_cast<const MemSpecDDR3&>(memSpec));
|
||||
}
|
||||
else if (memSpec.memoryType == Config::MemoryType::DDR4)
|
||||
else if (memSpec.memoryType == DRAMUtils::MemSpec::MemSpecDDR4::id)
|
||||
{
|
||||
checker = std::make_unique<CheckerDDR4>(dynamic_cast<const MemSpecDDR4&>(memSpec));
|
||||
}
|
||||
else if (memSpec.memoryType == Config::MemoryType::WideIO)
|
||||
else if (memSpec.memoryType == DRAMUtils::MemSpec::MemSpecWideIO::id)
|
||||
{
|
||||
checker = std::make_unique<CheckerWideIO>(dynamic_cast<const MemSpecWideIO&>(memSpec));
|
||||
}
|
||||
else if (memSpec.memoryType == Config::MemoryType::LPDDR4)
|
||||
else if (memSpec.memoryType == DRAMUtils::MemSpec::MemSpecLPDDR4::id)
|
||||
{
|
||||
checker = std::make_unique<CheckerLPDDR4>(dynamic_cast<const MemSpecLPDDR4&>(memSpec));
|
||||
}
|
||||
else if (memSpec.memoryType == Config::MemoryType::WideIO2)
|
||||
else if (memSpec.memoryType == DRAMUtils::MemSpec::MemSpecWideIO2::id)
|
||||
{
|
||||
checker =
|
||||
std::make_unique<CheckerWideIO2>(dynamic_cast<const MemSpecWideIO2&>(memSpec));
|
||||
}
|
||||
else if (memSpec.memoryType == Config::MemoryType::HBM2)
|
||||
else if (memSpec.memoryType == DRAMUtils::MemSpec::MemSpecHBM2::id)
|
||||
{
|
||||
checker = std::make_unique<CheckerHBM2>(dynamic_cast<const MemSpecHBM2&>(memSpec));
|
||||
}
|
||||
else if (memSpec.memoryType == Config::MemoryType::GDDR5)
|
||||
else if (memSpec.memoryType == DRAMUtils::MemSpec::MemSpecGDDR5::id)
|
||||
{
|
||||
checker = std::make_unique<CheckerGDDR5>(dynamic_cast<const MemSpecGDDR5&>(memSpec));
|
||||
}
|
||||
else if (memSpec.memoryType == Config::MemoryType::GDDR5X)
|
||||
else if (memSpec.memoryType == DRAMUtils::MemSpec::MemSpecGDDR5X::id)
|
||||
{
|
||||
checker = std::make_unique<CheckerGDDR5X>(dynamic_cast<const MemSpecGDDR5X&>(memSpec));
|
||||
}
|
||||
else if (memSpec.memoryType == Config::MemoryType::GDDR6)
|
||||
else if (memSpec.memoryType == DRAMUtils::MemSpec::MemSpecGDDR6::id)
|
||||
{
|
||||
checker = std::make_unique<CheckerGDDR6>(dynamic_cast<const MemSpecGDDR6&>(memSpec));
|
||||
}
|
||||
else if (memSpec.memoryType == Config::MemoryType::STTMRAM)
|
||||
else if (memSpec.memoryType == DRAMUtils::MemSpec::MemSpecSTTMRAM::id)
|
||||
{
|
||||
checker =
|
||||
std::make_unique<CheckerSTTMRAM>(dynamic_cast<const MemSpecSTTMRAM&>(memSpec));
|
||||
}
|
||||
#ifdef DDR5_SIM
|
||||
else if (memSpec.memoryType == Config::MemoryType::DDR5)
|
||||
else if (memSpec.memoryType == DRAMUtils::MemSpec::MemSpecDDR5::id)
|
||||
{
|
||||
checker = std::make_unique<CheckerDDR5>(dynamic_cast<const MemSpecDDR5&>(memSpec));
|
||||
}
|
||||
#endif
|
||||
#ifdef LPDDR5_SIM
|
||||
else if (memSpec.memoryType == Config::MemoryType::LPDDR5)
|
||||
else if (memSpec.memoryType == DRAMUtils::MemSpec::MemSpecLPDDR5::id)
|
||||
{
|
||||
checker = std::make_unique<CheckerLPDDR5>(dynamic_cast<const MemSpecLPDDR5&>(memSpec));
|
||||
}
|
||||
#endif
|
||||
#ifdef HBM3_SIM
|
||||
else if (memSpec.memoryType == Config::MemoryType::HBM3)
|
||||
else if (memSpec.memoryType == DRAMUtils::MemSpec::MemSpecHBM3::id)
|
||||
{
|
||||
checker = std::make_unique<CheckerHBM3>(dynamic_cast<const MemSpecHBM3&>(memSpec));
|
||||
}
|
||||
|
||||
@@ -36,6 +36,7 @@
|
||||
* Felipe S. Prado
|
||||
* Lukas Steiner
|
||||
* Derek Christ
|
||||
* Marco Mörz
|
||||
*/
|
||||
|
||||
#include "DRAMSys.h"
|
||||
@@ -45,6 +46,8 @@
|
||||
|
||||
#include "DRAMSys/simulation/Dram.h"
|
||||
|
||||
#include "DRAMSys/config/MemSpec.h"
|
||||
|
||||
#include "DRAMSys/configuration/memspec/MemSpecDDR3.h"
|
||||
#include "DRAMSys/configuration/memspec/MemSpecDDR4.h"
|
||||
#include "DRAMSys/configuration/memspec/MemSpecGDDR5.h"
|
||||
@@ -69,8 +72,9 @@
|
||||
#include <cstdlib>
|
||||
#include <iostream>
|
||||
#include <memory>
|
||||
#include <stdexcept>
|
||||
#include <vector>
|
||||
#include <variant>
|
||||
#include <type_traits>
|
||||
|
||||
namespace DRAMSys
|
||||
{
|
||||
@@ -223,7 +227,7 @@ void DRAMSys::setupTlmRecorders(const std::string& traceName, const Config::Conf
|
||||
nlohmann::json mcconfig;
|
||||
nlohmann::json memspec;
|
||||
mcconfig[Config::McConfig::KEY] = config.mcconfig;
|
||||
memspec[Config::MemSpec::KEY] = config.memspec;
|
||||
memspec[Config::MemSpecConstants::KEY] = config.memspec;
|
||||
|
||||
tlmRecorders.emplace_back(recorderName,
|
||||
simConfig,
|
||||
@@ -306,57 +310,49 @@ void DRAMSys::report()
|
||||
std::cout << headline << std::endl;
|
||||
}
|
||||
|
||||
std::unique_ptr<const MemSpec> DRAMSys::createMemSpec(const Config::MemSpec& memSpec)
|
||||
std::unique_ptr<const MemSpec> DRAMSys::createMemSpec(const DRAMUtils::MemSpec::MemSpecVariant& memSpec)
|
||||
{
|
||||
auto memoryType = memSpec.memoryType;
|
||||
|
||||
if (memoryType == Config::MemoryType::DDR3)
|
||||
return std::make_unique<const MemSpecDDR3>(memSpec);
|
||||
|
||||
if (memoryType == Config::MemoryType::DDR4)
|
||||
return std::make_unique<const MemSpecDDR4>(memSpec);
|
||||
|
||||
if (memoryType == Config::MemoryType::LPDDR4)
|
||||
return std::make_unique<const MemSpecLPDDR4>(memSpec);
|
||||
|
||||
if (memoryType == Config::MemoryType::WideIO)
|
||||
return std::make_unique<const MemSpecWideIO>(memSpec);
|
||||
|
||||
if (memoryType == Config::MemoryType::WideIO2)
|
||||
return std::make_unique<const MemSpecWideIO2>(memSpec);
|
||||
|
||||
if (memoryType == Config::MemoryType::HBM2)
|
||||
return std::make_unique<const MemSpecHBM2>(memSpec);
|
||||
|
||||
if (memoryType == Config::MemoryType::GDDR5)
|
||||
return std::make_unique<const MemSpecGDDR5>(memSpec);
|
||||
|
||||
if (memoryType == Config::MemoryType::GDDR5X)
|
||||
return std::make_unique<const MemSpecGDDR5X>(memSpec);
|
||||
|
||||
if (memoryType == Config::MemoryType::GDDR6)
|
||||
return std::make_unique<const MemSpecGDDR6>(memSpec);
|
||||
|
||||
if (memoryType == Config::MemoryType::STTMRAM)
|
||||
return std::make_unique<const MemSpecSTTMRAM>(memSpec);
|
||||
|
||||
return std::visit([](const auto& v) -> std::unique_ptr<const MemSpec> {
|
||||
using T = std::decay_t<decltype(v)>;
|
||||
|
||||
if constexpr (std::is_same_v<T, DRAMUtils::MemSpec::MemSpecDDR3>)
|
||||
return std::make_unique<const MemSpecDDR3>(v);
|
||||
else if constexpr (std::is_same_v<T, DRAMUtils::MemSpec::MemSpecDDR4>)
|
||||
return std::make_unique<const MemSpecDDR4>(v);
|
||||
else if constexpr (std::is_same_v<T, DRAMUtils::MemSpec::MemSpecLPDDR4>)
|
||||
return std::make_unique<const MemSpecLPDDR4>(v);
|
||||
else if constexpr (std::is_same_v<T, DRAMUtils::MemSpec::MemSpecWideIO>)
|
||||
return std::make_unique<const MemSpecWideIO>(v);
|
||||
else if constexpr (std::is_same_v<T, DRAMUtils::MemSpec::MemSpecWideIO2>)
|
||||
return std::make_unique<const MemSpecWideIO2>(v);
|
||||
else if constexpr (std::is_same_v<T, DRAMUtils::MemSpec::MemSpecHBM2>)
|
||||
return std::make_unique<const MemSpecHBM2>(v);
|
||||
else if constexpr (std::is_same_v<T, DRAMUtils::MemSpec::MemSpecGDDR5>)
|
||||
return std::make_unique<const MemSpecGDDR5>(v);
|
||||
else if constexpr (std::is_same_v<T, DRAMUtils::MemSpec::MemSpecGDDR5X>)
|
||||
return std::make_unique<const MemSpecGDDR5X>(v);
|
||||
else if constexpr (std::is_same_v<T, DRAMUtils::MemSpec::MemSpecGDDR6>)
|
||||
return std::make_unique<const MemSpecGDDR6>(v);
|
||||
else if constexpr (std::is_same_v<T, DRAMUtils::MemSpec::MemSpecSTTMRAM>)
|
||||
return std::make_unique<const MemSpecSTTMRAM>(v);
|
||||
#ifdef DDR5_SIM
|
||||
if (memoryType == Config::MemoryType::DDR5)
|
||||
return std::make_unique<const MemSpecDDR5>(memSpec);
|
||||
else if constexpr ((std::is_same_v<T, DRAMUtils::MemSpec::MemSpecDDR5>))
|
||||
return std::make_unique<const MemSpecDDR5>(v);
|
||||
#endif
|
||||
|
||||
#ifdef LPDDR5_SIM
|
||||
if (memoryType == Config::MemoryType::LPDDR5)
|
||||
return std::make_unique<const MemSpecLPDDR5>(memSpec);
|
||||
else if constexpr ((std::is_same_v<T, DRAMUtils::MemSpec::MemSpecLPDDR5>))
|
||||
return std::make_unique<const MemSpecLPDDR5>(v);
|
||||
#endif
|
||||
|
||||
#ifdef HBM3_SIM
|
||||
if (memoryType == Config::MemoryType::HBM3)
|
||||
return std::make_unique<const MemSpecHBM3>(memSpec);
|
||||
else if constexpr ((std::is_same_v<T, DRAMUtils::MemSpec::MemSpecHBM3>))
|
||||
return std::make_unique<const MemSpecHBM3>(v);
|
||||
#endif
|
||||
|
||||
SC_REPORT_FATAL("Configuration", "Unsupported DRAM type");
|
||||
return {};
|
||||
else
|
||||
{
|
||||
SC_REPORT_FATAL("Configuration", "Unsupported DRAM type");
|
||||
return nullptr;
|
||||
}
|
||||
}, memSpec.getVariant());
|
||||
}
|
||||
|
||||
std::unique_ptr<Arbiter> DRAMSys::createArbiter(const SimConfig& simConfig,
|
||||
|
||||
@@ -36,6 +36,7 @@
|
||||
* Felipe S. Prado
|
||||
* Lukas Steiner
|
||||
* Derek Christ
|
||||
* Marco Mörz
|
||||
*/
|
||||
|
||||
#ifndef DRAMSYS_H
|
||||
@@ -53,7 +54,8 @@
|
||||
#include "DRAMSys/simulation/Dram.h"
|
||||
#include "DRAMSys/simulation/SimConfig.h"
|
||||
|
||||
#include <list>
|
||||
#include <DRAMUtils/memspec/MemSpec.h>
|
||||
|
||||
#include <memory>
|
||||
#include <string>
|
||||
#include <systemc>
|
||||
@@ -93,7 +95,7 @@ public:
|
||||
|
||||
private:
|
||||
static void logo();
|
||||
static std::unique_ptr<const MemSpec> createMemSpec(const Config::MemSpec& memSpec);
|
||||
static std::unique_ptr<const MemSpec> createMemSpec(const DRAMUtils::MemSpec::MemSpecVariant& memSpec);
|
||||
static std::unique_ptr<Arbiter> createArbiter(const SimConfig& simConfig,
|
||||
const McConfig& mcConfig,
|
||||
const MemSpec& memSpec,
|
||||
|
||||
@@ -36,6 +36,7 @@
|
||||
* Eder F. Zulian
|
||||
* Felipe S. Prado
|
||||
* Derek Christ
|
||||
* Marco Mörz
|
||||
*/
|
||||
|
||||
#include "Dram.h"
|
||||
@@ -45,12 +46,7 @@
|
||||
#include "DRAMSys/config/SimConfig.h"
|
||||
#include <sysc/kernel/sc_module.h>
|
||||
|
||||
#ifdef DRAMPOWER
|
||||
#include "LibDRAMPower.h"
|
||||
#endif
|
||||
|
||||
#include <cassert>
|
||||
#include <cstdint>
|
||||
#include <cstdlib>
|
||||
|
||||
#ifdef _WIN32
|
||||
@@ -59,6 +55,11 @@
|
||||
#include <sys/mman.h>
|
||||
#endif
|
||||
|
||||
#ifdef DRAMPOWER
|
||||
#include "DRAMPower/data/energy.h"
|
||||
#include "DRAMPower/command/Command.h"
|
||||
#endif
|
||||
|
||||
using namespace sc_core;
|
||||
using namespace tlm;
|
||||
|
||||
@@ -114,7 +115,14 @@ Dram::Dram(const sc_module_name& name,
|
||||
#ifdef DRAMPOWER
|
||||
if (powerAnalysis)
|
||||
{
|
||||
DRAMPower = std::make_unique<libDRAMPower>(memSpec.toDramPowerMemSpec(), false);
|
||||
DRAMPower = memSpec.toDramPowerObject();
|
||||
if (DRAMPower && storeMode == Config::StoreModeType::NoStorage) {
|
||||
if (simConfig.togglingRate) {
|
||||
DRAMPower->setToggleRate(0, simConfig.togglingRate);
|
||||
} else {
|
||||
SC_REPORT_FATAL("DRAM", "Toggling rates for power estimation must be provided for storeMode NoStorage");
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if (simConfig.powerAnalysis && simConfig.enableWindowing)
|
||||
@@ -131,23 +139,25 @@ Dram::~Dram()
|
||||
void Dram::reportPower()
|
||||
{
|
||||
#ifdef DRAMPOWER
|
||||
DRAMPower->calcEnergy();
|
||||
if (!DRAMPower)
|
||||
return;
|
||||
double energy = DRAMPower->getTotalEnergy(DRAMPower->getLastCommandTime());
|
||||
double time = DRAMPower->getLastCommandTime() * memSpec.tCK.to_seconds();
|
||||
|
||||
// Print the final total energy and the average power for
|
||||
// the simulation:
|
||||
std::cout << name() << std::string(" Total Energy: ") << std::fixed << std::setprecision(2)
|
||||
<< DRAMPower->getEnergy().total_energy * memSpec.devicesPerRank << std::string(" pJ")
|
||||
std::cout << name() << std::string(" Total Energy: ") << std::defaultfloat << std::setprecision(3)
|
||||
<< energy << std::string(" J")
|
||||
<< std::endl;
|
||||
|
||||
std::cout << name() << std::string(" Average Power: ") << std::fixed << std::setprecision(2)
|
||||
<< DRAMPower->getPower().average_power * memSpec.devicesPerRank << std::string(" mW")
|
||||
std::cout << name() << std::string(" Average Power: ") << std::defaultfloat << std::setprecision(3)
|
||||
<< energy / time << std::string(" W")
|
||||
<< std::endl;
|
||||
|
||||
if (tlmRecorder != nullptr)
|
||||
{
|
||||
tlmRecorder->recordPower(sc_time_stamp().to_seconds(),
|
||||
this->DRAMPower->getPower().window_average_power *
|
||||
this->memSpec.devicesPerRank);
|
||||
energy / time);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
@@ -157,11 +167,29 @@ tlm_sync_enum Dram::nb_transport_fw(tlm_generic_payload& trans, tlm_phase& phase
|
||||
assert(phase >= BEGIN_RD && phase <= END_SREF);
|
||||
|
||||
#ifdef DRAMPOWER
|
||||
if (powerAnalysis)
|
||||
if (powerAnalysis && DRAMPower)
|
||||
{
|
||||
int bank = static_cast<int>(ControllerExtension::getBank(trans));
|
||||
int64_t cycle = std::lround((sc_time_stamp() + delay) / memSpec.tCK);
|
||||
DRAMPower->doCommand(phaseToDRAMPowerCommand(phase), bank, cycle);
|
||||
std::size_t rank = static_cast<std::size_t>(ControllerExtension::getRank(trans)); // relaitve to the channel
|
||||
std::size_t bank_group_abs = static_cast<std::size_t>(ControllerExtension::getBankGroup(trans)); // relative to the channel
|
||||
std::size_t bank_group = bank_group_abs - rank * memSpec.groupsPerRank; // relative to the rank
|
||||
std::size_t bank = static_cast<std::size_t>(ControllerExtension::getBank(trans)) - bank_group_abs * memSpec.banksPerGroup; // relative to the bank_group
|
||||
std::size_t row = static_cast<std::size_t>(ControllerExtension::getRow(trans));
|
||||
std::size_t column = static_cast<std::size_t>(ControllerExtension::getColumn(trans));
|
||||
uint64_t cycle = std::lround((sc_time_stamp() + delay) / memSpec.tCK);
|
||||
|
||||
// DRAMPower:
|
||||
// banks are relative to the rank
|
||||
// bankgroups are relative to the rank
|
||||
bank = bank + (bank_group * memSpec.banksPerGroup);
|
||||
|
||||
DRAMPower::TargetCoordinate target(bank, bank_group, rank, row, column);
|
||||
|
||||
// TODO read, write data for interface calculation
|
||||
uint8_t * data = trans.get_data_ptr(); // Can be nullptr if no data
|
||||
std::size_t datasize = trans.get_data_length() * 8; // Is always set
|
||||
|
||||
DRAMPower::Command command(cycle, phaseToDRAMPowerCommand(phase), target, data, datasize);
|
||||
DRAMPower->doCoreInterfaceCommand(command);
|
||||
}
|
||||
#endif
|
||||
|
||||
@@ -291,6 +319,10 @@ void Dram::deserialize(std::istream& stream)
|
||||
void Dram::powerWindow()
|
||||
{
|
||||
int64_t clkCycles = 0;
|
||||
double previousEnergy = 0;
|
||||
double currentEnergy = 0;
|
||||
double windowEnergy = 0;
|
||||
double powerWindowSizeSeconds = powerWindowSize.to_seconds();
|
||||
|
||||
while (true)
|
||||
{
|
||||
@@ -299,30 +331,28 @@ void Dram::powerWindow()
|
||||
|
||||
clkCycles = std::lround(sc_time_stamp() / this->memSpec.tCK);
|
||||
|
||||
this->DRAMPower->calcWindowEnergy(clkCycles);
|
||||
currentEnergy = this->DRAMPower->getTotalEnergy(clkCycles);
|
||||
windowEnergy = currentEnergy - previousEnergy;
|
||||
|
||||
// During operation the energy should never be zero since the device is always consuming
|
||||
assert(!this->DRAMPower->getEnergy().window_energy < 1e-05);
|
||||
assert(!(windowEnergy < 1e-15));
|
||||
|
||||
if (tlmRecorder)
|
||||
{
|
||||
// Store the time (in seconds) and the current average power (in mW) into the database
|
||||
tlmRecorder->recordPower(sc_time_stamp().to_seconds(),
|
||||
this->DRAMPower->getPower().window_average_power *
|
||||
this->memSpec.devicesPerRank);
|
||||
windowEnergy / powerWindowSizeSeconds);
|
||||
}
|
||||
|
||||
// Here considering that DRAMPower provides the energy in pJ and the power in mW
|
||||
// Here considering that DRAMPower provides the energy in J and the power in W
|
||||
PRINTDEBUGMESSAGE(this->name(),
|
||||
std::string("\tWindow Energy: \t") +
|
||||
std::to_string(this->DRAMPower->getEnergy().window_energy *
|
||||
this->memSpec.devicesPerRank) +
|
||||
std::string("\t[pJ]"));
|
||||
std::to_string(windowEnergy) +
|
||||
std::string("\t[J]"));
|
||||
PRINTDEBUGMESSAGE(this->name(),
|
||||
std::string("\tWindow Average Power: \t") +
|
||||
std::to_string(this->DRAMPower->getPower().window_average_power *
|
||||
this->memSpec.devicesPerRank) +
|
||||
std::string("\t[mW]"));
|
||||
std::to_string(windowEnergy / powerWindowSizeSeconds) +
|
||||
std::string("\t[W]"));
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
@@ -36,6 +36,7 @@
|
||||
* Eder F. Zulian
|
||||
* Felipe S. Prado
|
||||
* Derek Christ
|
||||
* Marco Mörz
|
||||
*/
|
||||
|
||||
#ifndef DRAM_H
|
||||
@@ -47,13 +48,15 @@
|
||||
#include "DRAMSys/configuration/memspec/MemSpec.h"
|
||||
#include "DRAMSys/simulation/SimConfig.h"
|
||||
|
||||
#include <memory>
|
||||
#ifdef DRAMPOWER
|
||||
#include "DRAMPower/command/CmdType.h"
|
||||
#include "DRAMPower/dram/dram_base.h"
|
||||
#endif
|
||||
|
||||
#include <systemc>
|
||||
#include <tlm>
|
||||
#include <tlm_utils/simple_target_socket.h>
|
||||
|
||||
class libDRAMPower;
|
||||
|
||||
namespace DRAMSys
|
||||
{
|
||||
|
||||
@@ -73,7 +76,7 @@ protected:
|
||||
sc_core::sc_time powerWindowSize;
|
||||
|
||||
#ifdef DRAMPOWER
|
||||
std::unique_ptr<libDRAMPower> DRAMPower;
|
||||
std::unique_ptr<DRAMPower::dram_base<DRAMPower::CmdType>> DRAMPower;
|
||||
// This Thread is only triggered when Power Simulation is enabled.
|
||||
// It estimates the current average power which will be stored in the trace database for
|
||||
// visualization purposes.
|
||||
|
||||
@@ -31,6 +31,7 @@
|
||||
*
|
||||
* Authors:
|
||||
* Derek Christ
|
||||
* Marco Mörz
|
||||
*/
|
||||
|
||||
#include "SimConfig.h"
|
||||
@@ -53,7 +54,8 @@ SimConfig::SimConfig(const Config::SimConfig& simConfig) :
|
||||
checkTLM2Protocol(simConfig.CheckTLM2Protocol.value_or(DEFAULT_CHECK_TLM2_PROTOCOL)),
|
||||
useMalloc(simConfig.UseMalloc.value_or(DEFAULT_USE_MALLOC)),
|
||||
addressOffset(simConfig.AddressOffset.value_or(DEFAULT_ADDRESS_OFFSET)),
|
||||
storeMode(simConfig.StoreMode.value_or(DEFAULT_STORE_MODE))
|
||||
storeMode(simConfig.StoreMode.value_or(DEFAULT_STORE_MODE)),
|
||||
togglingRate(simConfig.TogglingRate)
|
||||
{
|
||||
if (storeMode == Config::StoreModeType::Invalid)
|
||||
SC_REPORT_FATAL("SimConfig", "Invalid StoreMode");
|
||||
|
||||
@@ -31,14 +31,17 @@
|
||||
*
|
||||
* Authors:
|
||||
* Derek Christ
|
||||
* Marco Mörz
|
||||
*/
|
||||
|
||||
#ifndef SIM_CONFIG_H
|
||||
#define SIM_CONFIG_H
|
||||
|
||||
#include <DRAMSys/config/SimConfig.h>
|
||||
#include <DRAMUtils/config/toggling_rate.h>
|
||||
|
||||
#include <string>
|
||||
#include <optional>
|
||||
|
||||
namespace DRAMSys
|
||||
{
|
||||
@@ -58,6 +61,7 @@ struct SimConfig
|
||||
bool useMalloc;
|
||||
unsigned long long int addressOffset;
|
||||
Config::StoreModeType storeMode;
|
||||
std::optional<DRAMUtils::Config::ToggleRateDefinition> togglingRate;
|
||||
|
||||
static constexpr std::string_view DEFAULT_SIMULATION_NAME = "default";
|
||||
static constexpr bool DEFAULT_DATABASE_RECORDING = false;
|
||||
|
||||
Reference in New Issue
Block a user