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Integrate DRAMUtils and new DRAMPower

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This commit is contained in:
marcomoerz
2024-07-04 10:54:04 +02:00
committed by Derek Christ
parent 0bd943e588
commit 4120e9c35b
240 changed files with 10895 additions and 3138 deletions
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4
extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoDDR5.cpp
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@@ -47,7 +47,7 @@ void TimeDependenciesInfoDDR5::mInitializeValues()
burstLength = mMemspecJson["memarchitecturespec"].toObject()["burstLength"].toInt();
dataRate = mMemspecJson["memarchitecturespec"].toObject()["dataRate"].toInt();
refMode = mMemspecJson["memarchitecturespec"].toObject()["refMode"].toInt();
RefMode = mMemspecJson["memarchitecturespec"].toObject()["RefMode"].toInt();
cmdMode = mMemspecJson["memarchitecturespec"].toObject()["cmdMode"].toInt();
bitWidth = mMemspecJson["memarchitecturespec"].toObject()["width"].toInt();
@@ -100,7 +100,7 @@ void TimeDependenciesInfoDDR5::mInitializeValues()
tRC = tRAS + tRP;
if (refMode == 1)
if (RefMode == 1)
{
tRFC_slr = tCK * mMemspecJson["memtimingspec"].toObject()["RFC1_slr"].toInt();
tRFC_dlr = tCK * mMemspecJson["memtimingspec"].toObject()["RFC1_dlr"].toInt();

2
extensions/apps/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoDDR5.h
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@@ -33,7 +33,7 @@ protected:
uint burstLength;
uint dataRate;
uint refMode;
uint RefMode;
uint tRCD;
uint tPPD;

8
extensions/apps/traceAnalyzer/scripts/tests.py
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@@ -10,7 +10,7 @@ class DramConfig(object):
memoryType = ""
scheduler = ""
bankwiseLogic = 0
refMode = 1
RefMode = 1
clk = 0
unitOfTime = ""
dataRate = 0
@@ -53,7 +53,7 @@ class DramConfig(object):
self.unitOfTime = clkWithUnit[1].lower()
self.bankwiseLogic = 0
self.refMode = 0
self.RefMode = 0
self.scheduler = mcconfig.getValue("Scheduler")
self.numberOfBanks = memspec.getIntValue("memarchitecturespec","nbrOfBanks")
@@ -112,10 +112,10 @@ class DramConfig(object):
self.tXS = self.clk * memspec.getIntValue("memtimingspec","XS")
self.tXSDLL = self.clk * memspec.getIntValue("memtimingspec","XSDLL")
self.tAL = self.clk * memspec.getIntValue("memtimingspec","AL")
if (self.refMode == "4"):
if (self.RefMode == "4"):
self.tRFC = self.clk * memspec.getIntValue("memtimingspec","RFC4")
self.tREFI = self.clk * (memspec.getIntValue("memtimingspec","REFI") / 4)
elif (self.refMode == "2"):
elif (self.RefMode == "2"):
self.tRFC = self.clk * memspec.getIntValue("memtimingspec","RFC2")
self.tREFI = self.clk * (memspec.getIntValue("memtimingspec","REFI") / 2)
else:

161
extensions/standards/DDR5/DRAMSys/configuration/memspec/MemSpecDDR5.cpp
View File

@@ -4,6 +4,7 @@
* Authors:
* Lukas Steiner
* Derek Christ
* Marco Mörz
*/
#include "MemSpecDDR5.h"
@@ -18,81 +19,90 @@ using namespace tlm;
namespace DRAMSys
{
MemSpecDDR5::MemSpecDDR5(const Config::MemSpec& memSpec) :
MemSpecDDR5::MemSpecDDR5(const DRAMUtils::MemSpec::MemSpecDDR5& memSpec) :
MemSpec(memSpec,
memSpec.memarchitecturespec.entries.at("nbrOfChannels"),
memSpec.memarchitecturespec.entries.at("nbrOfRanks"),
memSpec.memarchitecturespec.entries.at("nbrOfBanks"),
memSpec.memarchitecturespec.entries.at("nbrOfBankGroups"),
memSpec.memarchitecturespec.entries.at("nbrOfBanks") /
memSpec.memarchitecturespec.entries.at("nbrOfBankGroups"),
memSpec.memarchitecturespec.entries.at("nbrOfBanks") *
memSpec.memarchitecturespec.entries.at("nbrOfRanks"),
memSpec.memarchitecturespec.entries.at("nbrOfBankGroups") *
memSpec.memarchitecturespec.entries.at("nbrOfRanks"),
memSpec.memarchitecturespec.entries.at("nbrOfDevices")),
dimmRanksPerChannel(memSpec.memarchitecturespec.entries.at("nbrOfDIMMRanks")),
physicalRanksPerDimmRank(memSpec.memarchitecturespec.entries.at("nbrOfPhysicalRanks")),
memSpec.memarchitecturespec.nbrOfChannels,
memSpec.memarchitecturespec.nbrOfRanks,
memSpec.memarchitecturespec.nbrOfBanks,
memSpec.memarchitecturespec.nbrOfBankGroups,
memSpec.memarchitecturespec.nbrOfBanks /
memSpec.memarchitecturespec.nbrOfBankGroups,
memSpec.memarchitecturespec.nbrOfBanks *
memSpec.memarchitecturespec.nbrOfRanks,
memSpec.memarchitecturespec.nbrOfBankGroups *
memSpec.memarchitecturespec.nbrOfRanks,
memSpec.memarchitecturespec.nbrOfDevices),
memSpec(memSpec),
dimmRanksPerChannel(memSpec.memarchitecturespec.nbrOfDIMMRanks),
physicalRanksPerDimmRank(memSpec.memarchitecturespec.nbrOfPhysicalRanks),
physicalRanksPerChannel(physicalRanksPerDimmRank * dimmRanksPerChannel),
logicalRanksPerPhysicalRank(memSpec.memarchitecturespec.entries.at("nbrOfLogicalRanks")),
logicalRanksPerPhysicalRank(memSpec.memarchitecturespec.nbrOfLogicalRanks),
logicalRanksPerChannel(logicalRanksPerPhysicalRank * physicalRanksPerChannel),
cmdMode(memSpec.memarchitecturespec.entries.at("cmdMode")),
refMode(memSpec.memarchitecturespec.entries.at("refMode")),
RAAIMT(memSpec.memarchitecturespec.entries.at("RAAIMT")),
RAAMMT(memSpec.memarchitecturespec.entries.at("RAAMMT")),
RAADEC(memSpec.memarchitecturespec.entries.at("RAADEC")),
tRCD(tCK * memSpec.memtimingspec.entries.at("RCD")),
tPPD(tCK * memSpec.memtimingspec.entries.at("PPD")),
tRP(tCK * memSpec.memtimingspec.entries.at("RP")),
tRAS(tCK * memSpec.memtimingspec.entries.at("RAS")),
cmdMode(memSpec.memarchitecturespec.cmdMode),
RefMode(memSpec.memarchitecturespec.RefMode),
RAAIMT(memSpec.memarchitecturespec.RAAIMT),
RAAMMT(memSpec.memarchitecturespec.RAAMMT),
RAADEC(memSpec.memarchitecturespec.RAADEC),
tRCD(tCK * memSpec.memtimingspec.RCD),
tPPD(tCK * memSpec.memtimingspec.PPD),
tRP(tCK * memSpec.memtimingspec.RP),
tRAS(tCK * memSpec.memtimingspec.RAS),
tRC(tRAS + tRP),
tRL(tCK * memSpec.memtimingspec.entries.at("RL")),
tRTP(tCK * memSpec.memtimingspec.entries.at("RTP")),
tRPRE(tCK * memSpec.memtimingspec.entries.at("RPRE")),
tRPST(tCK * memSpec.memtimingspec.entries.at("RPST")),
tRDDQS(tCK * memSpec.memtimingspec.entries.at("RDDQS")),
tWL(tCK * memSpec.memtimingspec.entries.at("WL")),
tWPRE(tCK * memSpec.memtimingspec.entries.at("WPRE")),
tWPST(tCK * memSpec.memtimingspec.entries.at("WPST")),
tWR(tCK * memSpec.memtimingspec.entries.at("WR")),
tCCD_L_slr(tCK * memSpec.memtimingspec.entries.at("CCD_L_slr")),
tCCD_L_WR_slr(tCK * memSpec.memtimingspec.entries.at("CCD_L_WR_slr")),
tCCD_L_WR2_slr(tCK * memSpec.memtimingspec.entries.at("CCD_L_WR2_slr")),
tCCD_M_slr(tCK * memSpec.memtimingspec.entries.at("CCD_M_slr")),
tCCD_M_WR_slr(tCK * memSpec.memtimingspec.entries.at("CCD_M_WR_slr")),
tCCD_S_slr(tCK * memSpec.memtimingspec.entries.at("CCD_S_slr")),
tCCD_S_WR_slr(tCK * memSpec.memtimingspec.entries.at("CCD_S_WR_slr")),
tCCD_dlr(tCK * memSpec.memtimingspec.entries.at("CCD_dlr")),
tCCD_WR_dlr(tCK * memSpec.memtimingspec.entries.at("CCD_WR_dlr")),
tCCD_WR_dpr(tCK * memSpec.memtimingspec.entries.at("CCD_WR_dpr")),
tRRD_L_slr(tCK * memSpec.memtimingspec.entries.at("RRD_L_slr")),
tRRD_S_slr(tCK * memSpec.memtimingspec.entries.at("RRD_S_slr")),
tRRD_dlr(tCK * memSpec.memtimingspec.entries.at("RRD_dlr")),
tFAW_slr(tCK * memSpec.memtimingspec.entries.at("FAW_slr")),
tFAW_dlr(tCK * memSpec.memtimingspec.entries.at("FAW_dlr")),
tWTR_L(tCK * memSpec.memtimingspec.entries.at("WTR_L")),
tWTR_M(tCK * memSpec.memtimingspec.entries.at("WTR_M")),
tWTR_S(tCK * memSpec.memtimingspec.entries.at("WTR_S")),
tRFC_slr((refMode == 1) ? tCK * memSpec.memtimingspec.entries.at("RFC1_slr")
: tCK * memSpec.memtimingspec.entries.at("RFC2_slr")),
tRFC_dlr((refMode == 1) ? tCK * memSpec.memtimingspec.entries.at("RFC1_dlr")
: tCK * memSpec.memtimingspec.entries.at("RFC2_dlr")),
tRFC_dpr((refMode == 1) ? tCK * memSpec.memtimingspec.entries.at("RFC1_dpr")
: tCK * memSpec.memtimingspec.entries.at("RFC2_dpr")),
tRFCsb_slr(tCK * memSpec.memtimingspec.entries.at("RFCsb_slr")),
tRFCsb_dlr(tCK * memSpec.memtimingspec.entries.at("RFCsb_dlr")),
tREFI((refMode == 1) ? tCK * memSpec.memtimingspec.entries.at("REFI1")
: tCK * memSpec.memtimingspec.entries.at("REFI2")),
tREFIsb(tCK * memSpec.memtimingspec.entries.at("REFISB")),
tREFSBRD_slr(tCK * memSpec.memtimingspec.entries.at("REFSBRD_slr")),
tREFSBRD_dlr(tCK * memSpec.memtimingspec.entries.at("REFSBRD_dlr")),
tRTRS(tCK * memSpec.memtimingspec.entries.at("RTRS")),
tCPDED(tCK * memSpec.memtimingspec.entries.at("CPDED")),
tPD(tCK * memSpec.memtimingspec.entries.at("PD")),
tXP(tCK * memSpec.memtimingspec.entries.at("XP")),
tACTPDEN(tCK * memSpec.memtimingspec.entries.at("ACTPDEN")),
tPRPDEN(tCK * memSpec.memtimingspec.entries.at("PRPDEN")),
tREFPDEN(tCK * memSpec.memtimingspec.entries.at("REFPDEN")),
tRL(tCK * memSpec.memtimingspec.RL),
tRTP(tCK * memSpec.memtimingspec.RTP),
tRPRE(tCK * memSpec.memtimingspec.RPRE),
tRPST(tCK * memSpec.memtimingspec.RPST),
tRDDQS(tCK * memSpec.memtimingspec.RDDQS),
tWL(tCK * memSpec.memtimingspec.WL),
tWPRE(tCK * memSpec.memtimingspec.WPRE),
tWPST(tCK * memSpec.memtimingspec.WPST),
tWR(tCK * memSpec.memtimingspec.WR),
tCCD_L_slr(tCK * memSpec.memtimingspec.CCD_L_slr),
tCCD_L_WR_slr(tCK * memSpec.memtimingspec.CCD_L_WR_slr),
tCCD_L_WR2_slr(tCK * memSpec.memtimingspec.CCD_L_WR2_slr),
tCCD_M_slr(tCK * memSpec.memtimingspec.CCD_M_slr),
tCCD_M_WR_slr(tCK * memSpec.memtimingspec.CCD_M_WR_slr),
tCCD_S_slr(tCK * memSpec.memtimingspec.CCD_S_slr),
tCCD_S_WR_slr(tCK * memSpec.memtimingspec.CCD_S_WR_slr),
tCCD_dlr(tCK * memSpec.memtimingspec.CCD_dlr),
tCCD_WR_dlr(tCK * memSpec.memtimingspec.CCD_WR_dlr),
tCCD_WR_dpr(tCK * memSpec.memtimingspec.CCD_WR_dpr),
tRRD_L_slr(tCK * memSpec.memtimingspec.RRD_L_slr),
tRRD_S_slr(tCK * memSpec.memtimingspec.RRD_S_slr),
tRRD_dlr(tCK * memSpec.memtimingspec.RRD_dlr),
tFAW_slr(tCK * memSpec.memtimingspec.FAW_slr),
tFAW_dlr(tCK * memSpec.memtimingspec.FAW_dlr),
tWTR_L(tCK * memSpec.memtimingspec.WTR_L),
tWTR_M(tCK * memSpec.memtimingspec.WTR_M),
tWTR_S(tCK * memSpec.memtimingspec.WTR_S),
tRFC_slr((RefMode == DRAMUtils::MemSpec::RefModeTypeDDR5::REF_MODE_2) ?
tCK * memSpec.memtimingspec.RFC2_slr
// DRAMUtils::MemSpec::RefModeTypeDDR5::REF_MODE_1 || DRAMUtils::MemSpec::RefModeTypeDDR5::INVALID
: tCK * memSpec.memtimingspec.RFC1_slr),
tRFC_dlr((RefMode == DRAMUtils::MemSpec::RefModeTypeDDR5::REF_MODE_2) ?
tCK * memSpec.memtimingspec.RFC2_dlr
// DRAMUtils::MemSpec::RefModeTypeDDR5::REF_MODE_1 || DRAMUtils::MemSpec::RefModeTypeDDR5::INVALID
: tCK * memSpec.memtimingspec.RFC1_dlr),
tRFC_dpr((RefMode == DRAMUtils::MemSpec::RefModeTypeDDR5::REF_MODE_2) ?
tCK * memSpec.memtimingspec.RFC2_dpr
// DRAMUtils::MemSpec::RefModeTypeDDR5::REF_MODE_1 || DRAMUtils::MemSpec::RefModeTypeDDR5::INVALID
: tCK * memSpec.memtimingspec.RFC1_dpr),
tRFCsb_slr(tCK * memSpec.memtimingspec.RFCsb_slr),
tRFCsb_dlr(tCK * memSpec.memtimingspec.RFCsb_dlr),
tREFI((RefMode == DRAMUtils::MemSpec::RefModeTypeDDR5::REF_MODE_2) ?
tCK * memSpec.memtimingspec.REFI2
// DRAMUtils::MemSpec::RefModeTypeDDR5::REF_MODE_1 || DRAMUtils::MemSpec::RefModeTypeDDR5::INVALID
: tCK * memSpec.memtimingspec.REFI1),
tREFIsb(tCK * memSpec.memtimingspec.REFISB),
tREFSBRD_slr(tCK * memSpec.memtimingspec.REFSBRD_slr),
tREFSBRD_dlr(tCK * memSpec.memtimingspec.REFSBRD_dlr),
tRTRS(tCK * memSpec.memtimingspec.RTRS),
tCPDED(tCK * memSpec.memtimingspec.CPDED),
tPD(tCK * memSpec.memtimingspec.PD),
tXP(tCK * memSpec.memtimingspec.XP),
tACTPDEN(tCK * memSpec.memtimingspec.ACTPDEN),
tPRPDEN(tCK * memSpec.memtimingspec.PRPDEN),
tREFPDEN(tCK * memSpec.memtimingspec.REFPDEN),
shortCmdOffset(cmdMode == 2 ? 1 * tCK : 0 * tCK),
longCmdOffset(cmdMode == 2 ? 3 * tCK : 1 * tCK),
tBURST16(tCK * 8),
@@ -134,7 +144,7 @@ MemSpecDDR5::MemSpecDDR5(const Config::MemSpec& memSpec) :
else
SC_REPORT_FATAL("MemSpecDDR5", "Invalid command mode!");
if (!(refMode == 1 || refMode == 2))
if (DRAMUtils::MemSpec::RefModeTypeDDR5::INVALID == RefMode)
SC_REPORT_FATAL("MemSpecDDR5",
"Invalid refresh mode! "
"Set 1 for normal or 2 for fine granularity refresh mode.");
@@ -268,4 +278,11 @@ bool MemSpecDDR5::requiresMaskedWrite(const tlm::tlm_generic_payload& payload) c
return !allBytesEnabled(payload);
}
#ifdef DRAMPOWER
std::unique_ptr<DRAMPower::dram_base<DRAMPower::CmdType>> MemSpecDDR5::toDramPowerObject() const
{
return std::make_unique<DRAMPower::DDR5>(std::move(DRAMPower::MemSpecDDR5(memSpec)));
}
#endif
} // namespace DRAMSys

19
extensions/standards/DDR5/DRAMSys/configuration/memspec/MemSpecDDR5.h
View File

@@ -4,12 +4,21 @@
* Authors:
* Lukas Steiner
* Derek Christ
* Marco Mörz
*/
#ifndef MEMSPECDDR5_H
#define MEMSPECDDR5_H
#include <DRAMSys/configuration/memspec/MemSpec.h>
#include <DRAMUtils/memspec/standards/MemSpecDDR5.h>
#ifdef DRAMPOWER
#include <DRAMPower/standards/ddr5/DDR5.h>
#include <DRAMPower/memspec/MemSpecDDR5.h>
#endif
#include <systemc>
namespace DRAMSys
@@ -18,15 +27,16 @@ namespace DRAMSys
class MemSpecDDR5 final : public MemSpec
{
public:
explicit MemSpecDDR5(const Config::MemSpec& memSpec);
explicit MemSpecDDR5(const DRAMUtils::MemSpec::MemSpecDDR5& memSpec);
const DRAMUtils::MemSpec::MemSpecDDR5& memSpec;
const unsigned dimmRanksPerChannel;
const unsigned physicalRanksPerDimmRank;
const unsigned physicalRanksPerChannel;
const unsigned logicalRanksPerPhysicalRank;
const unsigned logicalRanksPerChannel;
const unsigned cmdMode;
const unsigned refMode;
DRAMUtils::MemSpec::RefModeTypeDDR5 RefMode;
const unsigned RAAIMT;
const unsigned RAAMMT;
const unsigned RAADEC;
@@ -105,6 +115,11 @@ public:
const tlm::tlm_generic_payload& payload) const override;
[[nodiscard]] bool requiresMaskedWrite(const tlm::tlm_generic_payload& payload) const override;
#ifdef DRAMPOWER
[[nodiscard]] std::unique_ptr<DRAMPower::dram_base<DRAMPower::CmdType>> toDramPowerObject() const override;
#endif
};
} // namespace DRAMSys

90
extensions/standards/HBM3/DRAMSys/configuration/memspec/MemSpecHBM3.cpp
View File

@@ -4,6 +4,7 @@
* Authors:
* Lukas Steiner
* Derek Christ
* Marco Mörz
*/
#include <iostream>
@@ -17,54 +18,53 @@ using namespace tlm;
namespace DRAMSys
{
MemSpecHBM3::MemSpecHBM3(const Config::MemSpec& memSpec) :
MemSpecHBM3::MemSpecHBM3(const DRAMUtils::MemSpec::MemSpecHBM3& memSpec) :
MemSpec(memSpec,
memSpec.memarchitecturespec.entries.at("nbrOfChannels"),
memSpec.memarchitecturespec.entries.at("nbrOfPseudoChannels"),
memSpec.memarchitecturespec.entries.at("nbrOfBanks"),
memSpec.memarchitecturespec.entries.at("nbrOfBankGroups"),
memSpec.memarchitecturespec.entries.at("nbrOfBanks") /
memSpec.memarchitecturespec.entries.at("nbrOfBankGroups"),
memSpec.memarchitecturespec.entries.at("nbrOfBanks") *
memSpec.memarchitecturespec.entries.at("nbrOfPseudoChannels"),
memSpec.memarchitecturespec.entries.at("nbrOfBankGroups") *
memSpec.memarchitecturespec.entries.at("nbrOfPseudoChannels"),
memSpec.memarchitecturespec.entries.at("nbrOfDevices")),
stacksPerChannel(memSpec.memarchitecturespec.entries.at("nbrOfStacks")),
RAAIMT(memSpec.memarchitecturespec.entries.at("RAAIMT")),
RAAMMT(memSpec.memarchitecturespec.entries.at("RAAMMT")),
RAADEC(memSpec.memarchitecturespec.entries.at("RAADEC")),
tDQSCK(tCK * memSpec.memtimingspec.entries.at("DQSCK")),
tRC(tCK * memSpec.memtimingspec.entries.at("RC")),
tRAS(tCK * memSpec.memtimingspec.entries.at("RAS")),
tRCDRD(tCK * memSpec.memtimingspec.entries.at("RCDRD")),
tRCDWR(tCK * memSpec.memtimingspec.entries.at("RCDWR")),
tRRDL(tCK * memSpec.memtimingspec.entries.at("RRDL")),
tRRDS(tCK * memSpec.memtimingspec.entries.at("RRDS")),
tFAW(tCK * memSpec.memtimingspec.entries.at("FAW")),
tRTP(tCK * memSpec.memtimingspec.entries.at("RTP")),
tRP(tCK * memSpec.memtimingspec.entries.at("RP")),
tRL(tCK * memSpec.memtimingspec.entries.at("RL")),
tWL(tCK * memSpec.memtimingspec.entries.at("WL")),
tPL(tCK * memSpec.memtimingspec.entries.at("PL")),
tWR(tCK * memSpec.memtimingspec.entries.at("WR")),
tCCDL(tCK * memSpec.memtimingspec.entries.at("CCDL")),
tCCDS(tCK * memSpec.memtimingspec.entries.at("CCDS")),
tCCDR(tCK * memSpec.memtimingspec.entries.at("CCDR")),
tWTRL(tCK * memSpec.memtimingspec.entries.at("WTRL")),
tWTRS(tCK * memSpec.memtimingspec.entries.at("WTRS")),
tRTW(tCK * memSpec.memtimingspec.entries.at("RTW")),
tXP(tCK * memSpec.memtimingspec.entries.at("XP")),
tCKE(tCK * memSpec.memtimingspec.entries.at("CKE")),
memSpec.memarchitecturespec.nbrOfChannels,
memSpec.memarchitecturespec.nbrOfPseudoChannels,
memSpec.memarchitecturespec.nbrOfBanks,
memSpec.memarchitecturespec.nbrOfBankGroups,
memSpec.memarchitecturespec.nbrOfBanks /
memSpec.memarchitecturespec.nbrOfBankGroups,
memSpec.memarchitecturespec.nbrOfBanks *
memSpec.memarchitecturespec.nbrOfPseudoChannels,
memSpec.memarchitecturespec.nbrOfBankGroups *
memSpec.memarchitecturespec.nbrOfPseudoChannels,
memSpec.memarchitecturespec.nbrOfDevices),
stacksPerChannel(memSpec.memarchitecturespec.nbrOfStacks),
RAAIMT(memSpec.memarchitecturespec.RAAIMT),
RAAMMT(memSpec.memarchitecturespec.RAAMMT),
RAADEC(memSpec.memarchitecturespec.RAADEC),
tDQSCK(tCK * memSpec.memtimingspec.DQSCK),
tRC(tCK * memSpec.memtimingspec.RC),
tRAS(tCK * memSpec.memtimingspec.RAS),
tRCDRD(tCK * memSpec.memtimingspec.RCDRD),
tRCDWR(tCK * memSpec.memtimingspec.RCDWR),
tRRDL(tCK * memSpec.memtimingspec.RRDL),
tRRDS(tCK * memSpec.memtimingspec.RRDS),
tFAW(tCK * memSpec.memtimingspec.FAW),
tRTP(tCK * memSpec.memtimingspec.RTP),
tRP(tCK * memSpec.memtimingspec.RP),
tRL(tCK * memSpec.memtimingspec.RL),
tWL(tCK * memSpec.memtimingspec.WL),
tPL(tCK * memSpec.memtimingspec.PL),
tWR(tCK * memSpec.memtimingspec.WR),
tCCDL(tCK * memSpec.memtimingspec.CCDL),
tCCDS(tCK * memSpec.memtimingspec.CCDS),
tWTRL(tCK * memSpec.memtimingspec.WTRL),
tWTRS(tCK * memSpec.memtimingspec.WTRS),
tRTW(tCK * memSpec.memtimingspec.RTW),
tXP(tCK * memSpec.memtimingspec.XP),
tCKE(tCK * memSpec.memtimingspec.CKE),
tPD(tCKE),
tCKESR(tCKE + tCK),
tXS(tCK * memSpec.memtimingspec.entries.at("XS")),
tRFC(tCK * memSpec.memtimingspec.entries.at("RFC")),
tRFCPB(tCK * memSpec.memtimingspec.entries.at("RFCPB")),
tRREFD(tCK * memSpec.memtimingspec.entries.at("RREFD")),
tREFI(tCK * memSpec.memtimingspec.entries.at("REFI")),
tREFIPB(tCK * memSpec.memtimingspec.entries.at("REFIPB")),
tPPD(tCK * memSpec.memtimingspec.entries.at("PPD"))
tXS(tCK * memSpec.memtimingspec.XS),
tRFC(tCK * memSpec.memtimingspec.RFC),
tRFCPB(tCK * memSpec.memtimingspec.RFCPB),
tRREFD(tCK * memSpec.memtimingspec.RREFD),
tREFI(tCK * memSpec.memtimingspec.REFI),
tREFIPB(tCK * memSpec.memtimingspec.REFIPB),
tPPD(tCK * memSpec.memtimingspec.PPD)
{
commandLengthInCycles[Command::ACT] = 1.5;
commandLengthInCycles[Command::PREPB] = 0.5;

6
extensions/standards/HBM3/DRAMSys/configuration/memspec/MemSpecHBM3.h
View File

@@ -4,12 +4,16 @@
* Authors:
* Lukas Steiner
* Derek Christ
* Marco Mörz
*/
#ifndef MemSpecHBM3_H
#define MemSpecHBM3_H
#include <DRAMSys/configuration/memspec/MemSpec.h>
#include <DRAMUtils/memspec/standards/MemSpecHBM3.h>
#include <systemc>
namespace DRAMSys
@@ -18,7 +22,7 @@ namespace DRAMSys
class MemSpecHBM3 final : public MemSpec
{
public:
explicit MemSpecHBM3(const Config::MemSpec& memSpec);
explicit MemSpecHBM3(const DRAMUtils::MemSpec::MemSpecHBM3& memSpec);
const unsigned stacksPerChannel;

99
extensions/standards/LPDDR5/DRAMSys/configuration/memspec/MemSpecLPDDR5.cpp
View File

@@ -31,57 +31,55 @@
*
* Authors:
* Lukas Steiner
* Derek Christ
* Marco Mörz
*/
#include "MemSpecLPDDR5.h"
#include <DRAMSys/common/utils.h>
#include <iostream>
using namespace sc_core;
using namespace tlm;
namespace DRAMSys
{
MemSpecLPDDR5::MemSpecLPDDR5(const Config::MemSpec& memSpec) :
MemSpecLPDDR5::MemSpecLPDDR5(const DRAMUtils::MemSpec::MemSpecLPDDR5& memSpec) :
MemSpec(memSpec,
memSpec.memarchitecturespec.entries.at("nbrOfChannels"),
memSpec.memarchitecturespec.entries.at("nbrOfRanks"),
memSpec.memarchitecturespec.entries.at("nbrOfBanks"),
memSpec.memarchitecturespec.entries.at("nbrOfBankGroups"),
memSpec.memarchitecturespec.entries.at("nbrOfBanks") /
memSpec.memarchitecturespec.entries.at("nbrOfBankGroups"),
memSpec.memarchitecturespec.entries.at("nbrOfBanks") *
memSpec.memarchitecturespec.entries.at("nbrOfRanks"),
memSpec.memarchitecturespec.entries.at("nbrOfBankGroups") *
memSpec.memarchitecturespec.entries.at("nbrOfRanks"),
memSpec.memarchitecturespec.entries.at("nbrOfDevices")),
tREFI(tCK * memSpec.memtimingspec.entries.at("REFI")),
tREFIpb(tCK * memSpec.memtimingspec.entries.at("REFIpb")),
tRFCab(tCK * memSpec.memtimingspec.entries.at("RFCab")),
tRFCpb(tCK * memSpec.memtimingspec.entries.at("RFCpb")),
tRAS(tCK * memSpec.memtimingspec.entries.at("RAS")),
tRPab(tCK * memSpec.memtimingspec.entries.at("RPab")),
tRPpb(tCK * memSpec.memtimingspec.entries.at("RPpb")),
tRCpb(tCK * memSpec.memtimingspec.entries.at("RCpb")),
tRCab(tCK * memSpec.memtimingspec.entries.at("RCab")),
tPPD(tCK * memSpec.memtimingspec.entries.at("PPD")),
tRCD_L(tCK * memSpec.memtimingspec.entries.at("RCD_L")),
tRCD_S(tCK * memSpec.memtimingspec.entries.at("RCD_S")),
tFAW(tCK * memSpec.memtimingspec.entries.at("FAW")),
tRRD(tCK * memSpec.memtimingspec.entries.at("RRD")),
tRL(tCK * memSpec.memtimingspec.entries.at("RL")),
memSpec.memarchitecturespec.nbrOfChannels,
memSpec.memarchitecturespec.nbrOfRanks,
memSpec.memarchitecturespec.nbrOfBanks,
memSpec.memarchitecturespec.nbrOfBankGroups,
memSpec.memarchitecturespec.nbrOfBanks / memSpec.memarchitecturespec.nbrOfBankGroups,
memSpec.memarchitecturespec.nbrOfBanks * memSpec.memarchitecturespec.nbrOfRanks,
memSpec.memarchitecturespec.nbrOfBankGroups * memSpec.memarchitecturespec.nbrOfRanks,
memSpec.memarchitecturespec.nbrOfDevices),
memSpec(memSpec),
tREFI(tCK * memSpec.memtimingspec.REFI),
tREFIpb(tCK * memSpec.memtimingspec.REFIpb),
tRFCab(tCK * memSpec.memtimingspec.RFCab),
tRFCpb(tCK * memSpec.memtimingspec.RFCpb),
tRAS(tCK * memSpec.memtimingspec.RAS),
tRPab(tCK * memSpec.memtimingspec.RPab),
tRPpb(tCK * memSpec.memtimingspec.RPpb),
tRCpb(tCK * memSpec.memtimingspec.RCpb),
tRCab(tCK * memSpec.memtimingspec.RCab),
tPPD(tCK * memSpec.memtimingspec.PPD),
tRCD_L(tCK * memSpec.memtimingspec.RCD_L),
tRCD_S(tCK * memSpec.memtimingspec.RCD_S),
tFAW(tCK * memSpec.memtimingspec.FAW),
tRRD(tCK * memSpec.memtimingspec.RRD),
tRL(tCK * memSpec.memtimingspec.RL),
// tCCD (tCK * parseUint(memspec["memtimingspec"], "CCD")),
tRBTP(tCK * memSpec.memtimingspec.entries.at("RBTP")),
tRBTP(tCK * memSpec.memtimingspec.RBTP),
// tRPST (tCK * parseUint(memspec["memtimingspec"], "RPST")),
// tDQSCK (tCK * parseUint(memspec["memtimingspec"], "DQSCK")),
tWL(tCK * memSpec.memtimingspec.entries.at("WL")),
tWR(tCK * memSpec.memtimingspec.entries.at("WR")),
tWL(tCK * memSpec.memtimingspec.WL),
tWR(tCK * memSpec.memtimingspec.WR),
// tDQSS (tCK * parseUint(memspec["memtimingspec"], "DQSS")),
// tDQS2DQ (tCK * parseUint(memspec["memtimingspec"], "DQS2DQ")),
tRTRS(tCK * memSpec.memtimingspec.entries.at("RTRS")),
tRTRS(tCK * memSpec.memtimingspec.RTRS),
// tWPRE (tCK * parseUint(memspec["memtimingspec"], "WPRE")),
// tWTR (tCK * parseUint(memspec["memtimingspec"], "WTR")),
// tXP (tCK * parseUint(memspec["memtimingspec"] "XP")),
@@ -90,24 +88,24 @@ MemSpecLPDDR5::MemSpecLPDDR5(const Config::MemSpec& memSpec) :
// tESCKE (tCK * parseUint(memspec["memtimingspec"], "ESCKE")),
// tCKE (tCK * parseUint(memspec["memtimingspec"], "CKE")),
// tCMDCKE (tCK * parseUint(memspec["memtimingspec"], "CMDCKE")),
BL_n_min_16(tCK * memSpec.memtimingspec.entries.at("BL_n_min_16")),
BL_n_max_16(tCK * memSpec.memtimingspec.entries.at("BL_n_max_16")),
BL_n_L_16(tCK * memSpec.memtimingspec.entries.at("BL_n_L_16")),
BL_n_S_16(tCK * memSpec.memtimingspec.entries.at("BL_n_S_16")),
BL_n_min_32(tCK * memSpec.memtimingspec.entries.at("BL_n_min_32")),
BL_n_max_32(tCK * memSpec.memtimingspec.entries.at("BL_n_max_32")),
BL_n_L_32(tCK * memSpec.memtimingspec.entries.at("BL_n_L_32")),
BL_n_S_32(tCK * memSpec.memtimingspec.entries.at("BL_n_S_32")),
tWTR_L(tCK * memSpec.memtimingspec.entries.at("WTR_L")),
tWTR_S(tCK * memSpec.memtimingspec.entries.at("WTR_S")),
tWCK2DQO(tCK * memSpec.memtimingspec.entries.at("WCK2DQO")),
tpbR2act(tCK * memSpec.memtimingspec.entries.at("pbR2act")),
tpbR2pbR(tCK * memSpec.memtimingspec.entries.at("pbR2pbR")),
BL_n_min_16(tCK * memSpec.memtimingspec.BL_n_min_16),
BL_n_max_16(tCK * memSpec.memtimingspec.BL_n_max_16),
BL_n_L_16(tCK * memSpec.memtimingspec.BL_n_L_16),
BL_n_S_16(tCK * memSpec.memtimingspec.BL_n_S_16),
BL_n_min_32(tCK * memSpec.memtimingspec.BL_n_min_32),
BL_n_max_32(tCK * memSpec.memtimingspec.BL_n_max_32),
BL_n_L_32(tCK * memSpec.memtimingspec.BL_n_L_32),
BL_n_S_32(tCK * memSpec.memtimingspec.BL_n_S_32),
tWTR_L(tCK * memSpec.memtimingspec.WTR_L),
tWTR_S(tCK * memSpec.memtimingspec.WTR_S),
tWCK2DQO(tCK * memSpec.memtimingspec.WCK2DQO),
tpbR2act(tCK * memSpec.memtimingspec.pbR2act),
tpbR2pbR(tCK * memSpec.memtimingspec.pbR2pbR),
tBURST16(tCK * 16 / dataRate),
tBURST32(tCK * 32 / dataRate),
bankMode(groupsPerRank != 1 ? BankMode::MBG
: (banksPerRank == 16 ? BankMode::M16B : BankMode::M8B)),
per2BankOffset(memSpec.memarchitecturespec.entries.at("per2BankOffset"))
per2BankOffset(memSpec.memarchitecturespec.per2BankOffset)
{
commandLengthInCycles[Command::ACT] = 2;
@@ -257,4 +255,11 @@ bool MemSpecLPDDR5::requiresMaskedWrite(const tlm::tlm_generic_payload& payload)
return !allBytesEnabled(payload);
}
#ifdef DRAMPOWER
std::unique_ptr<DRAMPower::dram_base<DRAMPower::CmdType>> MemSpecLPDDR5::toDramPowerObject() const
{
return std::make_unique<DRAMPower::LPDDR5>(std::move(DRAMPower::MemSpecLPDDR5(memSpec)));
}
#endif
} // namespace DRAMSys

19
extensions/standards/LPDDR5/DRAMSys/configuration/memspec/MemSpecLPDDR5.h
View File

@@ -31,12 +31,23 @@
*
* Authors:
* Lukas Steiner
* Derek Christ
* Marco Mörz
*/
#ifndef MEMSPECLPDDR5_H
#define MEMSPECLPDDR5_H
#include <DRAMSys/configuration/memspec/MemSpec.h>
#include <DRAMUtils/memspec/standards/MemSpecLPDDR5.h>
#ifdef DRAMPOWER
#include <DRAMPower/memspec/MemSpecLPDDR5.h>
#include <DRAMPower/standards/lpddr5/LPDDR5.h>
#endif
#include <systemc>
namespace DRAMSys
@@ -45,9 +56,10 @@ namespace DRAMSys
class MemSpecLPDDR5 final : public MemSpec
{
public:
explicit MemSpecLPDDR5(const Config::MemSpec& memSpec);
explicit MemSpecLPDDR5(const DRAMUtils::MemSpec::MemSpecLPDDR5& memSpec);
// Memspec Variables:
const DRAMUtils::MemSpec::MemSpecLPDDR5& memSpec;
const sc_core::sc_time tREFI;
const sc_core::sc_time tREFIpb;
const sc_core::sc_time tRFCab;
@@ -122,6 +134,11 @@ public:
[[nodiscard]] bool requiresMaskedWrite(const tlm::tlm_generic_payload& payload) const override;
#ifdef DRAMPOWER
[[nodiscard]] std::unique_ptr<DRAMPower::dram_base<DRAMPower::CmdType>>
toDramPowerObject() const override;
#endif
private:
unsigned per2BankOffset;
};