Add hack in TimingCheckers to convert MWR to WR in insertion stage

extensions/standards/DDR5/DRAMSys/configuration/memspec/MemSpecDDR5.cpp

@@ -281,7 +281,13 @@ TimeInterval MemSpecDDR5::getIntervalOnDataStrobe(Command command, const tlm_gen
 
 bool MemSpecDDR5::requiresReadModifyWrite(const tlm::tlm_generic_payload& payload) const
 {
-    assert(false); // TODO
+    // auto burstLength = ControllerExtension::getBurstLength(payload);
+
+    // if (burstLength == 16 && bitWidth == 4)
+    //     return true;
+
+    // assert(false); // TODO
+
     return payload.get_byte_enable_ptr() != nullptr;
 }
 

extensions/standards/DDR5/DRAMSys/controller/checker/CheckerDDR5.cpp

@@ -950,6 +950,12 @@ void CheckerDDR5::insert(Command command, const tlm_generic_payload& payload)
             + static_cast<std::size_t>(bank) % memSpec->banksPerGroup);
     unsigned burstLength = ControllerExtension::getBurstLength(payload);
 
+    // Hack: Convert MWR to WR and MWRA to WRA
+    if (command == Command::MWR)
+        command = Command::WR;
+    else if (command == Command::MWRA)
+        command = Command::WRA;
+
     PRINTDEBUGMESSAGE("CheckerDDR5", "Changing state on bank " + std::to_string(static_cast<std::size_t>(bank))
                       + " command is " + command.toString());
 

extensions/standards/HBM3/DRAMSys/controller/checker/CheckerHBM3.cpp

@@ -733,6 +733,12 @@ void CheckerHBM3::insert(Command command, const tlm_generic_payload &payload)
     BankGroup bankGroup = ControllerExtension::getBankGroup(payload);
     Bank bank = ControllerExtension::getBank(payload);
 
+    // Hack: Convert MWR to WR and MWRA to WRA
+    if (command == Command::MWR)
+        command = Command::WR;
+    else if (command == Command::MWRA)
+        command = Command::WRA;
+
     PRINTDEBUGMESSAGE("CheckerHBM3", "Changing state on bank " + std::to_string(static_cast<std::size_t>(bank))
                       + " command is " + command.toString());
 

extensions/standards/LPDDR5/DRAMSys/configuration/memspec/MemSpecLPDDR5.cpp

@@ -250,7 +250,7 @@ TimeInterval MemSpecLPDDR5::getIntervalOnDataStrobe(Command command, const tlm_g
 
 bool MemSpecLPDDR5::requiresReadModifyWrite(const tlm::tlm_generic_payload& payload) const
 {
-    assert(false); // TODO
+    // assert(false); // TODO
     return payload.get_byte_enable_ptr() != nullptr;
 }
 

extensions/standards/LPDDR5/DRAMSys/controller/checker/CheckerLPDDR5.cpp

@@ -730,6 +730,12 @@ void CheckerLPDDR5::insert(Command command, const tlm_generic_payload& payload)
     Bank bank = ControllerExtension::getBank(payload);
     unsigned burstLength = ControllerExtension::getBurstLength(payload);
 
+    // Hack: Convert MWR to WR and MWRA to WRA
+    if (command == Command::MWR)
+        command = Command::WR;
+    else if (command == Command::MWRA)
+        command = Command::WRA;
+
     PRINTDEBUGMESSAGE("CheckerLPDDR5", "Changing state on bank " + std::to_string(static_cast<std::size_t>(bank))
                                        + " command is " + command.toString());
 

src/libdramsys/DRAMSys/controller/checker/CheckerDDR3.cpp

@@ -433,6 +433,12 @@ void CheckerDDR3::insert(Command command, const tlm_generic_payload& payload)
     Rank rank = ControllerExtension::getRank(payload);
     Bank bank = ControllerExtension::getBank(payload);
 
+    // Hack: Convert MWR to WR and MWRA to WRA
+    if (command == Command::MWR)
+        command = Command::WR;
+    else if (command == Command::MWRA)
+        command = Command::WRA;
+
     PRINTDEBUGMESSAGE("CheckerDDR3", "Changing state on bank " + std::to_string(static_cast<std::size_t>(bank))
                       + " command is " + command.toString());
 

src/libdramsys/DRAMSys/controller/checker/CheckerDDR4.cpp

@@ -467,6 +467,12 @@ void CheckerDDR4::insert(Command command, const tlm_generic_payload& payload)
     BankGroup bankGroup = ControllerExtension::getBankGroup(payload);
     Bank bank = ControllerExtension::getBank(payload);
 
+    // Hack: Convert MWR to WR and MWRA to WRA
+    if (command == Command::MWR)
+        command = Command::WR;
+    else if (command == Command::MWRA)
+        command = Command::WRA;
+
     PRINTDEBUGMESSAGE("CheckerDDR4", "Changing state on bank " + std::to_string(static_cast<std::size_t>(bank))
                       + " command is " + command.toString());
 

src/libdramsys/DRAMSys/controller/checker/CheckerGDDR5.cpp

@@ -53,7 +53,7 @@ CheckerGDDR5::CheckerGDDR5(const Configuration& config)
     lastScheduledByCommandAndBank = std::vector<ControllerVector<Bank, sc_time>>
             (Command::numberOfCommands(), ControllerVector<Bank, sc_time>(memSpec->banksPerChannel, scMaxTime));
     lastScheduledByCommandAndBankGroup = std::vector<ControllerVector<BankGroup, sc_time>>
-            (Command::numberOfCommands(), 
+            (Command::numberOfCommands(),
                     ControllerVector<BankGroup, sc_time>(memSpec->bankGroupsPerChannel, scMaxTime));
     lastScheduledByCommandAndRank = std::vector<ControllerVector<Rank, sc_time>>
             (Command::numberOfCommands(), ControllerVector<Rank, sc_time>(memSpec->ranksPerChannel, scMaxTime));
@@ -549,6 +549,12 @@ void CheckerGDDR5::insert(Command command, const tlm_generic_payload& payload)
     BankGroup bankGroup = ControllerExtension::getBankGroup(payload);
     Bank bank = ControllerExtension::getBank(payload);
 
+    // Hack: Convert MWR to WR and MWRA to WRA
+    if (command == Command::MWR)
+        command = Command::WR;
+    else if (command == Command::MWRA)
+        command = Command::WRA;
+
     PRINTDEBUGMESSAGE("CheckerGDDR5", "Changing state on bank " + std::to_string(static_cast<std::size_t>(bank))
                       + " command is " + command.toString());
 

src/libdramsys/DRAMSys/controller/checker/CheckerGDDR5X.cpp

@@ -53,7 +53,7 @@ CheckerGDDR5X::CheckerGDDR5X(const Configuration& config)
     lastScheduledByCommandAndBank = std::vector<ControllerVector<Bank, sc_time>>
             (Command::numberOfCommands(), ControllerVector<Bank, sc_time>(memSpec->banksPerChannel, scMaxTime));
     lastScheduledByCommandAndBankGroup = std::vector<ControllerVector<BankGroup, sc_time>>
-            (Command::numberOfCommands(), 
+            (Command::numberOfCommands(),
                     ControllerVector<BankGroup, sc_time>(memSpec->bankGroupsPerChannel, scMaxTime));
     lastScheduledByCommandAndRank = std::vector<ControllerVector<Rank, sc_time>>
             (Command::numberOfCommands(), ControllerVector<Rank, sc_time>(memSpec->ranksPerChannel, scMaxTime));
@@ -553,6 +553,12 @@ void CheckerGDDR5X::insert(Command command, const tlm_generic_payload& payload)
     BankGroup bankGroup = ControllerExtension::getBankGroup(payload);
     Bank bank = ControllerExtension::getBank(payload);
 
+    // Hack: Convert MWR to WR and MWRA to WRA
+    if (command == Command::MWR)
+        command = Command::WR;
+    else if (command == Command::MWRA)
+        command = Command::WRA;
+
     PRINTDEBUGMESSAGE("CheckerGDDR5X", "Changing state on bank " + std::to_string(static_cast<std::size_t>(bank))
                       + " command is " + command.toString());
 

src/libdramsys/DRAMSys/controller/checker/CheckerGDDR6.cpp

@@ -570,6 +570,12 @@ void CheckerGDDR6::insert(Command command, const tlm_generic_payload& payload)
     BankGroup bankGroup = ControllerExtension::getBankGroup(payload);
     Bank bank = ControllerExtension::getBank(payload);
 
+    // Hack: Convert MWR to WR and MWRA to WRA
+    if (command == Command::MWR)
+        command = Command::WR;
+    else if (command == Command::MWRA)
+        command = Command::WRA;
+
     PRINTDEBUGMESSAGE("CheckerGDDR6", "Changing state on bank " + std::to_string(static_cast<std::size_t>(bank))
                       + " command is " + command.toString());
 

src/libdramsys/DRAMSys/controller/checker/CheckerHBM2.cpp

@@ -502,6 +502,12 @@ void CheckerHBM2::insert(Command command, const tlm_generic_payload& payload)
     BankGroup bankGroup = ControllerExtension::getBankGroup(payload);
     Bank bank = ControllerExtension::getBank(payload);
 
+    // Hack: Convert MWR to WR and MWRA to WRA
+    if (command == Command::MWR)
+        command = Command::WR;
+    else if (command == Command::MWRA)
+        command = Command::WRA;
+
     PRINTDEBUGMESSAGE("CheckerHBM2", "Changing state on bank " + std::to_string(static_cast<std::size_t>(bank))
                       + " command is " + command.toString());
 

src/libdramsys/DRAMSys/controller/checker/CheckerLPDDR4.cpp

@@ -521,6 +521,12 @@ void CheckerLPDDR4::insert(Command command, const tlm_generic_payload& payload)
     Rank rank = ControllerExtension::getRank(payload);
     Bank bank = ControllerExtension::getBank(payload);
 
+    // Hack: Convert MWR to WR and MWRA to WRA
+    if (command == Command::MWR)
+        command = Command::WR;
+    else if (command == Command::MWRA)
+        command = Command::WRA;
+
     PRINTDEBUGMESSAGE("CheckerLPDDR4", "Changing state on bank " + std::to_string(static_cast<std::size_t>(bank))
                       + " command is " + command.toString());
 

src/libdramsys/DRAMSys/controller/checker/CheckerSTTMRAM.cpp

@@ -389,6 +389,12 @@ void CheckerSTTMRAM::insert(Command command, const tlm_generic_payload& payload)
     Rank rank = ControllerExtension::getRank(payload);
     Bank bank = ControllerExtension::getBank(payload);
 
+    // Hack: Convert MWR to WR and MWRA to WRA
+    if (command == Command::MWR)
+        command = Command::WR;
+    else if (command == Command::MWRA)
+        command = Command::WRA;
+
     PRINTDEBUGMESSAGE("CheckerSTTMRAM", "Changing state on bank " + std::to_string(static_cast<std::size_t>(bank))
                       + " command is " + command.toString());
 

src/libdramsys/DRAMSys/controller/checker/CheckerWideIO.cpp

@@ -410,6 +410,12 @@ void CheckerWideIO::insert(Command command, const tlm_generic_payload& payload)
     Rank rank = ControllerExtension::getRank(payload);
     Bank bank = ControllerExtension::getBank(payload);
 
+    // Hack: Convert MWR to WR and MWRA to WRA
+    if (command == Command::MWR)
+        command = Command::WR;
+    else if (command == Command::MWRA)
+        command = Command::WRA;
+
     PRINTDEBUGMESSAGE("CheckerWideIO", "Changing state on bank " + std::to_string(static_cast<std::size_t>(bank))
                       + " command is " + command.toString());
 

src/libdramsys/DRAMSys/controller/checker/CheckerWideIO2.cpp

@@ -488,6 +488,12 @@ void CheckerWideIO2::insert(Command command, const tlm_generic_payload& payload)
     Rank rank = ControllerExtension::getRank(payload);
     Bank bank = ControllerExtension::getBank(payload);
 
+    // Hack: Convert MWR to WR and MWRA to WRA
+    if (command == Command::MWR)
+        command = Command::WR;
+    else if (command == Command::MWRA)
+        command = Command::WRA;
+
     PRINTDEBUGMESSAGE("CheckerWideIO2", "Changing state on bank " + std::to_string(static_cast<std::size_t>(bank))
                       + " command is " + command.toString());