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Merge branch 'opensource_splitting' into 'development'

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Open source splitting simplifications

See merge request ems/astdm/dram.sys!253
This commit is contained in:
Lukas Steiner
2020-06-05 16:42:12 +02:00
parent 6d255af114 ca4bb46e10
commit 409556ef57
109 changed files with 1804 additions and 6414 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
DRAMSys/CMakeLists.txt
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@@ -43,7 +43,9 @@ set(DCMAKE_SH "CMAKE_SH-NOTFOUND" CACHE STRING "Ignore sh.exe error on Windows")
add_subdirectory(library)
# Add TraceAnalyzer:
add_subdirectory(traceAnalyzer)
if(EXISTS ${CMAKE_CURRENT_LIST_DIR}/library/src/simulation/DRAMSysRecordable.cpp)
add_subdirectory(traceAnalyzer)
endif()
# Add DRAMSysSimulator:
add_subdirectory(simulator)

BIN
DRAMSys/docs/Timings.ods
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9
DRAMSys/gem5/CMakeLists.txt
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@@ -41,6 +41,10 @@ set(DCMAKE_SH="CMAKE_SH-NOTFOUND")
find_library(GEM5_LIBRARY gem5_${GEM5_VARIANT} PATH $ENV{GEM5}/build/${GEM5_ARCH}/)
if(EXISTS ${CMAKE_CURRENT_LIST_DIR}/../library/src/simulation/DRAMSysRecordable.cpp)
add_definitions(-DRECORDING)
endif()
add_executable(DRAMSys_gem5
main.cpp
$ENV{GEM5}/util/systemc/sc_logger.cc
@@ -64,7 +68,6 @@ target_include_directories(DRAMSys_gem5
)
target_link_libraries(DRAMSys_gem5
${SYSTEMC_LIBRARY}
DRAMSysLibrary
${GEM5_LIBRARY}
PRIVATE DRAMSysLibrary
PRIVATE ${GEM5_LIBRARY}
)

4
DRAMSys/gem5/configs/configs.pri
View File

@@ -1,4 +0,0 @@
DISTFILES += dualElasticTraceReplay.ini
DISTFILES += nvdimmp.ini
DISTFILES += singleElasticTraceReplay.ini

70
DRAMSys/gem5/main.cpp
View File

@@ -41,25 +41,29 @@
#include <string>
#include <cstdlib>
#include "DRAMSys.h"
#include "TraceSetup.h"
#include "report_handler.hh"
#include "sc_target.hh"
#include "sim_control.hh"
#include "slave_transactor.hh"
#include "stats.hh"
using namespace std;
#include "DRAMSys.h"
#ifdef RECORDING
#include "DRAMSysRecordable.h"
#include "../common/third_party/nlohmann/single_include/nlohmann/json.hpp"
using json = nlohmann::json;
#endif
using namespace tlm;
class Gem5SimControlDRAMsys: public Gem5SystemC::Gem5SimControl
class Gem5SimControlDRAMsys : public Gem5SystemC::Gem5SimControl
{
public:
Gem5SimControlDRAMsys(string configFile) :
Gem5SimControlDRAMsys(std::string configFile) :
Gem5SystemC::Gem5SimControl("gem5", configFile, 0, "MemoryAccess")
{
}
{}
void afterSimulate()
{
@@ -68,7 +72,8 @@ public:
};
struct AddressOffset: sc_module {
class AddressOffset : sc_module
{
private:
unsigned long long int offset;
@@ -86,7 +91,7 @@ public:
}
//Forward Interface
tlm::tlm_sync_enum nb_transport_fw(tlm_generic_payload &trans, tlm_phase &phase,
tlm_sync_enum nb_transport_fw(tlm_generic_payload &trans, tlm_phase &phase,
sc_time &delay)
{
//std::cout << "NB "<< this->name() <<": " << trans.get_address() << " -" << offset;
@@ -95,7 +100,7 @@ public:
return i_socket->nb_transport_fw(trans, phase, delay);
}
unsigned int transport_dbg(tlm::tlm_generic_payload &trans)
unsigned int transport_dbg(tlm_generic_payload &trans)
{
// adjust address offset:
//std::cout << "Debug "<< this->name() <<": " << trans.get_address() << " -" << offset;
@@ -104,7 +109,7 @@ public:
return i_socket->transport_dbg(trans);
}
void b_transport(tlm::tlm_generic_payload &trans, sc_time &delay)
void b_transport(tlm_generic_payload &trans, sc_time &delay)
{
// adjust address offset:
//std::cout << "B "<< this->name() <<": " << trans.get_address() << " -" << offset;
@@ -114,7 +119,7 @@ public:
}
//Backward Interface
tlm::tlm_sync_enum nb_transport_bw(tlm_generic_payload &trans, tlm_phase &phase,
tlm_sync_enum nb_transport_bw(tlm_generic_payload &trans, tlm_phase &phase,
sc_time &delay)
{
//trans.set_address(trans.get_address()+offset);
@@ -123,7 +128,7 @@ public:
};
string pathOfFile(string file)
std::string pathOfFile(std::string file)
{
return file.substr(0, file.find_last_of('/'));
}
@@ -132,9 +137,9 @@ int sc_main(int argc, char **argv)
{
SC_REPORT_INFO("sc_main", "Simulation Setup");
string SimulationXML;
string gem5ConfigFile;
string resources;
std::string simulationJson;
std::string gem5ConfigFile;
std::string resources;
unsigned int numTransactors;
Gem5SystemC::Gem5SlaveTransactor *t;
std::vector<Gem5SystemC::Gem5SlaveTransactor *> transactors;
@@ -142,18 +147,28 @@ int sc_main(int argc, char **argv)
if (argc == 4) {
// Get path of resources:
resources = pathOfFile(argv[0])
+ string("/../../DRAMSys/library/resources/");
+ std::string("/../../DRAMSys/library/resources/");
SimulationXML = argv[1];
simulationJson = argv[1];
gem5ConfigFile = argv[2];
numTransactors = atoi(argv[3]);
numTransactors = std::stoul(argv[3]);
} else {
SC_REPORT_FATAL("sc_main", "Please provide configuration files and number of ports");
}
// Instantiate DRAMSys:
DRAMSys dramSys("DRAMSys", SimulationXML, resources);
DRAMSys *dramSys;
#ifdef RECORDING
json simulationdoc = parseJSON(simulationJson);
json simulatordoc = parseJSON(resources + "configs/simulator/"
+ std::string(simulationdoc["simulation"]["simconfig"]));
if (simulatordoc["simconfig"]["DatabaseRecording"])
dramSys = new DRAMSysRecordable("DRAMSys", simulationJson, resources);
else
#endif
dramSys = new DRAMSys("DRAMSys", simulationJson, resources);
// Instantiate gem5:
Gem5SimControlDRAMsys sim_control(gem5ConfigFile);
@@ -164,7 +179,7 @@ int sc_main(int argc, char **argv)
// Names generated here must match port names used by the gem5 config file, e.g., config.ini
if (numTransactors == 1) {
t = new Gem5SystemC::Gem5SlaveTransactor("transactor", "transactor");
t->socket.bind(dramSys.tSocket);
t->socket.bind(dramSys->tSocket);
t->sim_control.bind(sim_control);
transactors.push_back(t);
} else {
@@ -174,7 +189,7 @@ int sc_main(int argc, char **argv)
std::string name = "transactor" + std::to_string(index);
std::string portName = "transactor" + std::to_string(index);
t = new Gem5SystemC::Gem5SlaveTransactor(name.c_str(), portName.c_str());
t->socket.bind(dramSys.tSocket);
t->socket.bind(dramSys->tSocket);
t->sim_control.bind(sim_control);
transactors.push_back(t);
}
@@ -190,9 +205,9 @@ int sc_main(int argc, char **argv)
AddressOffset dramOffset("dramOffset", (2147483648 - 67108863)); //+67108863);
dramInterface.socket.bind(dramOffset.t_socket);
dramOffset.i_socket.bind(dramSys.tSocket); // ID0
dramOffset.i_socket.bind(dramSys->tSocket); // ID0
nvmInterface.socket.bind(nvmOffset.t_socket);
nvmOffset.i_socket.bind(dramSys.tSocket);
nvmOffset.i_socket.bind(dramSys->tSocket);
dramInterface.sim_control.bind(sim_control);
nvmInterface.sim_control.bind(sim_control);
@@ -208,9 +223,10 @@ int sc_main(int argc, char **argv)
sc_core::sc_stop();
}
for (auto t : transactors) {
for (auto t : transactors)
delete t;
}
delete dramSys;
SC_REPORT_INFO("sc_main", "End of Simulation");

200
DRAMSys/library/CMakeLists.txt
View File

@@ -39,11 +39,6 @@ project(DRAMSysLibrary)
set(CMAKE_CXX_STANDARD 11 CACHE STRING "C++ Version")
set(DCMAKE_SH="CMAKE_SH-NOTFOUND")
# Add sqlite3 Dependency:
set(BUILD_ENABLE_RTREE ON CACHE BOOL "Enable R-Tree Feature")
set(BUILD_ENABLE_RTREE ON)
add_subdirectory(src/common/third_party/sqlite-amalgamation)
# Add DRAMPower:
add_subdirectory(src/common/third_party/DRAMPower)
@@ -56,42 +51,36 @@ if(DEFINED ENV{SYSTEMC_HOME})
NAMES systemc SnpsVP
PATHS $ENV{SYSTEMC_HOME}/lib-$ENV{SYSTEMC_TARGET_ARCH}/ $ENV{SYSTEMC_HOME}/lib-linux64/ $ENV{SYSTEMC_HOME}/libso-$ENV{COWARE_CXX_COMPILER}/
)
message("Building with external SystemC located in $ENV{SYSTEMC_HOME}")
message("-- Building with external SystemC located in $ENV{SYSTEMC_HOME}")
else()
set(BUILD_SHARED_LIBS OFF CACHE BOOL "Build Shared Libs")
add_subdirectory(src/common/third_party/systemc)
set(SYSTEMC_LIBRARY systemc)
message("Building with SystemC submodule")
message("-- Building with SystemC submodule")
endif()
include_directories(
src/common
src/common/third_party/DRAMPower/src
src/configuration
src/configuration/memspec
src/controller
src/controller/checker
src/controller/cmdmux
src/controller/powerdown
src/controller/refresh
src/controller/respqueue
src/controller/scheduler
src/error
src/error/ECC
src/simulation
src/simulation/dram
)
if(EXISTS ${CMAKE_CURRENT_LIST_DIR}/src/simulation/DRAMSysRecordable.cpp)
# Add sqlite3 Dependency:
set(BUILD_ENABLE_RTREE ON CACHE BOOL "Enable R-Tree Feature")
set(BUILD_ENABLE_RTREE ON)
add_subdirectory(src/common/third_party/sqlite-amalgamation)
set(RECORDING_SOURCES
src/common/TlmRecorder.cpp
src/controller/ControllerRecordable.cpp
src/simulation/DRAMSysRecordable.cpp
src/simulation/dram/DramRecordable.cpp
)
endif()
add_library(DRAMSysLibrary
src/common/AddressDecoder.cpp
src/common/DebugManager.cpp
src/common/dramExtensions.cpp
src/common/tlm2_base_protocol_checker.h
src/common/TlmRecorder.cpp
src/common/utils.cpp
src/configuration/Configuration.cpp
src/configuration/ConfigurationLoader.cpp
src/configuration/TemperatureSimConfig.h
src/configuration/memspec/MemSpec.cpp
@@ -109,7 +98,6 @@ add_library(DRAMSysLibrary
src/controller/Command.cpp
src/controller/ControllerIF.h
src/controller/Controller.cpp
src/controller/ControllerRecordable.cpp
src/controller/checker/CheckerIF.h
src/controller/checker/CheckerDDR3.cpp
@@ -154,18 +142,10 @@ add_library(DRAMSysLibrary
src/simulation/Arbiter.cpp
src/simulation/DRAMSys.cpp
src/simulation/ExampleInitiator.h
src/simulation/MemoryManager.cpp
src/simulation/ReorderBuffer.h
src/simulation/StlPlayer.h
src/simulation/TemperatureController.cpp
src/simulation/TraceGenerator.h
src/simulation/TracePlayer.cpp
src/simulation/TracePlayerListener.h
src/simulation/TraceSetup.cpp
src/simulation/dram/Dram.cpp
src/simulation/dram/DramRecordable.cpp
src/simulation/dram/DramDDR3.cpp
src/simulation/dram/DramDDR4.cpp
src/simulation/dram/DramLPDDR4.cpp
@@ -175,19 +155,159 @@ add_library(DRAMSysLibrary
src/simulation/dram/DramGDDR5X.cpp
src/simulation/dram/DramGDDR6.cpp
src/simulation/dram/DramHBM2.cpp
${RECORDING_SOURCES}
# Simulation Config Files
resources/simulations/ddr3-boot-linux.json
resources/simulations/ddr3-ecc.json
resources/simulations/ddr3-example2.json
resources/simulations/ddr3-example.json
resources/simulations/ddr3-gem5-se.json
resources/simulations/ddr3_postpone_ref_test.json
resources/simulations/ddr3-single-device.json
resources/simulations/ddr4-example.json
resources/simulations/hbm2-example.json
resources/simulations/lpddr4-example.json
resources/simulations/ranktest.json
resources/simulations/wideio-example.json
# Address Mapping Config Files
resources/configs/amconfigs/am_ddr3_1Gbx8_p1KB_brc.json
resources/configs/amconfigs/am_ddr3_4x4Gbx16_dimm_p2KB_brc.json
resources/configs/amconfigs/am_ddr3_4x4Gbx16_dimm_p2KB_rbc.json
resources/configs/amconfigs/am_ddr3_8x1Gbx8_dimm_p1KB_brc.json
resources/configs/amconfigs/am_ddr3_8x1Gbx8_dimm_p1KB_rbc.json
resources/configs/amconfigs/am_ddr3_8x2Gbx8_dimm_p1KB_brc.json
resources/configs/amconfigs/am_ddr3_8x2Gbx8_dimm_p1KB_rbc.json
resources/configs/amconfigs/am_ddr3_x16_brc.json
resources/configs/amconfigs/am_ddr3_x16_rbc.json
resources/configs/amconfigs/am_ddr4_8x4Gbx8_dimm_p1KB_brc.json
resources/configs/amconfigs/am_hbm2_8Gb_pc_brc.json
resources/configs/amconfigs/am_lpddr4_8Gbx16_brc.json
resources/configs/amconfigs/am_ranktest.json
resources/configs/amconfigs/am_wideio2_4x64_4x2Gb_brc.json
resources/configs/amconfigs/am_wideio2_4x64_4x2Gb_rbc.json
resources/configs/amconfigs/am_wideio_4x1Gb_brc.json
resources/configs/amconfigs/am_wideio_4x1Gb_rbc.json
resources/configs/amconfigs/am_wideio_4x256Mb_brc.json
resources/configs/amconfigs/am_wideio_4x256Mb_rbc.json
resources/configs/amconfigs/am_wideio_4x2Gb_brc.json
resources/configs/amconfigs/am_wideio_4x2Gb_rbc.json
resources/configs/amconfigs/am_wideio_4x4Gb_brc.json
resources/configs/amconfigs/am_wideio_4x4Gb_rbc.json
resources/configs/amconfigs/am_wideio_4x512Mb_brc.json
resources/configs/amconfigs/am_wideio_4x512Mb_rbc.json
# Memory Controller Config Files
resources/configs/mcconfigs/fifo.json
resources/configs/mcconfigs/fifoStrict.json
resources/configs/mcconfigs/fr_fcfs_grp.json
resources/configs/mcconfigs/fr_fcfs.json
# Memspec Config Files
resources/configs/memspecs/HBM2.json
resources/configs/memspecs/JEDEC_256Mb_WIDEIO-200_128bit.json
resources/configs/memspecs/JEDEC_256Mb_WIDEIO-266_128bit.json
resources/configs/memspecs/JEDEC_4Gb_DDR4-1866_8bit_A.json
resources/configs/memspecs/JEDEC_4Gb_DDR4-2400_8bit_A.json
resources/configs/memspecs/JEDEC_4x64_2Gb_WIDEIO2-400_64bit.json
resources/configs/memspecs/JEDEC_4x64_2Gb_WIDEIO2-533_64bit.json
resources/configs/memspecs/JEDEC_8Gb_LPDDR4-3200_16bit.json
resources/configs/memspecs/memspec_ranktest.json
resources/configs/memspecs/MICRON_1Gb_DDR2-1066_16bit_H.json
resources/configs/memspecs/MICRON_1Gb_DDR2-800_16bit_H.json
resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G_2s.json
resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G_3s.json
resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G.json
resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G_mu.json
resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G_2s.json
resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G_3s.json
resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G.json
resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G_mu.json
resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_2s.json
resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_3s.json
resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G.json
resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_less_refresh.json
resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_mu.json
resources/configs/memspecs/MICRON_1Gb_DDR3-800_8bit_G.json
resources/configs/memspecs/MICRON_2GB_DDR3-1066_64bit_D_SODIMM.json
resources/configs/memspecs/MICRON_2GB_DDR3-1066_64bit_G_UDIMM.json
resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D_2s.json
resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D_3s.json
resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D.json
resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D_mu.json
resources/configs/memspecs/MICRON_2GB_DDR3-1333_64bit_D_SODIMM.json
resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D_2s.json
resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D_3s.json
resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D.json
resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D_mu.json
resources/configs/memspecs/MICRON_2GB_DDR3-1600_64bit_G_UDIMM.json
resources/configs/memspecs/MICRON_2Gb_LPDDR2-1066-S4_16bit_A.json
resources/configs/memspecs/MICRON_2Gb_LPDDR-266_16bit_A.json
resources/configs/memspecs/MICRON_2Gb_LPDDR2-800-S4_16bit_A.json
resources/configs/memspecs/MICRON_2Gb_LPDDR-333_16bit_A.json
resources/configs/memspecs/MICRON_4Gb_DDR4-1866_8bit_A.json
resources/configs/memspecs/MICRON_4Gb_DDR4-2400_8bit_A.json
resources/configs/memspecs/MICRON_4Gb_LPDDR3-1333_32bit_A.json
resources/configs/memspecs/MICRON_4Gb_LPDDR3-1600_32bit_A.json
resources/configs/memspecs/MICRON_6Gb_LPDDR4-3200_32bit_A.json
resources/configs/memspecs/SAMSUNG_K4B1G1646E_1Gb_DDR3-1600_16bit.json
resources/configs/memspecs/SAMSUNG_K4B4G1646Q_4Gb_DDR3-1066_16bit.json
# Simulator Config Files
resources/configs/simulator/ddr3_boot_linux.json
resources/configs/simulator/ddr3_ecc.json
resources/configs/simulator/ddr3.json
resources/configs/simulator/ddr3_gem5_se.json
resources/configs/simulator/ddr3-single-device.json
resources/configs/simulator/ddr4.json
resources/configs/simulator/hbm2.json
resources/configs/simulator/lpddr4.json
resources/configs/simulator/wideio.json
# Thermal Simulation Config Files
resources/configs/thermalsim/config.json
# Trace Files
resources/traces/test_ecc.stl
resources/traces/ddr3_example.stl
resources/traces/ddr3_single_dev_example.stl
resources/traces/ddr3_postpone_ref_test_1.stl
resources/traces/ranktest.stl
resources/traces/chstone-adpcm_32.stl
)
if(DEFINED ENV{LIBTHREED_ICE_HOME} AND DEFINED ENV{LIBSUPERLU_HOME})
message("-- 3D-ICE and SuperLU available")
add_definitions(-DTHERMALSIM)
target_include_directories(DRAMSysLibrary
PRIVATE $ENV{LIBTHREED_ICE_HOME}/include/
)
find_library(3DICE_LIBRARY NAMES threed-ice-2.2.4 PATHS $ENV{LIBTHREED_ICE_HOME}/lib/)
target_link_libraries(DRAMSysLibrary
PRIVATE ${3DICE_LIBRARY}
)
endif()
if(EXISTS ${CMAKE_CURRENT_LIST_DIR}/src/simulation/DRAMSysRecordable.cpp)
target_include_directories(DRAMSysLibrary
PRIVATE src/common/third_party/sqlite-amalgamation/
)
target_link_libraries(DRAMSysLibrary
PRIVATE sqlite3::sqlite3
)
endif()
# Build:
target_include_directories(DRAMSysLibrary
PUBLIC src/common/third_party/DRAMPower/src/
PUBLIC src/common/third_party/sqlite-amalgamation/
PUBLIC $ENV{SYSTEMC_HOME}/include/
PUBLIC $ENV{SYSTEMC_HOME}/include/tlm/
)
target_link_libraries(DRAMSysLibrary
${SYSTEMC_LIBRARY}
sqlite3::sqlite3
DRAMPower
PUBLIC ${SYSTEMC_LIBRARY}
PRIVATE DRAMPower
)

42
DRAMSys/library/resources/configs/amconfigs/am_ddr3.json
View File

@@ -1,42 +0,0 @@
{
"CONGEN": {
"BANK_BIT": [
27,
28,
29
],
"BYTE_BIT": [
0,
1,
2
],
"COLUMN_BIT": [
3,
4,
5,
6,
7,
8,
9,
10,
11,
12
],
"ROW_BIT": [
13,
14,
15,
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26
]
}
}

37
DRAMSys/library/resources/configs/amconfigs/am_ddr4.json
View File

@@ -1,37 +0,0 @@
{
"CONGEN": {
"BANK_BIT": [
5,
6,
7,
8
],
"COLUMN_BIT": [
9,
10,
11,
12,
13,
14,
15,
16,
17,
18
],
"ROW_BIT": [
19,
20,
21,
22,
23,
24,
25,
26,
27,
28,
29,
30,
31
]
}
}

12
DRAMSys/library/resources/configs/amconfigs/am_ddr4_8x4Gbx8_dimm_p1KB_brc.json
View File

@@ -1,13 +1,13 @@
{
"CONGEN": {
"BANKGROUP_BIT":[
30,
31
],
"BANK_BIT": [
"BANKGROUP_BIT":[
28,
29
],
"BANK_BIT": [
30,
31
],
"BYTE_BIT": [
0,
1,
@@ -43,4 +43,4 @@
27
]
}
}
}

10
DRAMSys/library/resources/configs/amconfigs/am_hbm2_8Gb_pc_brc.json
View File

@@ -1,11 +1,11 @@
{
"CONGEN": {
"RANK_BIT":[
29
"RANK_BIT":[
29
],
"BANKGROUP_BIT":[
"BANKGROUP_BIT":[
27,
28
28
],
"BANK_BIT": [
25,
@@ -43,4 +43,4 @@
24
]
}
}
}

37
DRAMSys/library/resources/configs/amconfigs/am_highHits.json
View File

@@ -1,37 +0,0 @@
{
"CONGEN": {
"BANK_BIT": [
15,
16,
17,
18
],
"COLUMN_BIT": [
5,
6,
7,
8,
9,
10,
11,
12,
13,
14
],
"ROW_BIT": [
19,
20,
21,
22,
23,
24,
25,
26,
27,
28,
29,
30,
31
]
}
}

37
DRAMSys/library/resources/configs/amconfigs/am_highPara.json
View File

@@ -1,37 +0,0 @@
{
"CONGEN": {
"BANK_BIT": [
5,
6,
7,
8
],
"COLUMN_BIT": [
9,
10,
11,
12,
13,
14,
15,
16,
17,
18
],
"ROW_BIT": [
19,
20,
21,
22,
23,
24,
25,
26,
27,
28,
29,
30,
31
]
}
}

37
DRAMSys/library/resources/configs/amconfigs/am_lowHits.json
View File

@@ -1,37 +0,0 @@
{
"CONGEN": {
"BANK_BIT": [
5,
6,
7,
8
],
"COLUMN_BIT": [
24,
25,
26,
27,
28,
29,
30,
31
],
"ROW_BIT": [
9,
10,
11,
12,
13,
14,
15,
16,
17,
18,
19,
20,
21,
22,
23
]
}
}

37
DRAMSys/library/resources/configs/amconfigs/am_lowPara.json
View File

@@ -1,37 +0,0 @@
{
"CONGEN": {
"BANK_BIT": [
30,
31
],
"COLUMN_BIT": [
5,
6,
7,
8,
9,
10,
11,
12,
13,
14
],
"ROW_BIT": [
15,
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26,
27,
28,
29
]
}
}

6
DRAMSys/library/resources/configs/amconfigs/am_ranktest.json
View File

@@ -1,7 +1,7 @@
{
"CONGEN": {
"RANK_BIT":[
30,
"RANK_BIT":[
30,
31
],
"BANK_BIT": [
@@ -43,4 +43,4 @@
26
]
}
}
}

43
DRAMSys/library/resources/configs/amconfigs/am_wideio.json
View File

@@ -1,43 +0,0 @@
{
"CONGEN": {
"BANK_BIT": [
11,
12,
13
],
"BYTE_BIT": [
0,
1,
2,
3
],
"CHANNEL_BIT": [
27,
28
],
"COLUMN_BIT": [
4,
5,
6,
7,
8,
9,
10
],
"ROW_BIT": [
14,
15,
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26
]
}
}

43
DRAMSys/library/resources/configs/amconfigs/am_wideioFourBanks.json
View File

@@ -1,43 +0,0 @@
{
"CONGEN": {
"BANK_BIT": [
11,
12
],
"BYTE_BIT": [
0,
1,
2,
3
],
"CHANNEL_BIT": [
27,
28
],
"COLUMN_BIT": [
4,
5,
6,
7,
8,
9,
10
],
"ROW_BIT": [
13,
14,
15,
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26
]
}
}

45
DRAMSys/library/resources/configs/amconfigs/orgr_ddr4_4x16Gbx16_dimm_p2KB_brc.json
View File

@@ -1,45 +0,0 @@
{
"CONGEN": {
"BANK_BIT": [
30,
31,
32
],
"BYTE_BIT": [
0,
1,
2
],
"COLUMN_BIT": [
3,
4,
5,
6,
7,
8,
9,
10,
11,
12
],
"ROW_BIT": [
13,
14,
15,
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26,
27,
28,
29
]
}
}

45
DRAMSys/library/resources/configs/amconfigs/rgram-rbc.json
View File

@@ -1,45 +0,0 @@
{
"CONGEN": {
"BANK_BIT": [
13,
14,
15
],
"BYTE_BIT": [
0,
1,
2
],
"COLUMN_BIT": [
3,
4,
5,
6,
7,
8,
9,
10,
11,
12
],
"ROW_BIT": [
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26,
27,
28,
29,
30,
31,
32
]
}
}

45
DRAMSys/library/resources/configs/amconfigs/rgram.json
View File

@@ -1,45 +0,0 @@
{
"CONGEN": {
"BANK_BIT": [
30,
31,
32
],
"BYTE_BIT": [
0,
1,
2
],
"COLUMN_BIT": [
3,
4,
5,
6,
7,
8,
9,
10,
11,
12
],
"ROW_BIT": [
13,
14,
15,
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26,
27,
28,
29
]
}
}

26
DRAMSys/library/resources/configs/mcconfigs/fifo.json
View File

@@ -1,11 +1,15 @@
{"mcconfig": {"PagePolicy": "Open",
"Scheduler": "Fifo",
"RequestBufferSize": 8,
"CmdMux": "Oldest",
"RespQueue": "Fifo",
"RefreshPolicy": "Rankwise",
"RefreshMode": 1,
"RefreshMaxPostponed": 8,
"RefreshMaxPulledin": 8,
"PowerDownPolicy": "NoPowerDown",
"PowerDownTimeout": 100}}
{
"mcconfig": {
"PagePolicy": "Open",
"Scheduler": "Fifo",
"RequestBufferSize": 8,
"CmdMux": "Oldest",
"RespQueue": "Fifo",
"RefreshPolicy": "Rankwise",
"RefreshMode": 1,
"RefreshMaxPostponed": 8,
"RefreshMaxPulledin": 8,
"PowerDownPolicy": "NoPowerDown",
"PowerDownTimeout": 100
}
}

26
DRAMSys/library/resources/configs/mcconfigs/fifoStrict.json
View File

@@ -1,11 +1,15 @@
{"mcconfig": {"PagePolicy": "Open",
"Scheduler": "Fifo",
"RequestBufferSize": 8,
"CmdMux": "Strict",
"RespQueue": "Fifo",
"RefreshPolicy": "Rankwise",
"RefreshMode": 1,
"RefreshMaxPostponed": 8,
"RefreshMaxPulledin": 8,
"PowerDownPolicy": "NoPowerDown",
"PowerDownTimeout": 100}}
{
"mcconfig": {
"PagePolicy": "Open",
"Scheduler": "Fifo",
"RequestBufferSize": 8,
"CmdMux": "Strict",
"RespQueue": "Fifo",
"RefreshPolicy": "Rankwise",
"RefreshMode": 1,
"RefreshMaxPostponed": 8,
"RefreshMaxPulledin": 8,
"PowerDownPolicy": "NoPowerDown",
"PowerDownTimeout": 100
}
}

27
DRAMSys/library/resources/configs/mcconfigs/fr_fcfs.json
View File

@@ -1,12 +1,15 @@
{"mcconfig": {
"PagePolicy": "Open",
"Scheduler": "FrFcfs",
"RequestBufferSize": 8,
"CmdMux": "Oldest",
"RespQueue": "Fifo",
"RefreshPolicy": "Rankwise",
"RefreshMode": 1,
"RefreshMaxPostponed": 8,
"RefreshMaxPulledin": 8,
"PowerDownPolicy": "NoPowerDown",
"PowerDownTimeout": 100}}
{
"mcconfig": {
"PagePolicy": "Open",
"Scheduler": "FrFcfs",
"RequestBufferSize": 8,
"CmdMux": "Oldest",
"RespQueue": "Fifo",
"RefreshPolicy": "Rankwise",
"RefreshMode": 1,
"RefreshMaxPostponed": 8,
"RefreshMaxPulledin": 8,
"PowerDownPolicy": "NoPowerDown",
"PowerDownTimeout": 100
}
}

27
DRAMSys/library/resources/configs/mcconfigs/fr_fcfs_grp.json
View File

@@ -1,12 +1,15 @@
{"mcconfig":
{"PagePolicy": "Open",
"Scheduler": "FrFcfsGrp",
"RequestBufferSize": 8,
"CmdMux": "Oldest",
"RespQueue": "Fifo",
"RefreshPolicy": "Rankwise",
"RefreshMode": 1,
"RefreshMaxPostponed": 8,
"RefreshMaxPulledin": 8,
"PowerDownPolicy": "NoPowerDown",
"PowerDownTimeout": 100}}
{
"mcconfig": {
"PagePolicy": "Open",
"Scheduler": "FrFcfsGrp",
"RequestBufferSize": 8,
"CmdMux": "Oldest",
"RespQueue": "Fifo",
"RefreshPolicy": "Rankwise",
"RefreshMode": 1,
"RefreshMaxPostponed": 8,
"RefreshMaxPulledin": 8,
"PowerDownPolicy": "NoPowerDown",
"PowerDownTimeout": 100
}
}

66
DRAMSys/library/resources/configs/memspecs/DDR4.json
View File

@@ -1,66 +0,0 @@
{
"memspec": {
"memarchitecturespec": {
"burstLength": 8,
"dataRate": 2,
"nbrOfBankGroups": 4,
"nbrOfBanks": 16,
"nbrOfColumns": 1024,
"nbrOfRanks": 1,
"nbrOfRows": 32768,
"width": 8
},
"memoryId": "MICRON_4Gb_DDR4-2400_8bit_A",
"memoryType": "DDR4",
"mempowerspec": {
"idd0": 60.75,
"idd02": 4.05,
"idd2n": 38.25,
"idd2p0": 17.0,
"idd2p1": 17.0,
"idd3n": 44.0,
"idd3p0": 22.5,
"idd3p1": 22.5,
"idd4r": 184.5,
"idd4w": 168.75,
"idd5": 118.0,
"idd6": 20.25,
"idd62": 2.6,
"vdd": 1.2,
"vdd2": 2.5
},
"memtimingspec": {
"AL": 0,
"CCD_L": 6,
"CCD_S": 4,
"CKE": 6,
"CKESR": 7,
"CL": 16,
"DQSCK": 2,
"FAW": 26,
"RAS": 39,
"RC": 55,
"RCD": 16,
"REFI": 4680,
"RFC": 313,
"RL": 16,
"RP": 16,
"RRD_L": 6,
"RRD_S": 4,
"RTP": 12,
"WL": 16,
"WR": 18,
"WTR_L": 9,
"WTR_S": 3,
"XP": 8,
"XPDLL": 325,
"XS": 324,
"XSDLL": 512,
"ACTPDEN": 2,
"PRPDEN": 2,
"REFPDEN": 2,
"RTRS": 1,
"clkMhz": 1200
}
}
}

59
DRAMSys/library/resources/configs/memspecs/orgr_16Gb_ddr4.json
View File

@@ -1,59 +0,0 @@
{
"memspec": {
"memarchitecturespec": {
"burstLength": 8,
"dataRate": 2,
"nbrOfBanks": 8,
"nbrOfColumns": 1024,
"nbrOfRanks": 1,
"nbrOfRows": 131072,
"width": 16
},
"memoryId": "orgr_16Gb_DDR4_16bit",
"memoryType": "DDR3",
"mempowerspec": {
"idd0": 210.5,
"idd2n": 99.0,
"idd2p0": 16.0,
"idd2p1": 55.0,
"idd3n": 115.0,
"idd3p0": 70.0,
"idd3p1": 70.0,
"idd4r": 1470.8,
"idd4w": 1511.4,
"idd5": 2000.0,
"idd6": 22.0,
"vdd": 1.2
},
"memtimingspec": {
"AL": 0,
"CCD": 4,
"CKE": 8,
"CKESR": 8,
"CL": 15,
"DQSCK": 0,
"FAW": 37,
"RAS": 34,
"RC": 52,
"RCD": 18,
"REFI": 9361,
"RFC": 673,
"RL": 18,
"RP": 18,
"RRD": 8,
"RTP": 6,
"WL": 12,
"WR": 15,
"WTR": 8,
"XP": 4,
"XPDLL": 13,
"XS": 64,
"XSDLL": 512,
"ACTPDEN": 2,
"PRPDEN": 2,
"REFPDEN": 2,
"RTRS": 1,
"clkMhz": 1200
}
}
}

59
DRAMSys/library/resources/configs/memspecs/orgr_16Gb_ddr4_2x.json
View File

@@ -1,59 +0,0 @@
{
"memspec": {
"memarchitecturespec": {
"burstLength": 8,
"dataRate": 2,
"nbrOfBanks": 8,
"nbrOfColumns": 1024,
"nbrOfRanks": 1,
"nbrOfRows": 131072,
"width": 16
},
"memoryId": "orgr_16Gb_DDR4_16bit",
"memoryType": "DDR3",
"mempowerspec": {
"idd0": 210.5,
"idd2n": 99.0,
"idd2p0": 16.0,
"idd2p1": 55.0,
"idd3n": 115.0,
"idd3p0": 70.0,
"idd3p1": 70.0,
"idd4r": 1470.8,
"idd4w": 1511.4,
"idd5": 1446.0,
"idd6": 22.0,
"vdd": 1.2
},
"memtimingspec": {
"AL": 0,
"CCD": 4,
"CKE": 8,
"CKESR": 8,
"CL": 15,
"DQSCK": 0,
"FAW": 37,
"RAS": 34,
"RC": 52,
"RCD": 18,
"REFI": 4681,
"RFC": 421,
"RL": 18,
"RP": 18,
"RRD": 8,
"RTP": 6,
"WL": 12,
"WR": 15,
"WTR": 8,
"XP": 4,
"XPDLL": 13,
"XS": 64,
"XSDLL": 512,
"ACTPDEN": 2,
"PRPDEN": 2,
"REFPDEN": 2,
"RTRS": 1,
"clkMhz": 1200
}
}
}

59
DRAMSys/library/resources/configs/memspecs/orgr_16Gb_ddr4_4x.json
View File

@@ -1,59 +0,0 @@
{
"memspec": {
"memarchitecturespec": {
"burstLength": 8,
"dataRate": 2,
"nbrOfBanks": 8,
"nbrOfColumns": 1024,
"nbrOfRanks": 1,
"nbrOfRows": 131072,
"width": 16
},
"memoryId": "orgr_16Gb_DDR4_16bit",
"memoryType": "DDR3",
"mempowerspec": {
"idd0": 210.5,
"idd2n": 99.0,
"idd2p0": 16.0,
"idd2p1": 55.0,
"idd3n": 115.0,
"idd3p0": 70.0,
"idd3p1": 70.0,
"idd4r": 1470.8,
"idd4w": 1511.4,
"idd5": 1226.0,
"idd6": 22.0,
"vdd": 1.2
},
"memtimingspec": {
"AL": 0,
"CCD": 4,
"CKE": 8,
"CKESR": 8,
"CL": 15,
"DQSCK": 0,
"FAW": 37,
"RAS": 34,
"RC": 52,
"RCD": 18,
"REFI": 2341,
"RFC": 313,
"RL": 18,
"RP": 18,
"RRD": 8,
"RTP": 6,
"WL": 12,
"WR": 15,
"WTR": 8,
"XP": 4,
"XPDLL": 13,
"XS": 64,
"XSDLL": 512,
"ACTPDEN": 2,
"PRPDEN": 2,
"REFPDEN": 2,
"RTRS": 1,
"clkMhz": 1200
}
}
}

67
DRAMSys/library/resources/configs/memspecs/rgrspec.json
View File

@@ -1,67 +0,0 @@
{
"memspec": {
"memarchitecturespec": {
"burstLength": 8,
"dataRate": 2,
"nbrOfBankGroups": 1,
"nbrOfBanks": 8,
"nbrOfColumns": 1024,
"nbrOfRanks": 1,
"nbrOfRows": 131072,
"width": 16
},
"memoryId": "rgrspec",
"memoryType": "DDR4",
"mempowerspec": {
"idd0": 210.5,
"idd02": 4.05,
"idd2n": 99.0,
"idd2p0": 16.0,
"idd2p1": 55.0,
"idd3n": 115.0,
"idd3p0": 70.0,
"idd3p1": 70.0,
"idd4r": 1470.8,
"idd4w": 1511.4,
"idd5": 2000.0,
"idd6": 22.0,
"idd62": 2.6,
"vdd": 1.2,
"vdd2": 2.5
},
"memtimingspec": {
"AL": 0,
"CCD": 4,
"CCD_L": 6,
"CCD_S": 4,
"CKE": 8,
"CKESR": 8,
"CL": 15,
"DQSCK": 0,
"FAW": 37,
"RAS": 34,
"RC": 52,
"RCD": 18,
"REFI": 9364,
"RFC": 673,
"RFC2": 420,
"RFC4": 312,
"RL": 18,
"RP": 18,
"RRD": 8,
"RRD_L": 6,
"RRD_S": 4,
"RTP": 6,
"WL": 12,
"WR": 15,
"WTR": 8,
"WTR_L": 9,
"WTR_S": 3,
"XP": 4,
"XPDLL": 13,
"XS": 64,
"XSDLL": 512,
"clkMhz": 1200
}
}
}

40
DRAMSys/library/resources/configs/simulator/orgr.json
View File

@@ -1,40 +0,0 @@
{
"simconfig": {
"ControllerCoreRGR": true,
"ControllerCoreRGRB0": true,
"ControllerCoreRGRB1": true,
"ControllerCoreRGRB10": false,
"ControllerCoreRGRB11": false,
"ControllerCoreRGRB12": false,
"ControllerCoreRGRB13": false,
"ControllerCoreRGRB14": false,
"ControllerCoreRGRB15": false,
"ControllerCoreRGRB2": true,
"ControllerCoreRGRB3": true,
"ControllerCoreRGRB4": true,
"ControllerCoreRGRB5": true,
"ControllerCoreRGRB6": true,
"ControllerCoreRGRB7": true,
"ControllerCoreRGRB8": false,
"ControllerCoreRGRB9": false,
"ControllerCoreRGRtFAWBInClkCycles": 27,
"ControllerCoreRGRtRASBInClkCycles": 20,
"ControllerCoreRGRtRCBInClkCycles": 27,
"ControllerCoreRGRtRPBInClkCycles": 8,
"ControllerCoreRGRtRRDB_LInClkCycles": 6,
"ControllerCoreRGRtRRDB_SInClkCycles": 6,
"ControllerCoreRefDisable": 0,
"ControllerCoreRefNumARCmdsIntREFI": 8192,
"DatabaseRecording": true,
"Debug": false,
"EnableWindowing": true,
"NumberOfDevicesOnDIMM": 4,
"NumberOfMemChannels": 1,
"PowerAnalysis": true,
"SimulationName": "orgr",
"SimulationProgressBar": true,
"ThermalSimulation": false,
"UseMalloc": false,
"WindowSize": 1000
}
}

40
DRAMSys/library/resources/configs/simulator/orgr_4b_opt_timings_ddr3.json
View File

@@ -1,40 +0,0 @@
{
"simconfig": {
"ControllerCoreRGR": true,
"ControllerCoreRGRB0": true,
"ControllerCoreRGRB1": true,
"ControllerCoreRGRB10": false,
"ControllerCoreRGRB11": false,
"ControllerCoreRGRB12": false,
"ControllerCoreRGRB13": false,
"ControllerCoreRGRB14": false,
"ControllerCoreRGRB15": false,
"ControllerCoreRGRB2": true,
"ControllerCoreRGRB3": true,
"ControllerCoreRGRB4": false,
"ControllerCoreRGRB5": false,
"ControllerCoreRGRB6": false,
"ControllerCoreRGRB7": false,
"ControllerCoreRGRB8": false,
"ControllerCoreRGRB9": false,
"ControllerCoreRGRtFAWBInClkCycles": 0,
"ControllerCoreRGRtRASBInClkCycles": 11,
"ControllerCoreRGRtRCBInClkCycles": 16,
"ControllerCoreRGRtRPBInClkCycles": 5,
"ControllerCoreRGRtRRDB_LInClkCycles": 2,
"ControllerCoreRGRtRRDB_SInClkCycles": 2,
"ControllerCoreRefDisable": 0,
"ControllerCoreRefNumARCmdsIntREFI": 8192,
"DatabaseRecording": true,
"Debug": false,
"EnableWindowing": true,
"NumberOfDevicesOnDIMM": 4,
"NumberOfMemChannels": 1,
"PowerAnalysis": true,
"SimulationName": "orgr_4b_opt_timings",
"SimulationProgressBar": true,
"ThermalSimulation": false,
"UseMalloc": false,
"WindowSize": 1000
}
}

40
DRAMSys/library/resources/configs/simulator/orgr_4b_std_timings_ddr3.json
View File

@@ -1,40 +0,0 @@
{
"simconfig": {
"ControllerCoreRGR": true,
"ControllerCoreRGRB0": true,
"ControllerCoreRGRB1": true,
"ControllerCoreRGRB10": false,
"ControllerCoreRGRB11": false,
"ControllerCoreRGRB12": false,
"ControllerCoreRGRB13": false,
"ControllerCoreRGRB14": false,
"ControllerCoreRGRB15": false,
"ControllerCoreRGRB2": true,
"ControllerCoreRGRB3": true,
"ControllerCoreRGRB4": false,
"ControllerCoreRGRB5": false,
"ControllerCoreRGRB6": false,
"ControllerCoreRGRB7": false,
"ControllerCoreRGRB8": false,
"ControllerCoreRGRB9": false,
"ControllerCoreRGRtFAWBInClkCycles": 27,
"ControllerCoreRGRtRASBInClkCycles": 20,
"ControllerCoreRGRtRCBInClkCycles": 27,
"ControllerCoreRGRtRPBInClkCycles": 8,
"ControllerCoreRGRtRRDB_LInClkCycles": 6,
"ControllerCoreRGRtRRDB_SInClkCycles": 6,
"ControllerCoreRefDisable": 0,
"ControllerCoreRefNumARCmdsIntREFI": 8192,
"DatabaseRecording": true,
"Debug": false,
"EnableWindowing": true,
"NumberOfDevicesOnDIMM": 4,
"NumberOfMemChannels": 1,
"PowerAnalysis": true,
"SimulationName": "orgr_4b_std_timings",
"SimulationProgressBar": true,
"ThermalSimulation": false,
"UseMalloc": false,
"WindowSize": 1000
}
}

40
DRAMSys/library/resources/configs/simulator/orgr_8b_opt_timings_ddr3.json
View File

@@ -1,40 +0,0 @@
{
"simconfig": {
"ControllerCoreRGR": true,
"ControllerCoreRGRB0": true,
"ControllerCoreRGRB1": true,
"ControllerCoreRGRB10": false,
"ControllerCoreRGRB11": false,
"ControllerCoreRGRB12": false,
"ControllerCoreRGRB13": false,
"ControllerCoreRGRB14": false,
"ControllerCoreRGRB15": false,
"ControllerCoreRGRB2": true,
"ControllerCoreRGRB3": true,
"ControllerCoreRGRB4": true,
"ControllerCoreRGRB5": true,
"ControllerCoreRGRB6": true,
"ControllerCoreRGRB7": true,
"ControllerCoreRGRB8": false,
"ControllerCoreRGRB9": false,
"ControllerCoreRGRtFAWBInClkCycles": 0,
"ControllerCoreRGRtRASBInClkCycles": 11,
"ControllerCoreRGRtRCBInClkCycles": 16,
"ControllerCoreRGRtRPBInClkCycles": 5,
"ControllerCoreRGRtRRDB_LInClkCycles": 2,
"ControllerCoreRGRtRRDB_SInClkCycles": 2,
"ControllerCoreRefDisable": 0,
"ControllerCoreRefNumARCmdsIntREFI": 8192,
"DatabaseRecording": true,
"Debug": false,
"EnableWindowing": true,
"NumberOfDevicesOnDIMM": 4,
"NumberOfMemChannels": 1,
"PowerAnalysis": true,
"SimulationName": "orgr_8b_opt_timings",
"SimulationProgressBar": true,
"ThermalSimulation": false,
"UseMalloc": false,
"WindowSize": 1000
}
}

40
DRAMSys/library/resources/configs/simulator/orgr_8b_std_timings_ddr3.json
View File

@@ -1,40 +0,0 @@
{
"simconfig": {
"ControllerCoreRGR": true,
"ControllerCoreRGRB0": true,
"ControllerCoreRGRB1": true,
"ControllerCoreRGRB10": false,
"ControllerCoreRGRB11": false,
"ControllerCoreRGRB12": false,
"ControllerCoreRGRB13": false,
"ControllerCoreRGRB14": false,
"ControllerCoreRGRB15": false,
"ControllerCoreRGRB2": true,
"ControllerCoreRGRB3": true,
"ControllerCoreRGRB4": true,
"ControllerCoreRGRB5": true,
"ControllerCoreRGRB6": true,
"ControllerCoreRGRB7": true,
"ControllerCoreRGRB8": false,
"ControllerCoreRGRB9": false,
"ControllerCoreRGRtFAWBInClkCycles": 27,
"ControllerCoreRGRtRASBInClkCycles": 20,
"ControllerCoreRGRtRCBInClkCycles": 27,
"ControllerCoreRGRtRPBInClkCycles": 8,
"ControllerCoreRGRtRRDB_LInClkCycles": 6,
"ControllerCoreRGRtRRDB_SInClkCycles": 6,
"ControllerCoreRefDisable": 0,
"ControllerCoreRefNumARCmdsIntREFI": 8192,
"DatabaseRecording": true,
"Debug": false,
"EnableWindowing": true,
"NumberOfDevicesOnDIMM": 4,
"NumberOfMemChannels": 1,
"PowerAnalysis": true,
"SimulationName": "orgr_8b_std_timings_ddr3",
"SimulationProgressBar": true,
"ThermalSimulation": false,
"UseMalloc": false,
"WindowSize": 1000
}
}

21
DRAMSys/library/resources/configs/simulator/orgr_ddr4.json
View File

@@ -1,21 +0,0 @@
{
"simconfig": {
"AddressOffset": 0,
"CheckTLM2Protocol": false,
"DatabaseRecording": true,
"Debug": false,
"ECCControllerMode": "Disabled",
"EnableWindowing": true,
"ErrorCSVFile": "",
"ErrorChipSeed": 42,
"NumberOfDevicesOnDIMM": 4,
"NumberOfMemChannels": 1,
"PowerAnalysis": true,
"SimulationName": "orgr_ddr4",
"SimulationProgressBar": true,
"StoreMode": "NoStorage",
"ThermalSimulation": false,
"UseMalloc": false,
"WindowSize": 1000
}
}

21
DRAMSys/library/resources/configs/simulator/rgrsimcfg-gem5-fs.json
View File

@@ -1,21 +0,0 @@
{
"simconfig": {
"AddressOffset": 2147483648,
"CheckTLM2Protocol": false,
"DatabaseRecording": false,
"Debug": false,
"ECCControllerMode": "Disabled",
"EnableWindowing": true,
"ErrorCSVFile": "",
"ErrorChipSeed": 42,
"NumberOfDevicesOnDIMM": 4,
"NumberOfMemChannels": 1,
"PowerAnalysis": true,
"SimulationName": "rgr",
"SimulationProgressBar": true,
"StoreMode": "Store",
"ThermalSimulation": false,
"UseMalloc": true,
"WindowSize": 1000
}
}

21
DRAMSys/library/resources/configs/simulator/rgrsimcfg-gem5-se.json
View File

@@ -1,21 +0,0 @@
{
"simconfig": {
"AddressOffset": 0,
"CheckTLM2Protocol": false,
"DatabaseRecording": true,
"Debug": false,
"ECCControllerMode": "Disabled",
"EnableWindowing": true,
"ErrorCSVFile": "",
"ErrorChipSeed": 42,
"NumberOfDevicesOnDIMM": 4,
"NumberOfMemChannels": 1,
"PowerAnalysis": true,
"SimulationName": "rgr",
"SimulationProgressBar": true,
"StoreMode": "Store",
"ThermalSimulation": false,
"UseMalloc": false,
"WindowSize": 1000
}
}

21
DRAMSys/library/resources/configs/simulator/rgrsimcfg.json
View File

@@ -1,21 +0,0 @@
{
"simconfig": {
"AddressOffset": 0,
"CheckTLM2Protocol": false,
"DatabaseRecording": true,
"Debug": false,
"ECCControllerMode": "Disabled",
"EnableWindowing": true,
"ErrorCSVFile": "",
"ErrorChipSeed": 42,
"NumberOfDevicesOnDIMM": 4,
"NumberOfMemChannels": 1,
"PowerAnalysis": true,
"SimulationName": "rgr",
"SimulationProgressBar": true,
"StoreMode": "NoStorage",
"ThermalSimulation": false,
"UseMalloc": false,
"WindowSize": 1000
}
}

16
DRAMSys/library/resources/configs/simulator/sms.json
View File

@@ -1,16 +0,0 @@
{
"simconfig": {
"CheckTLM2Protocol": false,
"DatabaseRecording": true,
"Debug": false,
"EnableWindowing": true,
"NumberOfDevicesOnDIMM": 1,
"NumberOfMemChannels": 4,
"PowerAnalysis": true,
"SimulationName": "sms",
"SimulationProgressBar": true,
"ThermalSimulation": false,
"UseMalloc": false,
"WindowSize": 1000
}
}

4
DRAMSys/library/resources/configs/simulator/wideio_thermal.json
View File

@@ -8,11 +8,11 @@
"ErrorCSVFile": "../../DRAMSys/library/resources/error/wideio.csv",
"ErrorChipSeed": 42,
"NumberOfDevicesOnDIMM": 1,
"NumberOfMemChannels": 1,
"NumberOfMemChannels": 4,
"PowerAnalysis": true,
"SimulationName": "wideio",
"SimulationProgressBar": true,
"StoreMode": "NoStorage",
"StoreMode": "ErrorModel",
"ThermalSimulation": true,
"UseMalloc": false,
"WindowSize": 1000

259
DRAMSys/library/resources/resources.pri
View File

@@ -1,259 +0,0 @@
# Relative paths to "DRAMSys/library" because this file is included in
# "DRAMSys/library/library.pro"
# Simulation Files
DISTFILES += resources/simulations/ddr3-example.xml
DISTFILES += resources/simulations/ddr3-single-device.xml
DISTFILES += resources/simulations/ddr3-rgr.xml
DISTFILES += resources/simulations/ddr3-rgr00.xml
DISTFILES += resources/simulations/ddr3-rgr01.xml
DISTFILES += resources/simulations/ddr3-rgr02.xml
DISTFILES += resources/simulations/ddr3-rgr03.xml
DISTFILES += resources/simulations/ddr3-rgr04.xml
DISTFILES += resources/simulations/ddr3-rgr05.xml
DISTFILES += resources/simulations/ddr3-rgr06.xml
DISTFILES += resources/simulations/ddr3-rgr07.xml
DISTFILES += resources/simulations/ddr3-rgr08.xml
DISTFILES += resources/simulations/ddr3-rgr09.xml
DISTFILES += resources/simulations/ddr3-rgr10.xml
DISTFILES += resources/simulations/ddr3-rgr11.xml
DISTFILES += resources/simulations/ddr3-rgr12.xml
DISTFILES += resources/simulations/ddr3-rgr13.xml
DISTFILES += resources/simulations/ddr3-rgr14.xml
DISTFILES += resources/simulations/ddr3-rgr15.xml
DISTFILES += resources/simulations/ddr3-rgr16.xml
DISTFILES += resources/simulations/ddr3-rgr17.xml
DISTFILES += resources/simulations/ddr3-rgr18.xml
DISTFILES += resources/simulations/ddr3-rgr19.xml
DISTFILES += resources/simulations/ddr3-rgr20.xml
DISTFILES += resources/simulations/ddr3-rgr21.xml
DISTFILES += resources/simulations/ddr3-rgr22.xml
DISTFILES += resources/simulations/ddr3-rgr23.xml
DISTFILES += resources/simulations/ddr3-rgr24.xml
DISTFILES += resources/simulations/ddr3-rgr25.xml
DISTFILES += resources/simulations/ddr3-rgr26.xml
DISTFILES += resources/simulations/ddr3-rgr27.xml
DISTFILES += resources/simulations/ddr3-rgr28.xml
DISTFILES += resources/simulations/ddr3-rgr29.xml
DISTFILES += resources/simulations/ddr3-rgr30.xml
DISTFILES += resources/simulations/ddr3-rgr31.xml
DISTFILES += resources/simulations/ddr3-rgr32.xml
DISTFILES += resources/simulations/ddr3-rgr33.xml
DISTFILES += resources/simulations/ddr3-rgr34.xml
DISTFILES += resources/simulations/ddr3-rgr35.xml
DISTFILES += resources/simulations/ddr3-rgr36.xml
DISTFILES += resources/simulations/ddr3-rgr37.xml
DISTFILES += resources/simulations/ddr3-rgr38.xml
DISTFILES += resources/simulations/ddr3-rgr39.xml
DISTFILES += resources/simulations/ddr3-rgr40.xml
DISTFILES += resources/simulations/ddr3-rgr41.xml
DISTFILES += resources/simulations/ddr3-rgr42.xml
DISTFILES += resources/simulations/ddr3-rgr43.xml
DISTFILES += resources/simulations/ddr3-rgr44.xml
DISTFILES += resources/simulations/wideio-example.xml
DISTFILES += resources/simulations/wideio-ecc.xml
DISTFILES += resources/simulations/ddr3-ecc.xml
DISTFILES += resources/simulations/sms-example.xml
DISTFILES += resources/simulations/ddr3_postpone_ref_test.xml
DISTFILES += resources/simulations/rgrsim.xml
DISTFILES += resources/simulations/lpddr4-single-device.xml
# Simulator Files
DISTFILES += resources/configs/simulator/wideio.xml
DISTFILES += resources/configs/simulator/ddr3.xml
DISTFILES += resources/configs/simulator/ddr3-single-device.xml
DISTFILES += resources/configs/simulator/wideio_thermal.xml
DISTFILES += resources/configs/simulator/wideio_ecc.xml
DISTFILES += resources/configs/simulator/ddr3_ecc.xml
DISTFILES += resources/configs/simulator/sms.xml
DISTFILES += resources/configs/simulator/rgrsimcfg.xml
DISTFILES += resources/configs/simulator/lpddr4.xml
# Scripts
DISTFILES += resources/scripts/address_scrambler.pl
DISTFILES += resources/scripts/createTraceDB.sql
DISTFILES += resources/scripts/stride_detection.pl
DISTFILES += resources/scripts/analyse_trace.pl
DISTFILES += resources/scripts/video_rendering/temperatur.job.pl
DISTFILES += resources/scripts/video_rendering/temperatur.pl
DISTFILES += resources/scripts/video_rendering/Makefile
DISTFILES += resources/scripts/DRAMSylva/collect.sh
DISTFILES += resources/scripts/DRAMSylva/common.in
DISTFILES += resources/scripts/DRAMSylva/DRAMSylva.jobscript
DISTFILES += resources/scripts/DRAMSylva/DRAMSylva.sh
DISTFILES += resources/scripts/DRAMSylva/DRAMSylvaCSVPlot.py
DISTFILES += resources/scripts/DRAMSylva/DRAMSyrup.py
DISTFILES += resources/scripts/DRAMSylva/gem5ilva.jobscript
DISTFILES += resources/scripts/DRAMSylva/gem5ilva.sh
DISTFILES += resources/scripts/DRAMSylva/gem5ilva_fs.jobscript
DISTFILES += resources/scripts/DRAMSylva/gem5ilva_fs.sh
DISTFILES += resources/scripts/DRAMSylva/LICENSE
DISTFILES += resources/scripts/DRAMSylva/README
DISTFILES += resources/scripts/DRAMSylva/configs_json/configs.json
DISTFILES += resources/scripts/DRAMSylva/configs_json/configsbrc.json
DISTFILES += resources/scripts/DRAMSylva/configs_json/configsbrc1x.json
DISTFILES += resources/scripts/DRAMSylva/configs_json/configsbrc1x_gem5.json
DISTFILES += resources/scripts/DRAMSylva/configs_json/configsbrc2x.json
DISTFILES += resources/scripts/DRAMSylva/configs_json/configsbrc2x_gem5.json
DISTFILES += resources/scripts/DRAMSylva/configs_json/configsbrc4x.json
DISTFILES += resources/scripts/DRAMSylva/configs_json/configsbrc4x_gem5.json
DISTFILES += resources/scripts/DRAMSylva/configs_json/configsrbc.json
DISTFILES += resources/scripts/DRAMSylva/configs_json/configsrbc1x.json
DISTFILES += resources/scripts/DRAMSylva/configs_json/configsrbc1x_gem5.json
DISTFILES += resources/scripts/DRAMSylva/configs_json/configsrbc1x_gem5_fs.json
DISTFILES += resources/scripts/DRAMSylva/configs_json/configsrbc1x_gem5_fs_nodb.json
DISTFILES += resources/scripts/DRAMSylva/configs_json/configsrbc2x.json
DISTFILES += resources/scripts/DRAMSylva/configs_json/configsrbc2x_gem5.json
DISTFILES += resources/scripts/DRAMSylva/configs_json/configsrbc4x.json
DISTFILES += resources/scripts/DRAMSylva/configs_json/configsrbc4x_gem5.json
DISTFILES += resources/scripts/DRAMSylva/configs_json/ref.json
DISTFILES += resources/scripts/DRAMSylva/configs_json/ref_bw.json
DISTFILES += resources/scripts/trace_gen.py
DISTFILES += resources/scripts/traceGenerationForNNTraining.pl
# Trace Files
DISTFILES += resources/traces/chstone-aes_32.stl
DISTFILES += resources/traces/test2.stl
DISTFILES += resources/traces/voco2.stl
DISTFILES += resources/traces/chstone-bf_32.stl
DISTFILES += resources/traces/trace2.stl
DISTFILES += resources/traces/chstone-sha_32.stl
DISTFILES += resources/traces/prettyTest
DISTFILES += resources/traces/test.stl
DISTFILES += resources/traces/mediabench-mpeg2encode_32.stl
DISTFILES += resources/traces/mediabench-unepic_32.stl
DISTFILES += resources/traces/chstone-mips_32.stl
DISTFILES += resources/traces/mediabench-gsmdecode_32.stl
DISTFILES += resources/traces/mediabench-c-ray-1.1_32.stl
DISTFILES += resources/traces/eiersalat.stl
DISTFILES += resources/traces/mediabench-fractal_32.stl
DISTFILES += resources/traces/wideio_multi_channel.stl
DISTFILES += resources/traces/mediabench-g721decode_32.stl
DISTFILES += resources/traces/mediabench-jpegencode_32.stl
DISTFILES += resources/traces/chstone-jpeg_32.stl
DISTFILES += resources/traces/trace.stl
DISTFILES += resources/traces/mediabench-h263decode_32.stl
DISTFILES += resources/traces/mediabench-h263encode_32.stl
DISTFILES += resources/traces/mediabench-mpeg2decode_32.stl
DISTFILES += resources/traces/chstone-gsm_32.stl
DISTFILES += resources/traces/mediabench-epic_32.stl
DISTFILES += resources/traces/empty.stl
DISTFILES += resources/traces/mediabench-adpcmencode_32.stl
DISTFILES += resources/traces/chstone-adpcm_32.stl
DISTFILES += resources/traces/mediabench-jpegdecode_32.stl
DISTFILES += resources/traces/mediabench-g721encode_32.stl
DISTFILES += resources/traces/small.stl
DISTFILES += resources/traces/chstone-motion_32.stl
DISTFILES += resources/traces/mediabench-adpcmdecode_32.stl
DISTFILES += resources/traces/ddr3_example.stl
DISTFILES += resources/traces/ddr3_exampleb.stl
DISTFILES += resources/traces/ddr3_rgr.stl
DISTFILES += resources/traces/ddr3_single_dev_example.stl
DISTFILES += resources/traces/ddr3_SAMSUNG_M471B5674QH0_DIMM_example.stl
DISTFILES += resources/traces/test_ecc.stl
DISTFILES += resources/traces/sms_t1.stl
DISTFILES += resources/traces/sms_t2.stl
DISTFILES += resources/traces/sms_t3.stl
DISTFILES += resources/traces/sms_t4.stl
DISTFILES += resources/traces/ddr3_postpone_ref_test_1.stl
DISTFILES += resources/traces/ddr3_postpone_ref_test_2.stl
DISTFILES += resources/traces/ddr3_postpone_ref_test_3.stl
DISTFILES += resources/traces/ip*.stl
DISTFILES += resources/traces/rgr*.stl
DISTFILES += resources/traces/read_write_switch.stl
# Memory Controller Configs
DISTFILES += resources/configs/mcconfigs/fifoStrict.xml
DISTFILES += resources/configs/mcconfigs/fifo.xml
DISTFILES += resources/configs/mcconfigs/fr_fcfs.xml
DISTFILES += resources/configs/mcconfigs/par_bs.xml
DISTFILES += resources/configs/mcconfigs/fifo_ecc.xml
DISTFILES += resources/configs/mcconfigs/sms.xml
DISTFILES += resources/configs/mcconfigs/rgrmccfg.xml
DISTFILES += resources/configs/mcconfigs/grp.xml
DISTFILES += resources/configs/mcconfigs/fr_fcfs_rp.xml
DISTFILES += resources/configs/mcconfigs/fr_fcfs_grp.xml
# Memspecs
DISTFILES += resources/configs/memspecs/memspec.dtd
DISTFILES += resources/configs/memspecs/MatzesWideIO.xml
DISTFILES += resources/configs/memspecs/DDR4.xml
DISTFILES += resources/configs/memspecs/MatzesWideIO-short.xml
DISTFILES += resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G.xml
DISTFILES += resources/configs/memspecs/JEDEC_256Mb_WIDEIO_SDR-200_128bit.xml
DISTFILES += resources/configs/memspecs/JEDEC_256Mb_WIDEIO_SDR-266_128bit.xml
DISTFILES += resources/configs/memspecs/MICRON_1Gb_DDR2-1066_16bit_H.xml
DISTFILES += resources/configs/memspecs/MICRON_1Gb_DDR2-800_16bit_H.xml
DISTFILES += resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G.xml
DISTFILES += resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G_2s.xml
DISTFILES += resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G_3s.xml
DISTFILES += resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G_mu.xml
DISTFILES += resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G.xml
DISTFILES += resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G_2s.xml
DISTFILES += resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G_3s.xml
DISTFILES += resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G_mu.xml
DISTFILES += resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G.xml
DISTFILES += resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_2s.xml
DISTFILES += resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_3s.xml
DISTFILES += resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_mu.xml
DISTFILES += resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D.xml
DISTFILES += resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D_2s.xml
DISTFILES += resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D_3s.xml
DISTFILES += resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D_mu.xml
DISTFILES += resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D.xml
DISTFILES += resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D_2s.xml
DISTFILES += resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D_3s.xml
DISTFILES += resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D_mu.xml
DISTFILES += resources/configs/memspecs/MICRON_2Gb_LPDDR-266_16bit_A.xml
DISTFILES += resources/configs/memspecs/MICRON_2Gb_LPDDR-333_16bit_A.xml
DISTFILES += resources/configs/memspecs/MICRON_2Gb_LPDDR2-1066-S4_16bit_A.xml
DISTFILES += resources/configs/memspecs/MICRON_2Gb_LPDDR2-800-S4_16bit_A.xml
DISTFILES += resources/configs/memspecs/MICRON_4Gb_DDR4-1866_8bit_A.xml
DISTFILES += resources/configs/memspecs/MICRON_4Gb_DDR4-2400_8bit_A.xml
DISTFILES += resources/configs/memspecs/MICRON_4Gb_LPDDR3-1333_32bit_A.xml
DISTFILES += resources/configs/memspecs/MICRON_4Gb_LPDDR3-1600_32bit_A.xml
DISTFILES += resources/configs/memspecs/SAMSUNG_K4B1G1646E_1Gb_DDR3-1600_16bit.xml
DISTFILES += resources/configs/memspecs/SAMSUNG_K4B4G1646Q_4Gb_DDR3-1066_16bit.xml
DISTFILES += resources/configs/memspecs/orgr_16Gb_ddr4.xml
DISTFILES += resources/configs/memspecs/wideio.xml
DISTFILES += resources/configs/memspecs/wideio_less_refresh.xml
DISTFILES += resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_less_refresh.xml
DISTFILES += resources/configs/memspecs/rgrspec.xml
DISTFILES += resources/configs/memspecs/MICRON_6Gb_LPDDR4-3200_NDA_NDA_NDA.xml
# Address Mapping Configs
DISTFILES += resources/configs/amconfigs/am_ddr3.xml
DISTFILES += resources/configs/amconfigs/am_ddr3_x16_brc.xml
DISTFILES += resources/configs/amconfigs/am_ddr3_x16_rbc.xml
DISTFILES += resources/configs/amconfigs/am_ddr3_8x1Gbx8_dimm_p1KB_brc.xml
DISTFILES += resources/configs/amconfigs/am_ddr3_8x1Gbx8_dimm_p1KB_rbc.xml
DISTFILES += resources/configs/amconfigs/am_ddr3_8x2Gbx8_dimm_p1KB_brc.xml
DISTFILES += resources/configs/amconfigs/am_ddr3_8x2Gbx8_dimm_p1KB_rbc.xml
DISTFILES += resources/configs/amconfigs/resources/configs/amconfigs/am_ddr4.xml
DISTFILES += resources/configs/amconfigs/am_highHits.xml
DISTFILES += resources/configs/amconfigs/am_highPara.xml
DISTFILES += resources/configs/amconfigs/am_wideio.xml
DISTFILES += resources/configs/amconfigs/am_lowHits.xml
DISTFILES += resources/configs/amconfigs/am_lowPara.xml
DISTFILES += resources/configs/amconfigs/am_wideioFourBanks.xml
DISTFILES += resources/configs/amconfigs/am_ddr3_1Gbx8_p1KB_brc.xml
DISTFILES += resources/configs/amconfigs/am_ddr3_4x4Gbx16_dimm_p2KB_brc.xml
DISTFILES += resources/configs/amconfigs/am_ddr3_4x4Gbx16_dimm_p2KB_rbc.xml
DISTFILES += resources/configs/amconfigs/rgram.xml
DISTFILES += resources/configs/amconfigs/am_test_congen_output.json
DISTFILES += resources/configs/amconfigs/am_lpddr4.xml
# Thermal Simulation configs
DISTFILES += resources/configs/thermalsim/core.flp
DISTFILES += resources/configs/thermalsim/mem.flp
DISTFILES += resources/configs/thermalsim/powerInfo.xml
DISTFILES += resources/configs/thermalsim/stack.stk
DISTFILES += resources/configs/thermalsim/config.xml
# Add DRAMPower
DISTFILES += src/common/third_party/DRAMPower/*
DISTFILES += src/common/third_party/DRAMPower/src/*
# Error Simulation data
DISTFILES += resources/error/wideio.csv

2
DRAMSys/library/resources/simulations/ddr3-boot-linux.json
View File

@@ -7,4 +7,4 @@
"simulationid": "ddr3-boot-linux",
"thermalconfig": "config.json"
}
}
}

2
DRAMSys/library/resources/simulations/ddr3-gem5-se.json
View File

@@ -7,4 +7,4 @@
"simulationid": "ddr3-gem5-se",
"thermalconfig": "config.json"
}
}
}

10
DRAMSys/library/resources/simulations/rgrsim-gem5-fs.json
View File

@@ -1,10 +0,0 @@
{
"simulation": {
"addressmapping": "rgram.json",
"mcconfig": "rgrmccfg.json",
"memspec": "rgrspec.json",
"simconfig": "rgrsimcfg-gem5-fs.json",
"simulationid": "rgrsim-gem5-fs",
"thermalconfig": "config.json"
}
}

10
DRAMSys/library/resources/simulations/rgrsim-gem5-se.json
View File

@@ -1,10 +0,0 @@
{
"simulation": {
"addressmapping": "rgram.json",
"mcconfig": "rgrmccfg.json",
"memspec": "rgrspec.json",
"simconfig": "rgrsimcfg-gem5-se.json",
"simulationid": "rgrsim-gem5-se",
"thermalconfig": "config.json"
}
}

16
DRAMSys/library/resources/simulations/rgrsim.json
View File

@@ -1,16 +0,0 @@
{
"simulation": {
"addressmapping": "rgram.json",
"mcconfig": "rgrmccfg.json",
"memspec": "rgrspec.json",
"simconfig": "rgrsimcfg.json",
"simulationid": "rgrsimid",
"thermalconfig": "config.json",
"tracesetup": [
{
"clkMhz": 1000,
"name": "1_720x1280_64-Pixelgroesse_imb3_str1_scram_ddr4_8b_same_clock.stl"
}
]
}
}

24
DRAMSys/library/resources/simulations/sms-example.json
View File

@@ -1,24 +0,0 @@
{
"simulation": {
"addressmapping": "am_wideio.json",
"mcconfig": "sms.json",
"memspec": "wideio.json",
"simconfig": "sms.json",
"simulationid": "sms-example",
"thermalconfig": "config.json",
"tracesetup": [
{
"clkMhz": 1000,
"name": "random.stl"
},
{
"clkMhz": 1000,
"name": "chstone-adpcm_32.stl"
},
{
"clkMhz": 1000,
"name": "stream.stl"
}
]
}
}

16
DRAMSys/library/resources/simulations/wideio-ecc.json
View File

@@ -1,16 +0,0 @@
{
"simulation": {
"addressmapping": "am_wideio.json",
"mcconfig": "fifo.json",
"memspec": "wideio_less_refresh.json",
"simconfig": "wideio_ecc.json",
"simulationid": "wideio-ecc",
"thermalconfig": "config.json",
"tracesetup": [
{
"clkMhz": 1000,
"name": "test_ecc.stl"
}
]
}
}

4
DRAMSys/library/resources/simulations/wideio-example.json
View File

@@ -1,8 +1,8 @@
{
"simulation": {
"addressmapping": "am_wideio.json",
"addressmapping": "am_wideio_4x256Mb_rbc.json",
"mcconfig": "fifoStrict.json",
"memspec": "wideio.json",
"memspec": "JEDEC_256Mb_WIDEIO-200_128bit.json",
"simconfig": "wideio.json",
"simulationid": "wideio-example",
"thermalconfig": "config.json",

16
DRAMSys/library/resources/simulations/wideio-thermal.json Normal file
View File

@@ -0,0 +1,16 @@
{
"simulation": {
"addressmapping": "am_wideio_4x256Mb_rbc.json",
"mcconfig": "fr_fcfs.json",
"memspec": "JEDEC_256Mb_WIDEIO-200_128bit.json",
"simconfig": "wideio_thermal.json",
"simulationid": "wideio-example",
"thermalconfig": "config.json",
"tracesetup": [
{
"clkMhz": 1000,
"name": "test_error.stl"
}
]
}
}

3248
DRAMSys/library/resources/traces/prettyTest
View File

File diff suppressed because it is too large Load Diff

14
DRAMSys/library/src/common/DebugManager.h
View File

@@ -50,10 +50,19 @@
class DebugManager
{
public:
static DebugManager &getInstance()
{
static DebugManager _instance;
return _instance;
}
~DebugManager();
DEF_SINGLETON(DebugManager);
private:
DebugManager();
DebugManager(const DebugManager &);
DebugManager & operator = (const DebugManager &);
public:
bool writeToConsole;
bool writeToFile;
@@ -62,9 +71,6 @@ public:
void openDebugFile(std::string filename);
private:
DebugManager();
DebugManager(const DebugManager &) {}
ofstream debugFile;
};
#endif

30
DRAMSys/library/src/common/TlmRecorder.cpp
View File

@@ -363,21 +363,21 @@ void TlmRecorder::insertCommandLengths()
{
MemSpec *memSpec = Configuration::getInstance().memSpec;
sqlite3_bind_int(insertCommandLengthsStatement, 1, memSpec->commandLengthInCycles[Command::ACT]);
sqlite3_bind_int(insertCommandLengthsStatement, 2, memSpec->commandLengthInCycles[Command::PRE]);
sqlite3_bind_int(insertCommandLengthsStatement, 3, memSpec->commandLengthInCycles[Command::PREA]);
sqlite3_bind_int(insertCommandLengthsStatement, 4, memSpec->commandLengthInCycles[Command::RD]);
sqlite3_bind_int(insertCommandLengthsStatement, 5, memSpec->commandLengthInCycles[Command::RDA]);
sqlite3_bind_int(insertCommandLengthsStatement, 6, memSpec->commandLengthInCycles[Command::WR]);
sqlite3_bind_int(insertCommandLengthsStatement, 7, memSpec->commandLengthInCycles[Command::WRA]);
sqlite3_bind_int(insertCommandLengthsStatement, 8, memSpec->commandLengthInCycles[Command::REFA]);
sqlite3_bind_int(insertCommandLengthsStatement, 9, memSpec->commandLengthInCycles[Command::REFB]);
sqlite3_bind_int(insertCommandLengthsStatement, 10, memSpec->commandLengthInCycles[Command::PDEA]);
sqlite3_bind_int(insertCommandLengthsStatement, 11, memSpec->commandLengthInCycles[Command::PDXA]);
sqlite3_bind_int(insertCommandLengthsStatement, 12, memSpec->commandLengthInCycles[Command::PDEP]);
sqlite3_bind_int(insertCommandLengthsStatement, 13, memSpec->commandLengthInCycles[Command::PDXP]);
sqlite3_bind_int(insertCommandLengthsStatement, 14, memSpec->commandLengthInCycles[Command::SREFEN]);
sqlite3_bind_int(insertCommandLengthsStatement, 15, memSpec->commandLengthInCycles[Command::SREFEX]);
sqlite3_bind_int(insertCommandLengthsStatement, 1, memSpec->getCommandLength(Command::ACT) / memSpec->tCK);
sqlite3_bind_int(insertCommandLengthsStatement, 2, memSpec->getCommandLength(Command::PRE) / memSpec->tCK);
sqlite3_bind_int(insertCommandLengthsStatement, 3, memSpec->getCommandLength(Command::PREA) / memSpec->tCK);
sqlite3_bind_int(insertCommandLengthsStatement, 4, memSpec->getCommandLength(Command::RD) / memSpec->tCK);
sqlite3_bind_int(insertCommandLengthsStatement, 5, memSpec->getCommandLength(Command::RDA) / memSpec->tCK);
sqlite3_bind_int(insertCommandLengthsStatement, 6, memSpec->getCommandLength(Command::WR) / memSpec->tCK);
sqlite3_bind_int(insertCommandLengthsStatement, 7, memSpec->getCommandLength(Command::WRA) / memSpec->tCK);
sqlite3_bind_int(insertCommandLengthsStatement, 8, memSpec->getCommandLength(Command::REFA) / memSpec->tCK);
sqlite3_bind_int(insertCommandLengthsStatement, 9, memSpec->getCommandLength(Command::REFB) / memSpec->tCK);
sqlite3_bind_int(insertCommandLengthsStatement, 10, memSpec->getCommandLength(Command::PDEA) / memSpec->tCK);
sqlite3_bind_int(insertCommandLengthsStatement, 11, memSpec->getCommandLength(Command::PDXA) / memSpec->tCK);
sqlite3_bind_int(insertCommandLengthsStatement, 12, memSpec->getCommandLength(Command::PDEP) / memSpec->tCK);
sqlite3_bind_int(insertCommandLengthsStatement, 13, memSpec->getCommandLength(Command::PDXP) / memSpec->tCK);
sqlite3_bind_int(insertCommandLengthsStatement, 14, memSpec->getCommandLength(Command::SREFEN) / memSpec->tCK);
sqlite3_bind_int(insertCommandLengthsStatement, 15, memSpec->getCommandLength(Command::SREFEX) / memSpec->tCK);
executeSqlStatement(insertCommandLengthsStatement);
}

85
DRAMSys/library/src/common/utils.cpp
View File

@@ -44,6 +44,7 @@
#include <sstream>
using namespace tlm;
using json = nlohmann::json;
bool TimeInterval::timeIsInInterval(sc_time time)
{
@@ -56,23 +57,23 @@ bool TimeInterval::intersects(TimeInterval other)
|| this->timeIsInInterval(other.start);
}
sc_time getDistance(sc_time a, sc_time b)
sc_time TimeInterval::getLength()
{
if (a > b)
return a - b;
if (end > start)
return end - start;
else
return b - a;
return start - end;
}
nlohmann::json parseJSON(std::string path)
json parseJSON(std::string path)
{
try
{
// parsing input with a syntax error
nlohmann::json j = nlohmann::json::parse(std::ifstream(path));
json j = json::parse(std::ifstream(path));
return j;
}
catch (nlohmann::json::parse_error& e)
catch (json::parse_error& e)
{
// output exception information
std::cout << "Error while trying to parse file: " << path << '\n'
@@ -80,6 +81,58 @@ nlohmann::json parseJSON(std::string path)
}
}
bool parseBool(json &obj, std::string name)
{
if (!obj.empty())
{
if (obj.is_boolean())
return obj;
else
throw std::invalid_argument("Expected type for '" + name + "': bool");
}
else
SC_REPORT_FATAL("Query json", ("Parameter '" + name + "' does not exist.").c_str());
}
unsigned int parseUint(json &obj, std::string name)
{
if (!obj.empty())
{
if (obj.is_number_unsigned())
return obj;
else
throw std::invalid_argument("Expected type for '" + name + "': unsigned int");
}
else
SC_REPORT_FATAL("Query json", ("Parameter '" + name + "' does not exist.").c_str());
}
double parseUdouble(json &obj, std::string name)
{
if (!obj.empty())
{
if (obj.is_number() && (obj > 0))
return obj;
else
throw std::invalid_argument("Expected type for '" + name + "': positive double");
}
else
SC_REPORT_FATAL("Query json", ("Parameter '" + name + "' does not exist.").c_str());
}
std::string parseString(json &obj, std::string name)
{
if (!obj.empty())
{
if (obj.is_string())
return obj;
else
throw std::invalid_argument("Expected type for '" + name + "': string");
}
else
SC_REPORT_FATAL("Query json", ("Parameter '" + name + "' does not exist.").c_str());
}
void setUpDummy(tlm_generic_payload &payload, Rank rank, Bank bank)
{
payload.set_address(bank.getStartAddress());
@@ -91,22 +144,4 @@ void setUpDummy(tlm_generic_payload &payload, Rank rank, Bank bank)
payload.set_streaming_width(0);
payload.set_extension(new DramExtension(Thread(UINT_MAX), rank, BankGroup(0),
bank, Row(0), Column(0), 0, 0));
// payload takes ownership
// TODO: Dummies muessen noch banggruppe und rank sauber bekommen .. noch was ueberlegen!!!
}
std::string getFileName(std::string uri)
{
// Remove directory if present.
// Do this before extension removal incase directory has a period character.
const size_t last_slash_idx = uri.find_last_of("\\/");
if (std::string::npos != last_slash_idx)
uri.erase(0, last_slash_idx + 1);
// Remove extension if present.
const size_t period_idx = uri.rfind('.');
if (std::string::npos != period_idx)
uri.erase(period_idx);
return uri;
}

47
DRAMSys/library/src/common/utils.h
View File

@@ -50,50 +50,18 @@
#include <sstream>
#include "../common/third_party/nlohmann/single_include/nlohmann/json.hpp"
#define DEF_SINGLETON( NAME ) \
public: \
static NAME& getInstance() \
{ \
static NAME _instance; \
return _instance; \
}
//TODO : move to timing specific header
sc_time getDistance(sc_time a, sc_time b);
struct TimeInterval {
class TimeInterval
{
public:
sc_time start, end;
TimeInterval() : start(SC_ZERO_TIME), end(SC_ZERO_TIME) {}
TimeInterval(sc_time start, sc_time end) : start(start), end(end) {}
sc_time getLength()
{
return getDistance(start, end);
}
sc_time getLength();
bool timeIsInInterval(sc_time time);
bool intersects(TimeInterval other);
};
template<typename Key, typename Val>
inline Val getElementFromMap(const std::map<Key, Val> &m, Key key)
{
if (m.count(key) == 0) {
SC_REPORT_FATAL("Map", "Element not in map");
}
return m.at(key);
}
template<typename T>
bool isIn(const T &value, const std::vector<T> &collection)
{
for (T t : collection) {
if (t == value)
return true;
}
return false;
}
constexpr const char headline[] =
"===========================================================================";
@@ -134,10 +102,11 @@ static inline void loadbar(unsigned int x,
std::cout << "|\r" << std::flush;
}
//TODO : Move to other source specific
std::string getFileName(std::string uri);
nlohmann::json parseJSON(std::string path);
bool parseBool(nlohmann::json &obj, std::string name);
unsigned int parseUint(nlohmann::json &obj, std::string name);
double parseUdouble(nlohmann::json &obj, std::string name);
std::string parseString(nlohmann::json &obj, std::string name);
void setUpDummy(tlm::tlm_generic_payload &payload, Rank rank = Rank(0), Bank bank = Bank(0));

64
DRAMSys/library/src/configuration/Configuration.cpp
View File

@@ -41,7 +41,17 @@
#include <cassert>
#include "Configuration.h"
#include "ConfigurationLoader.h"
#include "memspec/MemSpecDDR3.h"
#include "memspec/MemSpecDDR4.h"
#include "memspec/MemSpecWideIO.h"
#include "memspec/MemSpecLPDDR4.h"
#include "memspec/MemSpecWideIO2.h"
#include "memspec/MemSpecHBM2.h"
#include "memspec/MemSpecGDDR5.h"
#include "memspec/MemSpecGDDR5X.h"
#include "memspec/MemSpecGDDR6.h"
using json = nlohmann::json;
std::string Configuration::memspecUri = "";
std::string Configuration::mcconfigUri = "";
@@ -257,3 +267,55 @@ unsigned int Configuration::adjustNumBytesAfterECC(unsigned nBytes)
return 0;
}
}
void Configuration::loadSimConfig(Configuration &config, std::string simconfigUri)
{
json doc = parseJSON(simconfigUri);
for (auto& x : doc["simconfig"].items())
config.setParameter(x.key(), x.value());
}
void Configuration::loadTemperatureSimConfig(Configuration &config, std::string thermalsimconfigUri)
{
json doc = parseJSON(thermalsimconfigUri);
for (auto& x : doc["thermalsimconfig"].items())
config.setParameter(x.key(), x.value());
}
void Configuration::loadMCConfig(Configuration &config, std::string mcconfigUri)
{
config.mcconfigUri = mcconfigUri;
json doc = parseJSON(mcconfigUri);
for (auto& x : doc["mcconfig"].items())
config.setParameter(x.key(), x.value());
}
void Configuration::loadMemSpec(Configuration &config, std::string memspecUri)
{
config.memspecUri = memspecUri;
json doc = parseJSON(memspecUri);
json jMemSpec = doc["memspec"];
std::string memoryType = jMemSpec["memoryType"];
if (memoryType == "DDR3")
memSpec = new MemSpecDDR3(jMemSpec);
else if (memoryType == "DDR4")
memSpec = new MemSpecDDR4(jMemSpec);
else if (memoryType == "LPDDR4")
memSpec = new MemSpecLPDDR4(jMemSpec);
else if (memoryType == "WIDEIO_SDR")
memSpec = new MemSpecWideIO(jMemSpec);
else if (memoryType == "WIDEIO2")
memSpec = new MemSpecWideIO2(jMemSpec);
else if (memoryType == "HBM2")
memSpec = new MemSpecHBM2(jMemSpec);
else if (memoryType == "GDDR5")
memSpec = new MemSpecGDDR5(jMemSpec);
else if (memoryType == "GDDR5X")
memSpec = new MemSpecGDDR5X(jMemSpec);
else if (memoryType == "GDDR6")
memSpec = new MemSpecGDDR6(jMemSpec);
else
SC_REPORT_FATAL("Configuration", "Unsupported DRAM type");
}

24
DRAMSys/library/src/configuration/Configuration.h
View File

@@ -50,16 +50,24 @@
#include "../error/eccbaseclass.h"
enum class StorageMode {NoStorage, Store, ErrorModel};
struct Configuration
class Configuration
{
public:
static Configuration &getInstance()
{
static Configuration _instance;
return _instance;
}
private:
Configuration() {}
Configuration(const Configuration &);
Configuration & operator = (const Configuration &);
public:
static std::string memspecUri;
static std::string mcconfigUri;
std::string pathToResources;
DEF_SINGLETON(Configuration);
// MCConfig:
std::string pagePolicy = "Open";
std::string scheduler = "Fifo";
@@ -72,6 +80,7 @@ struct Configuration
unsigned int refreshMaxPulledin = 0;
std::string powerDownPolicy = "NoPowerDown";
unsigned int powerDownTimeout = 3;
// SimConfig
std::string simulationName = "default";
bool databaseRecording = false;
@@ -108,6 +117,11 @@ struct Configuration
unsigned int getBytesPerBurst();
unsigned int adjustNumBytesAfterECC(unsigned bytes);
void setPathToResources(std::string path);
void loadMCConfig(Configuration &config, std::string amconfigUri);
void loadSimConfig(Configuration &config, std::string simconfigUri);
void loadMemSpec(Configuration &config, std::string memspecUri);
void loadTemperatureSimConfig(Configuration &config, std::string simconfigUri);
};
#endif // CONFIGURATION_H

736
DRAMSys/library/src/configuration/ConfigurationLoader.cpp
View File

@@ -1,736 +0,0 @@
/*
* Copyright (c) 2015, University of Kaiserslautern
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
* OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors:
* Janik Schlemminger
* Matthias Jung
* Lukas Steiner
* Luiza Correa
*/
#include "ConfigurationLoader.h"
using json = nlohmann::json;
void ConfigurationLoader::loadSimConfig(Configuration &config, std::string simconfigUri)
{
json doc = parseJSON(simconfigUri);
for (auto& x : doc["simconfig"].items())
config.setParameter(x.key(), x.value());
}
void ConfigurationLoader::loadTemperatureSimConfig(Configuration &config, std::string thermalsimconfigUri)
{
json doc = parseJSON(thermalsimconfigUri);
for (auto& x : doc["thermalsimconfig"].items())
config.setParameter(x.key(), x.value());
}
void ConfigurationLoader::loadMCConfig(Configuration &config, std::string mcconfigUri)
{
config.mcconfigUri = mcconfigUri;
json doc = parseJSON(mcconfigUri);
for (auto& x : doc["mcconfig"].items())
config.setParameter(x.key(), x.value());
}
void ConfigurationLoader::loadMemSpec(Configuration &config, std::string memspecUri)
{
config.memspecUri = memspecUri;
json doc = parseJSON(memspecUri);
json memspec = doc["memspec"];
std::string memoryType = memspec["memoryType"];
if (memoryType == "DDR3")
{
Configuration::getInstance().memSpec = new MemSpecDDR3();
loadCommons(config, memspec);
loadDDR3(config, memspec);
}
else if (memoryType == "DDR4")
{
Configuration::getInstance().memSpec = new MemSpecDDR4();
loadCommons(config, memspec);
loadDDR4(config, memspec);
}
else if (memoryType == "LPDDR4")
{
Configuration::getInstance().memSpec = new MemSpecLPDDR4();
loadCommons(config, memspec);
loadLPDDR4(config, memspec);
}
else if (memoryType == "WIDEIO_SDR")
{
Configuration::getInstance().memSpec = new MemSpecWideIO();
loadCommons(config, memspec);
loadWideIO(config, memspec);
}
else if (memoryType == "WIDEIO2")
{
Configuration::getInstance().memSpec = new MemSpecWideIO2();
loadCommons(config, memspec);
loadWideIO2(config, memspec);
}
else if (memoryType == "HBM2")
{
Configuration::getInstance().memSpec = new MemSpecHBM2();
loadCommons(config, memspec);
loadHBM2(config, memspec);
}
else if (memoryType == "GDDR5")
{
Configuration::getInstance().memSpec = new MemSpecGDDR5();
loadCommons(config, memspec);
loadGDDR5(config, memspec);
}
else if (memoryType == "GDDR5X")
{
Configuration::getInstance().memSpec = new MemSpecGDDR5X();
loadCommons(config, memspec);
loadGDDR5X(config, memspec);
}
else if (memoryType == "GDDR6")
{
Configuration::getInstance().memSpec = new MemSpecGDDR6();
loadCommons(config, memspec);
loadGDDR6(config, memspec);
}
else
SC_REPORT_FATAL("ConfigurationLoader", "Unsupported DRAM type");
}
void ConfigurationLoader::loadCommons(Configuration &config, json &memspec)
{
MemSpec *memSpec = config.memSpec;
memSpec->memoryId = parseString(memspec["memoryId"], "memoryId");
memSpec->memoryType = parseString(memspec["memoryType"], "memoryType");
// MemArchitecture
memSpec->burstLength = parseUint(memspec["memarchitecturespec"]["burstLength"],"burstLength");
memSpec->dataRate = parseUint(memspec["memarchitecturespec"]["dataRate"],"dataRate");
memSpec->numberOfRows = parseUint(memspec["memarchitecturespec"]["nbrOfRows"],"nbrOfRows");
memSpec->numberOfColumns = parseUint(memspec["memarchitecturespec"]["nbrOfColumns"],"nbrOfColumns");
memSpec->bitWidth = parseUint(memspec["memarchitecturespec"]["width"],"width");
// Clock
memSpec->fCKMHz = parseUdouble(memspec["memtimingspec"]["clkMhz"], "clkMhz");
memSpec->tCK = sc_time(1.0 / memSpec->fCKMHz, SC_US);
memSpec->burstDuration = memSpec->tCK * (memSpec->burstLength / memSpec->dataRate);
}
void ConfigurationLoader::loadDDR3(Configuration &config, json &memspec)
{
MemSpecDDR3 *memSpec = dynamic_cast<MemSpecDDR3 *>(config.memSpec);
if (memSpec == nullptr)
SC_REPORT_FATAL("ConfigurationLoader", "Wrong MemSpec chosen");
// MemArchitecture
std::string arch = "memarchitecturespec";
memSpec->numberOfRanks = parseUint(memspec[arch]["nbrOfRanks"],"nbrOfRanks");
memSpec->banksPerRank = parseUint(memspec[arch]["nbrOfBanks"],"nbrOfBanks");
memSpec->groupsPerRank = 1;
memSpec->banksPerGroup = memSpec->banksPerRank / memSpec->groupsPerRank;
memSpec->numberOfBanks = memSpec->banksPerRank * memSpec->numberOfRanks;
memSpec->numberOfBankGroups = memSpec->groupsPerRank * memSpec->numberOfRanks;
// MemTimings specific for DDR3
std::string timings = "memtimingspec";
memSpec->tCKE = memSpec->tCK * parseUint(memspec[timings]["CKE"], "CKE");
memSpec->tPD = memSpec->tCKE;
memSpec->tCKESR = memSpec->tCK * parseUint(memspec[timings]["CKESR"], "CKESR");
memSpec->tCKE = memSpec->tCK * parseUint(memspec[timings]["DQSCK"], "DQSCK");
memSpec->tRAS = memSpec->tCK * parseUint(memspec[timings]["RAS"], "RAS");
memSpec->tRC = memSpec->tCK * parseUint(memspec[timings]["RC"], "RC");
memSpec->tRCD = memSpec->tCK * parseUint(memspec[timings]["RCD"], "RCD");
memSpec->tRL = memSpec->tCK * parseUint(memspec[timings]["RL"], "RL");
memSpec->tRTP = memSpec->tCK * parseUint(memspec[timings]["RTP"], "RTP");
memSpec->tWL = memSpec->tCK * parseUint(memspec[timings]["WL"], "WL");
memSpec->tWR = memSpec->tCK * parseUint(memspec[timings]["WR"], "WR");
memSpec->tXP = memSpec->tCK * parseUint(memspec[timings]["XP"], "XP");
memSpec->tXS = memSpec->tCK * parseUint(memspec[timings]["XS"], "XS");
memSpec->tCCD = memSpec->tCK * parseUint(memspec[timings]["CCD"], "CCD");
memSpec->tFAW = memSpec->tCK * parseUint(memspec[timings]["FAW"], "FAW");
memSpec->tREFI = memSpec->tCK * parseUint(memspec[timings]["REFI"], "REFI");
memSpec->tRFC = memSpec->tCK * parseUint(memspec[timings]["RFC"], "RFC");
memSpec->tRP = memSpec->tCK * parseUint(memspec[timings]["RP"], "RP");
memSpec->tRRD = memSpec->tCK * parseUint(memspec[timings]["RRD"], "RRD");
memSpec->tWTR = memSpec->tCK * parseUint(memspec[timings]["WTR"], "WTR");
memSpec->tAL = memSpec->tCK * parseUint(memspec[timings]["AL"], "AL");
memSpec->tXPDLL = memSpec->tCK * parseUint(memspec[timings]["XPDLL"], "XPDLL");
memSpec->tXSDLL = memSpec->tCK * parseUint(memspec[timings]["XSDLL"], "XSDLL");
memSpec->tACTPDEN = memSpec->tCK * parseUint(memspec[timings]["ACTPDEN"], "ACTPDEN");
memSpec->tPRPDEN = memSpec->tCK * parseUint(memspec[timings]["PRPDEN"], "PRPDEN");
memSpec->tREFPDEN = memSpec->tCK * parseUint(memspec[timings]["REFPDEN"], "REFPDEN");
memSpec->tRTRS = memSpec->tCK * parseUint(memspec[timings]["RTRS"], "RTRS");
// Currents and voltages
std::string power = "mempowerspec";
memSpec->iDD0 = parseUdouble(memspec[power]["idd0"], "idd0");
memSpec->iDD2N = parseUdouble(memspec[power]["idd2n"], "idd2n");
memSpec->iDD3N = parseUdouble(memspec[power]["idd3n"], "idd3n");
memSpec->iDD4R = parseUdouble(memspec[power]["idd4r"], "idd4r");
memSpec->iDD4W = parseUdouble(memspec[power]["idd4w"], "idd4w");
memSpec->iDD5 = parseUdouble(memspec[power]["idd5"], "idd5");
memSpec->iDD6 = parseUdouble(memspec[power]["idd6"], "idd6");
memSpec->vDD = parseUdouble(memspec[power]["vdd"], "vdd");
memSpec->iDD2P0 = parseUdouble(memspec[power]["idd2p0"], "idd2p0");
memSpec->iDD2P1 = parseUdouble(memspec[power]["idd2p1"], "idd2p1");
memSpec->iDD3P0 = parseUdouble(memspec[power]["idd3p0"], "idd3p0");
memSpec->iDD3P1 = parseUdouble(memspec[power]["idd3p1"], "idd3p1");
}
void ConfigurationLoader::loadDDR4(Configuration &config, json &memspec)
{
MemSpecDDR4 *memSpec = dynamic_cast<MemSpecDDR4 *>(config.memSpec);
if (memSpec == nullptr)
SC_REPORT_FATAL("ConfigurationLoader", "Wrong MemSpec chosen");
// MemArchitecture
std::string arch = "memarchitecturespec";
memSpec->numberOfRanks = parseUint(memspec[arch]["nbrOfRanks"],"nbrOfRanks");
memSpec->banksPerRank = parseUint(memspec[arch]["nbrOfBanks"],"nbrOfBanks");
memSpec->groupsPerRank = parseUint(memspec[arch]["nbrOfBankGroups"], "nbrOfBankGroups");
memSpec->banksPerGroup = memSpec->banksPerRank / memSpec->groupsPerRank;
memSpec->numberOfBanks = memSpec->banksPerRank * memSpec->numberOfRanks;
memSpec->numberOfBankGroups = memSpec->groupsPerRank * memSpec->numberOfRanks;
// MemTimings specific for DDR4
std::string timings = "memtimingspec";
memSpec->tCKE = memSpec->tCK * parseUint(memspec[timings]["CKE"], "CKE");
memSpec->tPD = memSpec->tCKE;
memSpec->tCKESR = memSpec->tCK * parseUint(memspec[timings]["CKESR"], "CKESR");
memSpec->tDQSCK = memSpec->tCK * parseUint(memspec[timings]["DQSCK"], "DQSCK");
memSpec->tRAS = memSpec->tCK * parseUint(memspec[timings]["RAS"], "RAS");
memSpec->tRC = memSpec->tCK * parseUint(memspec[timings]["RC"], "RC");
memSpec->tRCD = memSpec->tCK * parseUint(memspec[timings]["RCD"], "RCD");
memSpec->tRL = memSpec->tCK * parseUint(memspec[timings]["RL"], "RL");
memSpec->tRTP = memSpec->tCK * parseUint(memspec[timings]["RTP"], "RTP");
memSpec->tWL = memSpec->tCK * parseUint(memspec[timings]["WL"], "WL");
memSpec->tWR = memSpec->tCK * parseUint(memspec[timings]["WR"], "WR");
memSpec->tXP = memSpec->tCK * parseUint(memspec[timings]["XP"], "XP");
memSpec->tXS = memSpec->tCK * parseUint(memspec[timings]["XS"], "XS");
memSpec->tCCD_S = memSpec->tCK * parseUint(memspec[timings]["CCD_S"], "CCD_S");
memSpec->tCCD_L = memSpec->tCK * parseUint(memspec[timings]["CCD_L"], "CCD_L");
memSpec->tFAW = memSpec->tCK * parseUint(memspec[timings]["FAW"], "FAW");
unsigned refreshMode = Configuration::getInstance().refreshMode;
if (refreshMode == 1)
{
memSpec->tREFI = memSpec->tCK * parseUint(memspec[timings]["REFI"], "REFI");
memSpec->tRFC = memSpec->tCK * parseUint(memspec[timings]["RFC"], "RFC");
}
else if (refreshMode == 2)
{
memSpec->tREFI = memSpec->tCK * (parseUint(memspec[timings]["REFI"], "REFI") / 2);
memSpec->tRFC = memSpec->tCK * parseUint(memspec[timings]["RFC2"], "RFC2");
}
else if (refreshMode == 4)
{
memSpec->tREFI = memSpec->tCK * (parseUint(memspec[timings]["REFI"], "REFI") / 2);
memSpec->tRFC = memSpec->tCK * parseUint(memspec[timings]["RFC4"], "RFC4");
}
else
SC_REPORT_FATAL("ConfigurationLoader", "Refresh Mode not supported");
memSpec->tRP = memSpec->tCK * parseUint(memspec[timings]["RP"], "RP");
memSpec->tRRD_S = memSpec->tCK * parseUint(memspec[timings]["RRD_S"], "RRD_S");
memSpec->tRRD_L = memSpec->tCK * parseUint(memspec[timings]["RRD_L"], "RRD_L");
memSpec->tWTR_S = memSpec->tCK * parseUint(memspec[timings]["WTR_S"], "WTR_S");
memSpec->tWTR_L = memSpec->tCK * parseUint(memspec[timings]["WTR_L"], "WTR_L");
memSpec->tAL = memSpec->tCK * parseUint(memspec[timings]["AL"], "AL");
memSpec->tXPDLL = memSpec->tCK * parseUint(memspec[timings]["XPDLL"], "XPDLL");
memSpec->tXSDLL = memSpec->tCK * parseUint(memspec[timings]["XSDLL"], "XSDLL");
memSpec->tACTPDEN = memSpec->tCK * parseUint(memspec[timings]["ACTPDEN"], "ACTPDEN");
memSpec->tPRPDEN = memSpec->tCK * parseUint(memspec[timings]["PRPDEN"], "PRPDEN");
memSpec->tREFPDEN = memSpec->tCK * parseUint(memspec[timings]["REFPDEN"], "REFPDEN");
memSpec->tRTRS = memSpec->tCK * parseUint(memspec[timings]["RTRS"], "RTRS");
// Currents and voltages
std::string power = "mempowerspec";
memSpec->iDD0 = parseUdouble(memspec[power]["idd0"], "idd0");
memSpec->iDD2N = parseUdouble(memspec[power]["idd2n"], "idd2n");
memSpec->iDD3N = parseUdouble(memspec[power]["idd3n"], "idd3n");
memSpec->iDD4R = parseUdouble(memspec[power]["idd4r"], "idd4r");
memSpec->iDD4W = parseUdouble(memspec[power]["idd4w"], "idd4w");
memSpec->iDD5 = parseUdouble(memspec[power]["idd5"], "idd5");
memSpec->iDD6 = parseUdouble(memspec[power]["idd6"], "idd6");
memSpec->vDD = parseUdouble(memspec[power]["vdd"], "vdd");
memSpec->iDD02 = parseUdouble(memspec[power]["idd02"], "idd02");
memSpec->iDD2P0 = parseUdouble(memspec[power]["idd2p0"], "idd2p0");
memSpec->iDD2P1 = parseUdouble(memspec[power]["idd2p1"], "idd2p1");
memSpec->iDD3P0 = parseUdouble(memspec[power]["idd3p0"], "idd3p0");
memSpec->iDD3P1 = parseUdouble(memspec[power]["idd3p1"], "idd3p1");
memSpec->iDD62 = parseUdouble(memspec[power]["idd62"], "idd62");
memSpec->vDD2 = parseUdouble(memspec[power]["vdd2"], "vdd2");
}
void ConfigurationLoader::loadLPDDR4(Configuration &config, json &memspec)
{
MemSpecLPDDR4 *memSpec = dynamic_cast<MemSpecLPDDR4 *>(config.memSpec);
if (memSpec == nullptr)
SC_REPORT_FATAL("ConfigurationLoader", "Wrong MemSpec chosen");
// MemArchitecture:
std::string arch = "memarchitecturespec";
memSpec->numberOfRanks = parseUint(memspec[arch]["nbrOfRanks"],"nbrOfRanks");
memSpec->banksPerRank = parseUint(memspec[arch]["nbrOfBanks"],"nbrOfBanks");
memSpec->groupsPerRank = 1;
memSpec->banksPerGroup = memSpec->banksPerRank / memSpec->groupsPerRank;
memSpec->numberOfBanks = memSpec->banksPerRank * memSpec->numberOfRanks;
memSpec->numberOfBankGroups = memSpec->groupsPerRank * memSpec->numberOfRanks;
// MemTimings specific for LPDDR4
std::string timings = "memtimingspec";
memSpec->tREFI = memSpec->tCK * parseUint(memspec[timings]["REFI"], "REFI");
memSpec->tREFIpb = memSpec->tCK * parseUint(memspec[timings]["REFIPB"], "REFIPB");
memSpec->tRFCab = memSpec->tCK * parseUint(memspec[timings]["RFCAB"], "RFCAB");
memSpec->tRFCpb = memSpec->tCK * parseUint(memspec[timings]["RFCPB"], "RFCPB");
memSpec->tRPab = memSpec->tCK * parseUint(memspec[timings]["RPAB"], "RPAB");
memSpec->tRPpb = memSpec->tCK * parseUint(memspec[timings]["RPPB"], "RPPB");
memSpec->tRCab = memSpec->tCK * parseUint(memspec[timings]["RCAB"], "RCAB");
memSpec->tRCpb = memSpec->tCK * parseUint(memspec[timings]["RCPB"], "RCPB");
memSpec->tPPD = memSpec->tCK * parseUint(memspec[timings]["PPD"], "PPD");
memSpec->tRAS = memSpec->tCK * parseUint(memspec[timings]["RAS"], "RAS");
memSpec->tRCD = memSpec->tCK * parseUint(memspec[timings]["RCD"], "RCD");
memSpec->tFAW = memSpec->tCK * parseUint(memspec[timings]["FAW"], "FAW");
memSpec->tRRD = memSpec->tCK * parseUint(memspec[timings]["RRD"], "RRD");
memSpec->tCCD = memSpec->tCK * parseUint(memspec[timings]["CCD"], "CCD");
memSpec->tRL = memSpec->tCK * parseUint(memspec[timings]["RL"], "RL");
memSpec->tRPST = memSpec->tCK * parseUint(memspec[timings]["RPST"], "RPST");
memSpec->tDQSCK = memSpec->tCK * parseUint(memspec[timings]["DQSCK"], "DQSCK");
memSpec->tRTP = memSpec->tCK * parseUint(memspec[timings]["RTP"], "RTP");
memSpec->tWL = memSpec->tCK * parseUint(memspec[timings]["WL"], "WL");
memSpec->tDQSS = memSpec->tCK * parseUint(memspec[timings]["DQSS"], "DQSS");
memSpec->tDQS2DQ = memSpec->tCK * parseUint(memspec[timings]["DQS2DQ"], "DQS2DQ");
memSpec->tWR = memSpec->tCK * parseUint(memspec[timings]["WR"], "WR");
memSpec->tWPRE = memSpec->tCK * parseUint(memspec[timings]["WPRE"], "WPRE");
memSpec->tWTR = memSpec->tCK * parseUint(memspec[timings]["WTR"], "WTR");
memSpec->tXP = memSpec->tCK * parseUint(memspec[timings]["XP"], "XP");
memSpec->tSR = memSpec->tCK * parseUint(memspec[timings]["SR"], "SR");
memSpec->tXSR = memSpec->tCK * parseUint(memspec[timings]["XSR"], "XSR");
memSpec->tESCKE = memSpec->tCK * parseUint(memspec[timings]["ESCKE"], "ESCKE");
memSpec->tCKE = memSpec->tCK * parseUint(memspec[timings]["CKE"], "CKE");
memSpec->tCMDCKE = memSpec->tCK * parseUint(memspec[timings]["CMDCKE"], "CMDCKE");
memSpec->tRTRS = memSpec->tCK * parseUint(memspec[timings]["RTRS"], "RTRS");
// Currents and voltages
// TODO: to be completed
}
void ConfigurationLoader::loadWideIO(Configuration &config, json &memspec)
{
MemSpecWideIO *memSpec = dynamic_cast<MemSpecWideIO *>(config.memSpec);
if (memSpec == nullptr)
SC_REPORT_FATAL("ConfigurationLoader", "Wrong MemSpec chosen");
// MemArchitecture
std::string arch = "memarchitecturespec";
memSpec->numberOfRanks = parseUint(memspec[arch]["nbrOfRanks"], "nbrOfRanks");
memSpec->banksPerRank = parseUint(memspec[arch]["nbrOfBanks"], "nbrOfBanks");
memSpec->groupsPerRank = 1;
memSpec->banksPerGroup = memSpec->banksPerRank / memSpec->groupsPerRank;
memSpec->numberOfBanks = memSpec->banksPerRank * memSpec->numberOfRanks;
memSpec->numberOfBankGroups = memSpec->groupsPerRank * memSpec->numberOfRanks;
// MemTimings specific for WideIO
std::string timings = "memtimingspec";
memSpec->tCKE = memSpec->tCK * parseUint(memspec[timings]["CKE"], "CKE");
memSpec->tCKESR = memSpec->tCK * parseUint(memspec[timings]["CKESR"], "CKESR");
memSpec->tDQSCK = memSpec->tCK * parseUint(memspec[timings]["DQSCK"], "DQSCK");
memSpec->tAC = memSpec->tCK * parseUint(memspec[timings]["AC"], "AC");
memSpec->tRAS = memSpec->tCK * parseUint(memspec[timings]["RAS"], "RAS");
memSpec->tRC = memSpec->tCK * parseUint(memspec[timings]["RC"], "RC");
memSpec->tRCD = memSpec->tCK * parseUint(memspec[timings]["RCD"], "RCD");
memSpec->tRL = memSpec->tCK * parseUint(memspec[timings]["RL"], "RL");
memSpec->tWL = memSpec->tCK * parseUint(memspec[timings]["WL"], "WL");
memSpec->tWR = memSpec->tCK * parseUint(memspec[timings]["WR"], "WR");
memSpec->tXP = memSpec->tCK * parseUint(memspec[timings]["XP"], "XP");
memSpec->tXSR = memSpec->tCK * parseUint(memspec[timings]["XSR"], "XSR");
memSpec->tCCD_R = memSpec->tCK * parseUint(memspec[timings]["CCD_R"], "CCD_R");
memSpec->tCCD_W = memSpec->tCK * parseUint(memspec[timings]["CCD_W"], "CCD_W");
memSpec->tREFI = memSpec->tCK * parseUint(memspec[timings]["REFI"], "REFI");
memSpec->tRFC = memSpec->tCK * parseUint(memspec[timings]["RFC"], "RFC");
memSpec->tRP = memSpec->tCK * parseUint(memspec[timings]["RP"], "RP");
memSpec->tRRD = memSpec->tCK * parseUint(memspec[timings]["RRD"], "RRD");
memSpec->tTAW = memSpec->tCK * parseUint(memspec[timings]["TAW"], "TAW");
memSpec->tWTR = memSpec->tCK * parseUint(memspec[timings]["WTR"], "WTR");
memSpec->tRTRS = memSpec->tCK * parseUint(memspec[timings]["RTRS"], "RTRS");
// Currents and voltages
std::string power = "mempowerspec";
memSpec->iDD0 = parseUdouble(memspec[power]["idd0"], "idd0");
memSpec->iDD2N = parseUdouble(memspec[power]["idd2n"], "idd2n");
memSpec->iDD3N = parseUdouble(memspec[power]["idd3n"], "idd3n");
memSpec->iDD4R = parseUdouble(memspec[power]["idd4r"], "idd4r");
memSpec->iDD4W = parseUdouble(memspec[power]["idd4w"], "idd4w");
memSpec->iDD5 = parseUdouble(memspec[power]["idd5"], "idd5");
memSpec->iDD6 = parseUdouble(memspec[power]["idd6"], "idd6");
memSpec->vDD = parseUdouble(memspec[power]["vdd"], "vdd");
memSpec->iDD02 = parseUdouble(memspec[power]["idd02"], "idd02");
memSpec->iDD2P0 = parseUdouble(memspec[power]["idd2p0"], "idd2p0");
memSpec->iDD2P02 = parseUdouble(memspec[power]["idd2p02"], "idd2p02");
memSpec->iDD2P1 = parseUdouble(memspec[power]["idd2p1"], "idd2p1");
memSpec->iDD2P12 = parseUdouble(memspec[power]["idd2p12"], "idd2p12");
memSpec->iDD2N2 = parseUdouble(memspec[power]["idd2n2"], "idd2n2");
memSpec->iDD3P0 = parseUdouble(memspec[power]["idd3p0"], "idd3p0");
memSpec->iDD3P02 = parseUdouble(memspec[power]["idd3p02"], "idd3p02");
memSpec->iDD3P1 = parseUdouble(memspec[power]["idd3p1"], "idd3p1");
memSpec->iDD3P12 = parseUdouble(memspec[power]["idd3p12"], "idd3p12");
memSpec->iDD3N2 = parseUdouble(memspec[power]["idd3n2"], "idd3n2");
memSpec->iDD4R2 = parseUdouble(memspec[power]["idd4r2"], "idd4r2");
memSpec->iDD4W2 = parseUdouble(memspec[power]["idd4w2"], "idd4w2");
memSpec->iDD52 = parseUdouble(memspec[power]["idd52"], "idd52");
memSpec->iDD62 = parseUdouble(memspec[power]["idd62"], "idd62");
memSpec->vDD2 = parseUdouble(memspec[power]["vdd2"], "vdd2");
}
void ConfigurationLoader::loadWideIO2(Configuration &config, json &memspec)
{
MemSpecWideIO2 *memSpec = dynamic_cast<MemSpecWideIO2 *>(config.memSpec);
if (memSpec == nullptr)
SC_REPORT_FATAL("ConfigurationLoader", "Wrong MemSpec chosen");
// MemArchitecture
std::string arch = "memarchitecturespec";
memSpec->numberOfRanks = parseUint(memspec[arch]["nbrOfRanks"], "nbrOfRanks");
memSpec->banksPerRank = parseUint(memspec[arch]["nbrOfBanks"], "nbrOfBanks");
memSpec->groupsPerRank = 1;
memSpec->banksPerGroup = memSpec->banksPerRank / memSpec->groupsPerRank;
memSpec->numberOfBanks = memSpec->banksPerRank * memSpec->numberOfRanks;
memSpec->numberOfBankGroups = memSpec->groupsPerRank * memSpec->numberOfRanks;
// MemTimings specific for WideIO2
std::string timings = "memtimingspec";
memSpec->tDQSCK = memSpec->tCK * parseUint(memspec[timings]["DQSCK"], "DQSCK");
memSpec->tDQSS = memSpec->tCK * parseUint(memspec[timings]["DQSS"], "DQSS");
memSpec->tCKE = memSpec->tCK * parseUint(memspec[timings]["CKE"], "CKE");
memSpec->tRL = memSpec->tCK * parseUint(memspec[timings]["RL"], "RL");
memSpec->tWL = memSpec->tCK * parseUint(memspec[timings]["WL"], "WL");
memSpec->tRCpb = memSpec->tCK * parseUint(memspec[timings]["RCPB"], "RCPB");
memSpec->tRCab = memSpec->tCK * parseUint(memspec[timings]["RCAB"], "RCAB");
memSpec->tCKESR = memSpec->tCK * parseUint(memspec[timings]["CKESR"], "CKESR");
memSpec->tXSR = memSpec->tCK * parseUint(memspec[timings]["XSR"], "XSR");
memSpec->tXP = memSpec->tCK * parseUint(memspec[timings]["XP"], "XP");
memSpec->tCCD = memSpec->tCK * parseUint(memspec[timings]["CCD"], "CCD");
memSpec->tRTP = memSpec->tCK * parseUint(memspec[timings]["RTP"], "RTP");
memSpec->tRCD = memSpec->tCK * parseUint(memspec[timings]["RCD"], "RCD");
memSpec->tRPpb = memSpec->tCK * parseUint(memspec[timings]["RPPB"], "RPPB");
memSpec->tRPab = memSpec->tCK * parseUint(memspec[timings]["RPAB"], "RPAB");
memSpec->tRAS = memSpec->tCK * parseUint(memspec[timings]["RAS"], "RAS");
memSpec->tWR = memSpec->tCK * parseUint(memspec[timings]["WR"], "WR");
memSpec->tWTR = memSpec->tCK * parseUint(memspec[timings]["WTR"], "WTR");
memSpec->tRRD = memSpec->tCK * parseUint(memspec[timings]["RRD"], "RRD");
memSpec->tFAW = memSpec->tCK * parseUint(memspec[timings]["FAW"], "FAW");
memSpec->tREFI = memSpec->tCK * (unsigned)(parseUint(memspec[timings]["REFI"], "REFI")
* parseUdouble(memspec[timings]["REFM"], "REFM"));
memSpec->tREFIpb = memSpec->tCK * (unsigned)(parseUint(memspec[timings]["REFIPB"], "REFIPB")
* parseUdouble(memspec[timings]["REFM"], "REFM"));
memSpec->tRFCab = memSpec->tCK * parseUint(memspec[timings]["RFCAB"], "RFCAB");
memSpec->tRFCpb = memSpec->tCK * parseUint(memspec[timings]["RFCPB"], "RFCPB");
memSpec->tRTRS = memSpec->tCK * parseUint(memspec[timings]["RTRS"], "RTRS");
// Currents and voltages
// TODO: to be completed
}
void ConfigurationLoader::loadHBM2(Configuration &config, json &memspec)
{
MemSpecHBM2 *memSpec = dynamic_cast<MemSpecHBM2 *>(config.memSpec);
if (memSpec == nullptr)
SC_REPORT_FATAL("ConfigurationLoader", "Wrong MemSpec chosen");
// MemArchitecture
std::string arch = "memarchitecturespec";
memSpec->numberOfRanks = parseUint(memspec[arch]["nbrOfRanks"], "nbrOfRanks");
memSpec->banksPerRank = parseUint(memspec[arch]["nbrOfBanks"], "nbrOfBanks");
memSpec->groupsPerRank = parseUint(memspec[arch]["nbrOfBankGroups"], "nbrOfBankGroups");
memSpec->banksPerGroup = memSpec->banksPerRank / memSpec->groupsPerRank;
memSpec->numberOfBanks = memSpec->banksPerRank * memSpec->numberOfRanks;
memSpec->numberOfBankGroups = memSpec->groupsPerRank * memSpec->numberOfRanks;
// MemTimings specific for HBM2
std::string timings = "memtimingspec";
memSpec->tDQSCK = memSpec->tCK * parseUint(memspec[timings]["DQSCK"], "DQSCK");
memSpec->tRC = memSpec->tCK * parseUint(memspec[timings]["RC"], "RC");
memSpec->tRAS = memSpec->tCK * parseUint(memspec[timings]["RAS"], "RAS");
memSpec->tRCDRD = memSpec->tCK * parseUint(memspec[timings]["RCDRD"], "RCDRD");
memSpec->tRCDWR = memSpec->tCK * parseUint(memspec[timings]["RCDWR"], "RCDWR");
memSpec->tRRDL = memSpec->tCK * parseUint(memspec[timings]["RRDL"], "RRDL");
memSpec->tRRDS = memSpec->tCK * parseUint(memspec[timings]["RRDS"], "RRDS");
memSpec->tFAW = memSpec->tCK * parseUint(memspec[timings]["FAW"], "FAW");
memSpec->tRTP = memSpec->tCK * parseUint(memspec[timings]["RTP"], "RTP");
memSpec->tRP = memSpec->tCK * parseUint(memspec[timings]["RP"], "RP");
memSpec->tRL = memSpec->tCK * parseUint(memspec[timings]["RL"], "RL");
memSpec->tWL = memSpec->tCK * parseUint(memspec[timings]["WL"], "WL");
memSpec->tPL = memSpec->tCK * parseUint(memspec[timings]["PL"], "PL");
memSpec->tWR = memSpec->tCK * parseUint(memspec[timings]["WR"], "WR");
memSpec->tCCDL = memSpec->tCK * parseUint(memspec[timings]["CCDL"], "CCDL");
memSpec->tCCDS = memSpec->tCK * parseUint(memspec[timings]["CCDS"], "CCDS");
memSpec->tWTRL = memSpec->tCK * parseUint(memspec[timings]["WTRL"], "WTRL");
memSpec->tWTRS = memSpec->tCK * parseUint(memspec[timings]["WTRS"], "WTRS");
memSpec->tRTW = memSpec->tCK * parseUint(memspec[timings]["RTW"], "RTW");
memSpec->tXP = memSpec->tCK * parseUint(memspec[timings]["XP"], "XP");
memSpec->tCKE = memSpec->tCK * parseUint(memspec[timings]["CKE"], "CKE");
memSpec->tPD = memSpec->tCKE;
memSpec->tCKESR = memSpec->tCKE + memSpec->tCK;
memSpec->tXS = memSpec->tCK * parseUint(memspec[timings]["XS"], "XS");
memSpec->tRFC = memSpec->tCK * parseUint(memspec[timings]["RFC"], "RFC");
memSpec->tRFCSB = memSpec->tCK * parseUint(memspec[timings]["RFCSB"], "RFCSB");
memSpec->tRREFD = memSpec->tCK * parseUint(memspec[timings]["RREFD"], "RREFD");
memSpec->tREFI = memSpec->tCK * parseUint(memspec[timings]["REFI"], "REFI");
memSpec->tREFISB = memSpec->tCK * parseUint(memspec[timings]["REFISB"], "REFISB");
// Currents and voltages
// TODO: to be completed
}
void ConfigurationLoader::loadGDDR5(Configuration &config, json &memspec)
{
MemSpecGDDR5 *memSpec = dynamic_cast<MemSpecGDDR5 *>(config.memSpec);
if (memSpec == nullptr)
SC_REPORT_FATAL("ConfigurationLoader", "Wrong MemSpec chosen");
// MemArchitecture
std::string arch = "memarchitecturespec";
memSpec->numberOfRanks = parseUint(memspec[arch]["nbrOfRanks"], "nbrOfRanks");
memSpec->banksPerRank = parseUint(memspec[arch]["nbrOfBanks"], "nbrOfBanks");
memSpec->groupsPerRank = parseUint(memspec[arch]["nbrOfBankGroups"], "nbrOfBankGroups");
memSpec->banksPerGroup = memSpec->banksPerRank / memSpec->groupsPerRank;
memSpec->numberOfBanks = memSpec->banksPerRank * memSpec->numberOfRanks;
memSpec->numberOfBankGroups = memSpec->groupsPerRank * memSpec->numberOfRanks;
// MemTimings specific for GDDR5
std::string timings = "memtimingspec";
memSpec->tRP = memSpec->tCK * parseUint(memspec[timings]["RP"], "RP");
memSpec->tRAS = memSpec->tCK * parseUint(memspec[timings]["RAS"], "RAS");
memSpec->tRC = memSpec->tCK * parseUint(memspec[timings]["RC"], "RC");
memSpec->tRCDRD = memSpec->tCK * parseUint(memspec[timings]["RCDRD"], "RCDRD");
memSpec->tRCDWR = memSpec->tCK * parseUint(memspec[timings]["RCDWR"], "RCDWR");
memSpec->tRTP = memSpec->tCK * parseUint(memspec[timings]["RTP"], "RTP");
memSpec->tRRDS = memSpec->tCK * parseUint(memspec[timings]["RRDS"], "RRDS");
memSpec->tRRDL = memSpec->tCK * parseUint(memspec[timings]["RRDL"], "RRDL");
memSpec->tCCDS = memSpec->tCK * parseUint(memspec[timings]["CCDS"], "CCDS");
memSpec->tCCDL = memSpec->tCK * parseUint(memspec[timings]["CCDL"], "CCDL");
memSpec->tCL = memSpec->tCK * parseUint(memspec[timings]["CL"], "CL");
memSpec->tWCK2CKPIN = memSpec->tCK * parseUint(memspec[timings]["WCK2CKPIN"], "WCK2CKPIN");
memSpec->tWCK2CK = memSpec->tCK * parseUint(memspec[timings]["WCK2CK"], "WCK2CK");
memSpec->tWCK2DQO = memSpec->tCK * parseUint(memspec[timings]["WCK2DQO"], "WCK2DQO");
memSpec->tRTW = memSpec->tCK * parseUint(memspec[timings]["RTW"], "RTW");
memSpec->tWL = memSpec->tCK * parseUint(memspec[timings]["WL"], "WL");
memSpec->tWCK2DQI = memSpec->tCK * parseUint(memspec[timings]["WCK2DQI"], "WCK2DQI");
memSpec->tWR = memSpec->tCK * parseUint(memspec[timings]["WR"], "WR");
memSpec->tWTRS = memSpec->tCK * parseUint(memspec[timings]["WTRS"], "WTRS");
memSpec->tWTRL = memSpec->tCK * parseUint(memspec[timings]["WTRL"], "WTRL");
memSpec->tCKE = memSpec->tCK * parseUint(memspec[timings]["CKE"], "CKE");
memSpec->tPD = memSpec->tCK * parseUint(memspec[timings]["PD"], "PD");
memSpec->tXPN = memSpec->tCK * parseUint(memspec[timings]["XPN"], "XPN");
memSpec->tREFI = memSpec->tCK * parseUint(memspec[timings]["REFI"], "REFI");
memSpec->tREFIPB = memSpec->tCK * parseUint(memspec[timings]["REFIPB"], "REFIPB");
memSpec->tRFC = memSpec->tCK * parseUint(memspec[timings]["RFC"], "RFC");
memSpec->tRFCPB = memSpec->tCK * parseUint(memspec[timings]["RFCPB"], "RFCPB");
memSpec->tRREFD = memSpec->tCK * parseUint(memspec[timings]["RREFD"], "RREFD");
memSpec->tXS = memSpec->tCK * parseUint(memspec[timings]["XS"], "XS");
memSpec->tFAW = memSpec->tCK * parseUint(memspec[timings]["FAW"], "FAW");
memSpec->t32AW = memSpec->tCK * parseUint(memspec[timings]["32AW"], "32AW");
// memSpec->tRDSRE = memSpec->tCL + memSpec->tWCK2CKPIN + memSpec->tWCK2CK
// + memSpec->tWCK2DQO + memSpec->burstLength / memSpec->dataRate * memSpec->tCK;
// memSpec->tWRSRE = memSpec->tWL + memSpec->tWCK2CKPIN + memSpec->tWCK2CK
// + memSpec->tWCK2DQI + memSpec->burstLength / memSpec->dataRate * memSpec->tCK;
memSpec->tPPD = memSpec->tCK * parseUint(memspec[timings]["PPD"], "PPD");
memSpec->tLK = memSpec->tCK * parseUint(memspec[timings]["LK"], "LK");
memSpec->tRTRS = memSpec->tCK * parseUint(memspec[timings]["RTRS"], "RTRS");
// Currents and voltages
// TODO: to be completed
}
void ConfigurationLoader::loadGDDR5X(Configuration &config, json &memspec)
{
MemSpecGDDR5X *memSpec = dynamic_cast<MemSpecGDDR5X *>(config.memSpec);
if (memSpec == nullptr)
SC_REPORT_FATAL("ConfigurationLoader", "Wrong MemSpec chosen");
// MemArchitecture
std::string arch = "memarchitecturespec";
memSpec->numberOfRanks = parseUint(memspec[arch]["nbrOfRanks"], "nbrOfRanks");
memSpec->banksPerRank = parseUint(memspec[arch]["nbrOfBanks"], "nbrOfBanks");
memSpec->groupsPerRank = parseUint(memspec[arch]["nbrOfBankGroups"], "nbrOfBankGroups");
memSpec->banksPerGroup = memSpec->banksPerRank / memSpec->groupsPerRank;
memSpec->numberOfBanks = memSpec->banksPerRank * memSpec->numberOfRanks;
memSpec->numberOfBankGroups = memSpec->groupsPerRank * memSpec->numberOfRanks;
// MemTimings specific for GDDR5X
std::string timings = "memtimingspec";
memSpec->tRP = memSpec->tCK * parseUint(memspec[timings]["RP"], "RP");
memSpec->tRAS = memSpec->tCK * parseUint(memspec[timings]["RAS"], "RAS");
memSpec->tRC = memSpec->tCK * parseUint(memspec[timings]["RC"], "RC");
memSpec->tRCDRD = memSpec->tCK * parseUint(memspec[timings]["RCDRD"], "RCDRD");
memSpec->tRCDWR = memSpec->tCK * parseUint(memspec[timings]["RCDWR"], "RCDWR");
memSpec->tRTP = memSpec->tCK * parseUint(memspec[timings]["RTP"], "RTP");
memSpec->tRRDS = memSpec->tCK * parseUint(memspec[timings]["RRDS"], "RRDS");
memSpec->tRRDL = memSpec->tCK * parseUint(memspec[timings]["RRDL"], "RRDL");
memSpec->tCCDS = memSpec->tCK * parseUint(memspec[timings]["CCDS"], "CCDS");
memSpec->tCCDL = memSpec->tCK * parseUint(memspec[timings]["CCDL"], "CCDL");
memSpec->tRL = memSpec->tCK * parseUint(memspec[timings]["RL"], "RL");
memSpec->tWCK2CKPIN = memSpec->tCK * parseUint(memspec[timings]["WCK2CKPIN"], "WCK2CKPIN");
memSpec->tWCK2CK = memSpec->tCK * parseUint(memspec[timings]["WCK2CK"], "WCK2CK");
memSpec->tWCK2DQO = memSpec->tCK * parseUint(memspec[timings]["WCK2DQO"], "WCK2DQO");
memSpec->tRTW = memSpec->tCK * parseUint(memspec[timings]["RTW"], "RTW");
memSpec->tWL = memSpec->tCK * parseUint(memspec[timings]["WL"], "WL");
memSpec->tWCK2DQI = memSpec->tCK * parseUint(memspec[timings]["WCK2DQI"], "WCK2DQI");
memSpec->tWR = memSpec->tCK * parseUint(memspec[timings]["WR"], "WR");
memSpec->tWTRS = memSpec->tCK * parseUint(memspec[timings]["WTRS"], "WTRS");
memSpec->tWTRL = memSpec->tCK * parseUint(memspec[timings]["WTRL"], "WTRL");
memSpec->tCKE = memSpec->tCK * parseUint(memspec[timings]["CKE"], "CKE");
memSpec->tPD = memSpec->tCK * parseUint(memspec[timings]["PD"], "PD");
memSpec->tXP = memSpec->tCK * parseUint(memspec[timings]["XP"], "XP");
memSpec->tREFI = memSpec->tCK * parseUint(memspec[timings]["REFI"], "REFI");
memSpec->tREFIPB = memSpec->tCK * parseUint(memspec[timings]["REFIPB"], "REFIPB");
memSpec->tRFC = memSpec->tCK * parseUint(memspec[timings]["RFC"], "RFC");
memSpec->tRFCPB = memSpec->tCK * parseUint(memspec[timings]["RFCPB"], "RFCPB");
memSpec->tRREFD = memSpec->tCK * parseUint(memspec[timings]["RREFD"], "RREFD");
memSpec->tXS = memSpec->tCK * parseUint(memspec[timings]["XS"], "XS");
memSpec->tFAW = memSpec->tCK * parseUint(memspec[timings]["FAW"], "FAW");
memSpec->t32AW = memSpec->tCK * parseUint(memspec[timings]["32AW"], "32AW");
// memSpec->tRDSRE = memSpec->tRL + memSpec->tWCK2CKPIN + memSpec->tWCK2CK
// + memSpec->tWCK2DQO + memSpec->burstLength / memSpec->dataRate * memSpec->tCK;
// memSpec->tWRSRE = memSpec->tWL + memSpec->tWCK2CKPIN + memSpec->tWCK2CK
// + memSpec->tWCK2DQI + memSpec->burstLength / memSpec->dataRate * memSpec->tCK;
memSpec->tPPD = memSpec->tCK * parseUint(memspec[timings]["PPD"], "PPD");
memSpec->tLK = memSpec->tCK * parseUint(memspec[timings]["LK"], "LK");
memSpec->tRTRS = memSpec->tCK * parseUint(memspec[timings]["RTRS"], "RTRS");
// Currents and voltages
// TODO: to be completed
}
void ConfigurationLoader::loadGDDR6(Configuration &config, json &memspec)
{
MemSpecGDDR6 *memSpec = dynamic_cast<MemSpecGDDR6 *>(config.memSpec);
if (memSpec == nullptr)
SC_REPORT_FATAL("ConfigurationLoader", "Wrong MemSpec chosen");
// MemArchitecture
std::string arch = "memarchitecturespec";
memSpec->numberOfRanks = parseUint(memspec[arch]["nbrOfRanks"], "nbrOfRanks");
memSpec->banksPerRank = parseUint(memspec[arch]["nbrOfBanks"], "nbrOfBanks");
memSpec->groupsPerRank = parseUint(memspec[arch]["nbrOfBankGroups"], "nbrOfBankGroups");
memSpec->banksPerGroup = memSpec->banksPerRank / memSpec->groupsPerRank;
memSpec->numberOfBanks = memSpec->banksPerRank * memSpec->numberOfRanks;
memSpec->numberOfBankGroups = memSpec->groupsPerRank * memSpec->numberOfRanks;
// MemTimings specific for GDDR6
std::string timings = "memtimingspec";
memSpec->tRP = memSpec->tCK * parseUint(memspec[timings]["RP"], "RP");
memSpec->tRAS = memSpec->tCK * parseUint(memspec[timings]["RAS"], "RAS");
memSpec->tRC = memSpec->tCK * parseUint(memspec[timings]["RC"], "RC");
memSpec->tRCDRD = memSpec->tCK * parseUint(memspec[timings]["RCDRD"], "RCDRD");
memSpec->tRCDWR = memSpec->tCK * parseUint(memspec[timings]["RCDWR"], "RCDWR");
memSpec->tRTP = memSpec->tCK * parseUint(memspec[timings]["RTP"], "RTP");
memSpec->tRRDS = memSpec->tCK * parseUint(memspec[timings]["RRDS"], "RRDS");
memSpec->tRRDL = memSpec->tCK * parseUint(memspec[timings]["RRDL"], "RRDL");
memSpec->tCCDS = memSpec->tCK * parseUint(memspec[timings]["CCDS"], "CCDS");
memSpec->tCCDL = memSpec->tCK * parseUint(memspec[timings]["CCDL"], "CCDL");
memSpec->tRL = memSpec->tCK * parseUint(memspec[timings]["RL"], "RL");
memSpec->tWCK2CKPIN = memSpec->tCK * parseUint(memspec[timings]["WCK2CKPIN"], "WCK2CKPIN");
memSpec->tWCK2CK = memSpec->tCK * parseUint(memspec[timings]["WCK2CK"], "WCK2CK");
memSpec->tWCK2DQO = memSpec->tCK * parseUint(memspec[timings]["WCK2DQO"], "WCK2DQO");
memSpec->tRTW = memSpec->tCK * parseUint(memspec[timings]["RTW"], "RTW");
memSpec->tWL = memSpec->tCK * parseUint(memspec[timings]["WL"], "WL");
memSpec->tWCK2DQI = memSpec->tCK * parseUint(memspec[timings]["WCK2DQI"], "WCK2DQI");
memSpec->tWR = memSpec->tCK * parseUint(memspec[timings]["WR"], "WR");
memSpec->tWTRS = memSpec->tCK * parseUint(memspec[timings]["WTRS"], "WTRS");
memSpec->tWTRL = memSpec->tCK * parseUint(memspec[timings]["WTRL"], "WTRL");
memSpec->tPD = memSpec->tCK * parseUint(memspec[timings]["PD"], "PD");
memSpec->tCKESR = memSpec->tCK * parseUint(memspec[timings]["CKESR"], "CKESR");
memSpec->tXP = memSpec->tCK * parseUint(memspec[timings]["XP"], "XP");
memSpec->tREFI = memSpec->tCK * parseUint(memspec[timings]["REFI"], "REFI");
memSpec->tREFIPB = memSpec->tCK * parseUint(memspec[timings]["REFIPB"], "REFIPB");
memSpec->tRFC = memSpec->tCK * parseUint(memspec[timings]["RFC"], "RFC");
memSpec->tRFCPB = memSpec->tCK * parseUint(memspec[timings]["RFCPB"], "RFCPB");
memSpec->tRREFD = memSpec->tCK * parseUint(memspec[timings]["RREFD"], "RREFD");
memSpec->tXS = memSpec->tCK * parseUint(memspec[timings]["XS"], "XS");
memSpec->tFAW = memSpec->tCK * parseUint(memspec[timings]["FAW"], "FAW");
// memSpec->tRDSRE = memSpec->tRL + memSpec->tWCK2CKPIN + memSpec->tWCK2CK
// + memSpec->tWCK2DQO + memSpec->burstLength / memSpec->dataRate * memSpec->tCK;
// memSpec->tWRSRE = memSpec->tWL + memSpec->tWCK2CKPIN + memSpec->tWCK2CK
// + memSpec->tWCK2DQI + memSpec->burstLength / memSpec->dataRate * memSpec->tCK;
memSpec->tPPD = memSpec->tCK * parseUint(memspec[timings]["PPD"], "PPD");
memSpec->tLK = memSpec->tCK * parseUint(memspec[timings]["LK"], "LK");
memSpec->tACTPDE = memSpec->tCK * parseUint(memspec[timings]["ACTPDE"], "ACTPDE");
memSpec->tPREPDE = memSpec->tCK * parseUint(memspec[timings]["PREPDE"], "PREPDE");
memSpec->tREFPDE = memSpec->tCK * parseUint(memspec[timings]["REFPDE"], "REFPDE");
memSpec->tRTRS = memSpec->tCK * parseUint(memspec[timings]["RTRS"], "RTRS");
// Currents and voltages
// TODO: to be completed
}
unsigned int ConfigurationLoader::parseUint(json &obj, std::string name)
{
if (!obj.empty())
{
if (obj.is_number_unsigned())
return obj;
else
throw std::invalid_argument("Expected type for '" + name + "': unsigned int");
}
else
SC_REPORT_FATAL("Query json", ("Parameter '" + name + "' does not exist.").c_str());
}
double ConfigurationLoader::parseUdouble(json &obj, std::string name)
{
if (!obj.empty())
{
if (obj.is_number() && (obj > 0))
return obj;
else
throw std::invalid_argument("Expected type for '" + name + "': positive double");
}
else
SC_REPORT_FATAL("Query json", ("Parameter '" + name + "' does not exist.").c_str());
}
std::string ConfigurationLoader::parseString(json &obj, std::string name)
{
if (!obj.empty())
{
if (obj.is_string())
return obj;
else
throw std::invalid_argument("Expected type for '" + name + "': string");
}
else
SC_REPORT_FATAL("Query json", ("Parameter '" + name + "' does not exist.").c_str());
}

90
DRAMSys/library/src/configuration/ConfigurationLoader.h
View File

@@ -1,90 +0,0 @@
/*
* Copyright (c) 2015, University of Kaiserslautern
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
* OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors:
* Janik Schlemminger
* Matthias Jung
* Lukas Steiner
* Luiza Correa
*/
#ifndef CONFIGURATIONLOADER_H
#define CONFIGURATIONLOADER_H
#include <string>
#include "../common/third_party/nlohmann/single_include/nlohmann/json.hpp"
#include "../common/utils.h"
#include "Configuration.h"
#include "memspec/MemSpec.h"
#include "memspec/MemSpecDDR3.h"
#include "memspec/MemSpecDDR4.h"
#include "memspec/MemSpecWideIO.h"
#include "memspec/MemSpecLPDDR4.h"
#include "memspec/MemSpecWideIO2.h"
#include "memspec/MemSpecHBM2.h"
#include "memspec/MemSpecGDDR5.h"
#include "memspec/MemSpecGDDR5X.h"
#include "memspec/MemSpecGDDR6.h"
class ConfigurationLoader
{
public:
static void loadMCConfig(Configuration &config, std::string amconfigUri);
static void loadSimConfig(Configuration &config, std::string simconfigUri);
static void loadMemSpec(Configuration &config, std::string memspecUri);
static void loadTemperatureSimConfig(Configuration &config,
std::string simconfigUri);
private:
ConfigurationLoader() {}
// Loads common config of DRAMs
static void loadCommons(Configuration &config, nlohmann::json &memspec);
// Load specific config
static void loadDDR3(Configuration &config, nlohmann::json &memspec);
static void loadDDR4(Configuration &config, nlohmann::json &memspec);
static void loadLPDDR4(Configuration &config, nlohmann::json &memspec);
static void loadWideIO(Configuration &config, nlohmann::json &memspec);
static void loadWideIO2(Configuration &config, nlohmann::json &memspec);
static void loadHBM2(Configuration &config, nlohmann::json &memspec);
static void loadGDDR5(Configuration &config, nlohmann::json &memspec);
static void loadGDDR5X(Configuration &config, nlohmann::json &memspec);
static void loadGDDR6(Configuration &config, nlohmann::json &memspec);
static unsigned int parseUint(nlohmann::json &obj, std::string name);
static double parseUdouble(nlohmann::json &obj, std::string name);
static std::string parseString(nlohmann::json &obj, std::string name);
};
#endif // CONFIGURATIONLOADER_H

21
DRAMSys/library/src/configuration/memspec/MemSpec.cpp
View File

@@ -41,8 +41,27 @@
#include "../Configuration.h"
using namespace tlm;
using json = nlohmann::json;
MemSpec::MemSpec()
MemSpec::MemSpec(json &memspec, unsigned numberOfRanks, unsigned banksPerRank,
unsigned groupsPerRank, unsigned banksPerGroup,
unsigned numberOfBanks, unsigned numberOfBankGroups)
: numberOfRanks(numberOfRanks),
banksPerRank(banksPerRank),
groupsPerRank(groupsPerRank),
banksPerGroup(banksPerGroup),
numberOfBanks(numberOfBanks),
numberOfBankGroups(numberOfBankGroups),
numberOfRows(parseUint(memspec["memarchitecturespec"]["nbrOfRows"],"nbrOfRows")),
numberOfColumns(parseUint(memspec["memarchitecturespec"]["nbrOfColumns"],"nbrOfColumns")),
burstLength(parseUint(memspec["memarchitecturespec"]["burstLength"],"burstLength")),
dataRate(parseUint(memspec["memarchitecturespec"]["dataRate"],"dataRate")),
bitWidth(parseUint(memspec["memarchitecturespec"]["width"],"width")),
fCKMHz(parseUdouble(memspec["memtimingspec"]["clkMhz"], "clkMhz")),
tCK(sc_time(1.0 / fCKMHz, SC_US)),
burstDuration(tCK * (burstLength / dataRate)),
memoryId(parseString(memspec["memoryId"], "memoryId")),
memoryType(parseString(memspec["memoryType"], "memoryType"))
{
commandLengthInCycles = std::vector<unsigned>(numberOfCommands(), 1);
}

52
DRAMSys/library/src/configuration/memspec/MemSpec.h
View File

@@ -43,10 +43,30 @@
#include "../../common/dramExtensions.h"
#include "../../controller/Command.h"
#include "../../common/utils.h"
#include "../../common/third_party/nlohmann/single_include/nlohmann/json.hpp"
struct MemSpec
class MemSpec
{
MemSpec();
public:
unsigned numberOfRanks;
unsigned banksPerRank;
unsigned groupsPerRank;
unsigned banksPerGroup;
unsigned numberOfBanks;
unsigned numberOfBankGroups;
unsigned numberOfRows;
unsigned numberOfColumns;
unsigned burstLength;
unsigned dataRate;
unsigned bitWidth;
// Clock
double fCKMHz;
sc_time tCK;
std::string memoryId;
std::string memoryType;
virtual ~MemSpec() {}
virtual sc_time getRefreshIntervalAB() const = 0;
@@ -57,30 +77,14 @@ struct MemSpec
sc_time getCommandLength(Command) const;
std::string memoryId = "not defined.";
std::string memoryType = "not defined.";
protected:
MemSpec(nlohmann::json &memspec, unsigned numberOfRanks, unsigned banksPerRank,
unsigned groupsPerRank, unsigned banksPerGroup,
unsigned numberOfBanks, unsigned numberOfBankGroups);
unsigned int numberOfRanks;
unsigned int numberOfBankGroups;
unsigned int numberOfBanks;
unsigned int numberOfRows;
unsigned int numberOfColumns;
unsigned int burstLength;
unsigned int dataRate;
unsigned int bitWidth;
unsigned int banksPerRank;
unsigned int banksPerGroup;
unsigned int groupsPerRank;
// Clock
double fCKMHz;
sc_time tCK;
sc_time burstDuration;
// Command lengths on bus, usually one clock cycle
// Command lengths in cycles on bus, usually one clock cycle
std::vector<unsigned> commandLengthInCycles;
sc_time burstDuration;
};
#endif // MEMSPEC_H

51
DRAMSys/library/src/configuration/memspec/MemSpecDDR3.cpp
View File

@@ -36,6 +36,57 @@
#include "MemSpecDDR3.h"
using namespace tlm;
using json = nlohmann::json;
MemSpecDDR3::MemSpecDDR3(json &memspec)
: MemSpec(memspec,
parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"),
parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks"),
1,
parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks"),
parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks")
* parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"),
parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks")),
tCKE (tCK * parseUint(memspec["memtimingspec"]["CKE"], "CKE")),
tPD (tCKE),
tCKESR (tCK * parseUint(memspec["memtimingspec"]["CKESR"], "CKESR")),
tDQSCK (tCK * parseUint(memspec["memtimingspec"]["DQSCK"], "DQSCK")),
tRAS (tCK * parseUint(memspec["memtimingspec"]["RAS"], "RAS")),
tRC (tCK * parseUint(memspec["memtimingspec"]["RC"], "RC")),
tRCD (tCK * parseUint(memspec["memtimingspec"]["RCD"], "RCD")),
tRL (tCK * parseUint(memspec["memtimingspec"]["RL"], "RL")),
tRTP (tCK * parseUint(memspec["memtimingspec"]["RTP"], "RTP")),
tWL (tCK * parseUint(memspec["memtimingspec"]["WL"], "WL")),
tWR (tCK * parseUint(memspec["memtimingspec"]["WR"], "WR")),
tXP (tCK * parseUint(memspec["memtimingspec"]["XP"], "XP")),
tXS (tCK * parseUint(memspec["memtimingspec"]["XS"], "XS")),
tCCD (tCK * parseUint(memspec["memtimingspec"]["CCD"], "CCD")),
tFAW (tCK * parseUint(memspec["memtimingspec"]["FAW"], "FAW")),
tREFI (tCK * parseUint(memspec["memtimingspec"]["REFI"], "REFI")),
tRFC (tCK * parseUint(memspec["memtimingspec"]["RFC"], "RFC")),
tRP (tCK * parseUint(memspec["memtimingspec"]["RP"], "RP")),
tRRD (tCK * parseUint(memspec["memtimingspec"]["RRD"], "RRD")),
tWTR (tCK * parseUint(memspec["memtimingspec"]["WTR"], "WTR")),
tAL (tCK * parseUint(memspec["memtimingspec"]["AL"], "AL")),
tXPDLL (tCK * parseUint(memspec["memtimingspec"]["XPDLL"], "XPDLL")),
tXSDLL (tCK * parseUint(memspec["memtimingspec"]["XSDLL"], "XSDLL")),
tACTPDEN (tCK * parseUint(memspec["memtimingspec"]["ACTPDEN"], "ACTPDEN")),
tPRPDEN (tCK * parseUint(memspec["memtimingspec"]["PRPDEN"], "PRPDEN")),
tREFPDEN (tCK * parseUint(memspec["memtimingspec"]["REFPDEN"], "REFPDEN")),
tRTRS (tCK * parseUint(memspec["memtimingspec"]["RTRS"], "RTRS")),
iDD0 (parseUdouble(memspec["mempowerspec"]["idd0"], "idd0")),
iDD2N (parseUdouble(memspec["mempowerspec"]["idd2n"], "idd2n")),
iDD3N (parseUdouble(memspec["mempowerspec"]["idd3n"], "idd3n")),
iDD4R (parseUdouble(memspec["mempowerspec"]["idd4r"], "idd4r")),
iDD4W (parseUdouble(memspec["mempowerspec"]["idd4w"], "idd4w")),
iDD5 (parseUdouble(memspec["mempowerspec"]["idd5"], "idd5")),
iDD6 (parseUdouble(memspec["mempowerspec"]["idd6"], "idd6")),
vDD (parseUdouble(memspec["mempowerspec"]["vdd"], "vdd")),
iDD2P0 (parseUdouble(memspec["mempowerspec"]["idd2p0"], "idd2p0")),
iDD2P1 (parseUdouble(memspec["mempowerspec"]["idd2p1"], "idd2p1")),
iDD3P0 (parseUdouble(memspec["mempowerspec"]["idd3p0"], "idd3p0")),
iDD3P1 (parseUdouble(memspec["mempowerspec"]["idd3p1"], "idd3p1"))
{}
sc_time MemSpecDDR3::getRefreshIntervalAB() const
{

84
DRAMSys/library/src/configuration/memspec/MemSpecDDR3.h
View File

@@ -37,51 +37,55 @@
#define MEMSPECDDR3_H
#include "MemSpec.h"
#include "../../common/third_party/nlohmann/single_include/nlohmann/json.hpp"
struct MemSpecDDR3 final : public MemSpec
class MemSpecDDR3 final : public MemSpec
{
public:
MemSpecDDR3(nlohmann::json &memspec);
// Memspec Variables:
sc_time tCKE; // min time between pdx and pde
sc_time tPD; // min time in pdn
sc_time tCKESR; // min time in sref
sc_time tRAS; // active-time (act -> pre same bank)
sc_time tRC; // RAS-cycle-time (min time bw 2 succesive ACT to same bank)
sc_time tRCD; // act -> read/write
sc_time tRL; // read latency (read command start to data strobe)
sc_time tRTP; // read to precharge
sc_time tWL; // write latency
sc_time tWR; // write recovery (write to precharge)
sc_time tXP; // min delay to row access command after pdnpx pdnax
sc_time tXS; // min delay to row access command after srefx
sc_time tREFI;
sc_time tRFC;
sc_time tRP;
sc_time tDQSCK;
sc_time tCCD;
sc_time tFAW;
sc_time tRRD;
sc_time tWTR;
sc_time tXPDLL;
sc_time tXSDLL;
sc_time tAL;
sc_time tACTPDEN;
sc_time tPRPDEN;
sc_time tREFPDEN;
sc_time tRTRS;
const sc_time tCKE;
const sc_time tPD;
const sc_time tCKESR;
const sc_time tRAS;
const sc_time tRC;
const sc_time tRCD;
const sc_time tRL;
const sc_time tRTP;
const sc_time tWL;
const sc_time tWR;
const sc_time tXP;
const sc_time tXS;
const sc_time tREFI;
const sc_time tRFC;
const sc_time tRP;
const sc_time tDQSCK;
const sc_time tCCD;
const sc_time tFAW;
const sc_time tRRD;
const sc_time tWTR;
const sc_time tXPDLL;
const sc_time tXSDLL;
const sc_time tAL;
const sc_time tACTPDEN;
const sc_time tPRPDEN;
const sc_time tREFPDEN;
const sc_time tRTRS;
// Currents and Voltages:
double iDD0;
double iDD2N;
double iDD3N;
double iDD4R;
double iDD4W;
double iDD5;
double iDD6;
double vDD;
double iDD2P0;
double iDD2P1;
double iDD3P0;
double iDD3P1;
const double iDD0;
const double iDD2N;
const double iDD3N;
const double iDD4R;
const double iDD4W;
const double iDD5;
const double iDD6;
const double vDD;
const double iDD2P0;
const double iDD2P1;
const double iDD3P0;
const double iDD3P1;
virtual sc_time getRefreshIntervalAB() const override;
virtual sc_time getRefreshIntervalPB() const override;

68
DRAMSys/library/src/configuration/memspec/MemSpecDDR4.cpp
View File

@@ -34,8 +34,76 @@
*/
#include "MemSpecDDR4.h"
#include "../Configuration.h"
using namespace tlm;
using json = nlohmann::json;
MemSpecDDR4::MemSpecDDR4(json &memspec)
: MemSpec(memspec,
parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"),
parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks"),
parseUint(memspec["memarchitecturespec"]["nbrOfBankGroups"], "nbrOfBankGroups"),
parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks")
/ parseUint(memspec["memarchitecturespec"]["nbrOfBankGroups"], "nbrOfBankGroups"),
parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks")
* parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"),
parseUint(memspec["memarchitecturespec"]["nbrOfBankGroups"], "nbrOfBankGroups")
* parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks")),
tCKE (tCK * parseUint(memspec["memtimingspec"]["CKE"], "CKE")),
tPD (tCKE),
tCKESR (tCK * parseUint(memspec["memtimingspec"]["CKESR"], "CKESR")),
tDQSCK (tCK * parseUint(memspec["memtimingspec"]["DQSCK"], "DQSCK")),
tRAS (tCK * parseUint(memspec["memtimingspec"]["RAS"], "RAS")),
tRC (tCK * parseUint(memspec["memtimingspec"]["RC"], "RC")),
tRCD (tCK * parseUint(memspec["memtimingspec"]["RCD"], "RCD")),
tRL (tCK * parseUint(memspec["memtimingspec"]["RL"], "RL")),
tRTP (tCK * parseUint(memspec["memtimingspec"]["RTP"], "RTP")),
tWL (tCK * parseUint(memspec["memtimingspec"]["WL"], "WL")),
tWR (tCK * parseUint(memspec["memtimingspec"]["WR"], "WR")),
tXP (tCK * parseUint(memspec["memtimingspec"]["XP"], "XP")),
tXS (tCK * parseUint(memspec["memtimingspec"]["XS"], "XS")),
tCCD_S (tCK * parseUint(memspec["memtimingspec"]["CCD_S"], "CCD_S")),
tCCD_L (tCK * parseUint(memspec["memtimingspec"]["CCD_L"], "CCD_L")),
tFAW (tCK * parseUint(memspec["memtimingspec"]["FAW"], "FAW")),
tREFI ((Configuration::getInstance().refreshMode == 1) ?
(tCK * parseUint(memspec["memtimingspec"]["REFI"], "REFI")) :
((Configuration::getInstance().refreshMode == 2) ?
(tCK * (parseUint(memspec["memtimingspec"]["REFI"], "REFI") / 2)) :
(tCK * (parseUint(memspec["memtimingspec"]["REFI"], "REFI") / 4)))),
tRFC ((Configuration::getInstance().refreshMode == 1) ?
(tCK * parseUint(memspec["memtimingspec"]["RFC"], "RFC")) :
((Configuration::getInstance().refreshMode == 2) ?
(tCK * (parseUint(memspec["memtimingspec"]["RFC2"], "RFC2") / 2)) :
(tCK * (parseUint(memspec["memtimingspec"]["RFC4"], "RFC4") / 4)))),
tRP (tCK * parseUint(memspec["memtimingspec"]["RP"], "RP")),
tRRD_S (tCK * parseUint(memspec["memtimingspec"]["RRD_S"], "RRD_S")),
tRRD_L (tCK * parseUint(memspec["memtimingspec"]["RRD_L"], "RRD_L")),
tWTR_S (tCK * parseUint(memspec["memtimingspec"]["WTR_S"], "WTR_S")),
tWTR_L (tCK * parseUint(memspec["memtimingspec"]["WTR_L"], "WTR_L")),
tAL (tCK * parseUint(memspec["memtimingspec"]["AL"], "AL")),
tXPDLL (tCK * parseUint(memspec["memtimingspec"]["XPDLL"], "XPDLL")),
tXSDLL (tCK * parseUint(memspec["memtimingspec"]["XSDLL"], "XSDLL")),
tACTPDEN (tCK * parseUint(memspec["memtimingspec"]["ACTPDEN"], "ACTPDEN")),
tPRPDEN (tCK * parseUint(memspec["memtimingspec"]["PRPDEN"], "PRPDEN")),
tREFPDEN (tCK * parseUint(memspec["memtimingspec"]["REFPDEN"], "REFPDEN")),
tRTRS (tCK * parseUint(memspec["memtimingspec"]["RTRS"], "RTRS")),
iDD0 (parseUdouble(memspec["mempowerspec"]["idd0"], "idd0")),
iDD2N (parseUdouble(memspec["mempowerspec"]["idd2n"], "idd2n")),
iDD3N (parseUdouble(memspec["mempowerspec"]["idd3n"], "idd3n")),
iDD4R (parseUdouble(memspec["mempowerspec"]["idd4r"], "idd4r")),
iDD4W (parseUdouble(memspec["mempowerspec"]["idd4w"], "idd4w")),
iDD5 (parseUdouble(memspec["mempowerspec"]["idd5"], "idd5")),
iDD6 (parseUdouble(memspec["mempowerspec"]["idd6"], "idd6")),
vDD (parseUdouble(memspec["mempowerspec"]["vdd"], "vdd")),
iDD02 (parseUdouble(memspec["mempowerspec"]["idd02"], "idd02")),
iDD2P0 (parseUdouble(memspec["mempowerspec"]["idd2p0"], "idd2p0")),
iDD2P1 (parseUdouble(memspec["mempowerspec"]["idd2p1"], "idd2p1")),
iDD3P0 (parseUdouble(memspec["mempowerspec"]["idd3p0"], "idd3p0")),
iDD3P1 (parseUdouble(memspec["mempowerspec"]["idd3p1"], "idd3p1")),
iDD62 (parseUdouble(memspec["mempowerspec"]["idd62"], "idd62")),
vDD2 (parseUdouble(memspec["mempowerspec"]["vdd2"], "vdd2"))
{}
sc_time MemSpecDDR4::getRefreshIntervalAB() const
{

96
DRAMSys/library/src/configuration/memspec/MemSpecDDR4.h
View File

@@ -37,57 +37,61 @@
#define MEMSPECDDR4_H
#include "MemSpec.h"
#include "../../common/third_party/nlohmann/single_include/nlohmann/json.hpp"
struct MemSpecDDR4 final : public MemSpec
class MemSpecDDR4 final : public MemSpec
{
public:
MemSpecDDR4(nlohmann::json &memspec);
// Memspec Variables:
sc_time tCKE; // min time between pdx and pde
sc_time tPD; // min time in pdn
sc_time tCKESR; // min time in sref
sc_time tRAS; // active-time (act -> pre same bank)
sc_time tRC; // RAS-cycle-time (min time bw 2 succesive ACT to same bank)
sc_time tRCD; // act -> read/write
sc_time tRL; // read latency (read command start to data strobe)
sc_time tRTP; // read to precharge
sc_time tWL; // write latency
sc_time tWR; // write recovery (write to precharge)
sc_time tXP; // min delay to row access command after pdnpx pdnax
sc_time tXS; // min delay to row access command after srefx
sc_time tREFI;
sc_time tRFC;
sc_time tRP;
sc_time tDQSCK;
sc_time tCCD_S;
sc_time tCCD_L;
sc_time tFAW;
sc_time tRRD_S;
sc_time tRRD_L;
sc_time tWTR_S;
sc_time tWTR_L;
sc_time tAL;
sc_time tXPDLL;
sc_time tXSDLL;
sc_time tACTPDEN;
sc_time tPRPDEN;
sc_time tREFPDEN;
sc_time tRTRS;
const sc_time tCKE;
const sc_time tPD;
const sc_time tCKESR;
const sc_time tRAS;
const sc_time tRC;
const sc_time tRCD;
const sc_time tRL;
const sc_time tRTP;
const sc_time tWL;
const sc_time tWR;
const sc_time tXP;
const sc_time tXS;
const sc_time tREFI;
const sc_time tRFC;
const sc_time tRP;
const sc_time tDQSCK;
const sc_time tCCD_S;
const sc_time tCCD_L;
const sc_time tFAW;
const sc_time tRRD_S;
const sc_time tRRD_L;
const sc_time tWTR_S;
const sc_time tWTR_L;
const sc_time tAL;
const sc_time tXPDLL;
const sc_time tXSDLL;
const sc_time tACTPDEN;
const sc_time tPRPDEN;
const sc_time tREFPDEN;
const sc_time tRTRS;
// Currents and Voltages:
double iDD0;
double iDD2N;
double iDD3N;
double iDD4R;
double iDD4W;
double iDD5;
double iDD6;
double vDD;
double iDD02;
double iDD2P0;
double iDD2P1;
double iDD3P0;
double iDD3P1;
double iDD62;
double vDD2;
const double iDD0;
const double iDD2N;
const double iDD3N;
const double iDD4R;
const double iDD4W;
const double iDD5;
const double iDD6;
const double vDD;
const double iDD02;
const double iDD2P0;
const double iDD2P1;
const double iDD3P0;
const double iDD3P1;
const double iDD62;
const double vDD2;
virtual sc_time getRefreshIntervalPB() const override;
virtual sc_time getRefreshIntervalAB() const override;

48
DRAMSys/library/src/configuration/memspec/MemSpecGDDR5.cpp
View File

@@ -36,6 +36,54 @@
#include "MemSpecGDDR5.h"
using namespace tlm;
using json = nlohmann::json;
MemSpecGDDR5::MemSpecGDDR5(json &memspec)
: MemSpec(memspec,
parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"),
parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks"),
parseUint(memspec["memarchitecturespec"]["nbrOfBankGroups"], "nbrOfBankGroups"),
parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks")
/ parseUint(memspec["memarchitecturespec"]["nbrOfBankGroups"], "nbrOfBankGroups"),
parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks")
* parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"),
parseUint(memspec["memarchitecturespec"]["nbrOfBankGroups"], "nbrOfBankGroups")
* parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks")),
tRP (tCK * parseUint(memspec["memtimingspec"]["RP"], "RP")),
tRAS (tCK * parseUint(memspec["memtimingspec"]["RAS"], "RAS")),
tRC (tCK * parseUint(memspec["memtimingspec"]["RC"], "RC")),
tRCDRD (tCK * parseUint(memspec["memtimingspec"]["RCDRD"], "RCDRD")),
tRCDWR (tCK * parseUint(memspec["memtimingspec"]["RCDWR"], "RCDWR")),
tRTP (tCK * parseUint(memspec["memtimingspec"]["RTP"], "RTP")),
tRRDS (tCK * parseUint(memspec["memtimingspec"]["RRDS"], "RRDS")),
tRRDL (tCK * parseUint(memspec["memtimingspec"]["RRDL"], "RRDL")),
tCCDS (tCK * parseUint(memspec["memtimingspec"]["CCDS"], "CCDS")),
tCCDL (tCK * parseUint(memspec["memtimingspec"]["CCDL"], "CCDL")),
tCL (tCK * parseUint(memspec["memtimingspec"]["CL"], "CL")),
tWCK2CKPIN (tCK * parseUint(memspec["memtimingspec"]["WCK2CKPIN"], "WCK2CKPIN")),
tWCK2CK (tCK * parseUint(memspec["memtimingspec"]["WCK2CK"], "WCK2CK")),
tWCK2DQO (tCK * parseUint(memspec["memtimingspec"]["WCK2DQO"], "WCK2DQO")),
tRTW (tCK * parseUint(memspec["memtimingspec"]["RTW"], "RTW")),
tWL (tCK * parseUint(memspec["memtimingspec"]["WL"], "WL")),
tWCK2DQI (tCK * parseUint(memspec["memtimingspec"]["WCK2DQI"], "WCK2DQI")),
tWR (tCK * parseUint(memspec["memtimingspec"]["WR"], "WR")),
tWTRS (tCK * parseUint(memspec["memtimingspec"]["WTRS"], "WTRS")),
tWTRL (tCK * parseUint(memspec["memtimingspec"]["WTRL"], "WTRL")),
tCKE (tCK * parseUint(memspec["memtimingspec"]["CKE"], "CKE")),
tPD (tCK * parseUint(memspec["memtimingspec"]["PD"], "PD")),
tXPN (tCK * parseUint(memspec["memtimingspec"]["XPN"], "XPN")),
tREFI (tCK * parseUint(memspec["memtimingspec"]["REFI"], "REFI")),
tREFIPB (tCK * parseUint(memspec["memtimingspec"]["REFIPB"], "REFIPB")),
tRFC (tCK * parseUint(memspec["memtimingspec"]["RFC"], "RFC")),
tRFCPB (tCK * parseUint(memspec["memtimingspec"]["RFCPB"], "RFCPB")),
tRREFD (tCK * parseUint(memspec["memtimingspec"]["RREFD"], "RREFD")),
tXS (tCK * parseUint(memspec["memtimingspec"]["XS"], "XS")),
tFAW (tCK * parseUint(memspec["memtimingspec"]["FAW"], "FAW")),
t32AW (tCK * parseUint(memspec["memtimingspec"]["32AW"], "32AW")),
tPPD (tCK * parseUint(memspec["memtimingspec"]["PPD"], "PPD")),
tLK (tCK * parseUint(memspec["memtimingspec"]["LK"], "LK")),
tRTRS (tCK * parseUint(memspec["memtimingspec"]["RTRS"], "RTRS"))
{}
sc_time MemSpecGDDR5::getRefreshIntervalAB() const
{

74
DRAMSys/library/src/configuration/memspec/MemSpecGDDR5.h
View File

@@ -37,46 +37,50 @@
#define MEMSPECGDDR5_H
#include "MemSpec.h"
#include "../../common/third_party/nlohmann/single_include/nlohmann/json.hpp"
struct MemSpecGDDR5 final : public MemSpec
class MemSpecGDDR5 final : public MemSpec
{
public:
MemSpecGDDR5(nlohmann::json &memspec);
// Memspec Variables:
sc_time tRP;
sc_time tRAS;
sc_time tRC;
sc_time tRCDRD;
sc_time tRCDWR;
sc_time tRTP;
sc_time tRRDS;
sc_time tRRDL;
sc_time tCCDS;
sc_time tCCDL;
sc_time tCL;
sc_time tWCK2CKPIN;
sc_time tWCK2CK;
sc_time tWCK2DQO;
sc_time tRTW;
sc_time tWL;
sc_time tWCK2DQI;
sc_time tWR;
sc_time tWTRS;
sc_time tWTRL;
sc_time tCKE;
sc_time tPD;
sc_time tXPN;
sc_time tREFI;
sc_time tREFIPB;
sc_time tRFC;
sc_time tRFCPB;
sc_time tRREFD;
sc_time tXS;
sc_time tFAW;
sc_time t32AW;
const sc_time tRP;
const sc_time tRAS;
const sc_time tRC;
const sc_time tRCDRD;
const sc_time tRCDWR;
const sc_time tRTP;
const sc_time tRRDS;
const sc_time tRRDL;
const sc_time tCCDS;
const sc_time tCCDL;
const sc_time tCL;
const sc_time tWCK2CKPIN;
const sc_time tWCK2CK;
const sc_time tWCK2DQO;
const sc_time tRTW;
const sc_time tWL;
const sc_time tWCK2DQI;
const sc_time tWR;
const sc_time tWTRS;
const sc_time tWTRL;
const sc_time tCKE;
const sc_time tPD;
const sc_time tXPN;
const sc_time tREFI;
const sc_time tREFIPB;
const sc_time tRFC;
const sc_time tRFCPB;
const sc_time tRREFD;
const sc_time tXS;
const sc_time tFAW;
const sc_time t32AW;
// sc_time tRDSRE; // = tCL + tWCK2CKPIN + tWCK2CK + tWCK2DQO + BurstLength / DataRate * tCK;
// sc_time tWRSRE; // = tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI + BurstLength / DataRate * tCK;
sc_time tPPD;
sc_time tLK;
sc_time tRTRS;
const sc_time tPPD;
const sc_time tLK;
const sc_time tRTRS;
// Currents and Voltages:
// TODO: to be completed

48
DRAMSys/library/src/configuration/memspec/MemSpecGDDR5X.cpp
View File

@@ -36,6 +36,54 @@
#include "MemSpecGDDR5X.h"
using namespace tlm;
using json = nlohmann::json;
MemSpecGDDR5X::MemSpecGDDR5X(json &memspec)
: MemSpec(memspec,
parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"),
parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks"),
parseUint(memspec["memarchitecturespec"]["nbrOfBankGroups"], "nbrOfBankGroups"),
parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks")
/ parseUint(memspec["memarchitecturespec"]["nbrOfBankGroups"], "nbrOfBankGroups"),
parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks")
* parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"),
parseUint(memspec["memarchitecturespec"]["nbrOfBankGroups"], "nbrOfBankGroups")
* parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks")),
tRP (tCK * parseUint(memspec["memtimingspec"]["RP"], "RP")),
tRAS (tCK * parseUint(memspec["memtimingspec"]["RAS"], "RAS")),
tRC (tCK * parseUint(memspec["memtimingspec"]["RC"], "RC")),
tRCDRD (tCK * parseUint(memspec["memtimingspec"]["RCDRD"], "RCDRD")),
tRCDWR (tCK * parseUint(memspec["memtimingspec"]["RCDWR"], "RCDWR")),
tRTP (tCK * parseUint(memspec["memtimingspec"]["RTP"], "RTP")),
tRRDS (tCK * parseUint(memspec["memtimingspec"]["RRDS"], "RRDS")),
tRRDL (tCK * parseUint(memspec["memtimingspec"]["RRDL"], "RRDL")),
tCCDS (tCK * parseUint(memspec["memtimingspec"]["CCDS"], "CCDS")),
tCCDL (tCK * parseUint(memspec["memtimingspec"]["CCDL"], "CCDL")),
tRL (tCK * parseUint(memspec["memtimingspec"]["CL"], "CL")),
tWCK2CKPIN (tCK * parseUint(memspec["memtimingspec"]["WCK2CKPIN"], "WCK2CKPIN")),
tWCK2CK (tCK * parseUint(memspec["memtimingspec"]["WCK2CK"], "WCK2CK")),
tWCK2DQO (tCK * parseUint(memspec["memtimingspec"]["WCK2DQO"], "WCK2DQO")),
tRTW (tCK * parseUint(memspec["memtimingspec"]["RTW"], "RTW")),
tWL (tCK * parseUint(memspec["memtimingspec"]["WL"], "WL")),
tWCK2DQI (tCK * parseUint(memspec["memtimingspec"]["WCK2DQI"], "WCK2DQI")),
tWR (tCK * parseUint(memspec["memtimingspec"]["WR"], "WR")),
tWTRS (tCK * parseUint(memspec["memtimingspec"]["WTRS"], "WTRS")),
tWTRL (tCK * parseUint(memspec["memtimingspec"]["WTRL"], "WTRL")),
tCKE (tCK * parseUint(memspec["memtimingspec"]["CKE"], "CKE")),
tPD (tCK * parseUint(memspec["memtimingspec"]["PD"], "PD")),
tXP (tCK * parseUint(memspec["memtimingspec"]["XP"], "XP")),
tREFI (tCK * parseUint(memspec["memtimingspec"]["REFI"], "REFI")),
tREFIPB (tCK * parseUint(memspec["memtimingspec"]["REFIPB"], "REFIPB")),
tRFC (tCK * parseUint(memspec["memtimingspec"]["RFC"], "RFC")),
tRFCPB (tCK * parseUint(memspec["memtimingspec"]["RFCPB"], "RFCPB")),
tRREFD (tCK * parseUint(memspec["memtimingspec"]["RREFD"], "RREFD")),
tXS (tCK * parseUint(memspec["memtimingspec"]["XS"], "XS")),
tFAW (tCK * parseUint(memspec["memtimingspec"]["FAW"], "FAW")),
t32AW (tCK * parseUint(memspec["memtimingspec"]["32AW"], "32AW")),
tPPD (tCK * parseUint(memspec["memtimingspec"]["PPD"], "PPD")),
tLK (tCK * parseUint(memspec["memtimingspec"]["LK"], "LK")),
tRTRS (tCK * parseUint(memspec["memtimingspec"]["RTRS"], "RTRS"))
{}
sc_time MemSpecGDDR5X::getRefreshIntervalAB() const
{

74
DRAMSys/library/src/configuration/memspec/MemSpecGDDR5X.h
View File

@@ -37,46 +37,50 @@
#define MEMSPECGDDR5X_H
#include "MemSpec.h"
#include "../../common/third_party/nlohmann/single_include/nlohmann/json.hpp"
struct MemSpecGDDR5X final : public MemSpec
class MemSpecGDDR5X final : public MemSpec
{
public:
MemSpecGDDR5X(nlohmann::json &memspec);
// Memspec Variables:
sc_time tRP;
sc_time tRAS;
sc_time tRC;
sc_time tRCDRD;
sc_time tRCDWR;
sc_time tRTP;
sc_time tRRDS;
sc_time tRRDL;
sc_time tCCDS;
sc_time tCCDL;
sc_time tRL;
sc_time tWCK2CKPIN;
sc_time tWCK2CK;
sc_time tWCK2DQO;
sc_time tRTW;
sc_time tWL;
sc_time tWCK2DQI;
sc_time tWR;
sc_time tWTRS;
sc_time tWTRL;
sc_time tCKE;
sc_time tPD;
sc_time tXP;
sc_time tREFI;
sc_time tREFIPB;
sc_time tRFC;
sc_time tRFCPB;
sc_time tRREFD;
sc_time tXS;
sc_time tFAW;
sc_time t32AW;
const sc_time tRP;
const sc_time tRAS;
const sc_time tRC;
const sc_time tRCDRD;
const sc_time tRCDWR;
const sc_time tRTP;
const sc_time tRRDS;
const sc_time tRRDL;
const sc_time tCCDS;
const sc_time tCCDL;
const sc_time tRL;
const sc_time tWCK2CKPIN;
const sc_time tWCK2CK;
const sc_time tWCK2DQO;
const sc_time tRTW;
const sc_time tWL;
const sc_time tWCK2DQI;
const sc_time tWR;
const sc_time tWTRS;
const sc_time tWTRL;
const sc_time tCKE;
const sc_time tPD;
const sc_time tXP;
const sc_time tREFI;
const sc_time tREFIPB;
const sc_time tRFC;
const sc_time tRFCPB;
const sc_time tRREFD;
const sc_time tXS;
const sc_time tFAW;
const sc_time t32AW;
// sc_time tRDSRE; // = tCL + tWCK2CKPIN + tWCK2CK + tWCK2DQO + BurstLength / DataRate * tCK;
// sc_time tWRSRE; // = tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI + BurstLength / DataRate * tCK;
sc_time tPPD;
sc_time tLK;
sc_time tRTRS;
const sc_time tPPD;
const sc_time tLK;
const sc_time tRTRS;
// Currents and Voltages:
// TODO: to be completed

50
DRAMSys/library/src/configuration/memspec/MemSpecGDDR6.cpp
View File

@@ -36,6 +36,56 @@
#include "MemSpecGDDR6.h"
using namespace tlm;
using json = nlohmann::json;
MemSpecGDDR6::MemSpecGDDR6(json &memspec)
: MemSpec(memspec,
parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"),
parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks"),
parseUint(memspec["memarchitecturespec"]["nbrOfBankGroups"], "nbrOfBankGroups"),
parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks")
/ parseUint(memspec["memarchitecturespec"]["nbrOfBankGroups"], "nbrOfBankGroups"),
parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks")
* parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"),
parseUint(memspec["memarchitecturespec"]["nbrOfBankGroups"], "nbrOfBankGroups")
* parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks")),
tRP (tCK * parseUint(memspec["memtimingspec"]["RP"], "RP")),
tRAS (tCK * parseUint(memspec["memtimingspec"]["RAS"], "RAS")),
tRC (tCK * parseUint(memspec["memtimingspec"]["RC"], "RC")),
tRCDRD (tCK * parseUint(memspec["memtimingspec"]["RCDRD"], "RCDRD")),
tRCDWR (tCK * parseUint(memspec["memtimingspec"]["RCDWR"], "RCDWR")),
tRTP (tCK * parseUint(memspec["memtimingspec"]["RTP"], "RTP")),
tRRDS (tCK * parseUint(memspec["memtimingspec"]["RRDS"], "RRDS")),
tRRDL (tCK * parseUint(memspec["memtimingspec"]["RRDL"], "RRDL")),
tCCDS (tCK * parseUint(memspec["memtimingspec"]["CCDS"], "CCDS")),
tCCDL (tCK * parseUint(memspec["memtimingspec"]["CCDL"], "CCDL")),
tRL (tCK * parseUint(memspec["memtimingspec"]["RL"], "RL")),
tWCK2CKPIN (tCK * parseUint(memspec["memtimingspec"]["WCK2CKPIN"], "WCK2CKPIN")),
tWCK2CK (tCK * parseUint(memspec["memtimingspec"]["WCK2CK"], "WCK2CK")),
tWCK2DQO (tCK * parseUint(memspec["memtimingspec"]["WCK2DQO"], "WCK2DQO")),
tRTW (tCK * parseUint(memspec["memtimingspec"]["RTW"], "RTW")),
tWL (tCK * parseUint(memspec["memtimingspec"]["WL"], "WL")),
tWCK2DQI (tCK * parseUint(memspec["memtimingspec"]["WCK2DQI"], "WCK2DQI")),
tWR (tCK * parseUint(memspec["memtimingspec"]["WR"], "WR")),
tWTRS (tCK * parseUint(memspec["memtimingspec"]["WTRS"], "WTRS")),
tWTRL (tCK * parseUint(memspec["memtimingspec"]["WTRL"], "WTRL")),
tPD (tCK * parseUint(memspec["memtimingspec"]["PD"], "PD")),
tCKESR (tCK * parseUint(memspec["memtimingspec"]["CKESR"], "CKESR")),
tXP (tCK * parseUint(memspec["memtimingspec"]["XP"], "XP")),
tREFI (tCK * parseUint(memspec["memtimingspec"]["REFI"], "REFI")),
tREFIPB (tCK * parseUint(memspec["memtimingspec"]["REFIPB"], "REFIPB")),
tRFC (tCK * parseUint(memspec["memtimingspec"]["RFC"], "RFC")),
tRFCPB (tCK * parseUint(memspec["memtimingspec"]["RFCPB"], "RFCPB")),
tRREFD (tCK * parseUint(memspec["memtimingspec"]["RREFD"], "RREFD")),
tXS (tCK * parseUint(memspec["memtimingspec"]["XS"], "XS")),
tFAW (tCK * parseUint(memspec["memtimingspec"]["FAW"], "FAW")),
tPPD (tCK * parseUint(memspec["memtimingspec"]["PPD"], "PPD")),
tLK (tCK * parseUint(memspec["memtimingspec"]["LK"], "LK")),
tACTPDE (tCK * parseUint(memspec["memtimingspec"]["ACTPDE"], "ACTPDE")),
tPREPDE (tCK * parseUint(memspec["memtimingspec"]["PREPDE"], "PREPDE")),
tREFPDE (tCK * parseUint(memspec["memtimingspec"]["REFPDE"], "REFPDE")),
tRTRS (tCK * parseUint(memspec["memtimingspec"]["RTRS"], "RTRS"))
{}
sc_time MemSpecGDDR6::getRefreshIntervalAB() const
{

76
DRAMSys/library/src/configuration/memspec/MemSpecGDDR6.h
View File

@@ -37,48 +37,52 @@
#define MEMSPECGDDR6_H
#include "MemSpec.h"
#include "../../common/third_party/nlohmann/single_include/nlohmann/json.hpp"
struct MemSpecGDDR6 final : public MemSpec
{
public:
MemSpecGDDR6(nlohmann::json &memspec);
// Memspec Variables:
sc_time tRP;
sc_time tRAS;
sc_time tRC;
sc_time tRCDRD;
sc_time tRCDWR;
sc_time tRTP;
sc_time tRRDS;
sc_time tRRDL;
sc_time tCCDS;
sc_time tCCDL;
sc_time tRL;
sc_time tWCK2CKPIN;
sc_time tWCK2CK;
sc_time tWCK2DQO;
sc_time tRTW;
sc_time tWL;
sc_time tWCK2DQI;
sc_time tWR;
sc_time tWTRS;
sc_time tWTRL;
sc_time tPD;
sc_time tCKESR;
sc_time tXP;
sc_time tREFI;
sc_time tREFIPB;
sc_time tRFC;
sc_time tRFCPB;
sc_time tRREFD;
sc_time tXS;
sc_time tFAW;
const sc_time tRP;
const sc_time tRAS;
const sc_time tRC;
const sc_time tRCDRD;
const sc_time tRCDWR;
const sc_time tRTP;
const sc_time tRRDS;
const sc_time tRRDL;
const sc_time tCCDS;
const sc_time tCCDL;
const sc_time tRL;
const sc_time tWCK2CKPIN;
const sc_time tWCK2CK;
const sc_time tWCK2DQO;
const sc_time tRTW;
const sc_time tWL;
const sc_time tWCK2DQI;
const sc_time tWR;
const sc_time tWTRS;
const sc_time tWTRL;
const sc_time tPD;
const sc_time tCKESR;
const sc_time tXP;
const sc_time tREFI;
const sc_time tREFIPB;
const sc_time tRFC;
const sc_time tRFCPB;
const sc_time tRREFD;
const sc_time tXS;
const sc_time tFAW;
// sc_time tRDSRE; // = tCL + tWCK2CKPIN + tWCK2CK + tWCK2DQO + BurstLength / DataRate * tCK;
// sc_time tWRSRE; // = tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI + BurstLength / DataRate * tCK;
sc_time tPPD;
sc_time tLK;
sc_time tACTPDE;
sc_time tPREPDE;
sc_time tREFPDE;
sc_time tRTRS;
const sc_time tPPD;
const sc_time tLK;
const sc_time tACTPDE;
const sc_time tPREPDE;
const sc_time tREFPDE;
const sc_time tRTRS;
// Currents and Voltages:
// TODO: to be completed

42
DRAMSys/library/src/configuration/memspec/MemSpecHBM2.cpp
View File

@@ -36,8 +36,48 @@
#include "MemSpecHBM2.h"
using namespace tlm;
using json = nlohmann::json;
MemSpecHBM2::MemSpecHBM2()
MemSpecHBM2::MemSpecHBM2(json &memspec)
: MemSpec(memspec,
parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"),
parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks"),
parseUint(memspec["memarchitecturespec"]["nbrOfBankGroups"], "nbrOfBankGroups"),
parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks")
/ parseUint(memspec["memarchitecturespec"]["nbrOfBankGroups"], "nbrOfBankGroups"),
parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks")
* parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"),
parseUint(memspec["memarchitecturespec"]["nbrOfBankGroups"], "nbrOfBankGroups")
* parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks")),
tDQSCK (tCK * parseUint(memspec["memtimingspec"]["DQSCK"], "DQSCK")),
tRC (tCK * parseUint(memspec["memtimingspec"]["RC"], "RC")),
tRAS (tCK * parseUint(memspec["memtimingspec"]["RAS"], "RAS")),
tRCDRD (tCK * parseUint(memspec["memtimingspec"]["RCDRD"], "RCDRD")),
tRCDWR (tCK * parseUint(memspec["memtimingspec"]["RCDWR"], "RCDWR")),
tRRDL (tCK * parseUint(memspec["memtimingspec"]["RRDL"], "RRDL")),
tRRDS (tCK * parseUint(memspec["memtimingspec"]["RRDS"], "RRDS")),
tFAW (tCK * parseUint(memspec["memtimingspec"]["FAW"], "FAW")),
tRTP (tCK * parseUint(memspec["memtimingspec"]["RTP"], "RTP")),
tRP (tCK * parseUint(memspec["memtimingspec"]["RP"], "RP")),
tRL (tCK * parseUint(memspec["memtimingspec"]["RL"], "RL")),
tWL (tCK * parseUint(memspec["memtimingspec"]["WL"], "WL")),
tPL (tCK * parseUint(memspec["memtimingspec"]["PL"], "PL")),
tWR (tCK * parseUint(memspec["memtimingspec"]["WR"], "WR")),
tCCDL (tCK * parseUint(memspec["memtimingspec"]["CCDL"], "CCDL")),
tCCDS (tCK * parseUint(memspec["memtimingspec"]["CCDS"], "CCDS")),
tWTRL (tCK * parseUint(memspec["memtimingspec"]["WTRL"], "WTRL")),
tWTRS (tCK * parseUint(memspec["memtimingspec"]["WTRS"], "WTRS")),
tRTW (tCK * parseUint(memspec["memtimingspec"]["RTW"], "RTW")),
tXP (tCK * parseUint(memspec["memtimingspec"]["XP"], "XP")),
tCKE (tCK * parseUint(memspec["memtimingspec"]["CKE"], "CKE")),
tPD (tCKE),
tCKESR (tCKE + tCK),
tXS (tCK * parseUint(memspec["memtimingspec"]["XS"], "XS")),
tRFC (tCK * parseUint(memspec["memtimingspec"]["RFC"], "RFC")),
tRFCSB (tCK * parseUint(memspec["memtimingspec"]["RFCSB"], "RFCSB")),
tRREFD (tCK * parseUint(memspec["memtimingspec"]["RREFD"], "RREFD")),
tREFI (tCK * parseUint(memspec["memtimingspec"]["REFI"], "REFI")),
tREFISB (tCK * parseUint(memspec["memtimingspec"]["REFISB"], "REFISB"))
{
commandLengthInCycles[Command::ACT] = 2;
}

64
DRAMSys/library/src/configuration/memspec/MemSpecHBM2.h
View File

@@ -37,43 +37,45 @@
#define MEMSPECHBM2_H
#include "MemSpec.h"
#include "../../common/third_party/nlohmann/single_include/nlohmann/json.hpp"
struct MemSpecHBM2 final : public MemSpec
class MemSpecHBM2 final : public MemSpec
{
MemSpecHBM2();
public:
MemSpecHBM2(nlohmann::json &memspec);
// Memspec Variables:
sc_time tDQSCK;
const sc_time tDQSCK;
// sc_time tDQSQ; // TODO: check actual value of this parameter
sc_time tRC;
sc_time tRAS;
sc_time tRCDRD;
sc_time tRCDWR;
sc_time tRRDL;
sc_time tRRDS;
sc_time tFAW;
sc_time tRTP;
sc_time tRP;
sc_time tRL;
sc_time tWL;
sc_time tPL;
sc_time tWR;
sc_time tCCDL;
sc_time tCCDS;
const sc_time tRC;
const sc_time tRAS;
const sc_time tRCDRD;
const sc_time tRCDWR;
const sc_time tRRDL;
const sc_time tRRDS;
const sc_time tFAW;
const sc_time tRTP;
const sc_time tRP;
const sc_time tRL;
const sc_time tWL;
const sc_time tPL;
const sc_time tWR;
const sc_time tCCDL;
const sc_time tCCDS;
// sc_time tCCDR; // TODO: consecutive reads to different stack IDs
sc_time tWTRL;
sc_time tWTRS;
sc_time tRTW;
sc_time tXP;
sc_time tCKE;
sc_time tPD; // = tCKE;
sc_time tCKESR; // = tCKE + tCK;
sc_time tXS;
sc_time tRFC;
sc_time tRFCSB;
sc_time tRREFD;
sc_time tREFI;
sc_time tREFISB;
const sc_time tWTRL;
const sc_time tWTRS;
const sc_time tRTW;
const sc_time tXP;
const sc_time tCKE;
const sc_time tPD; // = tCKE;
const sc_time tCKESR; // = tCKE + tCK;
const sc_time tXS;
const sc_time tRFC;
const sc_time tRFCSB;
const sc_time tRREFD;
const sc_time tREFI;
const sc_time tREFISB;
// Currents and Voltages:
// TODO: to be completed

42
DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.cpp
View File

@@ -36,8 +36,48 @@
#include "MemSpecLPDDR4.h"
using namespace tlm;
using json = nlohmann::json;
MemSpecLPDDR4::MemSpecLPDDR4()
MemSpecLPDDR4::MemSpecLPDDR4(json &memspec)
: MemSpec(memspec,
parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"),
parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks"),
1,
parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks"),
parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks")
* parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"),
parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks")),
tREFI (tCK * parseUint(memspec["memtimingspec"]["REFI"], "REFI")),
tREFIpb (tCK * parseUint(memspec["memtimingspec"]["REFIPB"], "REFIPB")),
tRFCab (tCK * parseUint(memspec["memtimingspec"]["RFCAB"], "RFCAB")),
tRFCpb (tCK * parseUint(memspec["memtimingspec"]["RFCPB"], "RFCPB")),
tRPab (tCK * parseUint(memspec["memtimingspec"]["RPAB"], "RPAB")),
tRPpb (tCK * parseUint(memspec["memtimingspec"]["RPPB"], "RPPB")),
tRCab (tCK * parseUint(memspec["memtimingspec"]["RCAB"], "RCAB")),
tRCpb (tCK * parseUint(memspec["memtimingspec"]["RCPB"], "RCPB")),
tPPD (tCK * parseUint(memspec["memtimingspec"]["PPD"], "PPD")),
tRAS (tCK * parseUint(memspec["memtimingspec"]["RAS"], "RAS")),
tRCD (tCK * parseUint(memspec["memtimingspec"]["RCD"], "RCD")),
tFAW (tCK * parseUint(memspec["memtimingspec"]["FAW"], "FAW")),
tRRD (tCK * parseUint(memspec["memtimingspec"]["RRD"], "RRD")),
tCCD (tCK * parseUint(memspec["memtimingspec"]["CCD"], "CCD")),
tRL (tCK * parseUint(memspec["memtimingspec"]["RL"], "RL")),
tRPST (tCK * parseUint(memspec["memtimingspec"]["RPST"], "RPST")),
tDQSCK (tCK * parseUint(memspec["memtimingspec"]["DQSCK"], "DQSCK")),
tRTP (tCK * parseUint(memspec["memtimingspec"]["RTP"], "RTP")),
tWL (tCK * parseUint(memspec["memtimingspec"]["WL"], "WL")),
tDQSS (tCK * parseUint(memspec["memtimingspec"]["DQSS"], "DQSS")),
tDQS2DQ (tCK * parseUint(memspec["memtimingspec"]["DQS2DQ"], "DQS2DQ")),
tWR (tCK * parseUint(memspec["memtimingspec"]["WR"], "WR")),
tWPRE (tCK * parseUint(memspec["memtimingspec"]["WPRE"], "WPRE")),
tWTR (tCK * parseUint(memspec["memtimingspec"]["WTR"], "WTR")),
tXP (tCK * parseUint(memspec["memtimingspec"]["XP"], "XP")),
tSR (tCK * parseUint(memspec["memtimingspec"]["SR"], "SR")),
tXSR (tCK * parseUint(memspec["memtimingspec"]["XSR"], "XSR")),
tESCKE (tCK * parseUint(memspec["memtimingspec"]["ESCKE"], "ESCKE")),
tCKE (tCK * parseUint(memspec["memtimingspec"]["CKE"], "CKE")),
tCMDCKE (tCK * parseUint(memspec["memtimingspec"]["CMDCKE"], "CMDCKE")),
tRTRS (tCK * parseUint(memspec["memtimingspec"]["RTRS"], "RTRS"))
{
commandLengthInCycles[Command::ACT] = 4;
commandLengthInCycles[Command::PRE] = 2;

68
DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.h
View File

@@ -37,43 +37,45 @@
#define MEMSPECLPDDR4_H
#include "MemSpec.h"
#include "../../common/third_party/nlohmann/single_include/nlohmann/json.hpp"
struct MemSpecLPDDR4 final : public MemSpec
class MemSpecLPDDR4 final : public MemSpec
{
MemSpecLPDDR4();
public:
MemSpecLPDDR4(nlohmann::json &memspec);
// Memspec Variables:
sc_time tREFI;
sc_time tREFIpb;
sc_time tRFCab;
sc_time tRFCpb;
sc_time tRAS;
sc_time tRPab;
sc_time tRPpb;
sc_time tRCpb;
sc_time tRCab;
sc_time tPPD;
sc_time tRCD;
sc_time tFAW;
sc_time tRRD;
sc_time tCCD;
sc_time tRL;
sc_time tRPST;
sc_time tDQSCK;
sc_time tRTP;
sc_time tWL;
sc_time tDQSS;
sc_time tDQS2DQ;
sc_time tWR;
sc_time tWPRE;
sc_time tWTR;
sc_time tXP;
sc_time tSR;
sc_time tXSR;
sc_time tESCKE;
sc_time tCKE;
sc_time tCMDCKE;
sc_time tRTRS;
const sc_time tREFI;
const sc_time tREFIpb;
const sc_time tRFCab;
const sc_time tRFCpb;
const sc_time tRAS;
const sc_time tRPab;
const sc_time tRPpb;
const sc_time tRCpb;
const sc_time tRCab;
const sc_time tPPD;
const sc_time tRCD;
const sc_time tFAW;
const sc_time tRRD;
const sc_time tCCD;
const sc_time tRL;
const sc_time tRPST;
const sc_time tDQSCK;
const sc_time tRTP;
const sc_time tWL;
const sc_time tDQSS;
const sc_time tDQS2DQ;
const sc_time tWR;
const sc_time tWPRE;
const sc_time tWTR;
const sc_time tXP;
const sc_time tSR;
const sc_time tXSR;
const sc_time tESCKE;
const sc_time tCKE;
const sc_time tCMDCKE;
const sc_time tRTRS;
// Currents and Voltages:
// TODO: to be completed

57
DRAMSys/library/src/configuration/memspec/MemSpecWideIO.cpp
View File

@@ -36,6 +36,63 @@
#include "MemSpecWideIO.h"
using namespace tlm;
using json = nlohmann::json;
MemSpecWideIO::MemSpecWideIO(json &memspec)
: MemSpec(memspec,
parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"),
parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks"),
1,
parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks"),
parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks")
* parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"),
parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks")),
tCKE (tCK * parseUint(memspec["memtimingspec"]["CKE"], "CKE")),
tCKESR (tCK * parseUint(memspec["memtimingspec"]["CKESR"], "CKESR")),
tDQSCK (tCK * parseUint(memspec["memtimingspec"]["DQSCK"], "DQSCK")),
tAC (tCK * parseUint(memspec["memtimingspec"]["AC"], "AC")),
tRAS (tCK * parseUint(memspec["memtimingspec"]["RAS"], "RAS")),
tRC (tCK * parseUint(memspec["memtimingspec"]["RC"], "RC")),
tRCD (tCK * parseUint(memspec["memtimingspec"]["RCD"], "RCD")),
tRL (tCK * parseUint(memspec["memtimingspec"]["RL"], "RL")),
tWL (tCK * parseUint(memspec["memtimingspec"]["WL"], "WL")),
tWR (tCK * parseUint(memspec["memtimingspec"]["WR"], "WR")),
tXP (tCK * parseUint(memspec["memtimingspec"]["XP"], "XP")),
tXSR (tCK * parseUint(memspec["memtimingspec"]["XSR"], "XSR")),
tCCD_R (tCK * parseUint(memspec["memtimingspec"]["CCD_R"], "CCD_R")),
tCCD_W (tCK * parseUint(memspec["memtimingspec"]["CCD_W"], "CCD_W")),
tREFI (tCK * parseUint(memspec["memtimingspec"]["REFI"], "REFI")),
tRFC (tCK * parseUint(memspec["memtimingspec"]["RFC"], "RFC")),
tRP (tCK * parseUint(memspec["memtimingspec"]["RP"], "RP")),
tRRD (tCK * parseUint(memspec["memtimingspec"]["RRD"], "RRD")),
tTAW (tCK * parseUint(memspec["memtimingspec"]["TAW"], "TAW")),
tWTR (tCK * parseUint(memspec["memtimingspec"]["WTR"], "WTR")),
tRTRS (tCK * parseUint(memspec["memtimingspec"]["RTRS"], "RTRS")),
iDD0 (parseUdouble(memspec["mempowerspec"]["idd0"], "idd0")),
iDD2N (parseUdouble(memspec["mempowerspec"]["idd2n"], "idd2n")),
iDD3N (parseUdouble(memspec["mempowerspec"]["idd3n"], "idd3n")),
iDD4R (parseUdouble(memspec["mempowerspec"]["idd4r"], "idd4r")),
iDD4W (parseUdouble(memspec["mempowerspec"]["idd4w"], "idd4w")),
iDD5 (parseUdouble(memspec["mempowerspec"]["idd5"], "idd5")),
iDD6 (parseUdouble(memspec["mempowerspec"]["idd6"], "idd6")),
vDD (parseUdouble(memspec["mempowerspec"]["vdd"], "vdd")),
iDD02 (parseUdouble(memspec["mempowerspec"]["idd02"], "idd02")),
iDD2P0 (parseUdouble(memspec["mempowerspec"]["idd2p0"], "idd2p0")),
iDD2P02 (parseUdouble(memspec["mempowerspec"]["idd2p02"], "idd2p02")),
iDD2P1 (parseUdouble(memspec["mempowerspec"]["idd2p1"], "idd2p1")),
iDD2P12 (parseUdouble(memspec["mempowerspec"]["idd2p12"], "idd2p12")),
iDD2N2 (parseUdouble(memspec["mempowerspec"]["idd2n2"], "idd2n2")),
iDD3P0 (parseUdouble(memspec["mempowerspec"]["idd3p0"], "idd3p0")),
iDD3P02 (parseUdouble(memspec["mempowerspec"]["idd3p02"], "idd3p02")),
iDD3P1 (parseUdouble(memspec["mempowerspec"]["idd3p1"], "idd3p1")),
iDD3P12 (parseUdouble(memspec["mempowerspec"]["idd3p12"], "idd3p12")),
iDD3N2 (parseUdouble(memspec["mempowerspec"]["idd3n2"], "idd3n2")),
iDD4R2 (parseUdouble(memspec["mempowerspec"]["idd4r2"], "idd4r2")),
iDD4W2 (parseUdouble(memspec["mempowerspec"]["idd4w2"], "idd4w2")),
iDD52 (parseUdouble(memspec["mempowerspec"]["idd52"], "idd52")),
iDD62 (parseUdouble(memspec["mempowerspec"]["idd62"], "idd62")),
vDD2 (parseUdouble(memspec["mempowerspec"]["vdd2"], "vdd2"))
{}
sc_time MemSpecWideIO::getRefreshIntervalAB() const
{

96
DRAMSys/library/src/configuration/memspec/MemSpecWideIO.h
View File

@@ -37,57 +37,61 @@
#define MEMSPECWIDEIO_H
#include "MemSpec.h"
#include "../../common/third_party/nlohmann/single_include/nlohmann/json.hpp"
struct MemSpecWideIO final : public MemSpec
class MemSpecWideIO final : public MemSpec
{
public:
MemSpecWideIO(nlohmann::json &memspec);
// Memspec Variables:
sc_time tCKE; // min time in pdna or pdnp
sc_time tCKESR; // min time in sref
sc_time tRAS; // active-time (act -> pre same bank)
sc_time tRC; // RAS-cycle-time (min time bw 2 succesive ACT to same bank)
sc_time tRCD; // act -> read/write
sc_time tRL; // read latency (read command start to data strobe)
sc_time tWL; // write latency
sc_time tWR; // write recovery (write to precharge)
sc_time tXP; // min delay to row access command after pdnpx pdnax
sc_time tXSR; // min delay to row access command after srefx
sc_time tREFI;
sc_time tRFC;
sc_time tRP;
sc_time tDQSCK;
sc_time tAC;
sc_time tCCD_R;
sc_time tCCD_W;
sc_time tRRD;
sc_time tTAW;
sc_time tWTR;
sc_time tRTRS;
const sc_time tCKE;
const sc_time tCKESR;
const sc_time tRAS;
const sc_time tRC;
const sc_time tRCD;
const sc_time tRL;
const sc_time tWL;
const sc_time tWR;
const sc_time tXP;
const sc_time tXSR;
const sc_time tREFI;
const sc_time tRFC;
const sc_time tRP;
const sc_time tDQSCK;
const sc_time tAC;
const sc_time tCCD_R;
const sc_time tCCD_W;
const sc_time tRRD;
const sc_time tTAW;
const sc_time tWTR;
const sc_time tRTRS;
// Currents and Voltages:
double iDD0;
double iDD2N;
double iDD3N;
double iDD4R;
double iDD4W;
double iDD5;
double iDD6;
double vDD;
double iDD02;
double iDD2P0;
double iDD2P02;
double iDD2P1;
double iDD2P12;
double iDD2N2;
double iDD3P0;
double iDD3P02;
double iDD3P1;
double iDD3P12;
double iDD3N2;
double iDD4R2;
double iDD4W2;
double iDD52;
double iDD62;
double vDD2;
const double iDD0;
const double iDD2N;
const double iDD3N;
const double iDD4R;
const double iDD4W;
const double iDD5;
const double iDD6;
const double vDD;
const double iDD02;
const double iDD2P0;
const double iDD2P02;
const double iDD2P1;
const double iDD2P12;
const double iDD2N2;
const double iDD3P0;
const double iDD3P02;
const double iDD3P1;
const double iDD3P12;
const double iDD3N2;
const double iDD4R2;
const double iDD4W2;
const double iDD52;
const double iDD62;
const double vDD2;
virtual sc_time getRefreshIntervalPB() const override;
virtual sc_time getRefreshIntervalAB() const override;

39
DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.cpp
View File

@@ -36,6 +36,45 @@
#include "MemSpecWideIO2.h"
using namespace tlm;
using json = nlohmann::json;
MemSpecWideIO2::MemSpecWideIO2(json &memspec)
: MemSpec(memspec,
parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"),
parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks"),
1,
parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks"),
parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks")
* parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"),
parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks")),
tDQSCK (tCK * parseUint(memspec["memtimingspec"]["DQSCK"], "DQSCK")),
tDQSS (tCK * parseUint(memspec["memtimingspec"]["DQSS"], "DQSS")),
tCKE (tCK * parseUint(memspec["memtimingspec"]["CKE"], "CKE")),
tRL (tCK * parseUint(memspec["memtimingspec"]["RL"], "RL")),
tWL (tCK * parseUint(memspec["memtimingspec"]["WL"], "WL")),
tRCpb (tCK * parseUint(memspec["memtimingspec"]["RCPB"], "RCPB")),
tRCab (tCK * parseUint(memspec["memtimingspec"]["RCAB"], "RCAB")),
tCKESR (tCK * parseUint(memspec["memtimingspec"]["CKESR"], "CKESR")),
tXSR (tCK * parseUint(memspec["memtimingspec"]["XSR"], "XSR")),
tXP (tCK * parseUint(memspec["memtimingspec"]["XP"], "XP")),
tCCD (tCK * parseUint(memspec["memtimingspec"]["CCD"], "CCD")),
tRTP (tCK * parseUint(memspec["memtimingspec"]["RTP"], "RTP")),
tRCD (tCK * parseUint(memspec["memtimingspec"]["RCD"], "RCD")),
tRPpb (tCK * parseUint(memspec["memtimingspec"]["RPPB"], "RPPB")),
tRPab (tCK * parseUint(memspec["memtimingspec"]["RPAB"], "RPAB")),
tRAS (tCK * parseUint(memspec["memtimingspec"]["RAS"], "RAS")),
tWR (tCK * parseUint(memspec["memtimingspec"]["WR"], "WR")),
tWTR (tCK * parseUint(memspec["memtimingspec"]["WTR"], "WTR")),
tRRD (tCK * parseUint(memspec["memtimingspec"]["RRD"], "RRD")),
tFAW (tCK * parseUint(memspec["memtimingspec"]["FAW"], "FAW")),
tREFI (tCK * (unsigned)(parseUint(memspec["memtimingspec"]["REFI"], "REFI")
* parseUdouble(memspec["memtimingspec"]["REFM"], "REFM"))),
tREFIpb (tCK * (unsigned)(parseUint(memspec["memtimingspec"]["REFIPB"], "REFIPB")
* parseUdouble(memspec["memtimingspec"]["REFM"], "REFM"))),
tRFCab (tCK * parseUint(memspec["memtimingspec"]["RFCAB"], "RFCAB")),
tRFCpb (tCK * parseUint(memspec["memtimingspec"]["RFCPB"], "RFCPB")),
tRTRS (tCK * parseUint(memspec["memtimingspec"]["RTRS"], "RTRS"))
{}
sc_time MemSpecWideIO2::getRefreshIntervalAB() const
{

56
DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.h
View File

@@ -37,35 +37,39 @@
#define MEMSPECWIDEIO2_H
#include "MemSpec.h"
#include "../../common/third_party/nlohmann/single_include/nlohmann/json.hpp"
struct MemSpecWideIO2 final : public MemSpec
class MemSpecWideIO2 final : public MemSpec
{
public:
MemSpecWideIO2(nlohmann::json &memspec);
// Memspec Variables:
sc_time tDQSCK;
sc_time tDQSS;
sc_time tCKE;
sc_time tRL;
sc_time tWL;
sc_time tRCpb;
sc_time tRCab;
sc_time tCKESR;
sc_time tXSR;
sc_time tXP;
sc_time tCCD;
sc_time tRTP;
sc_time tRCD;
sc_time tRPpb;
sc_time tRPab;
sc_time tRAS;
sc_time tWR;
sc_time tWTR;
sc_time tRRD;
sc_time tFAW;
sc_time tREFI;
sc_time tREFIpb;
sc_time tRFCab;
sc_time tRFCpb;
sc_time tRTRS;
const sc_time tDQSCK;
const sc_time tDQSS;
const sc_time tCKE;
const sc_time tRL;
const sc_time tWL;
const sc_time tRCpb;
const sc_time tRCab;
const sc_time tCKESR;
const sc_time tXSR;
const sc_time tXP;
const sc_time tCCD;
const sc_time tRTP;
const sc_time tRCD;
const sc_time tRPpb;
const sc_time tRPab;
const sc_time tRAS;
const sc_time tWR;
const sc_time tWTR;
const sc_time tRRD;
const sc_time tFAW;
const sc_time tREFI;
const sc_time tREFIpb;
const sc_time tRFCab;
const sc_time tRFCpb;
const sc_time tRTRS;
// Currents and Voltages:
// TODO: to be completed

2
DRAMSys/library/src/controller/Controller.cpp
View File

@@ -349,7 +349,7 @@ tlm_sync_enum Controller::nb_transport_fw(tlm_generic_payload &trans,
else
SC_REPORT_FATAL("Controller", "nb_transport_fw in controller was triggered with unknown phase");
PRINTDEBUGMESSAGE(name(), "[fw] " + phaseNameToString(phase) + " notification in " +
PRINTDEBUGMESSAGE(name(), "[fw] " + std::string(phase.get_name()) + " notification in " +
notificationDelay.to_string());
return TLM_ACCEPTED;

2
DRAMSys/library/src/controller/ControllerRecordable.cpp
View File

@@ -80,7 +80,7 @@ void ControllerRecordable::recordPhase(tlm_generic_payload &trans, tlm_phase pha
unsigned int col __attribute__((unused)) = DramExtension::getExtension(trans).getColumn().ID();
uint64_t id __attribute__((unused)) = DramExtension::getExtension(trans).getPayloadID();
PRINTDEBUGMESSAGE(name(), "Recording " + phaseNameToString(phase) + " thread " +
PRINTDEBUGMESSAGE(name(), "Recording " + std::string(phase.get_name()) + " thread " +
std::to_string(thr) + " channel " + std::to_string(ch) + " bank group " + std::to_string(
bg) + " bank " + std::to_string(bank) + " row " + std::to_string(row) + " column " +
std::to_string(col) + " id " + std::to_string(id) + " at " + recTime.to_string());

2
DRAMSys/library/src/controller/checker/CheckerDDR3.cpp
View File

@@ -413,7 +413,7 @@ sc_time CheckerDDR3::timeToSatisfyConstraints(Command command, Rank rank, BankGr
void CheckerDDR3::insert(Command command, Rank rank, BankGroup, Bank bank)
{
PRINTDEBUGMESSAGE("CheckerDDR3", "Changing state on bank " + bank.ID()
PRINTDEBUGMESSAGE("CheckerDDR3", "Changing state on bank " + std::to_string(bank.ID())
+ " command is " + commandToString(command));
lastScheduledByCommandAndRank[command][rank.ID()] = sc_time_stamp();

5
DRAMSys/library/src/simulation/Arbiter.cpp
View File

@@ -37,6 +37,7 @@
#include "Arbiter.h"
#include "../common/AddressDecoder.h"
#include "../configuration/Configuration.h"
using namespace tlm;
@@ -92,7 +93,7 @@ tlm_sync_enum Arbiter::nb_transport_fw(int id, tlm_generic_payload &payload,
notDelay += Configuration::getInstance().memSpec->tCK;
}
PRINTDEBUGMESSAGE(name(), "[fw] " + phaseNameToString(phase) + " notification in " +
PRINTDEBUGMESSAGE(name(), "[fw] " + std::string(phase.get_name()) + " notification in " +
notDelay.to_string());
payloadEventQueue.notify(payload, phase, notDelay);
return TLM_ACCEPTED;
@@ -106,7 +107,7 @@ tlm_sync_enum Arbiter::nb_transport_bw(int channelId, tlm_generic_payload &paylo
// Check channel ID
assert((unsigned int)channelId == DramExtension::getExtension(payload).getChannel().ID());
PRINTDEBUGMESSAGE(name(), "[bw] " + phaseNameToString(phase) + " notification in " +
PRINTDEBUGMESSAGE(name(), "[bw] " + std::string(phase.get_name()) + " notification in " +
bwDelay.to_string());
payloadEventQueue.notify(payload, phase, bwDelay);
return TLM_ACCEPTED;

1
DRAMSys/library/src/simulation/Arbiter.h
View File

@@ -48,7 +48,6 @@
#include <tlm_utils/peq_with_cb_and_phase.h>
#include "../common/AddressDecoder.h"
#include "../common/dramExtensions.h"
#include "../configuration/ConfigurationLoader.h"
class Arbiter : public sc_module
{

217
DRAMSys/library/src/simulation/DRAMSys.cpp
View File

@@ -34,6 +34,7 @@
* Matthias Jung
* Eder F. Zulian
* Felipe S. Prado
* Lukas Steiner
*/
#include <stdlib.h>
@@ -44,13 +45,10 @@
#include "DRAMSys.h"
#include "../common/third_party/nlohmann/single_include/nlohmann/json.hpp"
#include "../common/TlmRecorder.h"
#include "../common/DebugManager.h"
#include "../configuration/ConfigurationLoader.h"
#include "../common/utils.h"
#include "../simulation/TemperatureController.h"
#include "../error/ecchamming.h"
#include "dram/DramRecordable.h"
#include "dram/DramDDR3.h"
#include "dram/DramDDR4.h"
#include "dram/DramWideIO.h"
@@ -61,11 +59,12 @@
#include "dram/DramGDDR5X.h"
#include "dram/DramGDDR6.h"
#include "../controller/Controller.h"
#include "../controller/ControllerRecordable.h"
DRAMSys::DRAMSys(sc_module_name name,
std::string simulationToRun,
std::string pathToResources) : sc_module(name), tSocket("DRAMSys_tSocket")
std::string pathToResources,
bool initAndBind)
: sc_module(name), tSocket("DRAMSys_tSocket")
{
// Initialize ecc pointer
ecc = nullptr;
@@ -79,56 +78,61 @@ DRAMSys::DRAMSys(sc_module_name name,
SC_REPORT_FATAL("SimulationManager",
"Cannot load simulation: simulation node expected");
// Load all sub-configuration JSON files
std::string memspec = simulationdoc["simulation"]["memspec"];
std::string mcconfig = simulationdoc["simulation"]["mcconfig"];
std::string amconfig = simulationdoc["simulation"]["addressmapping"];
std::string simconfig = simulationdoc["simulation"]["simconfig"];
std::string thermalconfig = simulationdoc["simulation"]["thermalconfig"];
Configuration::getInstance().setPathToResources(pathToResources);
// Load config and initialize modules
ConfigurationLoader::loadMemSpec(Configuration::getInstance(),
pathToResources
+ "configs/memspecs/"
+ memspec);
Configuration::getInstance().loadMCConfig(Configuration::getInstance(),
pathToResources
+ "configs/mcconfigs/"
+ std::string(simulationdoc["simulation"]["mcconfig"]));
ConfigurationLoader::loadMCConfig(Configuration::getInstance(),
pathToResources
+ "configs/mcconfigs/"
+ mcconfig);
Configuration::getInstance().loadMemSpec(Configuration::getInstance(),
pathToResources
+ "configs/memspecs/"
+ std::string(simulationdoc["simulation"]["memspec"]));
ConfigurationLoader::loadSimConfig(Configuration::getInstance(),
pathToResources
+ "configs/simulator/"
+ simconfig);
Configuration::getInstance().loadSimConfig(Configuration::getInstance(),
pathToResources
+ "configs/simulator/"
+ std::string(simulationdoc["simulation"]["simconfig"]));
ConfigurationLoader::loadTemperatureSimConfig(Configuration::getInstance(),
pathToResources
+ "configs/thermalsim/"
+ thermalconfig);
Configuration::getInstance().loadTemperatureSimConfig(Configuration::getInstance(),
pathToResources
+ "configs/thermalsim/"
+ std::string(simulationdoc["simulation"]["thermalconfig"]));
// Setup the debug manager:
setupDebugManager(Configuration::getInstance().simulationName);
// If a simulation file is passed as argument to DRAMSys the simulation ID
// is prepended to the simulation name if found.
std::string simName;
simName = Configuration::getInstance().simulationName;
if (!simulationdoc["simulation"]["simulationid"].empty())
if (initAndBind)
{
std::string sid = simulationdoc["simulation"]["simulationid"];
simName = sid + '_' + Configuration::getInstance().simulationName;
// Instantiate all internal DRAMSys modules:
std::string amconfig = simulationdoc["simulation"]["addressmapping"];
instantiateModules(pathToResources, amconfig);
// Connect all internal DRAMSys modules:
bindSockets();
report(headline);
}
}
// Instantiate all internal DRAMSys modules:
instantiateModules(simName, pathToResources, amconfig);
// Connect all internal DRAMSys modules:
bindSockets();
DRAMSys::~DRAMSys()
{
if (ecc)
delete ecc;
report(headline);
delete arbiter;
for (auto dram : drams)
delete dram;
for (auto controller : controllers)
delete controller;
for (auto tlmChecker : playersTlmCheckers)
delete tlmChecker;
for (auto tlmChecker : controllersTlmCheckers)
delete tlmChecker;
}
void DRAMSys::logo()
@@ -159,45 +163,13 @@ void DRAMSys::setupDebugManager(const std::string &traceName __attribute__((unus
#endif
}
void DRAMSys::setupTlmRecorders(const std::string &traceName,
const std::string &pathToResources)
{
// Create TLM Recorders, one per channel.
for (size_t i = 0; i < Configuration::getInstance().numberOfMemChannels; i++)
{
std::string sqlScriptURI = pathToResources
+ std::string("scripts/createTraceDB.sql");
std::string dbName = traceName + std::string("_ch") + std::to_string(i) + ".tdb";
std::string recorderName = "tlmRecorder" + std::to_string(i);
TlmRecorder *tlmRecorder =
new TlmRecorder(recorderName, sqlScriptURI.c_str(), dbName.c_str());
tlmRecorder->recordMCconfig(Configuration::getInstance().mcconfigUri);
tlmRecorder->recordMemspec(Configuration::getInstance().memspecUri);
std::string traceNames = Configuration::getInstance().simulationName;
tlmRecorder->recordTracenames(traceNames);
tlmRecorders.push_back(tlmRecorder);
}
}
void DRAMSys::instantiateModules(const std::string &traceName,
const std::string &pathToResources,
void DRAMSys::instantiateModules(const std::string &pathToResources,
const std::string &amconfig)
{
// The first call to getInstance() creates the Temperature Controller.
// The same instance will be accessed by all other modules.
TemperatureController::getInstance();
// Create and properly initialize TLM recorders.
// They need to be ready before creating some modules.
bool recordingEnabled = Configuration::getInstance().databaseRecording;
if (recordingEnabled)
setupTlmRecorders(traceName, pathToResources);
// Create new ECC Controller
if (Configuration::getInstance().ECCMode == "Hamming")
ecc = new ECCHamming("ECCHamming");
@@ -212,91 +184,43 @@ void DRAMSys::instantiateModules(const std::string &traceName,
// Create arbiter
arbiter = new Arbiter("arbiter", pathToResources + "configs/amconfigs/" + amconfig);
// Create DRAM
// Create controllers and DRAMs
std::string memoryType = Configuration::getInstance().memSpec->memoryType;
for (size_t i = 0; i < Configuration::getInstance().numberOfMemChannels; i++)
{
std::string str = "controller" + std::to_string(i);
ControllerIF *controller;
if (recordingEnabled)
controller = new ControllerRecordable(str.c_str(), tlmRecorders[i]);
else
controller = new Controller(str.c_str());
ControllerIF *controller = new Controller(str.c_str());
controllers.push_back(controller);
str = "dram" + std::to_string(i);
Dram *dram;
if (memoryType == "DDR3")
{
if (recordingEnabled)
dram = new DramRecordable<DramDDR3>(str.c_str(), tlmRecorders[i]);
else
dram = new DramDDR3(str.c_str());
}
dram = new DramDDR3(str.c_str());
else if (memoryType == "WIDEIO_SDR")
{
if (recordingEnabled)
dram = new DramRecordable<DramWideIO>(str.c_str(), tlmRecorders[i]);
else
dram = new DramWideIO(str.c_str());
}
dram = new DramWideIO(str.c_str());
else if (memoryType == "DDR4")
{
if (recordingEnabled)
dram = new DramRecordable<DramDDR4>(str.c_str(), tlmRecorders[i]);
else
dram = new DramDDR4(str.c_str());
}
dram = new DramDDR4(str.c_str());
else if (memoryType == "LPDDR4")
{
if (recordingEnabled)
dram = new DramRecordable<DramLPDDR4>(str.c_str(), tlmRecorders[i]);
else
dram = new DramLPDDR4(str.c_str());
}
dram = new DramLPDDR4(str.c_str());
else if (memoryType == "WIDEIO2")
{
if (recordingEnabled)
dram = new DramRecordable<DramWideIO2>(str.c_str(), tlmRecorders[i]);
else
dram = new DramWideIO2(str.c_str());
}
dram = new DramWideIO2(str.c_str());
else if (memoryType == "HBM2")
{
if (recordingEnabled)
dram = new DramRecordable<DramHBM2>(str.c_str(), tlmRecorders[i]);
else
dram = new DramHBM2(str.c_str());
}
dram = new DramHBM2(str.c_str());
else if (memoryType == "GDDR5")
{
if (recordingEnabled)
dram = new DramRecordable<DramGDDR5>(str.c_str(), tlmRecorders[i]);
else
dram = new DramGDDR5(str.c_str());
}
dram = new DramGDDR5(str.c_str());
else if (memoryType == "GDDR5X")
{
if (recordingEnabled)
dram = new DramRecordable<DramGDDR5X>(str.c_str(), tlmRecorders[i]);
else
dram = new DramGDDR5X(str.c_str());
}
dram = new DramGDDR5X(str.c_str());
else if (memoryType == "GDDR6")
{
if (recordingEnabled)
dram = new DramRecordable<DramGDDR6>(str.c_str(), tlmRecorders[i]);
else
dram = new DramGDDR6(str.c_str());
}
dram = new DramGDDR6(str.c_str());
else
SC_REPORT_FATAL("DRAMSys", "Unsupported DRAM type");
drams.push_back(dram);
if (Configuration::getInstance().checkTLM2Protocol) {
if (Configuration::getInstance().checkTLM2Protocol)
{
str = "TLMCheckerController" + std::to_string(i);
tlm_utils::tlm2_base_protocol_checker<> *controllerTlmChecker =
new tlm_utils::tlm2_base_protocol_checker<>(str.c_str());
@@ -338,29 +262,6 @@ void DRAMSys::bindSockets()
}
}
DRAMSys::~DRAMSys()
{
if (ecc)
delete ecc;
delete arbiter;
for (auto dram : drams)
delete dram;
for (auto rec : tlmRecorders)
delete rec;
for (auto tlmChecker : playersTlmCheckers)
delete tlmChecker;
for (auto tlmChecker : controllersTlmCheckers)
delete tlmChecker;
for (auto controller : controllers)
delete controller;
}
void DRAMSys::report(std::string message)
{
PRINTDEBUGMESSAGE(name(), message);

45
DRAMSys/library/src/simulation/DRAMSys.h
View File

@@ -34,6 +34,7 @@
* Matthias Jung
* Eder F. Zulian
* Felipe S. Prado
* Lukas Steiner
*/
#ifndef DRAMSYS_H
@@ -44,14 +45,12 @@
#include "dram/Dram.h"
#include "Arbiter.h"
#include "TraceGenerator.h"
#include "ReorderBuffer.h"
#include <tlm_utils/multi_passthrough_target_socket.h>
#include <tlm_utils/multi_passthrough_initiator_socket.h>
#include "../common/tlm2_base_protocol_checker.h"
#include "../error/eccbaseclass.h"
#include "../controller/ControllerIF.h"
#include "../common/TlmRecorder.h"
class DRAMSys : public sc_module
{
@@ -61,21 +60,19 @@ public:
std::vector<tlm_utils::tlm2_base_protocol_checker<>*>
playersTlmCheckers;
sc_event terminateSimulation;
SC_HAS_PROCESS(DRAMSys);
DRAMSys(sc_module_name name,
std::string simulationToRun,
std::string pathToResources);
std::string pathToResources)
: DRAMSys(name, simulationToRun, pathToResources, true) {}
~DRAMSys();
virtual ~DRAMSys();
void logo();
private:
std::string traceName;
//DramSetup setup;
protected:
DRAMSys(sc_module_name name,
std::string simulationToRun,
std::string pathToResources,
bool initAndBind);
//TLM 2.0 Protocol Checkers
std::vector<tlm_utils::tlm2_base_protocol_checker<>*>
@@ -83,28 +80,28 @@ private:
// All transactions pass first through the ECC Controller
ECCBaseClass *ecc;
// All transactions pass through the same arbiter
Arbiter *arbiter;
// Each DRAM unit has a controller
std::vector<ControllerIF *> controllers;
// TODO: Each DRAM has a reorder buffer (check this!)
ReorderBuffer *reorder;
// All transactions pass through the same arbiter
Arbiter *arbiter;
// Each DRAM unit has a controller
std::vector<ControllerIF *> controllers;
// DRAM units
std::vector<Dram *> drams;
// Transaction Recorders (one per channel).
// They generate the output databases.
std::vector<TlmRecorder *> tlmRecorders;
void report(std::string message);
void setupTlmRecorders(const std::string &traceName,
const std::string &pathToResources);
void instantiateModules(const std::string &traceName,
const std::string &pathToResources,
private:
void logo();
void instantiateModules(const std::string &pathToResources,
const std::string &amconfig);
void bindSockets();
void setupDebugManager(const std::string &traceName);
};

217
DRAMSys/library/src/simulation/DRAMSysRecordable.cpp Normal file
View File

@@ -0,0 +1,217 @@
/*
* Copyright (c) 2020, University of Kaiserslautern
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
* OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors:
* Lukas Steiner
*/
#include "DRAMSysRecordable.h"
#include "../controller/ControllerRecordable.h"
#include "dram/DramRecordable.h"
#include "dram/DramDDR3.h"
#include "dram/DramDDR4.h"
#include "dram/DramWideIO.h"
#include "dram/DramLPDDR4.h"
#include "dram/DramWideIO2.h"
#include "dram/DramHBM2.h"
#include "dram/DramGDDR5.h"
#include "dram/DramGDDR5X.h"
#include "dram/DramGDDR6.h"
#include "../common/TlmRecorder.h"
#include "../simulation/TemperatureController.h"
#include "../error/ecchamming.h"
DRAMSysRecordable::DRAMSysRecordable(sc_module_name name,
std::string simulationToRun,
std::string pathToResources)
: DRAMSys(name, simulationToRun, pathToResources, false)
{
// Read Configuration Setup:
nlohmann::json simulationdoc = parseJSON(simulationToRun);
// If a simulation file is passed as argument to DRAMSys the simulation ID
// is prepended to the simulation name if found.
std::string traceName;
if (!simulationdoc["simulation"]["simulationid"].empty())
{
std::string sid = simulationdoc["simulation"]["simulationid"];
traceName = sid + '_' + Configuration::getInstance().simulationName;
}
else
traceName = Configuration::getInstance().simulationName;
std::string amconfig = simulationdoc["simulation"]["addressmapping"];
instantiateModules(traceName, pathToResources, amconfig);
bindSockets();
report(headline);
}
DRAMSysRecordable::~DRAMSysRecordable()
{
if (Configuration::getInstance().powerAnalysis)
{
for (auto dram : drams)
dram->reportPower();
}
for (auto rec : tlmRecorders)
delete rec;
}
void DRAMSysRecordable::setupTlmRecorders(const std::string &traceName,
const std::string &pathToResources)
{
// Create TLM Recorders, one per channel.
for (size_t i = 0; i < Configuration::getInstance().numberOfMemChannels; i++)
{
std::string sqlScriptURI = pathToResources
+ std::string("scripts/createTraceDB.sql");
std::string dbName = traceName + std::string("_ch") + std::to_string(i) + ".tdb";
std::string recorderName = "tlmRecorder" + std::to_string(i);
TlmRecorder *tlmRecorder =
new TlmRecorder(recorderName, sqlScriptURI.c_str(), dbName.c_str());
tlmRecorder->recordMCconfig(Configuration::getInstance().mcconfigUri);
tlmRecorder->recordMemspec(Configuration::getInstance().memspecUri);
std::string traceNames = Configuration::getInstance().simulationName;
tlmRecorder->recordTracenames(traceNames);
tlmRecorders.push_back(tlmRecorder);
}
}
void DRAMSysRecordable::instantiateModules(const std::string &traceName,
const std::string &pathToResources,
const std::string &amconfig)
{
// The first call to getInstance() creates the Temperature Controller.
// The same instance will be accessed by all other modules.
TemperatureController::getInstance();
// Create and properly initialize TLM recorders.
// They need to be ready before creating some modules.
setupTlmRecorders(traceName, pathToResources);
// Create new ECC Controller
if (Configuration::getInstance().ECCMode == "Hamming")
ecc = new ECCHamming("ECCHamming");
else if (Configuration::getInstance().ECCMode == "Disabled")
ecc = nullptr;
else
SC_REPORT_FATAL("DRAMSys", "Unsupported ECC mode");
// Save ECC Controller into the configuration struct to adjust it dynamically
Configuration::getInstance().pECC = ecc;
// Create arbiter
arbiter = new Arbiter("arbiter", pathToResources + "configs/amconfigs/" + amconfig);
// Create controllers and DRAMs
std::string memoryType = Configuration::getInstance().memSpec->memoryType;
for (size_t i = 0; i < Configuration::getInstance().numberOfMemChannels; i++)
{
std::string str = "controller" + std::to_string(i);
ControllerIF *controller = new ControllerRecordable(str.c_str(), tlmRecorders[i]);
controllers.push_back(controller);
str = "dram" + std::to_string(i);
Dram *dram;
if (memoryType == "DDR3")
dram = new DramRecordable<DramDDR3>(str.c_str(), tlmRecorders[i]);
else if (memoryType == "WIDEIO_SDR")
dram = new DramRecordable<DramWideIO>(str.c_str(), tlmRecorders[i]);
else if (memoryType == "DDR4")
dram = new DramRecordable<DramDDR4>(str.c_str(), tlmRecorders[i]);
else if (memoryType == "LPDDR4")
dram = new DramRecordable<DramLPDDR4>(str.c_str(), tlmRecorders[i]);
else if (memoryType == "WIDEIO2")
dram = new DramRecordable<DramWideIO2>(str.c_str(), tlmRecorders[i]);
else if (memoryType == "HBM2")
dram = new DramRecordable<DramHBM2>(str.c_str(), tlmRecorders[i]);
else if (memoryType == "GDDR5")
dram = new DramRecordable<DramGDDR5>(str.c_str(), tlmRecorders[i]);
else if (memoryType == "GDDR5X")
dram = new DramRecordable<DramGDDR5X>(str.c_str(), tlmRecorders[i]);
else if (memoryType == "GDDR6")
dram = new DramRecordable<DramGDDR6>(str.c_str(), tlmRecorders[i]);
else
SC_REPORT_FATAL("DRAMSys", "Unsupported DRAM type");
drams.push_back(dram);
if (Configuration::getInstance().checkTLM2Protocol)
{
str = "TLMCheckerController" + std::to_string(i);
tlm_utils::tlm2_base_protocol_checker<> *controllerTlmChecker =
new tlm_utils::tlm2_base_protocol_checker<>(str.c_str());
controllersTlmCheckers.push_back(controllerTlmChecker);
}
}
}
void DRAMSysRecordable::bindSockets()
{
// If ECC Controller enabled, put it between Trace and arbiter
if (Configuration::getInstance().ECCMode == "Hamming")
{
assert(ecc != nullptr);
tSocket.bind(ecc->t_socket);
ecc->i_socket.bind(arbiter->tSocket);
}
else if (Configuration::getInstance().ECCMode == "Disabled")
tSocket.bind(arbiter->tSocket);
else
SC_REPORT_FATAL("DRAMSys", "Unsupported ECC mode");
if (Configuration::getInstance().checkTLM2Protocol)
{
for (size_t i = 0; i < Configuration::getInstance().numberOfMemChannels; i++)
{
arbiter->iSocket.bind(controllersTlmCheckers[i]->target_socket);
controllersTlmCheckers[i]->initiator_socket.bind(controllers[i]->tSocket);
controllers[i]->iSocket.bind(drams[i]->tSocket);
}
}
else
{
for (size_t i = 0; i < Configuration::getInstance().numberOfMemChannels; i++)
{
arbiter->iSocket.bind(controllers[i]->tSocket);
controllers[i]->iSocket.bind(drams[i]->tSocket);
}
}
}

66
DRAMSys/library/src/simulation/DRAMSysRecordable.h Normal file
View File

@@ -0,0 +1,66 @@
/*
* Copyright (c) 2020, University of Kaiserslautern
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
* OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors:
* Lukas Steiner
*/
#ifndef DRAMSYSRECORDABLE_H
#define DRAMSYSRECORDABLE_H
#include "DRAMSys.h"
#include "../common/TlmRecorder.h"
class DRAMSysRecordable : public DRAMSys
{
public:
DRAMSysRecordable(sc_module_name name,
std::string simulationToRun,
std::string pathToResources);
virtual ~DRAMSysRecordable();
private:
// Transaction Recorders (one per channel).
// They generate the output databases.
std::vector<TlmRecorder *> tlmRecorders;
void setupTlmRecorders(const std::string &traceName,
const std::string &pathToResources);
void instantiateModules(const std::string &traceName,
const std::string &pathToResources,
const std::string &amconfig);
void bindSockets();
};
#endif // DRAMSYSRECORDABLE_H

8
DRAMSys/library/src/simulation/ReorderBuffer.h
View File

@@ -39,11 +39,15 @@
#define REORDERBUFFER_H
#include <deque>
#include <set>
#include <systemc.h>
#include <tlm.h>
#include <set>
#include <tlm_utils/simple_initiator_socket.h>
#include <tlm_utils/simple_target_socket.h>
#include <tlm_utils/peq_with_cb_and_phase.h>
struct ReorderBuffer: public sc_module {
struct ReorderBuffer : public sc_module
{
public:
tlm_utils::simple_initiator_socket<ReorderBuffer> iSocket;
tlm_utils::simple_target_socket<ReorderBuffer> tSocket;

23
DRAMSys/library/src/simulation/dram/Dram.cpp
View File

@@ -107,8 +107,22 @@ Dram::~Dram()
{
if (Configuration::getInstance().powerAnalysis)
{
if (!Configuration::getInstance().databaseRecording)
DRAMPower->calcEnergy();
reportPower();
delete DRAMPower;
}
if (Configuration::getInstance().useMalloc)
free(memory);
}
void Dram::reportPower()
{
static bool alreadyCalled = false;
if (!alreadyCalled)
{
alreadyCalled = true;
DRAMPower->calcEnergy();
// Print the final total energy and the average power for
// the simulation:
@@ -124,12 +138,7 @@ Dram::~Dram()
<< DRAMPower->getPower().average_power
* Configuration::getInstance().numberOfDevicesOnDIMM
<< std::string(" mW") << std::endl;
delete DRAMPower;
}
if (Configuration::getInstance().useMalloc)
free(memory);
}
tlm_sync_enum Dram::nb_transport_fw(tlm_generic_payload &payload,

1
DRAMSys/library/src/simulation/dram/Dram.h
View File

@@ -73,6 +73,7 @@ protected:
public:
tlm_utils::simple_target_socket<Dram> tSocket;
virtual void reportPower();
virtual ~Dram();
};

16
DRAMSys/library/src/simulation/dram/DramRecordable.cpp
View File

@@ -62,16 +62,12 @@ DramRecordable<BaseDram>::DramRecordable(sc_module_name name, TlmRecorder *tlmRe
}
template<class BaseDram>
DramRecordable<BaseDram>::~DramRecordable()
void DramRecordable<BaseDram>::reportPower()
{
if (Configuration::getInstance().powerAnalysis)
{
this->DRAMPower->calcEnergy();
tlmRecorder->recordPower(sc_time_stamp().to_seconds(),
this->DRAMPower->getPower().window_average_power
* Configuration::getInstance().numberOfDevicesOnDIMM);
}
tlmRecorder->closeConnection();
BaseDram::reportPower();
tlmRecorder->recordPower(sc_time_stamp().to_seconds(),
this->DRAMPower->getPower().window_average_power
* Configuration::getInstance().numberOfDevicesOnDIMM);
}
template<class BaseDram>
@@ -99,7 +95,7 @@ void DramRecordable<BaseDram>::recordPhase(tlm_generic_payload &trans, tlm_phase
unsigned int row __attribute__((unused)) = DramExtension::getExtension(trans).getRow().ID();
unsigned int col __attribute__((unused)) = DramExtension::getExtension(trans).getColumn().ID();
PRINTDEBUGMESSAGE(this->name(), "Recording " + phaseNameToString(phase) + " thread " +
PRINTDEBUGMESSAGE(this->name(), "Recording " + std::string(phase.get_name()) + " thread " +
std::to_string(thr) + " channel " + std::to_string(ch) + " bank group " + std::to_string(
bg) + " bank " + std::to_string(bank) + " row " + std::to_string(row) + " column " +
std::to_string(col) + " at " + recTime.to_string());

3
DRAMSys/library/src/simulation/dram/DramRecordable.h
View File

@@ -48,7 +48,8 @@ class DramRecordable final : public BaseDram
public:
DramRecordable(sc_module_name, TlmRecorder *);
SC_HAS_PROCESS(DramRecordable);
~DramRecordable();
virtual void reportPower();
private:
virtual tlm::tlm_sync_enum nb_transport_fw(tlm::tlm_generic_payload &payload,

23
DRAMSys/simulator/CMakeLists.txt
View File

@@ -39,11 +39,24 @@ project(DRAMSysSimulator)
set(CMAKE_CXX_STANDARD 11 CACHE STRING "C++ Version")
set(DCMAKE_SH="CMAKE_SH-NOTFOUND")
add_executable(DRAMSys main.cpp)
if(EXISTS ${CMAKE_CURRENT_LIST_DIR}/../library/src/simulation/DRAMSysRecordable.cpp)
add_definitions(-DRECORDING)
endif()
add_executable(DRAMSys
main.cpp
ExampleInitiator.h
MemoryManager.cpp
StlPlayer.h
TraceGenerator.h
TracePlayer.cpp
TracePlayerListener.h
TraceSetup.cpp)
target_include_directories(DRAMSys
PUBLIC ../library/src/simulation/
PUBLIC ../library/src/
)
target_link_libraries(DRAMSys
${SYSTEMC_LIBRARY}
DRAMSysLibrary
target_link_libraries(DRAMSys
PRIVATE DRAMSysLibrary
)

9
DRAMSys/library/src/simulation/ExampleInitiator.h → DRAMSys/simulator/ExampleInitiator.h
View File

@@ -5,7 +5,7 @@
#include <iostream>
#include "MemoryManager.h"
#include "../common/dramExtensions.h"
#include "common/dramExtensions.h"
#include "TracePlayer.h"
struct ExampleInitiator : sc_module
@@ -14,12 +14,11 @@ struct ExampleInitiator : sc_module
tlm_utils::simple_initiator_socket<ExampleInitiator> socket;
SC_CTOR(ExampleInitiator)
: socket("socket") // Construct and name socket
, request_in_progress(0)
, m_peq(this, &ExampleInitiator::peq_cb)
: socket("socket"),
request_in_progress(0),
m_peq(this, &ExampleInitiator::peq_cb)
{
socket.register_nb_transport_bw(this, &ExampleInitiator::nb_transport_bw);
SC_THREAD(thread_process);
}

4
DRAMSys/library/src/simulation/MemoryManager.cpp → DRAMSys/simulator/MemoryManager.cpp
View File

@@ -35,8 +35,8 @@
*/
#include "MemoryManager.h"
#include "../common/DebugManager.h"
#include "../configuration/Configuration.h"
#include "common/DebugManager.h"
#include "configuration/Configuration.h"
#include <iostream>
using namespace tlm;

0
DRAMSys/library/src/simulation/MemoryManager.h → DRAMSys/simulator/MemoryManager.h
View File

0
DRAMSys/library/src/simulation/StlPlayer.h → DRAMSys/simulator/StlPlayer.h
View File

0
DRAMSys/library/src/simulation/TraceGenerator.h → DRAMSys/simulator/TraceGenerator.h
View File

0
DRAMSys/library/src/simulation/TracePlayer.cpp → DRAMSys/simulator/TracePlayer.cpp
View File

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