Saving changes to python scripts

These are intermediate changes, just pushing them to access from home.

DRAMSys/tests/continuous_testing_py/autotest.py

@@ -44,18 +44,20 @@ from memutil import *
 
 devnull = None
 # If you want to change the standard output and/or standard error output do
-# that in the Top-level script environment (the '__main__' at the very bottom
+# that in the top-level script environment (the '__main__' at the very bottom
 # of this file.
 out = None
 errout = None
 
 rootdir = '../../..'
-tempfile.tempdir = os.getcwd() + '/' + rootdir
+workingdir = os.getcwd()
+tempfile.tempdir = workingdir + '/' + rootdir
 builddir = tempfile.mkdtemp()
 simdir = builddir + '/simulator'
 
 mcConfigPath = rootdir + '/DRAMSys/simulator/resources/configs/mcconfigs'
 memSpecsPath = rootdir + '/DRAMSys/simulator/resources/configs/memspecs'
+baseConfig = workingdir + '/baseconfig.xml'
 
 
 def build_project():
@@ -70,6 +72,7 @@ def build_project():
     return ret
 
 
+@unittest.skip("skipping this")
 class TestBuild(unittest.TestCase):
     def test_build_project(self):
         """ The project's build process should succeed """
@@ -79,6 +82,7 @@ class TestBuild(unittest.TestCase):
         shutil.rmtree(builddir)
 
 
+@unittest.skip("skipping this")
 class TestOutput(unittest.TestCase):
     def setUp(self):
         build_project()
@@ -88,13 +92,24 @@ class TestOutput(unittest.TestCase):
         os.chdir(simdir)
         self.assertEqual(subprocess.call(['./dramSys'], stdout=out), 0)
 
+    def test_run_with_base_config(self):
+        """ running dramSys with base config file output match reference """
+        os.chdir(simdir)
+        self.assertEqual(subprocess.call(['./dramSys', baseConfig],
+                         stdout=out), 0)
+
     def tearDown(self):
         shutil.rmtree(builddir)
 
 
-@unittest.skip("skipping this")
+# This is an example that shows how to skip a test.
+# @unittest.skip("skipping this")
 class TestDummy(unittest.TestCase):
+    def setUp(self):
+        os.chdir(workingdir)
+
     def test_list_files(self):
+        print('Current working directory is {0}'.format(os.getcwd()))
         for file in os.listdir(mcConfigPath):
             if file.endswith(".xml"):
                 print(file)
@@ -109,4 +124,5 @@ if __name__ == '__main__':
         errout = devnull
         # out = sys.stdout
         # errout = sys.stderr
+        print('Base configuration file is {0}'.format(baseConfig))
         unittest.main()

DRAMSys/tests/continuous_testing_py/baseconfig.xml

@@ -0,0 +1,57 @@
+<simulation>
+    <!-- General Simulator Configuration (used for all simulation setups) -->
+    <simconfig>
+        <Debug value="0" />
+        <DatabaseRecording value="1" />
+        <PowerAnalysis value="1" />
+        <EnableWindowing value = "1" />
+        <WindowSize value="100" />
+        <NumberOfTracePlayers value="1"/>
+        <NumberOfMemChannels value="1"/>
+        <ControllerCoreDisableRefresh value="0"/>
+        <ControllerCoreManualRefresh value="0"/>
+        <ThermalSimulation value="0"/>
+        <SimulationProgressBar value="1"/>
+        <NumberOfDevicesOnDIMM value = "8" />
+    </simconfig>
+
+    <!-- Temperature Simulator Configuration (used for all simulation setups) -->
+    <thermalsimconfig>
+        <TemperatureScale value="Celsius" />
+        <StaticTemperatureDefaultValue value="89" />
+        <ThermalSimPeriod value="100" />
+        <ThermalSimUnit value="us" />
+        <PowerInfoFile value="../../DRAMSys/simulator/resources/configs/thermalsim/powerInfo.xml"/>
+        <IceServerIp value="127.0.0.1" />
+        <IceServerPort value="11880" />
+        <SimPeriodAdjustFactor value="10" />
+        <NPowStableCyclesToIncreasePeriod value="5" />
+        <GenerateTemperatureMap value="1" />
+        <GeneratePowerMap value="1" />
+    </thermalsimconfig>
+
+
+    <!-- Memory Device Specification: Which Device is on our simulated DDR3 DIMM -->
+    <memspecs>
+        <memspec src="../../DRAMSys/simulator/resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G.xml"></memspec>
+    </memspecs>
+
+    <!-- Addressmapping Configuration of the Memory Controller -->
+    <addressmappings>
+        <addressmapping src="../../DRAMSys/simulator/resources/configs/amconfigs/am_ddr3_8x1Gbx8_dimm_p1KB_brc.xml"></addressmapping>
+    </addressmappings>
+
+
+    <!-- Memory Controller Configuration -->
+    <mcconfigs>
+        <mcconfig src="../../DRAMSys/simulator/resources/configs/mcconfigs/fifoStrict.xml"/>
+    </mcconfigs>
+
+    <tracesetups>
+        <tracesetup id="continuous_testing_py">
+            <device clkMhz="200">ddr3_example.stl</device>
+        </tracesetup>
+    </tracesetups>
+
+</simulation>
+