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Remove unused config files, add large example files with LFS.

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This commit is contained in:
Lukas Steiner
2023-01-30 15:05:42 +01:00
parent b63c9beb50
commit 3139fc96a3
34 changed files with 38 additions and 189 deletions
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3
.gitattributes vendored Normal file
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@@ -0,0 +1,3 @@
*.stl filter=lfs diff=lfs merge=lfs -text
*.data.gz filter=lfs diff=lfs merge=lfs -text
*.inst.gz filter=lfs diff=lfs merge=lfs -text

19
resources/configs/simulator/ddr3.json
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@@ -1,19 +0,0 @@
{
"simconfig": {
"AddressOffset": 0,
"CheckTLM2Protocol": false,
"DatabaseRecording": true,
"Debug": false,
"ECCControllerMode": "Disabled",
"EnableWindowing": false,
"ErrorCSVFile": "",
"ErrorChipSeed": 42,
"PowerAnalysis": false,
"SimulationName": "ddr3",
"SimulationProgressBar": true,
"StoreMode": "NoStorage",
"ThermalSimulation": false,
"UseMalloc": false,
"WindowSize": 1000
}
}

19
resources/configs/simulator/ddr4.json
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@@ -1,19 +0,0 @@
{
"simconfig": {
"AddressOffset": 0,
"CheckTLM2Protocol": false,
"DatabaseRecording": true,
"Debug": false,
"ECCControllerMode": "Disabled",
"EnableWindowing": false,
"ErrorCSVFile": "",
"ErrorChipSeed": 42,
"PowerAnalysis": false,
"SimulationName": "ddr4",
"SimulationProgressBar": true,
"StoreMode": "NoStorage",
"ThermalSimulation": false,
"UseMalloc": false,
"WindowSize": 1000
}
}

19
resources/configs/simulator/ddr5.json
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@@ -1,19 +0,0 @@
{
"simconfig": {
"AddressOffset": 0,
"CheckTLM2Protocol": false,
"DatabaseRecording": true,
"Debug": false,
"ECCControllerMode": "Disabled",
"EnableWindowing": false,
"ErrorCSVFile": "",
"ErrorChipSeed": 42,
"PowerAnalysis": false,
"SimulationName": "ddr5",
"SimulationProgressBar": true,
"StoreMode": "NoStorage",
"ThermalSimulation": false,
"UseMalloc": false,
"WindowSize": 1000
}
}

0
resources/configs/simulator/ddr3_ecc.json → resources/configs/simulator/ecc.json
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0
resources/configs/simulator/ddr3_gem5_se.json → resources/configs/simulator/gem5_se.json
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19
resources/configs/simulator/hbm2.json
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@@ -1,19 +0,0 @@
{
"simconfig": {
"AddressOffset": 0,
"CheckTLM2Protocol": false,
"DatabaseRecording": true,
"Debug": false,
"ECCControllerMode": "Disabled",
"EnableWindowing": false,
"ErrorCSVFile": "",
"ErrorChipSeed": 42,
"PowerAnalysis": false,
"SimulationName": "hbm2",
"SimulationProgressBar": true,
"StoreMode": "NoStorage",
"ThermalSimulation": false,
"UseMalloc": false,
"WindowSize": 1000
}
}

19
resources/configs/simulator/hbm3.json
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@@ -1,19 +0,0 @@
{
"simconfig": {
"AddressOffset": 0,
"CheckTLM2Protocol": false,
"DatabaseRecording": true,
"Debug": false,
"ECCControllerMode": "Disabled",
"EnableWindowing": false,
"ErrorCSVFile": "",
"ErrorChipSeed": 42,
"PowerAnalysis": false,
"SimulationName": "hbm3",
"SimulationProgressBar": true,
"StoreMode": "NoStorage",
"ThermalSimulation": false,
"UseMalloc": false,
"WindowSize": 1000
}
}

19
resources/configs/simulator/lpddr4.json
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@@ -1,19 +0,0 @@
{
"simconfig": {
"AddressOffset": 0,
"CheckTLM2Protocol": false,
"DatabaseRecording": true,
"Debug": false,
"ECCControllerMode": "Disabled",
"EnableWindowing": false,
"ErrorCSVFile": "",
"ErrorChipSeed": 42,
"PowerAnalysis": false,
"SimulationName": "lpddr4",
"SimulationProgressBar": true,
"StoreMode": "NoStorage",
"ThermalSimulation": false,
"UseMalloc": false,
"WindowSize": 1000
}
}

19
resources/configs/simulator/stt-mram.json
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@@ -1,19 +0,0 @@
{
"simconfig": {
"AddressOffset": 0,
"CheckTLM2Protocol": false,
"DatabaseRecording": true,
"Debug": false,
"ECCControllerMode": "Disabled",
"EnableWindowing": false,
"ErrorCSVFile": "",
"ErrorChipSeed": 42,
"PowerAnalysis": false,
"SimulationName": "stt-mram",
"SimulationProgressBar": true,
"StoreMode": "NoStorage",
"ThermalSimulation": false,
"UseMalloc": false,
"WindowSize": 1000
}
}

0
src/gem5/gem5_etrace/config.ini → resources/gem5/gem5_etrace/config.ini
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resources/gem5/gem5_etrace/system.cpu.traceListener.data.gz LFS Normal file
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resources/gem5/gem5_etrace/system.cpu.traceListener.inst.gz LFS Normal file
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0
src/gem5/gem5_se/hello-ARM/config.ini → resources/gem5/gem5_se/hello-ARM/config.ini
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0
src/gem5/gem5_se/hello-ARM/hello → resources/gem5/gem5_se/hello-ARM/hello
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0
src/gem5/gem5_se/hello-X86/config.ini → resources/gem5/gem5_se/hello-X86/config.ini
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0
src/gem5/gem5_se/hello-X86/hello → resources/gem5/gem5_se/hello-X86/hello
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4
resources/simulations/ddr3-example.json
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@@ -3,13 +3,13 @@
"addressmapping": "am_ddr3_8x1Gbx8_dimm_p1KB_rbc.json",
"mcconfig": "fr_fcfs.json",
"memspec": "MICRON_1Gb_DDR3-1600_8bit_G.json",
"simconfig": "ddr3.json",
"simconfig": "example.json",
"simulationid": "ddr3-example",
"thermalconfig": "config.json",
"tracesetup": [
{
"clkMhz": 800,
"name": "ddr3_example.stl"
"name": "example.stl"
}
]
}

20
resources/simulations/ddr3-example2.json
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@@ -1,20 +0,0 @@
{
"simulation": {
"addressmapping": "am_ddr3_8x1Gbx8_dimm_p1KB_brc.json",
"mcconfig": "fr_fcfs.json",
"memspec": "MICRON_1Gb_DDR3-1600_8bit_G.json",
"simconfig": "ddr3.json",
"simulationid": "ddr3-example2",
"thermalconfig": "config.json",
"tracesetup": [
{
"clkMhz": 300,
"name": "ddr3_example.stl"
},
{
"clkMhz": 400,
"name": "ddr3_example.stl"
}
]
}
}

4
resources/simulations/ddr3-gem5-se.json
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@@ -3,8 +3,8 @@
"addressmapping": "am_ddr3_8x1Gbx8_dimm_p1KB_brc.json",
"mcconfig": "fifoStrict.json",
"memspec": "MICRON_1Gb_DDR3-1600_8bit_G.json",
"simconfig": "ddr3_gem5_se.json",
"simconfig": "gem5_se.json",
"simulationid": "ddr3-gem5-se",
"thermalconfig": "config.json"
}
}
}

4
resources/simulations/ddr4-example.json
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@@ -3,13 +3,13 @@
"addressmapping": "am_ddr4_8x4Gbx8_dimm_p1KB_brc.json",
"mcconfig": "fr_fcfs.json",
"memspec": "JEDEC_4Gb_DDR4-1866_8bit_A.json",
"simconfig": "ddr4.json",
"simconfig": "example.json",
"simulationid": "ddr4-example",
"thermalconfig": "config.json",
"tracesetup": [
{
"clkMhz": 200,
"name": "ddr3_example.stl"
"name": "example.stl"
}
]
}

4
resources/simulations/ddr5-example.json
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@@ -3,13 +3,13 @@
"addressmapping": "am_ddr5_2x8x2Gbx4_dimm_p1KB_rbc.json",
"mcconfig": "fr_fcfs.json",
"memspec": "JEDEC_2x8x2Gbx4_DDR5-3200A.json",
"simconfig": "ddr5.json",
"simconfig": "example.json",
"simulationid": "ddr5-example",
"thermalconfig": "config.json",
"tracesetup": [
{
"clkMhz": 2000,
"name": "ddr3_example.stl"
"name": "example.stl"
}
]
}

2
resources/simulations/ddr5-generator-example.json
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@@ -3,7 +3,7 @@
"addressmapping": "am_ddr5_2x8x2Gbx4_dimm_p1KB_rbc.json",
"mcconfig": "fr_fcfs.json",
"memspec": "JEDEC_2x8x2Gbx4_DDR5-3200A.json",
"simconfig": "ddr5.json",
"simconfig": "example.json",
"simulationid": "ddr5-example",
"thermalconfig": "config.json",
"tracesetup": [

2
resources/simulations/ddr5-rfm.json
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@@ -3,7 +3,7 @@
"addressmapping": "am_ddr5_2x2x8x4Gbx4_dimm_p1KB_rbc.json",
"mcconfig": "fr_fcfs_rfm.json",
"memspec": "JEDEC_2x2x8x4Gbx4_DDR5-3200A.json",
"simconfig": "ddr5.json",
"simconfig": "example.json",
"simulationid": "ddr5-example",
"thermalconfig": "config.json",
"tracesetup": [

4
resources/simulations/hbm2-example.json
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@@ -3,13 +3,13 @@
"addressmapping": "am_hbm2_8Gb_pc_brc.json",
"mcconfig": "fr_fcfs.json",
"memspec": "HBM2.json",
"simconfig": "hbm2.json",
"simconfig": "example.json",
"simulationid": "hbm2-example",
"thermalconfig": "config.json",
"tracesetup": [
{
"clkMhz": 1000,
"name": "ddr3_example.stl"
"name": "example.stl"
}
]
}

4
resources/simulations/hbm3-example.json
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@@ -3,13 +3,13 @@
"addressmapping": "am_hbm3_8Gb_pc_brc.json",
"mcconfig": "fr_fcfs.json",
"memspec": "HBM3.json",
"simconfig": "hbm3.json",
"simconfig": "example.json",
"simulationid": "hbm3-example",
"thermalconfig": "config.json",
"tracesetup": [
{
"clkMhz": 1000,
"name": "ddr3_example.stl"
"name": "example.stl"
}
]
}

4
resources/simulations/lpddr4-example.json
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@@ -3,13 +3,13 @@
"addressmapping": "am_lpddr4_8Gbx16_brc.json",
"mcconfig": "fr_fcfs.json",
"memspec": "JEDEC_8Gb_LPDDR4-3200_16bit.json",
"simconfig": "lpddr4.json",
"simconfig": "example.json",
"simulationid": "lpddr4-example",
"thermalconfig": "config.json",
"tracesetup": [
{
"clkMhz": 200,
"name": "ddr3_example.stl"
"name": "example.stl"
}
]
}

2
resources/simulations/lpddr5-example.json
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@@ -9,7 +9,7 @@
"tracesetup": [
{
"clkMhz": 200,
"name": "ddr3_example.stl"
"name": "example.stl"
}
]
}

2
resources/simulations/ranktest.json
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@@ -3,7 +3,7 @@
"addressmapping": "am_ranktest.json",
"mcconfig": "fr_fcfs.json",
"memspec": "memspec_ranktest.json",
"simconfig": "ddr3.json",
"simconfig": "example.json",
"simulationid": "ranktest",
"thermalconfig": "config.json",
"tracesetup": [

4
resources/simulations/stt-mram-example.json
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@@ -3,13 +3,13 @@
"addressmapping": "am_stt-mram_8x2Gbx8_dimm_p1KB_rbc.json",
"mcconfig": "fr_fcfs_noref.json",
"memspec": "STT-MRAM-1.2x.json",
"simconfig": "stt-mram.json",
"simconfig": "example.json",
"simulationid": "stt-mram-example",
"thermalconfig": "config.json",
"tracesetup": [
{
"clkMhz": 800,
"name": "ddr3_example.stl"
"name": "example.stl"
}
]
}

16
resources/simulations/wideio-example.json
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@@ -1,16 +0,0 @@
{
"simulation": {
"addressmapping": "am_wideio_4x256Mb_rbc.json",
"mcconfig": "fr_fcfs.json",
"memspec": "JEDEC_256Mb_WIDEIO-200_128bit.json",
"simconfig": "wideio.json",
"simulationid": "wideio-example",
"thermalconfig": "config.json",
"tracesetup": [
{
"clkMhz": 1000,
"name": "chstone-adpcm_32.stl"
}
]
}
}

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